diff options
Diffstat (limited to 'board')
35 files changed, 1258 insertions, 546 deletions
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c index c0f33b806e..9eec1b7838 100644 --- a/board/CarMediaLab/flea3/flea3.c +++ b/board/CarMediaLab/flea3/flea3.c @@ -205,7 +205,7 @@ u32 get_board_rev(void) */ int ft_board_setup(void *blob, bd_t *bd) { - struct node_info nodes[] = { + static const struct node_info nodes[] = { { "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */ { "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ }; diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index c114cdccbb..d42f57d4b7 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -519,7 +519,7 @@ int cm_fx6_setup_ecspi(void) { return 0; } #ifdef CONFIG_OF_BOARD_SETUP #define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/" -struct node_info nodes[] = { +static const struct node_info nodes[] = { /* * Both entries target the same flash chip. The st,m25p compatible * is used in the vendor device trees, while upstream uses (the diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index dffe4ebd45..04e9eab272 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -136,7 +136,31 @@ static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = { .grp_b7ds = 0x00000030, }; -static const struct mx6_mmdc_calibration dhcom_mmdc_calib = { +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = { + .p0_mpwldectrl0 = 0x00150019, + .p0_mpwldectrl1 = 0x001C000B, + .p1_mpwldectrl0 = 0x00020018, + .p1_mpwldectrl1 = 0x0002000C, + .p0_mpdgctrl0 = 0x43140320, + .p0_mpdgctrl1 = 0x03080304, + .p1_mpdgctrl0 = 0x43180320, + .p1_mpdgctrl1 = 0x03100254, + .p0_mprddlctl = 0x4830383C, + .p1_mprddlctl = 0x3836323E, + .p0_mpwrdlctl = 0x3E444642, + .p1_mpwrdlctl = 0x42344442, +}; + +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = { + .p0_mpwldectrl0 = 0x0040003C, + .p0_mpwldectrl1 = 0x0032003E, + .p0_mpdgctrl0 = 0x42350231, + .p0_mpdgctrl1 = 0x021A0218, + .p0_mprddlctl = 0x4B4B4E49, + .p0_mpwrdlctl = 0x3F3F3035, +}; + +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = { .p0_mpwldectrl0 = 0x0011000E, .p0_mpwldectrl1 = 0x000E001B, .p1_mpwldectrl0 = 0x00190015, @@ -151,23 +175,89 @@ static const struct mx6_mmdc_calibration dhcom_mmdc_calib = { .p1_mpwrdlctl = 0x473E4A3B, }; -static const struct mx6_ddr3_cfg dhcom_mem_ddr = { +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = { + .p0_mpwldectrl0 = 0x003A003A, + .p0_mpwldectrl1 = 0x0030002F, + .p1_mpwldectrl0 = 0x002F0038, + .p1_mpwldectrl1 = 0x00270039, + .p0_mpdgctrl0 = 0x420F020F, + .p0_mpdgctrl1 = 0x01760175, + .p1_mpdgctrl0 = 0x41640171, + .p1_mpdgctrl1 = 0x015E0160, + .p0_mprddlctl = 0x45464B4A, + .p1_mprddlctl = 0x49484A46, + .p0_mpwrdlctl = 0x40402E32, + .p1_mpwrdlctl = 0x3A3A3231, +}; + +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = { + .p0_mpwldectrl0 = 0x0040003C, + .p0_mpwldectrl1 = 0x0032003E, + .p0_mpdgctrl0 = 0x42350231, + .p0_mpdgctrl1 = 0x021A0218, + .p0_mprddlctl = 0x4B4B4E49, + .p0_mpwrdlctl = 0x3F3F3035, +}; + +/* + * 2 Gbit DDR3 memory + * - NANYA #NT5CC128M16IP-DII + * - NANYA #NT5CB128M16FP-DII + */ +static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = { .mem_speed = 1600, .density = 2, - .width = 64, + .width = 16, .banks = 8, .rowaddr = 14, .coladdr = 10, .pagesz = 2, - .trcd = 1312, + .trcd = 1375, .trcmin = 5863, .trasmin = 3750, }; -static const struct mx6_ddr_sysinfo dhcom_ddr_info = { +/* + * 4 Gbit DDR3 memory + * - Intelligent Memory #IM4G16D3EABG-125I + */ +static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* DDR3 64bit */ +static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = { /* width of data bus:0=16,1=32,2=64 */ .dsize = 2, - .cs_density = 16, + .cs_density = 32, + .ncs = 1, /* single chip select */ + .cs1_mirror = 1, + .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */ + .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 3, /* 4 refresh commands per refresh cycle */ +}; + +/* DDR3 32bit */ +static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 1, + .cs_density = 32, .ncs = 1, /* single chip select */ .cs1_mirror = 1, .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */ @@ -208,6 +298,45 @@ static void setup_iomux_boardid(void) SETUP_IOMUX_PADS(hwcode_pads); } +/* DDR Code */ +static iomux_v3_cfg_t const ddrcode_pads[] = { + IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), +}; + +static void setup_iomux_ddrcode(void) +{ + /* ddr code pins */ + SETUP_IOMUX_PADS(ddrcode_pads); +} + +enum dhcom_ddr3_code { + DH_DDR3_SIZE_256MIB = 0x00, + DH_DDR3_SIZE_512MIB = 0x01, + DH_DDR3_SIZE_1GIB = 0x02, + DH_DDR3_SIZE_2GIB = 0x03 +}; + +#define DDR3_CODE_BIT_0 IMX_GPIO_NR(2, 22) +#define DDR3_CODE_BIT_1 IMX_GPIO_NR(2, 21) + +enum dhcom_ddr3_code dhcom_get_ddr3_code(void) +{ + enum dhcom_ddr3_code ddr3_code; + + gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0"); + gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1"); + + gpio_direction_input(DDR3_CODE_BIT_0); + gpio_direction_input(DDR3_CODE_BIT_1); + + /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */ + ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1) + | (!!gpio_get_value(DDR3_CODE_BIT_0)); + + return ddr3_code; +} + /* GPIO */ static iomux_v3_cfg_t const gpio_pads[] = { IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), @@ -353,6 +482,81 @@ static void setup_iomux_usb(void) SETUP_IOMUX_PADS(usb_pads); } + +/* DRAM */ +static void dhcom_spl_dram_init(void) +{ + enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code(); + + if (is_mx6dq()) { + mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs, + &dhcom6dq_grp_ioregs); + switch (ddr3_code) { + default: + printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code); + printf(" choosing 1024 MB\n"); + /* fall through */ + case DH_DDR3_SIZE_1GIB: + mx6_dram_cfg(&dhcom_ddr_64bit, + &dhcom_mmdc_calib_4x2g_1066, + &dhcom_mem_ddr_2g); + break; + case DH_DDR3_SIZE_2GIB: + mx6_dram_cfg(&dhcom_ddr_64bit, + &dhcom_mmdc_calib_4x4g_1066, + &dhcom_mem_ddr_4g); + break; + } + + /* Perform DDR DRAM calibration */ + udelay(100); + mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + + } else if (is_cpu_type(MXC_CPU_MX6DL)) { + mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs, + &dhcom6sdl_grp_ioregs); + switch (ddr3_code) { + default: + printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code); + printf(" choosing 1024 MB\n"); + /* fall through */ + case DH_DDR3_SIZE_1GIB: + mx6_dram_cfg(&dhcom_ddr_64bit, + &dhcom_mmdc_calib_4x2g_800, + &dhcom_mem_ddr_2g); + break; + } + + /* Perform DDR DRAM calibration */ + udelay(100); + mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + + } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { + mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs, + &dhcom6sdl_grp_ioregs); + switch (ddr3_code) { + default: + printf("imx6s: unsupported ddr3 code %d\n", ddr3_code); + printf(" choosing 512 MB\n"); + /* fall through */ + case DH_DDR3_SIZE_512MIB: + mx6_dram_cfg(&dhcom_ddr_32bit, + &dhcom_mmdc_calib_2x2g_800, + &dhcom_mem_ddr_2g); + break; + case DH_DDR3_SIZE_1GIB: + mx6_dram_cfg(&dhcom_ddr_32bit, + &dhcom_mmdc_calib_2x4g_800, + &dhcom_mem_ddr_4g); + break; + } + + /* Perform DDR DRAM calibration */ + udelay(100); + mmdc_do_dqs_calibration(&dhcom_ddr_32bit); + } +} + void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ @@ -365,6 +569,7 @@ void board_init_f(ulong dummy) timer_init(); setup_iomux_boardid(); + setup_iomux_ddrcode(); setup_iomux_gpio(); setup_iomux_enet(); setup_iomux_sd(); @@ -375,14 +580,8 @@ void board_init_f(ulong dummy) /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); - /* Start the DDR DRAM */ - if (is_mx6dq()) - mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs, - &dhcom6dq_grp_ioregs); - else - mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs, - &dhcom6sdl_grp_ioregs); - mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr); + /* DDR3 initialization */ + dhcom_spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c index 1a1fe6c66a..4d293c8032 100644 --- a/board/engicam/common/spl.c +++ b/board/engicam/common/spl.c @@ -414,7 +414,8 @@ void board_init_f(ulong dummy) /* setup AIPS and disable watchdog */ arch_cpu_init(); - gpr_init(); + if (!(is_mx6ul())) + gpr_init(); /* iomux */ SETUP_IOMUX_PADS(uart_pads); diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c index 367152fa5f..9d9c83f716 100644 --- a/board/freescale/bsc9131rdb/bsc9131rdb.c +++ b/board/freescale/bsc9131rdb/bsc9131rdb.c @@ -53,7 +53,7 @@ int checkboard(void) #if defined(CONFIG_OF_BOARD_SETUP) #ifdef CONFIG_FDT_FIXUP_PARTITIONS -struct node_info nodes[] = { +static const struct node_info nodes[] = { { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, }; #endif diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index 6885668ff9..36a55285e8 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -357,7 +357,7 @@ void fdt_del_node_compat(void *blob, const char *compatible) #if defined(CONFIG_OF_BOARD_SETUP) #ifdef CONFIG_FDT_FIXUP_PARTITIONS -struct node_info nodes[] = { +static const struct node_info nodes[] = { { "cfi-flash", MTD_DEV_TYPE_NOR, }, { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, }; diff --git a/board/freescale/m5253evbe/Kconfig b/board/freescale/m5253evbe/Kconfig deleted file mode 100644 index d97b87c4ca..0000000000 --- a/board/freescale/m5253evbe/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_M5253EVBE - -config SYS_CPU - default "mcf52x2" - -config SYS_BOARD - default "m5253evbe" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "M5253EVBE" - -endif diff --git a/board/freescale/m5253evbe/MAINTAINERS b/board/freescale/m5253evbe/MAINTAINERS deleted file mode 100644 index 74acd1eee5..0000000000 --- a/board/freescale/m5253evbe/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -M5253EVBE BOARD -#M: Hayden Fraser <Hayden.Fraser@freescale.com> -S: Orphan (since 2014-06) -F: board/freescale/m5253evbe/ -F: include/configs/M5253EVBE.h -F: configs/M5253EVBE_defconfig diff --git a/board/freescale/m5253evbe/Makefile b/board/freescale/m5253evbe/Makefile deleted file mode 100644 index 79e20b7365..0000000000 --- a/board/freescale/m5253evbe/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = m5253evbe.o diff --git a/board/freescale/m5253evbe/README b/board/freescale/m5253evbe/README deleted file mode 100644 index f4eae67fc0..0000000000 --- a/board/freescale/m5253evbe/README +++ /dev/null @@ -1,102 +0,0 @@ -Freescale Amadeus Plus M5253EVBE board -====================================== - -Hayden Fraser(Hayden.Fraser@freescale.com) -Created 06/05/2007 -=========================================== - - -1. SWITCH SETTINGS -================== -1.1 N/A - - -2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL -=========================================== -2.1. For the initial bringup, we adopted a consistent memory scheme between U-Boot and - linux kernel, you can customize it based on your system requirements: - SDR: 0x00000000-0x00ffffff - SRAM0: 0x20010000-0x20017fff - SRAM1: 0x20000000-0x2000ffff - MBAR1: 0x10000000-0x4fffffff - MBAR2: 0x80000000-0xCfffffff - Flash: 0xffe00000-0xffffffff - -3. DEFINITIONS AND COMPILATION -============================== -3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h - CONFIG_MCF52x2 Processor family - CONFIG_MCF5253 MCF5253 specific - CONFIG_SYS_CLK Define Amadeus Plus CPU Clock - CONFIG_SYS_MBAR MBAR base address - CONFIG_SYS_MBAR2 MBAR2 base address - -3.2 Compilation - export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf- - cd u-boot-1-2-x - make distclean - make M5253EVBE_config - make - - -4. SCREEN DUMP -============== -4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00) - -CPU: Freescale Coldfire MCF5253 at 62 MHz -Board: Freescale MCF5253 EVBE -DRAM: 16 MB -FLASH: 2 MB -In: serial -Out: serial -Err: serial -=> flinfo - -Bank # 1: CFI conformant FLASH (16 x 16) Size: 2 MB in 35 Sectors - AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49 - Erase timeout: 16384 ms, write timeout: 1 ms - - Sector Start Addresses: - FFE00000 RO FFE04000 RO FFE06000 RO FFE08000 RO FFE10000 RO - FFE20000 FFE30000 FFE40000 FFE50000 FFE60000 - FFE70000 FFE80000 FFE90000 FFEA0000 FFEB0000 - FFEC0000 FFED0000 FFEE0000 FFEF0000 FFF00000 - FFF10000 FFF20000 FFF30000 FFF40000 FFF50000 - FFF60000 FFF70000 FFF80000 FFF90000 FFFA0000 - FFFB0000 FFFC0000 FFFD0000 FFFE0000 FFFF0000 - -=> bdinfo -boot_params = 0x00F62F90 -memstart = 0x00000000 -memsize = 0x01000000 -flashstart = 0xFFE00000 -flashsize = 0x00200000 -flashoffset = 0x00000000 -baudrate = 19200 bps - -=> printenv -bootdelay=5 -baudrate=19200 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 134/8188 bytes -=> saveenv -Saving Environment to Flash... -Un-Protected 1 sectors -Erasing Flash... -. done -Erased 1 sectors -Writing to Flash... done -Protected 1 sectors -=> - -5. COMPILER ------------ -To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture -compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used. -You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html - -compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M -codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c deleted file mode 100644 index 04447faaa4..0000000000 --- a/board/freescale/m5253evbe/m5253evbe.c +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * Hayden Fraser (Hayden.Fraser@freescale.com) - */ - -#include <common.h> -#include <asm/immap.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Board: "); - puts("Freescale MCF5253 EVBE\n"); - return 0; -}; - -int dram_init(void) -{ - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { - u32 RC, dramsize; - - RC = (CONFIG_SYS_CLK / 1000000) >> 1; - RC = (RC * 15) >> 4; - - /* Initialize DRAM Control Register: DCR */ - mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); - asm("nop"); - - mbar_writeLong(MCFSIM_DACR0, 0x00002320); - asm("nop"); - - /* Initialize DMR0 */ - dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; - mbar_writeLong(MCFSIM_DMR0, dramsize | 1); - asm("nop"); - - mbar_writeLong(MCFSIM_DACR0, 0x00002328); - asm("nop"); - - /* Write to this block to initiate precharge */ - *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; - asm("nop"); - - /* Set RE bit in DACR */ - mbar_writeLong(MCFSIM_DACR0, - mbar_readLong(MCFSIM_DACR0) | 0x8000); - asm("nop"); - - /* Wait for at least 8 auto refresh cycles to occur */ - udelay(500); - - /* Finish the configuration by issuing the MRS */ - mbar_writeLong(MCFSIM_DACR0, - mbar_readLong(MCFSIM_DACR0) | 0x0040); - asm("nop"); - - *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; - } - - gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - - return 0; -} - -int testdram(void) -{ - /* TODO: XXX XXX XXX */ - printf("DRAM test not implemented!\n"); - - return (0); -} - -#ifdef CONFIG_IDE -#include <ata.h> -int ide_preinit(void) -{ - return (0); -} - -void ide_set_reset(int idereset) -{ - atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; - long period; - /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ - int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ - {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */ - {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */ - {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */ - {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */ - }; - - if (idereset) { - /* control reset */ - out_8(&ata->cr, 0); - udelay(100); - } else { - mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); - -#define CALC_TIMING(t) (t + period - 1) / period - period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ - - /*ata->ton = CALC_TIMING (180); */ - out_8(&ata->t1, CALC_TIMING(piotms[2][0])); - out_8(&ata->t2w, CALC_TIMING(piotms[2][1])); - out_8(&ata->t2r, CALC_TIMING(piotms[2][1])); - out_8(&ata->ta, CALC_TIMING(piotms[2][8])); - out_8(&ata->trd, CALC_TIMING(piotms[2][7])); - out_8(&ata->t4, CALC_TIMING(piotms[2][3])); - out_8(&ata->t9, CALC_TIMING(piotms[2][6])); - - /* IORDY enable */ - out_8(&ata->cr, 0x40); - udelay(2000); - /* IORDY enable */ - setbits_8(&ata->cr, 0x01); - } -} -#endif /* CONFIG_IDE */ diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index b86924ebe2..c4ec97435f 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1114,7 +1114,7 @@ int ft_board_setup(void *blob, bd_t *bd) { struct ventana_board_info *info = &ventana_info; struct ventana_eeprom_config *cfg; - struct node_info nodes[] = { + static const struct node_info nodes[] = { { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ }; diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c index cc55bcc81a..965a009a9f 100644 --- a/board/isee/igep003x/board.c +++ b/board/isee/igep003x/board.c @@ -211,7 +211,7 @@ int board_late_init(void) int ft_board_setup(void *blob, bd_t *bd) { #ifdef CONFIG_FDT_FIXUP_PARTITIONS - static struct node_info nodes[] = { + static const struct node_info nodes[] = { { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, }; diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 45a414c153..367af82d4a 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -157,7 +157,7 @@ static int ft_enable_by_compatible(void *blob, char *compat, int enable) int ft_board_setup(void *blob, bd_t *bd) { #ifdef CONFIG_FDT_FIXUP_PARTITIONS - static struct node_info nodes[] = { + static const struct node_info nodes[] = { { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, }, }; diff --git a/board/logicpd/am3517evm/MAINTAINERS b/board/logicpd/am3517evm/MAINTAINERS index 7f03ac12ee..198023fb15 100644 --- a/board/logicpd/am3517evm/MAINTAINERS +++ b/board/logicpd/am3517evm/MAINTAINERS @@ -1,5 +1,5 @@ AM3517EVM BOARD -M: Vaibhav Hiremath <hvaibhav@ti.com> +M: Adam Ford <aford173@gmail.com> S: Maintained F: board/logicpd/am3517evm/ F: include/configs/am3517_evm.h diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index 84405635a5..ce1c8a5d6b 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -182,3 +182,144 @@ int board_late_init(void) return 0; } + +#ifdef CONFIG_SPL_BUILD +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6q-ddr.h> +#include <spl.h> +#include <linux/libfdt.h> + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0xFFFFF300, &ccm->CCGR4); + writel(0x0F0000F3, &ccm->CCGR5); + writel(0x00000FFF, &ccm->CCGR6); +} + +static int mx6q_dcd_table[] = { + MX6_IOM_GRP_DDR_TYPE, 0x000C0000, + MX6_IOM_GRP_DDRPKE, 0x00000000, + MX6_IOM_DRAM_SDCLK_0, 0x00000030, + MX6_IOM_DRAM_SDCLK_1, 0x00000030, + MX6_IOM_DRAM_CAS, 0x00000030, + MX6_IOM_DRAM_RAS, 0x00000030, + MX6_IOM_GRP_ADDDS, 0x00000030, + MX6_IOM_DRAM_RESET, 0x00000030, + MX6_IOM_DRAM_SDBA2, 0x00000000, + MX6_IOM_DRAM_SDODT0, 0x00000030, + MX6_IOM_DRAM_SDODT1, 0x00000030, + MX6_IOM_GRP_CTLDS, 0x00000030, + MX6_IOM_DDRMODE_CTL, 0x00020000, + MX6_IOM_DRAM_SDQS0, 0x00000030, + MX6_IOM_DRAM_SDQS1, 0x00000030, + MX6_IOM_DRAM_SDQS2, 0x00000030, + MX6_IOM_DRAM_SDQS3, 0x00000030, + MX6_IOM_GRP_DDRMODE, 0x00020000, + MX6_IOM_GRP_B0DS, 0x00000030, + MX6_IOM_GRP_B1DS, 0x00000030, + MX6_IOM_GRP_B2DS, 0x00000030, + MX6_IOM_GRP_B3DS, 0x00000030, + MX6_IOM_DRAM_DQM0, 0x00000030, + MX6_IOM_DRAM_DQM1, 0x00000030, + MX6_IOM_DRAM_DQM2, 0x00000030, + MX6_IOM_DRAM_DQM3, 0x00000030, + MX6_MMDC_P0_MDSCR, 0x00008000, + MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, + MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A, + MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B, + MX6_MMDC_P0_MPDGCTRL0, 0x03340338, + MX6_MMDC_P0_MPDGCTRL1, 0x0334032C, + MX6_MMDC_P0_MPRDDLCTL, 0x4036383C, + MX6_MMDC_P0_MPWRDLCTL, 0x2E384038, + MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, + MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, + MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, + MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, + MX6_MMDC_P0_MPMUR0, 0x00000800, + MX6_MMDC_P0_MDPDC, 0x00020036, + MX6_MMDC_P0_MDOTC, 0x09444040, + MX6_MMDC_P0_MDCFG0, 0xB8BE7955, + MX6_MMDC_P0_MDCFG1, 0xFF328F64, + MX6_MMDC_P0_MDCFG2, 0x01FF00DB, + MX6_MMDC_P0_MDMISC, 0x00011740, + MX6_MMDC_P0_MDSCR, 0x00008000, + MX6_MMDC_P0_MDRWD, 0x000026D2, + MX6_MMDC_P0_MDOR, 0x00BE1023, + MX6_MMDC_P0_MDASP, 0x00000047, + MX6_MMDC_P0_MDCTL, 0x85190000, + MX6_MMDC_P0_MDSCR, 0x00888032, + MX6_MMDC_P0_MDSCR, 0x00008033, + MX6_MMDC_P0_MDSCR, 0x00008031, + MX6_MMDC_P0_MDSCR, 0x19408030, + MX6_MMDC_P0_MDSCR, 0x04008040, + MX6_MMDC_P0_MDREF, 0x00007800, + MX6_MMDC_P0_MPODTCTRL, 0x00000007, + MX6_MMDC_P0_MDPDC, 0x00025576, + MX6_MMDC_P0_MAPSR, 0x00011006, + MX6_MMDC_P0_MDSCR, 0x00000000, + /* enable AXI cache for VDOA/VPU/IPU */ + + MX6_IOMUXC_GPR4, 0xF00000CF, + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + MX6_IOMUXC_GPR6, 0x007F007F, + MX6_IOMUXC_GPR7, 0x007F007F, +}; + +static void ddr_init(int *table, int size) +{ + int i; + + for (i = 0; i < size / 2 ; i++) + writel(table[2 * i + 1], table[2 * i]); +} + +static void spl_dram_init(void) +{ + if (is_mx6dq()) + ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table)); +} + +void board_init_f(ulong dummy) +{ + /* DDR initialization */ + spl_dram_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* iomux and setup of uart and NAND pins */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg deleted file mode 100644 index 6d7e29d627..0000000000 --- a/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Logic PD, Inc. - * Adam Ford <aford173@gmail.com> - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -#include <asm/mach-imx/imximage.cfg> - -/* image version */ -IMAGE_VERSION 2 - -BOOT_OFFSET FLASH_OFFSET_STANDARD - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch-mx6/mx6-ddr.h" -#include "asm/arch-mx6/iomux.h" -#include "asm/arch-mx6/crm_regs.h" - -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 -DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038 -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 -DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 -DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0xFFFFF300 -DATA 4, CCM_CCGR5, 0x0F0000F3 -DATA 4, CCM_CCGR6, 0x00000FFF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 MX6_IOMUXC_GPR4 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 MX6_IOMUXC_GPR6 0x007F007F -DATA 4 MX6_IOMUXC_GPR7 0x007F007F diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README index ada8ca7f3c..8321467046 100644 --- a/board/rockchip/evb_rk3399/README +++ b/board/rockchip/evb_rk3399/README @@ -65,7 +65,7 @@ Compile the U-Boot Compile the rkdeveloptool ======================= Follow instructions in latest README - > cd ../rkflashtool + > cd ../rkdeveloptool > autoreconf -i > ./configure > make diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 38d89f0130..cf63427e52 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -126,6 +126,20 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + static iomux_v3_cfg_t const board_detect[] = { /* These pins are for sensing if it is a CuBox-i or a HummingBoard */ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)), @@ -148,23 +162,95 @@ static void setup_iomux_uart(void) SETUP_IOMUX_PADS(uart1_pads); } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC2_BASE_ADDR}, +static struct fsl_esdhc_cfg usdhc_cfg = { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 4, }; +static struct fsl_esdhc_cfg emmc_cfg = { + .esdhc_base = USDHC3_BASE_ADDR, + .max_bus_width = 8, +}; + +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) + int board_mmc_getcd(struct mmc *mmc) { - return 1; /* uSDHC2 is always present */ + struct fsl_esdhc_cfg *cfg = mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = (mmc_get_op_cond(mmc) < 0) ? 0 : 1; /* eMMC/uSDHC3 has no CD GPIO */ + break; + } + + return ret; } -int board_mmc_init(bd_t *bis) +static int mmc_init_main(bd_t *bis) { + int ret; + + /* + * Following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 Carrier board MicroSD + * mmc1 SOM eMMC + */ SETUP_IOMUX_PADS(usdhc2_pads); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg); + if (ret) + return ret; + + SETUP_IOMUX_PADS(usdhc3_pads); + emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + return fsl_esdhc_initialize(bis, &emmc_cfg); +} + +static int mmc_init_spl(bd_t *bis) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD2 + * 0x2 SD3 + */ + switch (reg & 0x3) { + case 0x1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg); + case 0x2: + SETUP_IOMUX_PADS(usdhc3_pads); + emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = emmc_cfg.sdhc_clk; + return fsl_esdhc_initialize(bis, &emmc_cfg); + } + + return -ENODEV; +} + +int board_mmc_init(bd_t *bis) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) + return mmc_init_spl(bis); + + return mmc_init_main(bis); } static iomux_v3_cfg_t const enet_pads[] = { @@ -441,6 +527,15 @@ static bool is_rev_15_som(void) return false; } +static bool has_emmc(void) +{ + struct mmc *mmc; + mmc = find_mmc_device(1); + if (!mmc) + return 0; + return (mmc_get_op_cond(mmc) < 0) ? 0 : 1; +} + int checkboard(void) { switch (board_type()) { @@ -493,6 +588,10 @@ int board_late_init(void) if (is_rev_15_som()) env_set("som_rev", "V15"); + + if (has_emmc()) + env_set("has_emmc", "yes"); + #endif return 0; diff --git a/board/technexion/pico-imx7d/Makefile b/board/technexion/pico-imx7d/Makefile index 6cfa80368d..4ae3d606b5 100644 --- a/board/technexion/pico-imx7d/Makefile +++ b/board/technexion/pico-imx7d/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ # (C) Copyright 2017 NXP Semiconductors -obj-y := pico-imx7d.o +obj-y := pico-imx7d.o spl.o diff --git a/board/technexion/pico-imx7d/README b/board/technexion/pico-imx7d/README index 8af4effa78..aa9d72c5d1 100644 --- a/board/technexion/pico-imx7d/README +++ b/board/technexion/pico-imx7d/README @@ -35,32 +35,20 @@ Use the default environment variables: => env default -f -a => saveenv -Run the UMS command: -=> ums 0 mmc 0 +Run the DFU agent so we can flash the new images using dfu-util tool: -Transfer u-boot.imx to be flashed into the eMMC: +=> dfu 0 mmc 0 -$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1; sync +Flash SPL into the eMMC: -Remove power from the pico board. - -Put pico board into normal boot mode. +$ sudo dfu-util -D SPL -a spl -Power up the board and the new updated U-Boot should boot from eMMC. - -Building U-Boot to boot with NXP 4.1 kernel: +Flash u-boot.img into the eMMC: -The NXP 4.1 kernel boots only in secure boot mode on mx7. +$ sudo dfu-util -D u-boot.img -a u-boot -Follow the next steps to enable secure boot: +Remove power from the pico board. -$ make mrproper -$ make pico-imx7d_defconfig -$ make menuconfig - -> ARM architecture - -> [*] Enable support for booting in non-secure mode - -> [*] Boot in secure mode by default - -> Exit -$ make +Put pico board into normal boot mode. -Flash u-boot.imx using the imx_usb_loader tool. +Power up the board and the new updated U-Boot should boot from eMMC. diff --git a/board/technexion/pico-imx7d/imximage.cfg b/board/technexion/pico-imx7d/imximage.cfg deleted file mode 100644 index c5caff46b4..0000000000 --- a/board/technexion/pico-imx7d/imximage.cfg +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Freescale Semiconductor, Inc. - * - * Refer docs/README.imxmage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -#define __ASSEMBLY__ -#include <config.h> - -/* image version */ - -IMAGE_VERSION 2 - -BOOT_FROM sd - -/* Secure boot support */ -#ifdef CONFIG_SECURE_BOOT -CSF CONFIG_CSF_SIZE -#endif - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -DATA 4 0x30340004 0x4F400005 -/* Clear then set bit30 to ensure exit from DDR retention */ -DATA 4 0x30360388 0x40000000 -DATA 4 0x30360384 0x40000000 - -DATA 4 0x30391000 0x00000002 -DATA 4 0x307a0000 0x01040001 -DATA 4 0x307a01a0 0x80400003 -DATA 4 0x307a01a4 0x00100020 -DATA 4 0x307a01a8 0x80100004 -DATA 4 0x307a0064 0x00400046 -DATA 4 0x307a0490 0x00000001 -DATA 4 0x307a00d0 0x00020083 -DATA 4 0x307a00d4 0x00690000 -DATA 4 0x307a00dc 0x09300004 -DATA 4 0x307a00e0 0x04080000 -DATA 4 0x307a00e4 0x00100004 -DATA 4 0x307a00f4 0x0000033f -DATA 4 0x307a0100 0x09081109 -DATA 4 0x307a0104 0x0007020d -DATA 4 0x307a0108 0x03040407 -DATA 4 0x307a010c 0x00002006 -DATA 4 0x307a0110 0x04020205 -DATA 4 0x307a0114 0x03030202 -DATA 4 0x307a0120 0x00000803 -DATA 4 0x307a0180 0x00800020 -DATA 4 0x307a0184 0x02000100 -DATA 4 0x307a0190 0x02098204 -DATA 4 0x307a0194 0x00030303 -DATA 4 0x307a0200 0x00000016 -DATA 4 0x307a0204 0x00080808 -DATA 4 0x307a0210 0x00000f0f -DATA 4 0x307a0214 0x07070707 -DATA 4 0x307a0218 0x0f070707 -DATA 4 0x307a0240 0x06000604 -DATA 4 0x307a0244 0x00000001 -DATA 4 0x30391000 0x00000000 -DATA 4 0x30790000 0x17420f40 -DATA 4 0x30790004 0x10210100 -DATA 4 0x30790010 0x00060807 -DATA 4 0x307900b0 0x1010007e -DATA 4 0x3079009c 0x00000b24 -DATA 4 0x30790020 0x08080808 -DATA 4 0x30790030 0x08080808 -DATA 4 0x30790050 0x01000010 -DATA 4 0x30790050 0x00000010 - -DATA 4 0x307900c0 0x0e407304 -DATA 4 0x307900c0 0x0e447304 -DATA 4 0x307900c0 0x0e447306 - -CHECK_BITS_SET 4 0x307900c4 0x1 - -DATA 4 0x307900c0 0x0e407304 - -DATA 4 0x30384130 0x00000000 -DATA 4 0x30340020 0x00000178 -DATA 4 0x30384130 0x00000002 -DATA 4 0x30790018 0x0000000f - -CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 44c81ecdb3..0767d0462f 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -58,7 +58,7 @@ static struct i2c_pads_info i2c_pad_info4 = { int dram_init(void) { - gd->ram_size = PHYS_SDRAM_SIZE; + gd->ram_size = imx_ddr_size(); return 0; } diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c new file mode 100644 index 0000000000..8c3443875d --- /dev/null +++ b/board/technexion/pico-imx7d/spl.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Technexion Ltd. + * + * Author: Richard Hu <richard.hu@technexion.com> + */ + +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-mx7/mx7-ddr.h> +#include <asm/gpio.h> +#include <spl.h> + +#if defined(CONFIG_SPL_BUILD) + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 0; +} +#endif + +static struct ddrc ddrc_regs_val = { + .mstr = 0x01040001, + .rfshtmg = 0x00400046, + .init1 = 0x00690000, + .init0 = 0x00020083, + .init3 = 0x09300004, + .init4 = 0x04080000, + .init5 = 0x00100004, + .rankctl = 0x0000033F, + .dramtmg0 = 0x09081109, + .dramtmg1 = 0x0007020d, + .dramtmg2 = 0x03040407, + .dramtmg3 = 0x00002006, + .dramtmg4 = 0x04020205, + .dramtmg5 = 0x03030202, + .dramtmg8 = 0x00000803, + .zqctl0 = 0x00800020, + .dfitmg0 = 0x02098204, + .dfitmg1 = 0x00030303, + .dfiupd0 = 0x80400003, + .dfiupd1 = 0x00100020, + .dfiupd2 = 0x80100004, + .addrmap4 = 0x00000F0F, + .odtcfg = 0x06000604, + .odtmap = 0x00000001, + .rfshtmg = 0x00400046, + .dramtmg0 = 0x09081109, + .addrmap0 = 0x0000001f, + .addrmap1 = 0x00080808, + .addrmap4 = 0x00000f0f, + .addrmap5 = 0x07070707, + .addrmap6 = 0x0f0f0707, +}; + +static struct ddrc_mp ddrc_mp_val = { + .pctrl_0 = 0x00000001, +}; + +static struct ddr_phy ddr_phy_regs_val = { + .phy_con0 = 0x17420f40, + .phy_con1 = 0x10210100, + .phy_con4 = 0x00060807, + .mdll_con0 = 0x1010007e, + .drvds_con0 = 0x00000d6e, + .cmd_sdll_con0 = 0x00000010, + .offset_lp_con0 = 0x0000000f, + .offset_rd_con0 = 0x08080808, + .offset_wr_con0 = 0x08080808, +}; + +static struct mx7_calibration calib_param = { + .num_val = 5, + .values = { + 0x0E407304, + 0x0E447304, + 0x0E447306, + 0x0E447304, + 0x0E447304, + }, +}; + +static void gpr_init(void) +{ + struct iomuxc_gpr_base_regs *gpr_regs = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + writel(0x4F400005, &gpr_regs->gpr[1]); +} + +static bool is_1g(void) +{ + gpio_direction_input(IMX_GPIO_NR(1, 12)); + return !gpio_get_value(IMX_GPIO_NR(1, 12)); +} + +static void ddr_init(void) +{ + if (is_1g()) + ddrc_regs_val.addrmap6 = 0x0f070707; + + mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, + &calib_param); +} + +void board_init_f(ulong dummy) +{ + arch_cpu_init(); + gpr_init(); + board_early_init_f(); + timer_init(); + preloader_console_init(); + ddr_init(); + memset(__bss_start, 0, __bss_end - __bss_start); + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} +#endif diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 6af94111d6..573e691457 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -196,11 +196,85 @@ static void setup_iodomain(void) rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT); } +/* + * Swap mmc0 and mmc1 in boot_targets if booted from SD-Card. + * + * If bootsource is uSD-card we can assume that we want to use the + * SD-Card instead of the eMMC as first boot_target for distroboot. + * We only want to swap the defaults and not any custom environment a + * user has set. We exit early if a changed boot_targets environment + * is detected. + */ +static int setup_boottargets(void) +{ + const char *boot_device = + ofnode_get_chosen_prop("u-boot,spl-boot-device"); + char *env_default, *env; + + if (!boot_device) { + debug("%s: /chosen/u-boot,spl-boot-device not set\n", + __func__); + return -1; + } + debug("%s: booted from %s\n", __func__, boot_device); + + env_default = env_get_default("boot_targets"); + env = env_get("boot_targets"); + if (!env) { + debug("%s: boot_targets does not exist\n", __func__); + return -1; + } + debug("%s: boot_targets current: %s - default: %s\n", + __func__, env, env_default); + + if (strcmp(env_default, env) != 0) { + debug("%s: boot_targets not default, don't change it\n", + __func__); + return 0; + } + + /* + * Only run, if booting from mmc1 (i.e. /dwmmc@fe320000) and + * only consider cases where the default boot-order first + * tries to boot from mmc0 (eMMC) and then from mmc1 + * (i.e. external SD). + * + * In other words: the SD card will be moved to earlier in the + * order, if U-Boot was also loaded from the SD-card. + */ + if (!strcmp(boot_device, "/dwmmc@fe320000")) { + char *mmc0, *mmc1; + + debug("%s: booted from SD-Card\n", __func__); + mmc0 = strstr(env, "mmc0"); + mmc1 = strstr(env, "mmc1"); + + if (!mmc0 || !mmc1) { + debug("%s: only one mmc boot_target found\n", __func__); + return -1; + } + + /* + * If mmc0 comes first in the boot order, we need to change + * the strings to make mmc1 first. + */ + if (mmc0 < mmc1) { + mmc0[3] = '1'; + mmc1[3] = '0'; + debug("%s: set boot_targets to: %s\n", __func__, env); + env_set("boot_targets", env); + } + } + + return 0; +} + int misc_init_r(void) { setup_serial(); setup_macaddr(); setup_iodomain(); + setup_boottargets(); return 0; } diff --git a/board/toradex/colibri-imx6ull/Kconfig b/board/toradex/colibri-imx6ull/Kconfig new file mode 100644 index 0000000000..3ce9885c12 --- /dev/null +++ b/board/toradex/colibri-imx6ull/Kconfig @@ -0,0 +1,29 @@ +if TARGET_COLIBRI_IMX6ULL + +config SYS_BOARD + default "colibri-imx6ull" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "colibri-imx6ull" + +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_NAND + default y + +config TDX_CFG_BLOCK_OFFSET + default "2048" + +config TDX_CFG_BLOCK_OFFSET2 + default "133120" + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS new file mode 100644 index 0000000000..7cda555984 --- /dev/null +++ b/board/toradex/colibri-imx6ull/MAINTAINERS @@ -0,0 +1,10 @@ +Colibri iMX6ULL +M: Stefan Agner <stefan.agner@toradex.com> +M: Toradex ARM Support <support.arm@toradex.com> +W: http://developer.toradex.com/software/linux/linux-software +W: https://www.toradex.com/community +S: Maintained +F: arch/arm/dts/imx6ull-colibri.dts +F: board/toradex/colibri-imx6ull/ +F: configs/colibri-imx6ull_defconfig +F: include/configs/colibri-imx6ull.h diff --git a/board/toradex/colibri-imx6ull/Makefile b/board/toradex/colibri-imx6ull/Makefile new file mode 100644 index 0000000000..f478e68049 --- /dev/null +++ b/board/toradex/colibri-imx6ull/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2018 Toradex AG + +obj-y := colibri-imx6ull.o diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c new file mode 100644 index 0000000000..fcb49a0718 --- /dev/null +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Toradex AG + */ +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch-mx6/clock.h> +#include <asm/arch-mx6/imx-regs.h> +#include <asm/arch-mx6/mx6ull_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/io.h> +#include <common.h> +#include <dm.h> +#include <dm/platform_data/serial_mxc.h> +#include <fdt_support.h> +#include <fsl_esdhc.h> +#include <imx_thermal.h> +#include <jffs2/load_kernel.h> +#include <linux/sizes.h> +#include <mmc.h> +#include <miiphy.h> +#include <mtd_node.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h> +#include "../common/tdx-common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_40ohm) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_DSE_48ohm) + +#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP) + +#define USB_CDET_GPIO IMX_GPIO_NR(7, 14) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RTS_B__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_CTS_B__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_ESDHC +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +static iomux_v3_cfg_t const usb_cdet_pads[] = { + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const backlight_pads[] = { + /* Backlight On */ + MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Backlight PWM<A> (multiplexed pin) */ + MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define GPIO_BL_ON IMX_GPIO_NR(1, 11) +#define GPIO_PWM_A IMX_GPIO_NR(4, 11) + +static int setup_lcd(void) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); + + /* Set BL_ON */ + gpio_request(GPIO_BL_ON, "BL_ON"); + gpio_direction_output(GPIO_BL_ON, 1); + + /* Set PWM<A> to full brightness (assuming inversed polarity) */ + gpio_request(GPIO_PWM_A, "PWM<A>"); + gpio_direction_output(GPIO_PWM_A, 0); + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* USDHC1 is mmc0 */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC + +static int setup_fec(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + setup_iomux_fec(); + + /* provide the PHY clock from the i.MX 6 */ + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + + /* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */ + clrsetbits_le32(&iomuxc_regs->gpr[1], + IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_VIDEO_MXS + setup_lcd(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 + imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); + gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +/* TODO */ +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)}, + {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ + int minc, maxc; + + if (get_cpu_temp_grade(&minc, &maxc) != TEMP_COMMERCIAL) + env_set("variant", "-wifi"); + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_CMD_USB_SDP + if (is_boot_from_usb()) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootdelay", "0"); + env_set("bootcmd", "sdp 0"); + } +#endif /* CONFIG_CMD_USB_SDP */ + + return 0; +} + +int checkboard(void) +{ + printf("Model: Toradex Colibri iMX6ULL\n"); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_FDT_FIXUP_PARTITIONS) + static struct node_info nodes[] = { + { "fsl,imx6ull-gpmi-nand", MTD_DEV_TYPE_NAND, }, + { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, + }; + + /* Update partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif + + return ft_common_board_setup(blob, bd); +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +static iomux_v3_cfg_t const usb_otg2_pads[] = { + MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, + ARRAY_SIZE(usb_otg2_pads)); + break; + default: + return -EINVAL; + } + return 0; +} + +int board_usb_phy_mode(int port) +{ + switch (port) { + case 0: + if (gpio_get_value(USB_CDET_GPIO)) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; + case 1: + default: + return USB_INIT_HOST; + } +} +#endif + +static struct mxc_serial_platdata mxc_serial_plat = { + .reg = (struct mxc_uart *)UART1_BASE, + .use_dte = 1, +}; + +U_BOOT_DEVICE(mxc_serial) = { + .name = "serial_mxc", + .platdata = &mxc_serial_plat, +}; diff --git a/board/toradex/colibri-imx6ull/imximage.cfg b/board/toradex/colibri-imx6ull/imximage.cfg new file mode 100644 index 0000000000..2ce55a610a --- /dev/null +++ b/board/toradex/colibri-imx6ull/imximage.cfg @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2018 Toradex AG + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : nand + */ + +BOOT_FROM nand + +/* + * Secure boot support + */ +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x000C0030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000004 +DATA 4 0x021B083C 0x41640158 +DATA 4 0x021B0848 0x40403237 +DATA 4 0x021B0850 0x40403C33 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00944009 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 + diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index cd98ec8216..2210095d7a 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -9,7 +9,6 @@ #include <asm/arch/mx7-pins.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/io.h> #include <common.h> @@ -322,24 +321,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)}, - {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - - return 0; -} - #ifdef CONFIG_DM_PMIC int power_init_board(void) { @@ -408,8 +389,9 @@ int checkboard(void) int ft_board_setup(void *blob, bd_t *bd) { #if defined(CONFIG_FDT_FIXUP_PARTITIONS) - static struct node_info nodes[] = { + static const struct node_info nodes[] = { { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ + { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, }; /* Update partition nodes using info from mtdparts env var */ diff --git a/board/toradex/colibri_imx7/imximage.cfg b/board/toradex/colibri_imx7/imximage.cfg index 1d66884df4..25cfd5c6f8 100644 --- a/board/toradex/colibri_imx7/imximage.cfg +++ b/board/toradex/colibri_imx7/imximage.cfg @@ -57,7 +57,7 @@ DATA 4 0x307a01a4 0x00100020 /* DDRC_DFIUPD2 */ DATA 4 0x307a01a8 0x80100004 /* DDRC_RFSHTMG */ -DATA 4 0x307a0064 0x00400045 +DATA 4 0x307a0064 0x00400046 /* DDRC_MP_PCTRL_0 */ DATA 4 0x307a0490 0x00000001 /* DDRC_INIT0 */ @@ -73,15 +73,15 @@ DATA 4 0x307a00e4 0x00100004 /* DDRC_RANKCTL */ DATA 4 0x307a00f4 0x0000033f /* DDRC_DRAMTMG0 */ -DATA 4 0x307a0100 0x090b090a +DATA 4 0x307a0100 0x0910090a /* DDRC_DRAMTMG1 */ -DATA 4 0x307a0104 0x000d020d +DATA 4 0x307a0104 0x000d020e /* DDRC_DRAMTMG2 */ DATA 4 0x307a0108 0x03040307 /* DDRC_DRAMTMG3 */ DATA 4 0x307a010c 0x00002006 /* DDRC_DRAMTMG4 */ -DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0110 0x04020204 /* DDRC_DRAMTMG5 */ DATA 4 0x307a0114 0x03030202 /* DDRC_DRAMTMG8 */ @@ -105,7 +105,7 @@ DATA 4 0x307a0218 0x07070707 /* DDRC_ODTCFG */ DATA 4 0x307a0240 0x06000601 /* DDRC_ODTMAP */ -DATA 4 0x307a0244 0x00000011 +DATA 4 0x307a0244 0x00000001 /* SRC_DDRC_RCR */ DATA 4 0x30391000 0x00000000 /* DDR_PHY_PHY_CON0 */ diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 83c3503007..4db1757469 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -580,7 +580,7 @@ int ft_board_setup(void *blob, bd_t *bd) { int ret = 0; #ifdef CONFIG_FDT_FIXUP_PARTITIONS - static struct node_info nodes[] = { + static const struct node_info nodes[] = { { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */ }; diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index f6231ff2f9..57edb6c5c9 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -91,6 +91,13 @@ const char * const toradex_modules[] = { [33] = "Colibri iMX7 Dual 512MB", [34] = "Apalis TK1 2GB", [35] = "Apalis iMX6 Dual 1GB IT", + [36] = "Colibri iMX6ULL 256MB", + [37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / Bluetooth", + [38] = "Colibri iMX8X", + [39] = "Colibri iMX7 Dual 1GB (eMMC)", + [40] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth IT", + [41] = "Colibri iMX7 Dual 512MB EPDC", + [42] = "Apalis TK1 4GB", }; #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 29b933c307..da60e789a7 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -54,6 +54,13 @@ enum { COLIBRI_IMX7D, APALIS_TK1_2GB, APALIS_IMX6D_IT, + COLIBRI_IMX6ULL, + APALIS_IMX8QM, /* 37 */ + COLIBRI_IMX8X, + COLIBRI_IMX7D_EMMC, + COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */ + COLIBRI_IMX7D_EPDC, + APALIS_TK1_4GB, }; extern const char * const toradex_modules[]; |