diff options
Diffstat (limited to 'board')
24 files changed, 857 insertions, 66 deletions
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index c7f6479a0c..c21d2f3ffa 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -379,7 +379,7 @@ int board_init(void) puts("Cannot find Armada 385 watchdog!\n"); } else { puts("Enabling Armada 385 watchdog.\n"); - wdt_start(watchdog_dev, (u32) 25000000 * 120, 0); + wdt_start(watchdog_dev, 120000, 0); } # endif diff --git a/board/Marvell/db-xc3-24g4xg/.gitignore b/board/Marvell/db-xc3-24g4xg/.gitignore new file mode 100644 index 0000000000..775b9346b8 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/.gitignore @@ -0,0 +1 @@ +kwbimage.cfg diff --git a/board/Marvell/db-xc3-24g4xg/MAINTAINERS b/board/Marvell/db-xc3-24g4xg/MAINTAINERS new file mode 100644 index 0000000000..2b27e48181 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/MAINTAINERS @@ -0,0 +1,7 @@ +DB-XC3-24G4XG BOARD +M: Chris Packham <chris.packham@alliedtelesis.co.nz> +S: Maintained +F: board/Marvell/db-xc3-24g4xg/ +F: include/configs/db-xc3-24g4xg.h +F: configs/db-xc3-24g4xg_defconfig +F: arch/arm/dts/armada-xp-db-xc3-24g4xg.dts diff --git a/board/Marvell/db-xc3-24g4xg/Makefile b/board/Marvell/db-xc3-24g4xg/Makefile new file mode 100644 index 0000000000..4dd57902d4 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> + +obj-y := db-xc3-24g4xg.o +extra-y := kwbimage.cfg + +quiet_cmd_sed = SED $@ + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F) + +SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|" +$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ + include/config/auto.conf + $(call if_changed,sed) diff --git a/board/Marvell/db-xc3-24g4xg/README b/board/Marvell/db-xc3-24g4xg/README new file mode 100644 index 0000000000..5e479b433e --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/README @@ -0,0 +1,4 @@ +To generate binary.0 from Marvell's bin_hdr.elf use the following command + + arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \ + board/Marvell/db-xc3-24g4xg/binary.0 diff --git a/board/Marvell/db-xc3-24g4xg/binary.0 b/board/Marvell/db-xc3-24g4xg/binary.0 new file mode 100644 index 0000000000..8dd687286a --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/binary.0 @@ -0,0 +1,11 @@ +-------- +WARNING: +-------- +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. diff --git a/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c new file mode 100644 index 0000000000..cae428ffd0 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + */ + +#include <common.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * These values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-2016_T1.0.eng_drop_v6" + */ +#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \ + | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30))) +#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0)) +#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \ + | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30)) +#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0 +#define DB_DX_AC3_GPP_POL_LOW 0x0 +#define DB_DX_AC3_GPP_POL_MID 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00142222, MVEBU_MPP_BASE + 0x00); + writel(0x11122000, MVEBU_MPP_BASE + 0x04); + writel(0x44444004, MVEBU_MPP_BASE + 0x08); + writel(0x14444444, MVEBU_MPP_BASE + 0x0c); + writel(0x00000001, MVEBU_MPP_BASE + 0x10); + + /* Set GPP Out value */ + writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + puts("Board: " CONFIG_SYS_BOARD "\n"); + + return 0; +} +#endif diff --git a/board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in new file mode 100644 index 0000000000..b8bb7a6eb7 --- /dev/null +++ b/board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068 diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c index eb3694ea6e..d23e97c9b9 100644 --- a/board/Synology/ds414/ds414.c +++ b/board/Synology/ds414/ds414.c @@ -115,14 +115,14 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) return &ds414_ddr_modes[0]; } -MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) { return &ds414_serdes_cfg[0]; } u8 board_sat_r_get(u8 dev_num, u8 reg) { - return (0x1 << 1 | 1); + return 0xf; /* All PEX ports support PCIe Gen2 */ } int board_early_init_f(void) diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index d7d1942fe6..6934fd8017 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -7,6 +7,7 @@ #include <command.h> #include <dm.h> #include <i2c.h> +#include <wdt.h> #include <asm/gpio.h> #include <linux/mbus.h> #include <linux/io.h> @@ -24,6 +25,10 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_NVS_LOCATION 0xf4800000 #define CONFIG_NVS_SIZE (512 << 10) +#ifdef CONFIG_WATCHDOG +static struct udevice *watchdog_dev; +#endif + static struct serdes_map board_serdes_map[] = { {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, @@ -75,6 +80,10 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) int board_early_init_f(void) { +#ifdef CONFIG_WATCHDOG + watchdog_dev = NULL; +#endif + /* Configure MPP */ writel(0x00001111, MVEBU_MPP_BASE + 0x00); writel(0x00000000, MVEBU_MPP_BASE + 0x04); @@ -88,6 +97,17 @@ int board_early_init_f(void) return 0; } +void spl_board_init(void) +{ +#ifdef CONFIG_WATCHDOG + int ret; + + ret = uclass_get_device(UCLASS_WDT, 0, &watchdog_dev); + if (!ret) + wdt_start(watchdog_dev, 120000, 0); +#endif +} + int board_init(void) { /* address of boot parameters */ @@ -100,9 +120,37 @@ int board_init(void) /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */ writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8); + spl_board_init(); + return 0; } +void arch_preboot_os(void) +{ +#ifdef CONFIG_WATCHDOG + wdt_stop(watchdog_dev); +#endif +} + +#ifdef CONFIG_WATCHDOG +void watchdog_reset(void) +{ + static ulong next_reset = 0; + ulong now; + + if (!watchdog_dev) + return; + + now = timer_get_us(); + + /* Do not reset the watchdog too often */ + if (now > next_reset) { + wdt_reset(watchdog_dev); + next_reset = now + 1000; + } +} +#endif + static int led_7seg_init(unsigned int segments) { int node; diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c index e8f8f7ba5b..395904f8c8 100644 --- a/board/maxbcm/maxbcm.c +++ b/board/maxbcm/maxbcm.c @@ -95,7 +95,7 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) return &maxbcm_ddr_modes[0]; } -MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) { return &maxbcm_serdes_cfg[0]; } diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c index 58a4a04162..6e5ef4c97f 100644 --- a/board/mscc/jr2/jr2.c +++ b/board/mscc/jr2/jr2.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/io.h> #include <led.h> +#include <miiphy.h> enum { BOARD_TYPE_PCB110 = 0xAABBCE00, @@ -64,6 +65,28 @@ static void vcoreiii_gpio_set_alternate(int gpio, int mode) } } +int board_phy_config(struct phy_device *phydev) +{ + if (gd->board_type == BOARD_TYPE_PCB110 || + gd->board_type == BOARD_TYPE_PCB112) { + phy_write(phydev, 0, 31, 0x10); + phy_write(phydev, 0, 18, 0x80F0); + while (phy_read(phydev, 0, 18) & 0x8000) + ; + phy_write(phydev, 0, 31, 0); + } + if (gd->board_type == BOARD_TYPE_PCB111) { + phy_write(phydev, 0, 31, 0x10); + phy_write(phydev, 0, 18, 0x80A0); + while (phy_read(phydev, 0, 18) & 0x8000) + ; + phy_write(phydev, 0, 14, 0x800); + phy_write(phydev, 0, 31, 0); + } + + return 0; +} + void board_debug_uart_init(void) { /* too early for the pinctrl driver, so configure the UART pins here */ diff --git a/board/qca/ap152/Kconfig b/board/qca/ap152/Kconfig new file mode 100644 index 0000000000..f6ad498e85 --- /dev/null +++ b/board/qca/ap152/Kconfig @@ -0,0 +1,15 @@ +if TARGET_AP152 + +config SYS_VENDOR + default "qca" + +config SYS_BOARD + default "ap152" + +config SYS_CONFIG_NAME + default "ap152" + +config SYS_TEXT_BASE + default 0x9f000000 + +endif diff --git a/board/qca/ap152/MAINTAINERS b/board/qca/ap152/MAINTAINERS new file mode 100644 index 0000000000..785ec2766d --- /dev/null +++ b/board/qca/ap152/MAINTAINERS @@ -0,0 +1,6 @@ +AP152 BOARD +M: Rosy Song <rosysong@rosinson.com> +S: Maintained +F: board/qca/ap152/ +F: include/configs/ap152.h +F: configs/ap152_defconfig diff --git a/board/qca/ap152/Makefile b/board/qca/ap152/Makefile new file mode 100644 index 0000000000..4270afa129 --- /dev/null +++ b/board/qca/ap152/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y = ap152.o diff --git a/board/qca/ap152/ap152.c b/board/qca/ap152/ap152.c new file mode 100644 index 0000000000..30cd56563b --- /dev/null +++ b/board/qca/ap152/ap152.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Rosy Song <rosysong@rosinson.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/ddr.h> +#include <mach/ath79.h> +#include <debug_uart.h> + +#define RST_RESET_RTC_RESET_LSB 27 +#define RST_RESET_RTC_RESET_MASK 0x08000000 +#define RST_RESET_RTC_RESET_SET(x) \ + (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK) + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* UART : RX18, TX22 done + * GPIO18 as input, GPIO22 as output + */ + val = readl(regs + AR71XX_GPIO_REG_OE); + val |= QCA956X_GPIO(18); + val &= ~QCA956X_GPIO(22); + writel(val, regs + AR71XX_GPIO_REG_OE); + + /* + * Enable GPIO22 as UART0_SOUT + */ + val = readl(regs + QCA956X_GPIO_REG_OUT_FUNC5); + val &= ~QCA956X_GPIO_MUX_MASK(16); + val |= QCA956X_GPIO_OUT_MUX_UART0_SOUT << 16; + writel(val, regs + QCA956X_GPIO_REG_OUT_FUNC5); + + /* + * Enable GPIO18 as UART0_SIN + */ + val = readl(regs + QCA956X_GPIO_REG_IN_ENABLE0); + val &= ~QCA956X_GPIO_MUX_MASK(8); + val |= QCA956X_GPIO_IN_MUX_UART0_SIN << 8; + writel(val, regs + QCA956X_GPIO_REG_IN_ENABLE0); + + /* + * Enable GPIO22 output + */ + val = readl(regs + AR71XX_GPIO_REG_OUT); + val |= QCA956X_GPIO(22); + writel(val, regs + AR71XX_GPIO_REG_OUT); +} +#endif + +int board_early_init_f(void) +{ + u32 reg; + void __iomem *rst_regs = map_physmem(AR71XX_RESET_BASE, + AR71XX_RESET_SIZE, MAP_NOCACHE); + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* CPU:775, DDR:650, AHB:258 */ + qca956x_pll_init(); + qca956x_ddr_init(); +#endif + + /* Take WMAC out of reset */ + reg = readl(rst_regs + QCA956X_RESET_REG_RESET_MODULE); + reg &= (~RST_RESET_RTC_RESET_SET(1)); + writel(reg, rst_regs + QCA956X_RESET_REG_RESET_MODULE); + + ath79_eth_reset(); + return 0; +} diff --git a/board/solidrun/clearfog/README b/board/solidrun/clearfog/README index a7bc0d4e23..0b0e98de90 100644 --- a/board/solidrun/clearfog/README +++ b/board/solidrun/clearfog/README @@ -17,6 +17,29 @@ $ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1 Please use the correct device node for your setup instead of "/dev/sdX" here! +Install U-Boot on eMMC: +----------------------- + +The ROM loads the bootloader from eMMC first boot partition at offset 0. This +is unlike load from SD card that is at offset 512. As a result, the offset of +the main U-Boot image on the eMMC boot partition changes. Set +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x140 for SPL to load U-Boot from +the correct location. + +To make SPL load the main U-Boot image from the eMMC boot partition enable +eMMC boot acknowledgement and boot partition with the following U-Boot +command: + + mmc partconf 0 1 1 0 + +Install U-Boot on eMMC boot partition from Linux running on Clearfog: + + echo 0 > /sys/block/mmcblk0boot0/force_ro + dd if=u-boot-spl.kwb of=/dev/mmcblk0boot0 + +Note that the SD card is not accessible when the Clearfog SOM has eMMC. +Consider initial boot from UART (see below). + Boot selection: --------------- diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS index 48d8fd2c3f..0a2eddbe03 100644 --- a/board/st/stm32mp1/MAINTAINERS +++ b/board/st/stm32mp1/MAINTAINERS @@ -2,7 +2,8 @@ STM32MP1 BOARD M: Patrick Delaunay <patrick.delaunay@st.com> L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) S: Maintained +F: arch/arm/dts/stm32mp157* F: board/st/stm32mp1 -F: include/configs/stm32mp1.h F: configs/stm32mp15_basic_defconfig -F: arch/arm/dts/stm32mp157* +F: configs/stm32mp15_trusted_defconfig +F: include/configs/stm32mp1.h diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README index 174e6db148..1cd3534ae4 100644 --- a/board/st/stm32mp1/README +++ b/board/st/stm32mp1/README @@ -28,14 +28,15 @@ Everything is supported in Linux but U-Boot is limited to: And the necessary drivers 1. I2C -2. STPMU1 -2. STPMU1 (PMIC and regulator) +2. STPMIC1 (PMIC and regulator) 3. Clock, Reset, Sysreset 4. Fuse Currently the following boards are supported: + stm32mp157c-ev1 + stm32mp157c-ed1 ++ stm32mp157a-dk1 ++ stm32mp157c-dk2 3. Boot Sequences ================= @@ -45,15 +46,22 @@ BootRom => FSBL in SYSRAM => SSBL in DDR => OS (Linux Kernel) with FSBL = First Stage Bootloader SSBL = Second Stage Bootloader -One boot configuration is supported: +2 boot configurations are supported: - The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig) +1) The "Trusted" boot chain (defconfig_file : stm32mp15_trusted_defconfig) + BootRom => FSBL = Trusted Firmware-A (TF-A) => SSBL = U-Boot + TF-A performs a full initialization of Secure peripherals and installs a + secure monitor. + U-Boot is running in normal world and uses TF-A monitor + to access to secure resources + +2) The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig) BootRom => FSBL = U-Boot SPL => SSBL = U-Boot SPL has limited security initialisation U-Boot is running in secure mode and provide a secure monitor to the kernel with only PSCI support (Power State Coordination Interface defined by ARM) -All the STM32MP1 board supported by U-Boot use the same generic board +All the STM32MP1 boards supported by U-Boot use the same generic board stm32mp1 which support all the bootable devices. Each board is configurated only with the associated device tree. @@ -64,12 +72,18 @@ Each board is configurated only with the associated device tree. You need to select the appropriate device tree for your board, the supported device trees for stm32mp157 are: -+ ev1: eval board with pmic stpmu1 (ev1 = mother board + daughter ed1) ++ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1) dts: stm32mp157c-ev1 -+ ed1: daughter board with pmic stpmu1 ++ ed1: daughter board with pmic stpmic1 dts: stm32mp157c-ed1 ++ dk1: Discovery board + dts: stm32mp157a-dk1 + ++ dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel + dts: stm32mp157c-dk2 + 5. Build Procedure ================== @@ -90,12 +104,14 @@ the supported device trees for stm32mp157 are: # export KBUILD_OUTPUT=/path/to/output for example: use one output directory for each configuration + # export KBUILD_OUTPUT=stm32mp15_trusted # export KBUILD_OUTPUT=stm32mp15_basic -4. Configure the U-Boot: +4. Configure U-Boot: # make <defconfig_file> + - For trusted boot mode : "stm32mp15_trusted_defconfig" - For basic boot mode: "stm32mp15_basic_defconfig" 5. Configure the device-tree and build the U-Boot image: @@ -104,16 +120,26 @@ the supported device trees for stm32mp157 are: example: - basic boot on ev1 + a) trusted boot on ev1 + # export KBUILD_OUTPUT=stm32mp15_trusted + # make stm32mp15_trusted_defconfig + # make DEVICE_TREE=stm32mp157c-ev1 all + + b) basic boot on ev1 # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig # make DEVICE_TREE=stm32mp157c-ev1 all - basic boot on ed1 + c) basic boot on ed1 # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig # make DEVICE_TREE=stm32mp157c-ed1 all + d) basic boot on dk2 + # export KBUILD_OUTPUT=stm32mp15_basic + # make stm32mp15_basic_defconfig + # make DEVICE_TREE=stm32mp157c-dk2 all + 6. Output files BootRom and TF-A expect binaries with STM32 image header @@ -122,6 +148,11 @@ the supported device trees for stm32mp157 are: So in the output directory (selected by KBUILD_OUTPUT), you can found the needed files: + a) For Trusted boot + + FSBL = tf-a.stm32 (provided by TF-A compilation) + + SSBL = u-boot.stm32 + + b) For Basic boot + FSBL = spl/u-boot-spl.stm32 + SSBL = u-boot.img @@ -135,13 +166,22 @@ You can select the boot mode, on the board ed1 with the switch SW1 ----------------------------------- Reserved 0 0 0 NOR 0 0 1 - SD-Card 1 1 1 SD-Card 1 0 1 eMMC 0 1 0 NAND 0 1 1 Recovery 1 1 0 Recovery 0 0 0 +- on board DK1/DK2 with the switch SW1 : BOOT0, BOOT2 + (BOOT1 forced to 0, NOR not supported) + + -------------------------- + Boot Mode BOOT2 BOOT0 + -------------------------- + Reserved 1 0 + SD-Card 1 1 + Recovery 0 0 + Recovery is a boot from serial link (UART/USB) and it is used with STM32CubeProgrammer tool to load executable in RAM and to update the flash devices available on the board (NOR/NAND/eMMC/SDCARD). @@ -158,14 +198,14 @@ The minimal requirements for STMP32MP1 boot up to U-Boot are: - one ssbl partition for U-Boot Then the minimal GPT partition is: - ----- ------- --------- ------------- - | Num | Name | Size | Content | - ----- ------- -------- -------------- + ----- ------- --------- -------------- + | Num | Name | Size | Content | + ----- ------- -------- --------------- | 1 | fsbl1 | 256 KiB | TF-A or SPL | | 2 | fsbl2 | 256 KiB | TF-A or SPL | - | 3 | ssbl | enought | U-Boot | - | * | - | - | Boot/Rootfs| - ----- ------- --------- ------------- + | 3 | ssbl | enought | U-Boot | + | * | - | - | Boot/Rootfs | + ----- ------- --------- -------------- (*) add bootable partition for extlinux.conf following Generic Distribution @@ -189,7 +229,7 @@ for example: with gpt table with 128 entries you can add other partitions for kernel one partition rootfs for example: - -n 3:5154: -c 4:rootfs + -n 4:5154: -c 4:rootfs \ c) copy the FSBL (2 times) and SSBL file on the correct partition. in this example in partition 1 to 3 @@ -199,6 +239,11 @@ for example: with gpt table with 128 entries # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2 # dd if=u-boot.img of=/dev/mmcblk0p3 + for trusted boot mode : + # dd if=tf-a.stm32 of=/dev/mmcblk0p1 + # dd if=tf-a.stm32 of=/dev/mmcblk0p2 + # dd if=u-boot.stm32 of=/dev/mmcblk0p3 + To boot from SDCard, select BootPinMode = 1 1 1 and reset. 8. Prepare eMMC @@ -208,7 +253,7 @@ You can use U-Boot to copy binary in eMMC. In the next example, you need to boot from SDCARD and the images (u-boot-spl.stm32, u-boot.img) are presents on SDCARD (mmc 0) in ext4 partition 4 (bootfs). -To boot from SDCard, select BootPinMode = 1 1 1 and reset. +To boot from SDCard, select BootPinMode = 1 0 1 and reset. Then you update the eMMC with the next U-Boot command : @@ -227,7 +272,7 @@ b) copy SPL on eMMC on firts boot partition # mmc write ${fileaddr} 0 200 # mmc partconf 1 1 1 0 -b) copy U-Boot in first GPT partition of eMMC +c) copy U-Boot in first GPT partition of eMMC # ext4load mmc 0:4 0xC0000000 u-boot.img # mmc dev 1 diff --git a/board/st/stm32mp1/board.c b/board/st/stm32mp1/board.c index 5f31ea99f5..5c1acca20d 100644 --- a/board/st/stm32mp1/board.c +++ b/board/st/stm32mp1/board.c @@ -8,7 +8,7 @@ #include <asm/io.h> #include <asm/arch/ddr.h> #include <power/pmic.h> -#include <power/stpmu1.h> +#include <power/stpmic1.h> #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) @@ -37,64 +37,65 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_PMIC_STPMU1 +#ifdef CONFIG_PMIC_STPMIC1 int board_ddr_power_init(void) { struct udevice *dev; int ret; ret = uclass_get_device_by_driver(UCLASS_PMIC, - DM_GET_DRIVER(pmic_stpmu1), &dev); + DM_GET_DRIVER(pmic_stpmic1), &dev); if (ret) /* No PMIC on board */ return 0; - /* Set LDO3 to sync mode */ - ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3)); + /* VTT = Set LDO3 to sync mode */ + ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); if (ret < 0) return ret; - ret &= ~STPMU1_LDO3_MODE; - ret &= ~STPMU1_LDO12356_OUTPUT_MASK; - ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT; + ret &= ~STPMIC1_LDO3_MODE; + ret &= ~STPMIC1_LDO12356_VOUT_MASK; + ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); - ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3), + ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), ret); if (ret < 0) return ret; - /* Set BUCK2 to 1.35V */ + /* VDD_DDR = Set BUCK2 to 1.35V */ ret = pmic_clrsetbits(dev, - STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2), - STPMU1_BUCK_OUTPUT_MASK, - STPMU1_BUCK2_1350000V); + STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2), + STPMIC1_BUCK_VOUT_MASK, + STPMIC1_BUCK2_1350000V); if (ret < 0) return ret; - /* Enable BUCK2 and VREF */ + /* Enable VDD_DDR = BUCK2 */ ret = pmic_clrsetbits(dev, - STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2), - STPMU1_BUCK_EN, STPMU1_BUCK_EN); + STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2), + STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA); if (ret < 0) return ret; - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); - ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG, - STPMU1_VREF_EN, STPMU1_VREF_EN); + /* Enable VREF */ + ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR, + STPMIC1_VREF_ENA, STPMIC1_VREF_ENA); if (ret < 0) return ret; - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); /* Enable LDO3 */ ret = pmic_clrsetbits(dev, - STPMU1_LDOX_CTRL_REG(STPMU1_LDO3), - STPMU1_LDO_EN, STPMU1_LDO_EN); + STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); if (ret < 0) return ret; - mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); + mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); return 0; } diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index f3db0d6385..a7844f244b 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -11,22 +11,22 @@ #include <asm/io.h> #include <post.h> #include <power/pmic.h> -#include <power/stpmu1.h> +#include <power/stpmic1.h> #include <asm/arch/ddr.h> void spl_board_init(void) { /* Keep vdd on during the reset cycle */ -#if defined(CONFIG_PMIC_STPMU1) && defined(CONFIG_SPL_POWER_SUPPORT) +#if defined(CONFIG_PMIC_STPMIC1) && defined(CONFIG_SPL_POWER_SUPPORT) struct udevice *dev; int ret; ret = uclass_get_device_by_driver(UCLASS_PMIC, - DM_GET_DRIVER(pmic_stpmu1), &dev); + DM_GET_DRIVER(pmic_stpmic1), &dev); if (!ret) pmic_clrsetbits(dev, - STPMU1_MASK_RESET_BUCK, - STPMU1_MASK_RESET_BUCK3, - STPMU1_MASK_RESET_BUCK3); + STPMIC1_BUCKS_MRST_CR, + STPMIC1_MRST_BUCK(STPMIC1_BUCK3), + STPMIC1_MRST_BUCK(STPMIC1_BUCK3)); #endif } diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 54feca0ecf..24d299ac33 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -2,20 +2,57 @@ /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved */ -#include <config.h> #include <common.h> -#include <led.h> +#include <adc.h> +#include <config.h> #include <clk.h> #include <dm.h> #include <generic-phy.h> +#include <led.h> +#include <misc.h> #include <phy.h> #include <reset.h> +#include <syscon.h> #include <usb.h> -#include <asm/arch/stm32.h> #include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/stm32.h> #include <power/regulator.h> #include <usb/dwc2_udc.h> +/* SYSCFG registers */ +#define SYSCFG_BOOTR 0x00 +#define SYSCFG_PMCSETR 0x04 +#define SYSCFG_IOCTRLSETR 0x18 +#define SYSCFG_ICNR 0x1C +#define SYSCFG_CMPCR 0x20 +#define SYSCFG_CMPENSETR 0x24 +#define SYSCFG_PMCCLRR 0x44 + +#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) +#define SYSCFG_BOOTR_BOOTPD_SHIFT 4 + +#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0) +#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1) +#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2) +#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3) +#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4) + +#define SYSCFG_CMPCR_SW_CTRL BIT(1) +#define SYSCFG_CMPCR_READY BIT(8) + +#define SYSCFG_CMPENSETR_MPU_EN BIT(0) + +#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16) +#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17) + +#define SYSCFG_PMCSETR_ETH_SELMII BIT(20) + +#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21) +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII (0 << 21) +#define SYSCFG_PMCSETR_ETH_SEL_RGMII (1 << 21) +#define SYSCFG_PMCSETR_ETH_SEL_RMII (4 << 21) + /* * Get a global data pointer */ @@ -26,6 +63,98 @@ DECLARE_GLOBAL_DATA_PTR; #define STM32MP_GGPIO 0x38 #define STM32MP_GGPIO_VBUS_SENSING BIT(21) +#define USB_WARNING_LOW_THRESHOLD_UV 660000 +#define USB_START_LOW_THRESHOLD_UV 1230000 +#define USB_START_HIGH_THRESHOLD_UV 2100000 + +int checkboard(void) +{ + int ret; + char *mode; + u32 otp; + struct udevice *dev; + const char *fdt_compat; + int fdt_compat_len; + + if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED)) + mode = "trusted"; + else + mode = "basic"; + + printf("Board: stm32mp1 in %s mode", mode); + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) + printf(" (%s)", fdt_compat); + puts("\n"); + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + + if (!ret) + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), + &otp, sizeof(otp)); + if (!ret && otp) { + printf("Board: MB%04x Var%d Rev.%c-%02d\n", + otp >> 16, + (otp >> 12) & 0xF, + ((otp >> 8) & 0xF) - 1 + 'A', + otp & 0xF); + } + + return 0; +} + +static void board_key_check(void) +{ +#if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG) + ofnode node; + struct gpio_desc gpio; + enum forced_boot_mode boot_mode = BOOT_NORMAL; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return; + } +#ifdef CONFIG_FASTBOOT + if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0, + &gpio, GPIOD_IS_IN)) { + debug("%s: could not find a /config/st,fastboot-gpios\n", + __func__); + } else { + if (dm_gpio_get_value(&gpio)) { + puts("Fastboot key pressed, "); + boot_mode = BOOT_FASTBOOT; + } + + dm_gpio_free(NULL, &gpio); + } +#endif +#ifdef CONFIG_CMD_STM32PROG + if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0, + &gpio, GPIOD_IS_IN)) { + debug("%s: could not find a /config/st,stm32prog-gpios\n", + __func__); + } else { + if (dm_gpio_get_value(&gpio)) { + puts("STM32Programmer key pressed, "); + boot_mode = BOOT_STM32PROG; + } + dm_gpio_free(NULL, &gpio); + } +#endif + + if (boot_mode != BOOT_NORMAL) { + puts("entering download mode...\n"); + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_FORCED_MASK, + boot_mode); + } +#endif +} + static struct dwc2_plat_otg_data stm32mp_otg_data = { .usb_gusbcfg = STM32MP_GUSBCFG, }; @@ -170,6 +299,145 @@ clk_err: return ret; } +static int get_led(struct udevice **dev, char *led_string) +{ + char *led_name; + int ret; + + led_name = fdtdec_get_config_string(gd->fdt_blob, led_string); + if (!led_name) { + pr_debug("%s: could not find %s config string\n", + __func__, led_string); + return -ENOENT; + } + ret = led_get_by_label(led_name, dev); + if (ret) { + debug("%s: get=%d\n", __func__, ret); + return ret; + } + + return 0; +} + +static int setup_led(enum led_state_t cmd) +{ + struct udevice *dev; + int ret; + + ret = get_led(&dev, "u-boot,boot-led"); + if (ret) + return ret; + + ret = led_set_state(dev, cmd); + return ret; +} + +static int board_check_usb_power(void) +{ + struct ofnode_phandle_args adc_args; + struct udevice *adc; + struct udevice *led; + ofnode node; + unsigned int raw; + int max_uV = 0; + int ret, uV, adc_count; + u8 i, nb_blink; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return -ENOENT; + } + + /* + * Retrieve the ADC channels devices and get measurement + * for each of them + */ + adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd", + "#io-channel-cells"); + if (adc_count < 0) { + if (adc_count == -ENOENT) + return 0; + + pr_err("%s: can't find adc channel (%d)\n", __func__, + adc_count); + + return adc_count; + } + + for (i = 0; i < adc_count; i++) { + if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd", + "#io-channel-cells", 0, i, + &adc_args)) { + pr_debug("%s: can't find /config/st,adc_usb_pd\n", + __func__); + return 0; + } + + ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node, + &adc); + + if (ret) { + pr_err("%s: Can't get adc device(%d)\n", __func__, + ret); + return ret; + } + + ret = adc_channel_single_shot(adc->name, adc_args.args[0], + &raw); + if (ret) { + pr_err("%s: single shot failed for %s[%d]!\n", + __func__, adc->name, adc_args.args[0]); + return ret; + } + /* Convert to uV */ + if (!adc_raw_to_uV(adc, raw, &uV)) { + if (uV > max_uV) + max_uV = uV; + pr_debug("%s: %s[%02d] = %u, %d uV\n", __func__, + adc->name, adc_args.args[0], raw, uV); + } else { + pr_err("%s: Can't get uV value for %s[%d]\n", + __func__, adc->name, adc_args.args[0]); + } + } + + /* + * If highest value is inside 1.23 Volts and 2.10 Volts, that means + * board is plugged on an USB-C 3A power supply and boot process can + * continue. + */ + if (max_uV > USB_START_LOW_THRESHOLD_UV && + max_uV < USB_START_HIGH_THRESHOLD_UV) + return 0; + + /* Display warning message and make u-boot,error-led blinking */ + pr_err("\n*******************************************\n"); + + if (max_uV < USB_WARNING_LOW_THRESHOLD_UV) { + pr_err("* WARNING 500mA power supply detected *\n"); + nb_blink = 2; + } else { + pr_err("* WARNING 1.5A power supply detected *\n"); + nb_blink = 3; + } + + pr_err("* Current too low, use a 3A power supply! *\n"); + pr_err("*******************************************\n\n"); + + ret = get_led(&led, "u-boot,error-led"); + if (ret) + return ret; + + for (i = 0; i < nb_blink * 2; i++) { + led_set_state(led, LEDST_TOGGLE); + mdelay(125); + } + led_set_state(led, LEDST_ON); + + return 0; +} + int board_usb_cleanup(int index, enum usb_init_type init) { /* Reset usbotg */ @@ -180,19 +448,146 @@ int board_usb_cleanup(int index, enum usb_init_type init) return 0; } -int board_late_init(void) +static void sysconf_init(void) { - return 0; +#ifndef CONFIG_STM32MP1_TRUSTED + u8 *syscfg; +#ifdef CONFIG_DM_REGULATOR + struct udevice *pwr_dev; + struct udevice *pwr_reg; + struct udevice *dev; + int ret; + u32 otp = 0; +#endif + u32 bootr; + + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + /* interconnect update : select master using the port 1 */ + /* LTDC = AXI_M9 */ + /* GPU = AXI_M8 */ + /* today information is hardcoded in U-Boot */ + writel(BIT(9), syscfg + SYSCFG_ICNR); + + /* disable Pull-Down for boot pin connected to VDD */ + bootr = readl(syscfg + SYSCFG_BOOTR); + bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT); + bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT; + writel(bootr, syscfg + SYSCFG_BOOTR); + +#ifdef CONFIG_DM_REGULATOR + /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI + * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection. + * The customer will have to disable this for low frequencies + * or if AFMUX is selected but the function not used, typically for + * TRACE. Otherwise, impact on power consumption. + * + * WARNING: + * enabling High Speed mode while VDD>2.7V + * with the OTP product_below_2v5 (OTP 18, BIT 13) + * erroneously set to 1 can damage the IC! + * => U-Boot set the register only if VDD < 2.7V (in DT) + * but this value need to be consistent with board design + */ + ret = syscon_get_by_driver_data(STM32MP_SYSCON_PWR, &pwr_dev); + if (!ret) { + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + if (ret) { + pr_err("Can't find stm32mp_bsec driver\n"); + return; + } + + ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4); + if (!ret) + otp = otp & BIT(13); + + /* get VDD = pwr-supply */ + ret = device_get_supply_regulator(pwr_dev, "pwr-supply", + &pwr_reg); + + /* check if VDD is Low Voltage */ + if (!ret) { + if (regulator_get_value(pwr_reg) < 2700000) { + writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE | + SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI | + SYSCFG_IOCTRLSETR_HSLVEN_ETH | + SYSCFG_IOCTRLSETR_HSLVEN_SDMMC | + SYSCFG_IOCTRLSETR_HSLVEN_SPI, + syscfg + SYSCFG_IOCTRLSETR); + + if (!otp) + pr_err("product_below_2v5=0: HSLVEN protected by HW\n"); + } else { + if (otp) + pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n"); + } + } else { + debug("VDD unknown"); + } + } +#endif + + /* activate automatic I/O compensation + * warning: need to ensure CSI enabled and ready in clock driver + */ + writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR); + + while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY)) + ; + clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); +#endif } /* board dependent setup after realloc */ int board_init(void) { + struct udevice *dev; + /* address of boot parameters */ gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; + /* probe all PINCTRL for hog */ + for (uclass_first_device(UCLASS_PINCTRL, &dev); + dev; + uclass_next_device(&dev)) { + pr_debug("probe pincontrol = %s\n", dev->name); + } + + board_key_check(); + + sysconf_init(); + if (IS_ENABLED(CONFIG_LED)) led_default_state(); return 0; } + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + const void *fdt_compat; + int fdt_compat_len; + + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) { + if (strncmp(fdt_compat, "st,", 3) != 0) + env_set("board_name", fdt_compat); + else + env_set("board_name", fdt_compat + 3); + } +#endif + + /* for DK1/DK2 boards */ + board_check_usb_power(); + + return 0; +} + +void board_quiesce_devices(void) +{ + setup_led(LEDST_OFF); +} diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 8e2f90fc68..338f374e56 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -341,6 +341,11 @@ M: FUKAUMI Naoki <naobsd@gmail.com> S: Maintained F: configs/Nintendo_NES_Classic_Edition_defconfig +OCEANIC 5205 5INMFD BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/oceanic_5205_5inmfd_defconfig + OLIMEX A20-SOM204 BOARD M: Stefan Mavrodiev <stefan@olimex.com> S: Maintained @@ -348,7 +353,7 @@ F: configs/A20-Olimex-SOM204-EVB_defconfig F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig ORANGEPI LITE2 BOARD -M: Jagan Teki <jagan@openedev.com> +M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: configs/orangepi_lite2_defconfig diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index dd6def5e6e..d42350319c 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -1,11 +1,15 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> + * Copyright (C) 2015-2019 Stefan Roese <sr@denx.de> */ #include <common.h> +#include <console.h> #include <i2c.h> #include <pci.h> +#if !defined(CONFIG_SPL_BUILD) +#include <bootcount.h> +#endif #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/cpu.h> @@ -42,6 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; #define STM_I2C_BUS 1 #define STM_I2C_ADDR 0x27 #define REBOOT_DELAY 1000 /* reboot-delay in ms */ +#define ABORT_TIMEOUT 3000 /* 3 seconds reboot abort timeout */ /* DDR3 static configuration */ static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = { @@ -127,15 +132,15 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) return &board_ddr_modes[0]; } -MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) { return &theadorable_serdes_cfg[0]; } u8 board_sat_r_get(u8 dev_num, u8 reg) { - /* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */ - return 0x01; + /* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */ + return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */ } int board_early_init_f(void) @@ -218,7 +223,7 @@ int board_eth_init(bd_t *bis) } #endif -#ifdef CONFIG_BOARD_LATE_INIT +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT) int board_late_init(void) { pci_dev_t bdf; @@ -232,6 +237,7 @@ int board_late_init(void) */ bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0); if (bdf == -1) { + unsigned long start_time = get_timer(0); u8 i2c_buf[8]; int ret; @@ -239,6 +245,28 @@ int board_late_init(void) bootcount = bootcount_load(); printf("Failed to find PLX PEX-switch (bootcount=%ld)\n", bootcount); + + /* + * The user can exit this boot-loop in the error case by + * hitting Ctrl-C. So wait some time for this key here. + */ + printf("Continue booting with Ctrl-C, otherwise rebooting\n"); + do { + /* Handle control-c and timeouts */ + if (ctrlc()) { + printf("PEX error boot-loop aborted!\n"); + return 0; + } + } while (get_timer(start_time) < ABORT_TIMEOUT); + + + /* + * At this stage the bootcounter has not been incremented + * yet. We need to do this manually here to get an actually + * working bootcounter in this error case. + */ + bootcount_inc(); + if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) { printf("Issuing power-switch via uC!\n"); |