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-rw-r--r--board/cm-bf537u/Makefile54
-rw-r--r--board/cm-bf537u/cm-bf537u.c66
-rw-r--r--board/cm-bf537u/config.mk34
-rw-r--r--board/cm-bf537u/flash.c34
-rw-r--r--board/cm-bf537u/gpio_cfi_flash.c60
-rw-r--r--board/cm-bf537u/gpio_cfi_flash.h10
-rw-r--r--board/cm-bf548/video.c6
-rw-r--r--board/eNET/Makefile11
-rw-r--r--board/eNET/eNET.c90
-rw-r--r--board/eNET/eNET_pci.c95
-rw-r--r--board/lwmon/lwmon.c1
-rw-r--r--board/sc520_cdp/Makefile14
-rw-r--r--board/sc520_cdp/flash.c14
-rw-r--r--board/sc520_cdp/sc520_cdp.c383
-rw-r--r--board/sc520_cdp/sc520_cdp_pci.c271
-rw-r--r--board/sc520_spunk/Makefile14
-rw-r--r--board/sc520_spunk/sc520_spunk.c514
-rw-r--r--board/sc520_spunk/sc520_spunk_pci.c323
-rw-r--r--board/tqc/tqm5200/Makefile2
19 files changed, 1216 insertions, 780 deletions
diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile
new file mode 100644
index 0000000000..3812ba1e72
--- /dev/null
+++ b/board/cm-bf537u/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o flash.o gpio_cfi_flash.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c
new file mode 100644
index 0000000000..9628e0f949
--- /dev/null
+++ b/board/cm-bf537u/cm-bf537u.c
@@ -0,0 +1,66 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include "gpio_cfi_flash.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix CM-BF537U board\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ return gd->bd->bi_memsize;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+ puts("Warning: Generating 'random' MAC address\n");
+ bfin_gen_rand_mac(mac_addr);
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+ gpio_cfi_flash_init();
+
+ return 0;
+}
diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk
new file mode 100644
index 0000000000..3c0b46f721
--- /dev/null
+++ b/board/cm-bf537u/config.mk
@@ -0,0 +1,34 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+CFLAGS_lib_generic += -O2
+CFLAGS_lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/cm-bf537u/flash.c b/board/cm-bf537u/flash.c
new file mode 100644
index 0000000000..ebe17b6531
--- /dev/null
+++ b/board/cm-bf537u/flash.c
@@ -0,0 +1,34 @@
+/*
+ * flash.c - helper commands for working with GPIO-assisted flash
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include "gpio_cfi_flash.h"
+
+int do_ph(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong faddr = CONFIG_SYS_FLASH_BASE;
+ ushort data;
+ ulong dflg;
+
+ if (argc > 1) {
+ dflg = simple_strtoul(argv[1], NULL, 16);
+ faddr |= (dflg << 21);
+ gpio_cfi_flash_swizzle((void *)faddr);
+ } else {
+ data = bfin_read_PORTHIO();
+ printf("Port H data %04x (PH0:%i)\n", data, !!(data & PH0));
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(ph, 3, 0, do_ph,
+ "set/clear PH0 GPIO flash bank switch\n",
+ "<ph0> - set PH0 GPIO pin state\n");
diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c
new file mode 100644
index 0000000000..68633ec78d
--- /dev/null
+++ b/board/cm-bf537u/gpio_cfi_flash.c
@@ -0,0 +1,60 @@
+/*
+ * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+#include "gpio_cfi_flash.h"
+
+#define GPIO_PIN_1 PH0
+#define GPIO_MASK_1 (1 << 21)
+#define GPIO_MASK (GPIO_MASK_1)
+
+void *gpio_cfi_flash_swizzle(void *vaddr)
+{
+ unsigned long addr = (unsigned long)vaddr;
+
+ if (addr & GPIO_MASK_1)
+ bfin_write_PORTHIO_SET(GPIO_PIN_1);
+ else
+ bfin_write_PORTHIO_CLEAR(GPIO_PIN_1);
+
+#ifdef GPIO_MASK_2
+ if (addr & GPIO_MASK_2)
+ bfin_write_PORTGIO_SET(GPIO_PIN_2);
+ else
+ bfin_write_PORTGIO_CLEAR(GPIO_PIN_2);
+#endif
+
+ SSYNC();
+
+ return (void *)(addr & ~GPIO_MASK);
+}
+
+#define __raw_writeq(value, addr) *(volatile u64 *)addr = value
+#define __raw_readq(addr) *(volatile u64 *)addr
+
+#define MAKE_FLASH(size, sfx) \
+void flash_write##size(u##size value, void *addr) \
+{ \
+ __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \
+} \
+u##size flash_read##size(void *addr) \
+{ \
+ return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
+}
+MAKE_FLASH(8, b) /* flash_write8() flash_read8() */
+MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
+MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
+MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
+
+void gpio_cfi_flash_init(void)
+{
+ bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1);
+ gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
+}
diff --git a/board/cm-bf537u/gpio_cfi_flash.h b/board/cm-bf537u/gpio_cfi_flash.h
new file mode 100644
index 0000000000..5211e972ad
--- /dev/null
+++ b/board/cm-bf537u/gpio_cfi_flash.h
@@ -0,0 +1,10 @@
+/*
+ * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+void *gpio_cfi_flash_swizzle(void *vaddr);
+void gpio_cfi_flash_init(void);
diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
index 49dbe77da5..078734269d 100644
--- a/board/cm-bf548/video.c
+++ b/board/cm-bf548/video.c
@@ -14,7 +14,7 @@
#include <asm/mach-common/bits/dma.h>
#include <i2c.h>
#include <linux/types.h>
-#include <devices.h>
+#include <stdio_dev.h>
int gunzip(void *, int, unsigned char *, unsigned long *);
@@ -291,7 +291,7 @@ void video_puts(const char *s)
int drv_video_init(void)
{
int error, devices = 1;
- device_t videodev;
+ struct stdio_dev videodev;
u8 *dst;
u32 fbmem_size =
@@ -331,7 +331,7 @@ int drv_video_init(void)
videodev.putc = video_putc; /* 'putc' function */
videodev.puts = video_puts; /* 'puts' function */
- error = device_register(&videodev);
+ error = stdio_register(&videodev);
return (error == 0) ? devices : error;
}
diff --git a/board/eNET/Makefile b/board/eNET/Makefile
index 4813b4b53a..588d21d269 100644
--- a/board/eNET/Makefile
+++ b/board/eNET/Makefile
@@ -31,12 +31,13 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := eNET.o
-SOBJS := eNET_start16.o eNET_start.o
+COBJS-y += eNET.o
+COBJS-$(CONFIG_PCI) += eNET_pci.o
+SOBJS-y += eNET_start16.o
+SOBJS-y += eNET_start.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 57dd6359e7..29cf29518a 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -46,17 +46,17 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
void init_sc520_enet (void)
{
/* Set CPU Speed to 100MHz */
- write_mmcr_byte(SC520_CPUCTL, 1);
+ sc520_mmcr->cpuctl = 0x01;
gd->cpu_clk = 100000000;
/* wait at least one millisecond */
asm("movl $0x2000,%%ecx\n"
- "wait_loop: pushl %%ecx\n"
+ "0: pushl %%ecx\n"
"popl %%ecx\n"
- "loop wait_loop\n": : : "ecx");
+ "loop 0b\n": : : "ecx");
/* turn on the SDRAM write buffer */
- write_mmcr_byte(SC520_DBCTL, 0x11);
+ sc520_mmcr->dbctl = 0x11;
/* turn on the cache and disable write through */
asm("movl %%cr0, %%eax\n"
@@ -71,51 +71,51 @@ int board_init(void)
{
init_sc520_enet();
- write_mmcr_byte(SC520_GPCSRT, 0x01); /* GP Chip Select Recovery Time */
- write_mmcr_byte(SC520_GPCSPW, 0x07); /* GP Chip Select Pulse Width */
- write_mmcr_byte(SC520_GPCSOFF, 0x00); /* GP Chip Select Offset */
- write_mmcr_byte(SC520_GPRDW, 0x05); /* GP Read pulse width */
- write_mmcr_byte(SC520_GPRDOFF, 0x01); /* GP Read offset */
- write_mmcr_byte(SC520_GPWRW, 0x05); /* GP Write pulse width */
- write_mmcr_byte(SC520_GPWROFF, 0x01); /* GP Write offset */
-
- write_mmcr_word(SC520_PIODATA15_0, 0x0630); /* PIO15_PIO0 Data */
- write_mmcr_word(SC520_PIODATA31_16, 0x2000); /* PIO31_PIO16 Data */
- write_mmcr_word(SC520_PIODIR31_16, 0x2000); /* GPIO Direction */
- write_mmcr_word(SC520_PIODIR15_0, 0x87b5); /* GPIO Direction */
- write_mmcr_word(SC520_PIOPFS31_16, 0x0dfe); /* GPIO pin function 31-16 reg */
- write_mmcr_word(SC520_PIOPFS15_0, 0x200a); /* GPIO pin function 15-0 reg */
- write_mmcr_byte(SC520_CSPFS, 0x00f8); /* Chip Select Pin Function Select */
-
- write_mmcr_long(SC520_PAR2, 0x200713f8); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
- write_mmcr_long(SC520_PAR3, 0x2c0712f8); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
- write_mmcr_long(SC520_PAR4, 0x300711f8); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
- write_mmcr_long(SC520_PAR5, 0x340710f8); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
- write_mmcr_long(SC520_PAR6, 0xe3ffc000); /* SDRAM (0x00000000, 128MB) */
- write_mmcr_long(SC520_PAR7, 0xaa3fd000); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
- write_mmcr_long(SC520_PAR8, 0xca3fd100); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
- write_mmcr_long(SC520_PAR9, 0x4203d900); /* SRAM (GPCS0, 0x19000000, 1MB) */
- write_mmcr_long(SC520_PAR10, 0x4e03d910); /* SRAM (GPCS3, 0x19100000, 1MB) */
- write_mmcr_long(SC520_PAR11, 0x50018100); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
- write_mmcr_long(SC520_PAR12, 0x54020000); /* CFLASH1 (0x200000000, 4kB) */
- write_mmcr_long(SC520_PAR13, 0x5c020001); /* CFLASH2 (0x200010000, 4kB) */
-/* write_mmcr_long(SC520_PAR14, 0x8bfff800); */ /* BOOTCS at 0x18000000 */
-/* write_mmcr_long(SC520_PAR15, 0x38201000); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
+ sc520_mmcr->gpcsrt = 0x01; /* GP Chip Select Recovery Time */
+ sc520_mmcr->gpcspw = 0x07; /* GP Chip Select Pulse Width */
+ sc520_mmcr->gpcsoff = 0x00; /* GP Chip Select Offset */
+ sc520_mmcr->gprdw = 0x05; /* GP Read pulse width */
+ sc520_mmcr->gprdoff = 0x01; /* GP Read offset */
+ sc520_mmcr->gpwrw = 0x05; /* GP Write pulse width */
+ sc520_mmcr->gpwroff = 0x01; /* GP Write offset */
+
+ sc520_mmcr->piodata15_0 = 0x0630; /* PIO15_PIO0 Data */
+ sc520_mmcr->piodata31_16 = 0x2000; /* PIO31_PIO16 Data */
+ sc520_mmcr->piodir31_16 = 0x2000; /* GPIO Direction */
+ sc520_mmcr->piodir15_0 = 0x87b5; /* GPIO Direction */
+ sc520_mmcr->piopfs31_16 = 0x0dfe; /* GPIO pin function 31-16 reg */
+ sc520_mmcr->piopfs15_0 = 0x200a; /* GPIO pin function 15-0 reg */
+ sc520_mmcr->cspfs = 0x00f8; /* Chip Select Pin Function Select */
+
+ sc520_mmcr->par[2] = 0x200713f8; /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
+ sc520_mmcr->par[3] = 0x2c0712f8; /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
+ sc520_mmcr->par[4] = 0x300711f8; /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
+ sc520_mmcr->par[5] = 0x340710f8; /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
+ sc520_mmcr->par[6] = 0xe3ffc000; /* SDRAM (0x00000000, 128MB) */
+ sc520_mmcr->par[7] = 0xaa3fd000; /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
+ sc520_mmcr->par[8] = 0xca3fd100; /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
+ sc520_mmcr->par[9] = 0x4203d900; /* SRAM (GPCS0, 0x19000000, 1MB) */
+ sc520_mmcr->par[10] = 0x4e03d910; /* SRAM (GPCS3, 0x19100000, 1MB) */
+ sc520_mmcr->par[11] = 0x50018100; /* DP-RAM (GPCS4, 0x18100000, 4kB) */
+ sc520_mmcr->par[12] = 0x54020000; /* CFLASH1 (0x200000000, 4kB) */
+ sc520_mmcr->par[13] = 0x5c020001; /* CFLASH2 (0x200010000, 4kB) */
+/* sc520_mmcr->par14 = 0x8bfff800; */ /* BOOTCS at 0x18000000 */
+/* sc520_mmcr->par15 = 0x38201000; */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
/* Disable Watchdog */
- write_mmcr_word(0x0cb0, 0x3333);
- write_mmcr_word(0x0cb0, 0xcccc);
- write_mmcr_word(0x0cb0, 0x0000);
+ sc520_mmcr->wdtmrctl = 0x3333;
+ sc520_mmcr->wdtmrctl = 0xcccc;
+ sc520_mmcr->wdtmrctl = 0x0000;
/* Chip Select Configuration */
- write_mmcr_word(SC520_BOOTCSCTL, 0x0033);
- write_mmcr_word(SC520_ROMCS1CTL, 0x0615);
- write_mmcr_word(SC520_ROMCS2CTL, 0x0615);
-
- write_mmcr_byte(SC520_ADDDECCTL, 0x02);
- write_mmcr_byte(SC520_UART1CTL, 0x07);
- write_mmcr_byte(SC520_SYSARBCTL,0x06);
- write_mmcr_word(SC520_SYSARBMENB, 0x0003);
+ sc520_mmcr->bootcsctl = 0x0033;
+ sc520_mmcr->romcs1ctl = 0x0615;
+ sc520_mmcr->romcs2ctl = 0x0615;
+
+ sc520_mmcr->adddecctl = 0x02;
+ sc520_mmcr->uart1ctl = 0x07;
+ sc520_mmcr->sysarbctl = 0x06;
+ sc520_mmcr->sysarbmenb = 0x0003;
/* Crystal is 33.000MHz */
gd->bus_clk = 33000000;
diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c
new file mode 100644
index 0000000000..e80a8feb16
--- /dev/null
+++ b/board/eNET/eNET_pci.c
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/ic/pci.h>
+
+static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ /* a configurable lists of IRQs to steal when we need one */
+ static int irq_list[] = {
+ CONFIG_SYS_FIRST_PCI_IRQ,
+ CONFIG_SYS_SECOND_PCI_IRQ,
+ CONFIG_SYS_THIRD_PCI_IRQ,
+ CONFIG_SYS_FORTH_PCI_IRQ
+ };
+ static int next_irq_index=0;
+
+ uchar tmp_pin;
+ int pin;
+
+ pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+ pin = tmp_pin;
+
+ pin -= 1; /* PCI config space use 1-based numbering */
+ if (pin == -1) {
+ return; /* device use no irq */
+ }
+
+ /* map device number + pin to a pin on the sc520 */
+ switch (PCI_DEV(dev)) {
+ case 12: /* First Ethernet Chip */
+ pin += SC520_PCI_INTA;
+ break;
+
+ case 13: /* Second Ethernet Chip */
+ pin += SC520_PCI_INTB;
+ break;
+
+ default:
+ return;
+ }
+
+ pin &= 3; /* wrap around */
+
+ if (sc520_pci_ints[pin] == -1) {
+ /* re-route one interrupt for us */
+ if (next_irq_index > 3) {
+ return;
+ }
+ if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+ return;
+ }
+ next_irq_index++;
+ }
+
+ if (-1 != sc520_pci_ints[pin]) {
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+ sc520_pci_ints[pin]);
+ }
+ printf("fixup_irq: device %d pin %c irq %d\n",
+ PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+}
+
+static struct pci_controller enet_hose = {
+ fixup_irq: pci_enet_fixup_irq,
+};
+
+void pci_init_board(void)
+{
+ pci_sc520_init(&enet_hose);
+}
diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
index 75b32090d1..8e27778939 100644
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c
@@ -7,7 +7,6 @@ M* Content: LWMON specific U-Boot commands.
* (C) Copyright 2001, 2002
* DENX Software Engineering
* Wolfgang Denk, wd@denx.de
- * All rights reserved.
*
D* Design: wd@denx.de
C* Coding: wd@denx.de
diff --git a/board/sc520_cdp/Makefile b/board/sc520_cdp/Makefile
index 0d2800d5e4..7944a01a64 100644
--- a/board/sc520_cdp/Makefile
+++ b/board/sc520_cdp/Makefile
@@ -28,12 +28,14 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := sc520_cdp.o flash.o
-SOBJS := sc520_cdp_asm.o sc520_cdp_asm16.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+COBJS-y += sc520_cdp.o
+COBJS-y += flash.o
+COBJS-$(CONFIG_PCI) += sc520_cdp_pci.o
+SOBJS-y += sc520_cdp_asm.o
+SOBJS-y += sc520_cdp_asm16.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
diff --git a/board/sc520_cdp/flash.c b/board/sc520_cdp/flash.c
index dcb8c57e81..64831b7eda 100644
--- a/board/sc520_cdp/flash.c
+++ b/board/sc520_cdp/flash.c
@@ -337,12 +337,12 @@ done: ;
unsigned micro; \
unsigned milli=0; \
\
- micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+ micro = sc520_mmcr->swtmrmilli; \
\
for (;;) { \
\
- milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
- micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \
+ milli += sc520_mmcr->swtmrmilli; \
+ micro = sc520_mmcr->swtmrmicro; \
\
if ((delay) <= (micro + (milli * 1000))) { \
break; \
@@ -364,12 +364,12 @@ static u32 _amd_erase_flash(u32 addr, u32 sector)
/* Sector erase command comes last */
*(volatile u32*)(addr + sector) = 0x30303030;
- elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+ elapsed = sc520_mmcr->swtmrmilli; /* dummy read */
elapsed = 0;
__udelay(50);
while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) {
- elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+ elapsed += sc520_mmcr->swtmrmilli;
if (elapsed > ((CONFIG_SYS_FLASH_ERASE_TOUT/CONFIG_SYS_HZ) * 1000)) {
*(volatile u32*)(addr) = 0xf0f0f0f0;
return 1;
@@ -487,12 +487,12 @@ static int _amd_write_word(unsigned start, unsigned dest, unsigned data)
dest2[0] = data;
- elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+ elapsed = sc520_mmcr->swtmrmilli; /* dummy read */
elapsed = 0;
/* data polling for D7 */
while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) {
- elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+ elapsed += sc520_mmcr->swtmrmilli;
if (elapsed > ((CONFIG_SYS_FLASH_WRITE_TOUT/CONFIG_SYS_HZ) * 1000)) {
addr2[0] = 0xf0f0f0f0;
return 1;
diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c
index 830ec37dd7..4c44b2414c 100644
--- a/board/sc520_cdp/sc520_cdp.c
+++ b/board/sc520_cdp/sc520_cdp.c
@@ -23,9 +23,7 @@
*/
#include <common.h>
-#include <pci.h>
#include <asm/io.h>
-#include <asm/pci.h>
#include <asm/ic/sc520.h>
#include <ali512x.h>
#include <spi.h>
@@ -57,144 +55,62 @@ DECLARE_GLOBAL_DATA_PTR;
static void irq_init(void)
{
/* disable global interrupt mode */
- write_mmcr_byte(SC520_PICICR, 0x40);
+ sc520_mmcr->picicr = 0x40;
/* set all irqs to edge */
- write_mmcr_byte(SC520_MPICMODE, 0x00);
- write_mmcr_byte(SC520_SL1PICMODE, 0x00);
- write_mmcr_byte(SC520_SL2PICMODE, 0x00);
+ sc520_mmcr->pic_mode[0] = 0x00;
+ sc520_mmcr->pic_mode[1] = 0x00;
+ sc520_mmcr->pic_mode[2] = 0x00;
/* active low polarity on PIC interrupt pins,
* active high polarity on all other irq pins */
- write_mmcr_word(SC520_INTPINPOL, 0x0000);
+ sc520_mmcr->intpinpol = 0x0000;
/* set irq number mapping */
- write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */
- write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */
- write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */
- write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */
- write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */
- write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */
- write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */
- write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */
- write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */
- write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */
- write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
- write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED); /* disable Synchronius serial INT */
- write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */
- write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */
- write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */
- write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */
- write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */
+ sc520_mmcr->gp_tmr_int_map[0] = SC520_IRQ_DISABLED; /* disable GP timer 0 INT */
+ sc520_mmcr->gp_tmr_int_map[1] = SC520_IRQ_DISABLED; /* disable GP timer 1 INT */
+ sc520_mmcr->gp_tmr_int_map[2] = SC520_IRQ_DISABLED; /* disable GP timer 2 INT */
+ sc520_mmcr->pit_int_map[0] = SC520_IRQ0; /* Set PIT timer 0 INT to IRQ0 */
+ sc520_mmcr->pit_int_map[1] = SC520_IRQ_DISABLED; /* disable PIT timer 1 INT */
+ sc520_mmcr->pit_int_map[2] = SC520_IRQ_DISABLED; /* disable PIT timer 2 INT */
+ sc520_mmcr->pci_int_map[0] = SC520_IRQ_DISABLED; /* disable PCI INT A */
+ sc520_mmcr->pci_int_map[1] = SC520_IRQ_DISABLED; /* disable PCI INT B */
+ sc520_mmcr->pci_int_map[2] = SC520_IRQ_DISABLED; /* disable PCI INT C */
+ sc520_mmcr->pci_int_map[3] = SC520_IRQ_DISABLED; /* disable PCI INT D */
+ sc520_mmcr->dmabcintmap = SC520_IRQ_DISABLED; /* disable DMA INT */
+ sc520_mmcr->ssimap = SC520_IRQ_DISABLED; /* disable Synchronius serial INT */
+ sc520_mmcr->wdtmap = SC520_IRQ_DISABLED; /* disable Watchdog INT */
+ sc520_mmcr->rtcmap = SC520_IRQ8; /* Set RTC int to 8 */
+ sc520_mmcr->wpvmap = SC520_IRQ_DISABLED; /* disable write protect INT */
+ sc520_mmcr->icemap = SC520_IRQ1; /* Set ICE Debug Serielport INT to IRQ1 */
+ sc520_mmcr->ferrmap = SC520_IRQ13; /* Set FP error INT to IRQ13 */
if (CONFIG_SYS_USE_SIO_UART) {
- write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
- write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
- write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
- write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4); /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
+ sc520_mmcr->uart_int_map[0] = SC520_IRQ_DISABLED; /* disable internal UART1 INT */
+ sc520_mmcr->uart_int_map[1] = SC520_IRQ_DISABLED; /* disable internal UART2 INT */
+ sc520_mmcr->gp_int_map[3] = SC520_IRQ3; /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
+ sc520_mmcr->gp_int_map[4] = SC520_IRQ4; /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
} else {
- write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */
- write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */
- write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ3 (ISA IRQ3) */
- write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ4 (ISA IRQ4) */
+ sc520_mmcr->uart_int_map[0] = SC520_IRQ4; /* Set internal UART2 INT to IRQ4 */
+ sc520_mmcr->uart_int_map[1] = SC520_IRQ3; /* Set internal UART2 INT to IRQ3 */
+ sc520_mmcr->gp_int_map[3] = SC520_IRQ_DISABLED; /* disable GPIRQ3 (ISA IRQ3) */
+ sc520_mmcr->gp_int_map[4] = SC520_IRQ_DISABLED; /* disable GPIRQ4 (ISA IRQ4) */
}
- write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1); /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
- write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5); /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
- write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6); /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
- write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7); /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
- write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8); /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
- write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9); /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
- write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11); /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
- write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12); /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
- write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14); /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
-
- write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */
- write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */
-
-}
-
-#ifdef CONFIG_PCI
-/* PCI stuff */
-static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- /* a configurable lists of irqs to steal
- * when we need one (a board with more pci interrupt pins
- * would use a larger table */
- static int irq_list[] = {
- CONFIG_SYS_FIRST_PCI_IRQ,
- CONFIG_SYS_SECOND_PCI_IRQ,
- CONFIG_SYS_THIRD_PCI_IRQ,
- CONFIG_SYS_FORTH_PCI_IRQ
- };
- static int next_irq_index=0;
-
- uchar tmp_pin;
- int pin;
-
- pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
- pin = tmp_pin;
-
- pin-=1; /* pci config space use 1-based numbering */
- if (-1 == pin) {
- return; /* device use no irq */
- }
-
-
- /* map device number + pin to a pin on the sc520 */
- switch (PCI_DEV(dev)) {
- case 20:
- pin+=SC520_PCI_INTA;
- break;
-
- case 19:
- pin+=SC520_PCI_INTB;
- break;
-
- case 18:
- pin+=SC520_PCI_INTC;
- break;
-
- case 17:
- pin+=SC520_PCI_INTD;
- break;
-
- default:
- return;
- }
-
- pin&=3; /* wrap around */
-
- if (sc520_pci_ints[pin] == -1) {
- /* re-route one interrupt for us */
- if (next_irq_index > 3) {
- return;
- }
- if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
- return;
- }
- next_irq_index++;
- }
-
-
- if (-1 != sc520_pci_ints[pin]) {
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
- sc520_pci_ints[pin]);
- }
- PRINTF("fixup_irq: device %d pin %c irq %d\n",
- PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+ sc520_mmcr->gp_int_map[1] = SC520_IRQ1; /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
+ sc520_mmcr->gp_int_map[5] = SC520_IRQ5; /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
+ sc520_mmcr->gp_int_map[6] = SC520_IRQ6; /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
+ sc520_mmcr->gp_int_map[7] = SC520_IRQ7; /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
+ sc520_mmcr->gp_int_map[8] = SC520_IRQ8; /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
+ sc520_mmcr->gp_int_map[9] = SC520_IRQ9; /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
+ sc520_mmcr->gp_int_map[0] = SC520_IRQ11; /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
+ sc520_mmcr->gp_int_map[2] = SC520_IRQ12; /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
+ sc520_mmcr->gp_int_map[10] = SC520_IRQ14; /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
+
+ sc520_mmcr->pcihostmap = 0x11f; /* Map PCI hostbridge INT to NMI */
+ sc520_mmcr->eccmap = 0x100; /* Map SDRAM ECC failure INT to NMI */
}
-static struct pci_controller sc520_cdp_hose = {
- fixup_irq: pci_sc520_cdp_fixup_irq,
-};
-
-void pci_init_board(void)
-{
- pci_sc520_init(&sc520_cdp_hose);
-}
-#endif
-
static void silence_uart(int port)
{
outb(0, port+1);
@@ -234,23 +150,22 @@ static void bus_init(void)
{
/* set up the GP IO pins */
- write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */
- write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */
- write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */
- write_mmcr_byte(SC520_CLKSEL, 0x70);
-
-
- write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */
- write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */
- write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */
- write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */
- write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */
- write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */
- write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */
-
- write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */
- write_mmcr_word(SC520_ROMCS1CTL, 0x1823); /* set up timing of ROMCS1 */
- write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */
+ sc520_mmcr->piopfs31_16 = 0xf7ff; /* set the GPIO pin function 31-16 reg */
+ sc520_mmcr->piopfs15_0 = 0xffff; /* set the GPIO pin function 15-0 reg */
+ sc520_mmcr->cspfs = 0xf8; /* set the CS pin function reg */
+ sc520_mmcr->clksel = 0x70;
+
+ sc520_mmcr->gpcsrt = 1; /* set the GP CS offset */
+ sc520_mmcr->gpcspw = 3; /* set the GP CS pulse width */
+ sc520_mmcr->gpcsoff = 1; /* set the GP CS offset */
+ sc520_mmcr->gprdw = 3; /* set the RD pulse width */
+ sc520_mmcr->gprdoff = 1; /* set the GP RD offset */
+ sc520_mmcr->gpwrw = 3; /* set the GP WR pulse width */
+ sc520_mmcr->gpwroff = 1; /* set the GP WR offset */
+
+ sc520_mmcr->bootcsctl = 0x1823; /* set up timing of BOOTCS */
+ sc520_mmcr->romcs1ctl = 0x1823; /* set up timing of ROMCS1 */
+ sc520_mmcr->romcs2ctl = 0x1823; /* set up timing of ROMCS2 */
/* adjust the memory map:
* by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
@@ -259,31 +174,31 @@ static void bus_init(void)
/* SRAM = GPCS3 128k @ d0000-effff*/
- write_mmcr_long(SC520_PAR2, 0x4e00400d);
+ sc520_mmcr->par[2] = 0x4e00400d;
/* IDE0 = GPCS6 1f0-1f7 */
- write_mmcr_long(SC520_PAR3, 0x380801f0);
+ sc520_mmcr->par[3] = 0x380801f0;
/* IDE1 = GPCS7 3f6 */
- write_mmcr_long(SC520_PAR4, 0x3c0003f6);
+ sc520_mmcr->par[4] = 0x3c0003f6;
/* bootcs */
- write_mmcr_long(SC520_PAR12, 0x8bffe800);
+ sc520_mmcr->par[12] = 0x8bffe800;
/* romcs2 */
- write_mmcr_long(SC520_PAR13, 0xcbfff000);
+ sc520_mmcr->par[13] = 0xcbfff000;
/* romcs1 */
- write_mmcr_long(SC520_PAR14, 0xabfff800);
+ sc520_mmcr->par[14] = 0xabfff800;
/* 680 LEDS */
- write_mmcr_long(SC520_PAR15, 0x30000640);
+ sc520_mmcr->par[15] = 0x30000640;
- write_mmcr_byte(SC520_ADDDECCTL, 0);
+ sc520_mmcr->adddecctl = 0;
asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
if (CONFIG_SYS_USE_SIO_UART) {
- write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
+ sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | UART2_DIS | UART1_DIS;
setup_ali_sio(1);
} else {
- write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
+ sc520_mmcr->adddecctl = sc520_mmcr->adddecctl & ~(UART2_DIS|UART1_DIS);
setup_ali_sio(0);
silence_uart(0x3e8);
silence_uart(0x2e8);
@@ -323,162 +238,6 @@ static void bus_init(void)
*/
/*
- * This function should map a chunk of size bytes
- * of the system address space to the ISA bus
- *
- * The function will return the memory address
- * as seen by the host (which may very will be the
- * same as the bus address)
- */
-u32 isa_map_rom(u32 bus_addr, int size)
-{
- u32 par;
-
- PRINTF("isa_map_rom asked to map %d bytes at %x\n",
- size, bus_addr);
-
- par = size;
- if (par < 0x80000) {
- par = 0x80000;
- }
- par >>= 12;
- par--;
- par&=0x7f;
- par <<= 18;
- par |= (bus_addr>>12);
- par |= 0x50000000;
-
- PRINTF ("setting PAR11 to %x\n", par);
-
- /* Map rom 0x10000 with PAR1 */
- write_mmcr_long(SC520_PAR11, par);
-
- return bus_addr;
-}
-
-/*
- * this function removed any mapping created
- * with pci_get_rom_window()
- */
-void isa_unmap_rom(u32 addr)
-{
- PRINTF("isa_unmap_rom asked to unmap %x", addr);
- if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
- write_mmcr_long(SC520_PAR11, 0);
- PRINTF(" done\n");
- return;
- }
- PRINTF(" not ours\n");
-}
-
-#ifdef CONFIG_PCI
-#define PCI_ROM_TEMP_SPACE 0x10000
-/*
- * This function should map a chunk of size bytes
- * of the system address space to the PCI bus,
- * suitable to map PCI ROMS (bus address < 16M)
- * the function will return the host memory address
- * which should be converted into a bus address
- * before used to configure the PCI rom address
- * decoder
- */
-u32 pci_get_rom_window(struct pci_controller *hose, int size)
-{
- u32 par;
-
- par = size;
- if (par < 0x80000) {
- par = 0x80000;
- }
- par >>= 16;
- par--;
- par&=0x7ff;
- par <<= 14;
- par |= (PCI_ROM_TEMP_SPACE>>16);
- par |= 0x72000000;
-
- PRINTF ("setting PAR1 to %x\n", par);
-
- /* Map rom 0x10000 with PAR1 */
- write_mmcr_long(SC520_PAR1, par);
-
- return PCI_ROM_TEMP_SPACE;
-}
-
-/*
- * this function removed any mapping created
- * with pci_get_rom_window()
- */
-void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
-{
- PRINTF("pci_remove_rom_window: %x", addr);
- if (addr == PCI_ROM_TEMP_SPACE) {
- write_mmcr_long(SC520_PAR1, 0);
- PRINTF(" done\n");
- return;
- }
- PRINTF(" not ours\n");
-
-}
-
-/*
- * This function is called in order to provide acces to the
- * legacy video I/O ports on the PCI bus.
- * After this function accesses to I/O ports 0x3b0-0x3bb and
- * 0x3c0-0x3df shuld result in transactions on the PCI bus.
- *
- */
-int pci_enable_legacy_video_ports(struct pci_controller *hose)
-{
- /* Map video memory to 0xa0000*/
- write_mmcr_long(SC520_PAR0, 0x7200400a);
-
- /* forward all I/O accesses to PCI */
- write_mmcr_byte(SC520_ADDDECCTL,
- read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
-
-
- /* so we map away all io ports to pci (only way to access pci io
- * below 0x400. But then we have to map back the portions that we dont
- * use so that the generate cycles on the GPIO bus where the sio and
- * ISA slots are connected, this requre the use of several PAR registers
- */
-
- /* bring 0x100 - 0x1ef back to ISA using PAR5 */
- write_mmcr_long(SC520_PAR5, 0x30ef0100);
-
- /* IDE use 1f0-1f7 */
-
- /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
- write_mmcr_long(SC520_PAR6, 0x30ff01f8);
-
- /* com2 use 2f8-2ff */
-
- /* bring 0x300 - 0x3af back to ISA using PAR7 */
- write_mmcr_long(SC520_PAR7, 0x30af0300);
-
- /* vga use 3b0-3bb */
-
- /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
- write_mmcr_long(SC520_PAR8, 0x300303bc);
-
- /* vga use 3c0-3df */
-
- /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
- write_mmcr_long(SC520_PAR9, 0x301503e0);
-
- /* ide use 3f6 */
-
- /* bring 0x3f7 back to ISA using PAR10 */
- write_mmcr_long(SC520_PAR10, 0x300003f7);
-
- /* com1 use 3f8-3ff */
-
- return 0;
-}
-#endif
-
-/*
* Miscelaneous platform dependent initialisations
*/
@@ -489,12 +248,12 @@ int board_init(void)
irq_init();
/* max drive current on SDRAM */
- write_mmcr_word(SC520_DSCTL, 0x0100);
+ sc520_mmcr->dsctl = 0x0100;
/* enter debug mode after next reset (only if jumper is also set) */
- write_mmcr_byte(SC520_RESCFG, 0x08);
+ sc520_mmcr->rescfg = 0x08;
/* configure the software timer to 33.333MHz */
- write_mmcr_byte(SC520_SWTMRCFG, 0);
+ sc520_mmcr->swtmrcfg = 0;
gd->bus_clk = 33333000;
return 0;
diff --git a/board/sc520_cdp/sc520_cdp_pci.c b/board/sc520_cdp/sc520_cdp_pci.c
new file mode 100644
index 0000000000..ccb79888dc
--- /dev/null
+++ b/board/sc520_cdp/sc520_cdp_pci.c
@@ -0,0 +1,271 @@
+/*
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+#include <asm/ic/pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef SC520_CDP_DEBUG
+
+#ifdef SC520_CDP_DEBUG
+#define PRINTF(fmt,args...) printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ /* a configurable lists of irqs to steal
+ * when we need one (a board with more pci interrupt pins
+ * would use a larger table */
+ static int irq_list[] = {
+ CONFIG_SYS_FIRST_PCI_IRQ,
+ CONFIG_SYS_SECOND_PCI_IRQ,
+ CONFIG_SYS_THIRD_PCI_IRQ,
+ CONFIG_SYS_FORTH_PCI_IRQ
+ };
+ static int next_irq_index=0;
+
+ uchar tmp_pin;
+ int pin;
+
+ pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+ pin = tmp_pin;
+
+ pin-=1; /* pci config space use 1-based numbering */
+ if (-1 == pin) {
+ return; /* device use no irq */
+ }
+
+
+ /* map device number + pin to a pin on the sc520 */
+ switch (PCI_DEV(dev)) {
+ case 20:
+ pin+=SC520_PCI_INTA;
+ break;
+
+ case 19:
+ pin+=SC520_PCI_INTB;
+ break;
+
+ case 18:
+ pin+=SC520_PCI_INTC;
+ break;
+
+ case 17:
+ pin+=SC520_PCI_INTD;
+ break;
+
+ default:
+ return;
+ }
+
+ pin&=3; /* wrap around */
+
+ if (sc520_pci_ints[pin] == -1) {
+ /* re-route one interrupt for us */
+ if (next_irq_index > 3) {
+ return;
+ }
+ if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+ return;
+ }
+ next_irq_index++;
+ }
+
+
+ if (-1 != sc520_pci_ints[pin]) {
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+ sc520_pci_ints[pin]);
+ }
+ PRINTF("fixup_irq: device %d pin %c irq %d\n",
+ PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+}
+
+static struct pci_controller sc520_cdp_hose = {
+ fixup_irq: pci_sc520_cdp_fixup_irq,
+};
+
+void pci_init_board(void)
+{
+ pci_sc520_init(&sc520_cdp_hose);
+}
+
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ *
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size)
+{
+ u32 par;
+
+ PRINTF("isa_map_rom asked to map %d bytes at %x\n",
+ size, bus_addr);
+
+ par = size;
+ if (par < 0x80000) {
+ par = 0x80000;
+ }
+ par >>= 12;
+ par--;
+ par&=0x7f;
+ par <<= 18;
+ par |= (bus_addr>>12);
+ par |= 0x50000000;
+
+ PRINTF ("setting PAR11 to %x\n", par);
+
+ /* Map rom 0x10000 with PAR1 */
+ sc520_mmcr->par[11] = par;
+
+ return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+ PRINTF("isa_unmap_rom asked to unmap %x", addr);
+ if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
+ sc520_mmcr->par[11] = 0;
+ PRINTF(" done\n");
+ return;
+ }
+ PRINTF(" not ours\n");
+}
+
+#define PCI_ROM_TEMP_SPACE 0x10000
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size)
+{
+ u32 par;
+
+ par = size;
+ if (par < 0x80000) {
+ par = 0x80000;
+ }
+ par >>= 16;
+ par--;
+ par&=0x7ff;
+ par <<= 14;
+ par |= (PCI_ROM_TEMP_SPACE>>16);
+ par |= 0x72000000;
+
+ PRINTF ("setting PAR1 to %x\n", par);
+
+ /* Map rom 0x10000 with PAR1 */
+ sc520_mmcr->par[1] = par;
+
+ return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+ PRINTF("pci_remove_rom_window: %x", addr);
+ if (addr == PCI_ROM_TEMP_SPACE) {
+ sc520_mmcr->par[1] = 0;
+ PRINTF(" done\n");
+ return;
+ }
+ PRINTF(" not ours\n");
+
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus.
+ * After this function accesses to I/O ports 0x3b0-0x3bb and
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ *
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+ /* Map video memory to 0xa0000*/
+ sc520_mmcr->par[0] = 0x7200400a;
+
+ /* forward all I/O accesses to PCI */
+ sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
+
+
+ /* so we map away all io ports to pci (only way to access pci io
+ * below 0x400. But then we have to map back the portions that we dont
+ * use so that the generate cycles on the GPIO bus where the sio and
+ * ISA slots are connected, this requre the use of several PAR registers
+ */
+
+ /* bring 0x100 - 0x1ef back to ISA using PAR5 */
+ sc520_mmcr->par[5] = 0x30ef0100;
+
+ /* IDE use 1f0-1f7 */
+
+ /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
+ sc520_mmcr->par[6] = 0x30ff01f8;
+
+ /* com2 use 2f8-2ff */
+
+ /* bring 0x300 - 0x3af back to ISA using PAR7 */
+ sc520_mmcr->par[7] = 0x30af0300;
+
+ /* vga use 3b0-3bb */
+
+ /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+ sc520_mmcr->par[8] = 0x300303bc;
+
+ /* vga use 3c0-3df */
+
+ /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
+ sc520_mmcr->par[9] = 0x301503e0;
+
+ /* ide use 3f6 */
+
+ /* bring 0x3f7 back to ISA using PAR10 */
+ sc520_mmcr->par[10] = 0x300003f7;
+
+ /* com1 use 3f8-3ff */
+
+ return 0;
+}
diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile
index e04172e3b9..06fa2f3f44 100644
--- a/board/sc520_spunk/Makefile
+++ b/board/sc520_spunk/Makefile
@@ -28,12 +28,14 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := sc520_spunk.o flash.o
-SOBJS := sc520_spunk_asm.o sc520_spunk_asm16.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+COBJS-y += sc520_spunk.o
+COBJS-y += flash.o
+COBJS-$(CONFIG_PCI) += sc520_spunk_pci.o
+SOBJS-y += sc520_spunk_asm.o
+SOBJS-y += sc520_spunk_asm16.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c
index d3bd869306..09f11bb4f3 100644
--- a/board/sc520_spunk/sc520_spunk.c
+++ b/board/sc520_spunk/sc520_spunk.c
@@ -23,12 +23,11 @@
*/
#include <common.h>
-#include <pci.h>
-#include <ssi.h>
#include <netdev.h>
+#include <ds1722.h>
#include <asm/io.h>
-#include <asm/pci.h>
#include <asm/ic/sc520.h>
+#include <asm/ic/ssi.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -45,206 +44,57 @@ DECLARE_GLOBAL_DATA_PTR;
static void irq_init(void)
{
/* disable global interrupt mode */
- write_mmcr_byte(SC520_PICICR, 0x40);
+ sc520_mmcr->picicr = 0x40;
/* set all irqs to edge */
- write_mmcr_byte(SC520_MPICMODE, 0x00);
- write_mmcr_byte(SC520_SL1PICMODE, 0x00);
- write_mmcr_byte(SC520_SL2PICMODE, 0x00);
+ sc520_mmcr->pic_mode[0] = 0x00;
+ sc520_mmcr->pic_mode[1] = 0x00;
+ sc520_mmcr->pic_mode[2] = 0x00;
/* active low polarity on PIC interrupt pins,
* active high polarity on all other irq pins */
- write_mmcr_word(SC520_INTPINPOL, 0x0000);
+ sc520_mmcr->intpinpol = 0x0000;
/* set irq number mapping */
- write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */
- write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */
- write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */
- write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */
- write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */
- write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */
- write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */
- write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */
- write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */
- write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */
- write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
- write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6); /* Set Synchronius serial INT to IRQ6*/
- write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */
- write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */
- write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */
- write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */
- write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */
-
- write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */
- write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */
-
- write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7); /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
- write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14); /* Set GPIRQ1 (CF IRQ) to IRQ14 */
- write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5); /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
- write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disbale GIRQ4 ( IRR IRQ ) */
- write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ5 */
- write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ6 */
- write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ7 */
- write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ8 */
- write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ9 */
- write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ2 */
- write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED); /* disable GPIRQ10 */
-
- write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */
- write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */
+ sc520_mmcr->gp_tmr_int_map[0] = SC520_IRQ_DISABLED; /* disable GP timer 0 INT */
+ sc520_mmcr->gp_tmr_int_map[1] = SC520_IRQ_DISABLED; /* disable GP timer 1 INT */
+ sc520_mmcr->gp_tmr_int_map[2] = SC520_IRQ_DISABLED; /* disable GP timer 2 INT */
+ sc520_mmcr->pit_int_map[0] = SC520_IRQ0; /* Set PIT timer 0 INT to IRQ0 */
+ sc520_mmcr->pit_int_map[1] = SC520_IRQ_DISABLED; /* disable PIT timer 1 INT */
+ sc520_mmcr->pit_int_map[2] = SC520_IRQ_DISABLED; /* disable PIT timer 2 INT */
+ sc520_mmcr->pci_int_map[0] = SC520_IRQ_DISABLED; /* disable PCI INT A */
+ sc520_mmcr->pci_int_map[1] = SC520_IRQ_DISABLED; /* disable PCI INT B */
+ sc520_mmcr->pci_int_map[2] = SC520_IRQ_DISABLED; /* disable PCI INT C */
+ sc520_mmcr->pci_int_map[3] = SC520_IRQ_DISABLED; /* disable PCI INT D */
+ sc520_mmcr->dmabcintmap = SC520_IRQ_DISABLED; /* disable DMA INT */
+ sc520_mmcr->ssimap = SC520_IRQ6; /* Set Synchronius serial INT to IRQ6*/
+ sc520_mmcr->wdtmap = SC520_IRQ_DISABLED; /* disable Watchdog INT */
+ sc520_mmcr->rtcmap = SC520_IRQ8; /* Set RTC int to 8 */
+ sc520_mmcr->wpvmap = SC520_IRQ_DISABLED; /* disable write protect INT */
+ sc520_mmcr->icemap = SC520_IRQ1; /* Set ICE Debug Serielport INT to IRQ1 */
+ sc520_mmcr->ferrmap = SC520_IRQ13; /* Set FP error INT to IRQ13 */
+
+
+ sc520_mmcr->uart_int_map[0] = SC520_IRQ4; /* Set internal UART1 INT to IRQ4 */
+ sc520_mmcr->uart_int_map[1] = SC520_IRQ3; /* Set internal UART2 INT to IRQ3 */
+
+ sc520_mmcr->gp_int_map[0] = SC520_IRQ7; /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
+ sc520_mmcr->gp_int_map[1] = SC520_IRQ14; /* Set GPIRQ1 (CF IRQ) to IRQ14 */
+ sc520_mmcr->gp_int_map[3] = SC520_IRQ5; /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
+ sc520_mmcr->gp_int_map[4] = SC520_IRQ_DISABLED; /* disbale GIRQ4 ( IRR IRQ ) */
+ sc520_mmcr->gp_int_map[5] = SC520_IRQ_DISABLED; /* disable GPIRQ5 */
+ sc520_mmcr->gp_int_map[6] = SC520_IRQ_DISABLED; /* disable GPIRQ6 */
+ sc520_mmcr->gp_int_map[7] = SC520_IRQ_DISABLED; /* disable GPIRQ7 */
+ sc520_mmcr->gp_int_map[8] = SC520_IRQ_DISABLED; /* disable GPIRQ8 */
+ sc520_mmcr->gp_int_map[9] = SC520_IRQ_DISABLED; /* disable GPIRQ9 */
+ sc520_mmcr->gp_int_map[2] = SC520_IRQ_DISABLED; /* disable GPIRQ2 */
+ sc520_mmcr->gp_int_map[10] = SC520_IRQ_DISABLED; /* disable GPIRQ10 */
+
+ sc520_mmcr->pcihostmap = 0x11f; /* Map PCI hostbridge INT to NMI */
+ sc520_mmcr->eccmap = 0x100; /* Map SDRAM ECC failure INT to NMI */
}
-
-/* PCI stuff */
-static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- int version = read_mmcr_byte(SC520_SYSINFO);
-
- /* a configurable lists of irqs to steal
- * when we need one (a board with more pci interrupt pins
- * would use a larger table */
- static int irq_list[] = {
- CONFIG_SYS_FIRST_PCI_IRQ,
- CONFIG_SYS_SECOND_PCI_IRQ,
- CONFIG_SYS_THIRD_PCI_IRQ,
- CONFIG_SYS_FORTH_PCI_IRQ
- };
- static int next_irq_index=0;
-
- char tmp_pin;
- int pin;
-
- pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
- pin = tmp_pin;
-
- pin-=1; /* pci config space use 1-based numbering */
- if (-1 == pin) {
- return; /* device use no irq */
- }
-
-
- /* map device number + pin to a pin on the sc520 */
- switch (PCI_DEV(dev)) {
- case 6: /* ETH0 */
- pin+=SC520_PCI_INTA;
- break;
-
- case 7: /* ETH1 */
- pin+=SC520_PCI_INTB;
- break;
-
- case 8: /* Crypto */
- pin+=SC520_PCI_INTC;
- break;
-
- case 9: /* PMC slot */
- pin+=SC520_PCI_INTD;
- break;
-
- case 10: /* PC-Card */
-
- if (version < 10) {
- pin+=SC520_PCI_INTD;
- } else {
- pin+=SC520_PCI_INTC;
- }
- break;
-
- default:
- return;
- }
-
- pin&=3; /* wrap around */
-
- if (sc520_pci_ints[pin] == -1) {
- /* re-route one interrupt for us */
- if (next_irq_index > 3) {
- return;
- }
- if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
- return;
- }
- next_irq_index++;
- }
-
-
- if (-1 != sc520_pci_ints[pin]) {
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
- sc520_pci_ints[pin]);
- }
-#if 0
- printf("fixup_irq: device %d pin %c irq %d\n",
- PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
-#endif
-}
-
-
-static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *te)
-{
- u32 io_base;
- u32 temp;
-
- pciauto_config_device(hose, dev);
-
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07); /* enable device */
- pci_hose_write_config_byte(hose, dev, 0x0c, 0x10); /* cacheline size */
- pci_hose_write_config_byte(hose, dev, 0x0d, 0x40); /* latency timer */
- pci_hose_write_config_byte(hose, dev, 0x1b, 0x40); /* cardbus latency timer */
- pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040); /* reset cardbus */
- pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080); /* route interrupts though ExCA */
- pci_hose_write_config_word(hose, dev, 0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
-
- pci_hose_read_config_dword(hose, dev, 0x80, &temp); /* System control */
- pci_hose_write_config_dword(hose, dev, 0x80, temp | 0x60); /* System control: disable clockrun */
- /* route MF0 to ~INT and MF3 to IRQ7
- * reserve all others */
- pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002);
- pci_hose_write_config_byte(hose, dev, 0x91, 0x00); /* card control */
- pci_hose_write_config_byte(hose, dev, 0x92, 0x62); /* device control */
-
- if (te->device != 0xac56) {
- pci_hose_write_config_byte(hose, dev, 0x93, 0x21); /* async interrupt enable */
- pci_hose_write_config_word(hose, dev, 0xa8, 0x0000); /* reset GPIO */
- pci_hose_write_config_word(hose, dev, 0xac, 0x0000); /* reset GPIO */
- pci_hose_write_config_word(hose, dev, 0xaa, 0x0000); /* reset GPIO */
- pci_hose_write_config_word(hose, dev, 0xae, 0x0000); /* reset GPIO */
- } else {
- pci_hose_write_config_byte(hose, dev, 0x93, 0x20); /* */
- }
- pci_hose_write_config_word(hose, dev, 0xa4, 0x8000); /* reset power management */
-
-
- pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
- io_base &= ~0xfL;
-
- writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
- writel(0, io_base+0x10); /* CLKRUN default */
- writel(0, io_base+0x20); /* CLKRUN default */
-
-}
-
-
-static struct pci_config_table pci_sc520_spunk_config_table[] = {
- { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
- { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
- { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
-};
-
-static struct pci_controller sc520_spunk_hose = {
- fixup_irq: pci_sc520_spunk_fixup_irq,
- config_table: pci_sc520_spunk_config_table,
- first_busno: 0x00,
- last_busno: 0xff,
-};
-
-void pci_init_board(void)
-{
- pci_sc520_init(&sc520_spunk_hose);
-}
-
-
/* set up the ISA bus timing and system address mappings */
static void bus_init(void)
{
@@ -253,41 +103,41 @@ static void bus_init(void)
* ?? Hyglo version 0.97 (small board)
* 10 Spunk board
*/
- int version = read_mmcr_byte(SC520_SYSINFO);
+ int version = sc520_mmcr->sysinfo;
if (version) {
/* set up the GP IO pins (for the Spunk board) */
- write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); /* set the GPIO pin function 31-16 reg */
- write_mmcr_word(SC520_PIOPFS15_0, 0x000f); /* set the GPIO pin function 15-0 reg */
- write_mmcr_word(SC520_PIODIR31_16, 0x000f); /* set the GPIO direction 31-16 reg */
- write_mmcr_word(SC520_PIODIR15_0, 0x1ff0); /* set the GPIO direction 15-0 reg */
- write_mmcr_byte(SC520_CSPFS, 0xc0); /* set the CS pin function reg */
- write_mmcr_byte(SC520_CLKSEL, 0x70);
+ sc520_mmcr->piopfs31_16 = 0xfff0; /* set the GPIO pin function 31-16 reg */
+ sc520_mmcr->piopfs15_0 = 0x000f; /* set the GPIO pin function 15-0 reg */
+ sc520_mmcr->piodir31_16 = 0x000f; /* set the GPIO direction 31-16 reg */
+ sc520_mmcr->piodir15_0 = 0x1ff0; /* set the GPIO direction 15-0 reg */
+ sc520_mmcr->cspfs = 0xc0; /* set the CS pin function reg */
+ sc520_mmcr->clksel = 0x70;
- write_mmcr_word(SC520_PIOCLR31_16, 0x0003); /* reset SSI chip-selects */
- write_mmcr_word(SC520_PIOSET31_16, 0x000c);
+ sc520_mmcr->pioclr31_16 = 0x0003; /* reset SSI chip-selects */
+ sc520_mmcr->pioset31_16 = 0x000c;
} else {
/* set up the GP IO pins (for the Hyglo board) */
- write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); /* set the GPIO pin function 31-16 reg */
- write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f); /* set the GPIO pin function 15-0 reg */
- write_mmcr_word(SC520_PIODIR31_16, 0x003f); /* set the GPIO direction 31-16 reg */
- write_mmcr_word(SC520_PIODIR15_0, 0xe180); /* set the GPIO direction 15-0 reg */
- write_mmcr_byte(SC520_CSPFS, 0x00); /* set the CS pin function reg */
- write_mmcr_byte(SC520_CLKSEL, 0x70);
-
- write_mmcr_word(SC520_PIOCLR15_0, 0x0180); /* reset SSI chip-selects */
+ sc520_mmcr->piopfs31_16 = 0xffc0; /* set the GPIO pin function 31-16 reg */
+ sc520_mmcr->piopfs15_0 = 0x1e7f; /* set the GPIO pin function 15-0 reg */
+ sc520_mmcr->piodir31_16 = 0x003f; /* set the GPIO direction 31-16 reg */
+ sc520_mmcr->piodir15_0 = 0xe180; /* set the GPIO direction 15-0 reg */
+ sc520_mmcr->cspfs = 0x00; /* set the CS pin function reg */
+ sc520_mmcr->clksel = 0x70;
+
+ sc520_mmcr->pioclr15_0 = 0x0180; /* reset SSI chip-selects */
}
- write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */
- write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */
- write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */
- write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */
- write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */
- write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */
- write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */
+ sc520_mmcr->gpcsrt = 1; /* set the GP CS offset */
+ sc520_mmcr->gpcspw = 3; /* set the GP CS pulse width */
+ sc520_mmcr->gpcsoff = 1; /* set the GP CS offset */
+ sc520_mmcr->gprdw = 3; /* set the RD pulse width */
+ sc520_mmcr->gprdoff = 1; /* set the GP RD offset */
+ sc520_mmcr->gpwrw = 3; /* set the GP WR pulse width */
+ sc520_mmcr->gpwroff = 1; /* set the GP WR offset */
- write_mmcr_word(SC520_BOOTCSCTL, 0x0407); /* set up timing of BOOTCS */
+ sc520_mmcr->bootcsctl = 0x0407; /* set up timing of BOOTCS */
/* adjust the memory map:
* by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
@@ -296,17 +146,17 @@ static void bus_init(void)
/* bootcs */
- write_mmcr_long(SC520_PAR12, 0x8bffe800);
+ sc520_mmcr->par[12] = 0x8bffe800;
/* IDE0 = GPCS6 1f0-1f7 */
- write_mmcr_long(SC520_PAR3, 0x380801f0);
+ sc520_mmcr->par[3] = 0x380801f0;
/* IDE1 = GPCS7 3f6 */
- write_mmcr_long(SC520_PAR4, 0x3c0003f6);
+ sc520_mmcr->par[4] = 0x3c0003f6;
asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
- write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
+ sc520_mmcr->adddecctl = sc520_mmcr->adddecctl & ~(UART2_DIS|UART1_DIS);
}
@@ -331,152 +181,6 @@ static void bus_init(void)
*/
/*
- * This function should map a chunk of size bytes
- * of the system address space to the ISA bus
- *
- * The function will return the memory address
- * as seen by the host (which may very will be the
- * same as the bus address)
- */
-u32 isa_map_rom(u32 bus_addr, int size)
-{
- u32 par;
-
- printf("isa_map_rom asked to map %d bytes at %x\n",
- size, bus_addr);
-
- par = size;
- if (par < 0x80000) {
- par = 0x80000;
- }
- par >>= 12;
- par--;
- par&=0x7f;
- par <<= 18;
- par |= (bus_addr>>12);
- par |= 0x50000000;
-
- printf ("setting PAR11 to %x\n", par);
-
- /* Map rom 0x10000 with PAR1 */
- write_mmcr_long(SC520_PAR11, par);
-
- return bus_addr;
-}
-
-/*
- * this function removed any mapping created
- * with pci_get_rom_window()
- */
-void isa_unmap_rom(u32 addr)
-{
- printf("isa_unmap_rom asked to unmap %x", addr);
- if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
- write_mmcr_long(SC520_PAR11, 0);
- printf(" done\n");
- return;
- }
- printf(" not ours\n");
-}
-
-#ifdef CONFIG_PCI
-#define PCI_ROM_TEMP_SPACE 0x10000
-/*
- * This function should map a chunk of size bytes
- * of the system address space to the PCI bus,
- * suitable to map PCI ROMS (bus address < 16M)
- * the function will return the host memory address
- * which should be converted into a bus address
- * before used to configure the PCI rom address
- * decoder
- */
-u32 pci_get_rom_window(struct pci_controller *hose, int size)
-{
- u32 par;
-
- par = size;
- if (par < 0x80000) {
- par = 0x80000;
- }
- par >>= 16;
- par--;
- par&=0x7ff;
- par <<= 14;
- par |= (PCI_ROM_TEMP_SPACE>>16);
- par |= 0x72000000;
-
- printf ("setting PAR1 to %x\n", par);
-
- /* Map rom 0x10000 with PAR1 */
- write_mmcr_long(SC520_PAR1, par);
-
- return PCI_ROM_TEMP_SPACE;
-}
-
-/*
- * this function removed any mapping created
- * with pci_get_rom_window()
- */
-void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
-{
- printf("pci_remove_rom_window: %x", addr);
- if (addr == PCI_ROM_TEMP_SPACE) {
- write_mmcr_long(SC520_PAR1, 0);
- printf(" done\n");
- return;
- }
- printf(" not ours\n");
-
-}
-
-/*
- * This function is called in order to provide acces to the
- * legacy video I/O ports on the PCI bus.
- * After this function accesses to I/O ports 0x3b0-0x3bb and
- * 0x3c0-0x3df shuld result in transactions on the PCI bus.
- *
- */
-int pci_enable_legacy_video_ports(struct pci_controller *hose)
-{
- /* Map video memory to 0xa0000*/
- write_mmcr_long(SC520_PAR0, 0x7200400a);
-
- /* forward all I/O accesses to PCI */
- write_mmcr_byte(SC520_ADDDECCTL,
- read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
-
-
- /* so we map away all io ports to pci (only way to access pci io
- * below 0x400. But then we have to map back the portions that we dont
- * use so that the generate cycles on the GPIO bus where the sio and
- * ISA slots are connected, this requre the use of several PAR registers
- */
-
- /* bring 0x100 - 0x2f7 back to ISA using PAR5 */
- write_mmcr_long(SC520_PAR5, 0x31f70100);
-
- /* com2 use 2f8-2ff */
-
- /* bring 0x300 - 0x3af back to ISA using PAR7 */
- write_mmcr_long(SC520_PAR7, 0x30af0300);
-
- /* vga use 3b0-3bb */
-
- /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
- write_mmcr_long(SC520_PAR8, 0x300303bc);
-
- /* vga use 3c0-3df */
-
- /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
- write_mmcr_long(SC520_PAR9, 0x301703e0);
-
- /* com1 use 3f8-3ff */
-
- return 0;
-}
-#endif
-
-/*
* Miscelaneous platform dependent initialisations
*/
@@ -487,12 +191,12 @@ int board_init(void)
irq_init();
/* max drive current on SDRAM */
- write_mmcr_word(SC520_DSCTL, 0x0100);
+ sc520_mmcr->dsctl = 0x0100;
/* enter debug mode after next reset (only if jumper is also set) */
- write_mmcr_byte(SC520_RESCFG, 0x08);
+ sc520_mmcr->rescfg = 0x08;
/* configure the software timer to 33.000MHz */
- write_mmcr_byte(SC520_SWTMRCFG, 1);
+ sc520_mmcr->swtmrcfg = 1;
gd->bus_clk = 33000000;
return 0;
@@ -506,17 +210,15 @@ int dram_init(void)
void show_boot_progress(int val)
{
- int version = read_mmcr_byte(SC520_SYSINFO);
+ int version = sc520_mmcr->sysinfo;
if (val < -32) val = -1; /* let things compatible */
if (version == 0) {
/* PIO31-PIO16 Data */
- write_mmcr_word(SC520_PIODATA31_16,
- (read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */
+ sc520_mmcr->piodata31_16 = (sc520_mmcr->piodata31_16 & 0xffc0) | ((val&0x7e)>>1); /* 0x1f8 >> 3 */
/* PIO0-PIO15 Data */
- write_mmcr_word(SC520_PIODATA15_0,
- (read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13));
+ sc520_mmcr->piodata15_0 = (sc520_mmcr->piodata15_0 & 0x1fff)| ((val&0x7)<<13);
} else {
/* newer boards use PIO4-PIO12 */
/* PIO0-PIO15 Data */
@@ -525,8 +227,7 @@ void show_boot_progress(int val)
#else
val = (val & 0x007) | ((val & 0x07e) << 2);
#endif
- write_mmcr_word(SC520_PIODATA15_0,
- (read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4));
+ sc520_mmcr->piodata15_0 = (sc520_mmcr->piodata15_0 & 0xe00f) | ((val&0x01ff)<<4);
}
}
@@ -534,7 +235,7 @@ void show_boot_progress(int val)
int last_stage_init(void)
{
- int version = read_mmcr_byte(SC520_SYSINFO);
+ int version = sc520_mmcr->sysinfo;
printf("Omicron Ceti SC520 Spunk revision %x\n", version);
@@ -585,30 +286,30 @@ int last_stage_init(void)
void ssi_chip_select(int dev)
{
- int version = read_mmcr_byte(SC520_SYSINFO);
+ int version = sc520_mmcr->sysinfo;
if (version) {
/* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */
switch (dev) {
case 1: /* EEPROM */
- write_mmcr_word(SC520_PIOCLR31_16, 0x0004);
+ sc520_mmcr->pioclr31_16 = 0x0004;
break;
case 2: /* Temp Probe */
- write_mmcr_word(SC520_PIOSET31_16, 0x0002);
+ sc520_mmcr->pioset31_16 = 0x0002;
break;
case 3: /* CAN */
- write_mmcr_word(SC520_PIOCLR31_16, 0x0008);
+ sc520_mmcr->pioclr31_16 = 0x0008;
break;
case 4: /* AUX */
- write_mmcr_word(SC520_PIOSET31_16, 0x0001);
+ sc520_mmcr->pioset31_16 = 0x0001;
break;
case 0:
- write_mmcr_word(SC520_PIOCLR31_16, 0x0003);
- write_mmcr_word(SC520_PIOSET31_16, 0x000c);
+ sc520_mmcr->pioclr31_16 = 0x0003;
+ sc520_mmcr->pioset31_16 = 0x000c;
break;
default:
@@ -620,15 +321,15 @@ void ssi_chip_select(int dev)
switch (dev) {
case 1: /* EEPROM */
- write_mmcr_word(SC520_PIOSET15_0, 0x0100);
+ sc520_mmcr->pioset15_0 = 0x0100;
break;
case 2: /* Temp Probe */
- write_mmcr_word(SC520_PIOSET15_0, 0x0080);
+ sc520_mmcr->pioset15_0 = 0x0080;
break;
case 0:
- write_mmcr_word(SC520_PIOCLR15_0, 0x0180);
+ sc520_mmcr->pioclr15_0 = 0x0180;
break;
default:
@@ -637,12 +338,37 @@ void ssi_chip_select(int dev)
}
}
+void spi_eeprom_probe(int x)
+{
+}
+
+int spi_eeprom_read(int x, int offset, uchar *buffer, int len)
+{
+ return 0;
+}
+
+int spi_eeprom_write(int x, int offset, uchar *buffer, int len)
+{
+ return 0;
+}
+
+void mw_eeprom_probe(int x)
+{
+}
+
+int mw_eeprom_read(int x, int offset, uchar *buffer, int len)
+{
+ return 0;
+}
+
+int mw_eeprom_write(int x, int offset, uchar *buffer, int len)
+{
+ return 0;
+}
void spi_init_f(void)
{
- read_mmcr_byte(SC520_SYSINFO) ?
- spi_eeprom_probe(1) :
- mw_eeprom_probe(1);
+ sc520_mmcr->sysinfo ? spi_eeprom_probe(1) : mw_eeprom_probe(1);
}
@@ -657,7 +383,7 @@ ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
offset |= addr[i];
}
- return read_mmcr_byte(SC520_SYSINFO) ?
+ return sc520_mmcr->sysinfo ?
spi_eeprom_read(1, offset, buffer, len) :
mw_eeprom_read(1, offset, buffer, len);
}
@@ -673,7 +399,7 @@ ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
offset |= addr[i];
}
- return read_mmcr_byte(SC520_SYSINFO) ?
+ return sc520_mmcr->sysinfo ?
spi_eeprom_write(1, offset, buffer, len) :
mw_eeprom_write(1, offset, buffer, len);
}
diff --git a/board/sc520_spunk/sc520_spunk_pci.c b/board/sc520_spunk/sc520_spunk_pci.c
new file mode 100644
index 0000000000..1b5d0f17f6
--- /dev/null
+++ b/board/sc520_spunk/sc520_spunk_pci.c
@@ -0,0 +1,323 @@
+/*
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <ds1722.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+#include <asm/ic/pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ int version = sc520_mmcr->sysinfo;
+
+ /* a configurable lists of irqs to steal
+ * when we need one (a board with more pci interrupt pins
+ * would use a larger table */
+ static int irq_list[] = {
+ CONFIG_SYS_FIRST_PCI_IRQ,
+ CONFIG_SYS_SECOND_PCI_IRQ,
+ CONFIG_SYS_THIRD_PCI_IRQ,
+ CONFIG_SYS_FORTH_PCI_IRQ
+ };
+ static int next_irq_index=0;
+
+ uchar tmp_pin;
+ int pin;
+
+ pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+ pin = tmp_pin;
+
+ pin-=1; /* pci config space use 1-based numbering */
+ if (-1 == pin) {
+ return; /* device use no irq */
+ }
+
+
+ /* map device number + pin to a pin on the sc520 */
+ switch (PCI_DEV(dev)) {
+ case 6: /* ETH0 */
+ pin+=SC520_PCI_INTA;
+ break;
+
+ case 7: /* ETH1 */
+ pin+=SC520_PCI_INTB;
+ break;
+
+ case 8: /* Crypto */
+ pin+=SC520_PCI_INTC;
+ break;
+
+ case 9: /* PMC slot */
+ pin+=SC520_PCI_INTD;
+ break;
+
+ case 10: /* PC-Card */
+
+ if (version < 10) {
+ pin+=SC520_PCI_INTD;
+ } else {
+ pin+=SC520_PCI_INTC;
+ }
+ break;
+
+ default:
+ return;
+ }
+
+ pin&=3; /* wrap around */
+
+ if (sc520_pci_ints[pin] == -1) {
+ /* re-route one interrupt for us */
+ if (next_irq_index > 3) {
+ return;
+ }
+ if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+ return;
+ }
+ next_irq_index++;
+ }
+
+
+ if (-1 != sc520_pci_ints[pin]) {
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+ sc520_pci_ints[pin]);
+ }
+#if 0
+ printf("fixup_irq: device %d pin %c irq %d\n",
+ PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+#endif
+}
+
+
+static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *te)
+{
+ u32 io_base;
+ u32 temp;
+
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07); /* enable device */
+ pci_hose_write_config_byte(hose, dev, 0x0c, 0x10); /* cacheline size */
+ pci_hose_write_config_byte(hose, dev, 0x0d, 0x40); /* latency timer */
+ pci_hose_write_config_byte(hose, dev, 0x1b, 0x40); /* cardbus latency timer */
+ pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040); /* reset cardbus */
+ pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080); /* route interrupts though ExCA */
+ pci_hose_write_config_word(hose, dev, 0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
+
+ pci_hose_read_config_dword(hose, dev, 0x80, &temp); /* System control */
+ pci_hose_write_config_dword(hose, dev, 0x80, temp | 0x60); /* System control: disable clockrun */
+ /* route MF0 to ~INT and MF3 to IRQ7
+ * reserve all others */
+ pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002);
+ pci_hose_write_config_byte(hose, dev, 0x91, 0x00); /* card control */
+ pci_hose_write_config_byte(hose, dev, 0x92, 0x62); /* device control */
+
+ if (te->device != 0xac56) {
+ pci_hose_write_config_byte(hose, dev, 0x93, 0x21); /* async interrupt enable */
+ pci_hose_write_config_word(hose, dev, 0xa8, 0x0000); /* reset GPIO */
+ pci_hose_write_config_word(hose, dev, 0xac, 0x0000); /* reset GPIO */
+ pci_hose_write_config_word(hose, dev, 0xaa, 0x0000); /* reset GPIO */
+ pci_hose_write_config_word(hose, dev, 0xae, 0x0000); /* reset GPIO */
+ } else {
+ pci_hose_write_config_byte(hose, dev, 0x93, 0x20); /* */
+ }
+ pci_hose_write_config_word(hose, dev, 0xa4, 0x8000); /* reset power management */
+
+
+ pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
+ io_base &= ~0xfL;
+
+ writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
+ writel(0, io_base+0x10); /* CLKRUN default */
+ writel(0, io_base+0x20); /* CLKRUN default */
+
+}
+
+
+static struct pci_config_table pci_sc520_spunk_config_table[] = {
+ { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
+ { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
+ { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
+};
+
+static struct pci_controller sc520_spunk_hose = {
+ fixup_irq: pci_sc520_spunk_fixup_irq,
+ config_table: pci_sc520_spunk_config_table,
+ first_busno: 0x00,
+ last_busno: 0xff,
+};
+
+void pci_init_board(void)
+{
+ pci_sc520_init(&sc520_spunk_hose);
+}
+
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ *
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size)
+{
+ u32 par;
+
+ printf("isa_map_rom asked to map %d bytes at %x\n",
+ size, bus_addr);
+
+ par = size;
+ if (par < 0x80000) {
+ par = 0x80000;
+ }
+ par >>= 12;
+ par--;
+ par&=0x7f;
+ par <<= 18;
+ par |= (bus_addr>>12);
+ par |= 0x50000000;
+
+ printf ("setting PAR11 to %x\n", par);
+
+ /* Map rom 0x10000 with PAR1 */
+ sc520_mmcr->par[11] = par;
+
+ return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+ printf("isa_unmap_rom asked to unmap %x", addr);
+ if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
+ sc520_mmcr->par[11] = 0;
+ printf(" done\n");
+ return;
+ }
+ printf(" not ours\n");
+}
+
+#define PCI_ROM_TEMP_SPACE 0x10000
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size)
+{
+ u32 par;
+
+ par = size;
+ if (par < 0x80000) {
+ par = 0x80000;
+ }
+ par >>= 16;
+ par--;
+ par&=0x7ff;
+ par <<= 14;
+ par |= (PCI_ROM_TEMP_SPACE>>16);
+ par |= 0x72000000;
+
+ printf ("setting PAR1 to %x\n", par);
+
+ /* Map rom 0x10000 with PAR1 */
+ sc520_mmcr->par[1] = par;
+
+ return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+ printf("pci_remove_rom_window: %x", addr);
+ if (addr == PCI_ROM_TEMP_SPACE) {
+ sc520_mmcr->par[1] = 0;
+ printf(" done\n");
+ return;
+ }
+ printf(" not ours\n");
+
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus.
+ * After this function accesses to I/O ports 0x3b0-0x3bb and
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ *
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+ /* Map video memory to 0xa0000*/
+ sc520_mmcr->par[0] = 0x7200400a;
+
+ /* forward all I/O accesses to PCI */
+ sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
+
+
+ /* so we map away all io ports to pci (only way to access pci io
+ * below 0x400. But then we have to map back the portions that we dont
+ * use so that the generate cycles on the GPIO bus where the sio and
+ * ISA slots are connected, this requre the use of several PAR registers
+ */
+
+ /* bring 0x100 - 0x2f7 back to ISA using PAR5 */
+ sc520_mmcr->par[5] = 0x31f70100;
+
+ /* com2 use 2f8-2ff */
+
+ /* bring 0x300 - 0x3af back to ISA using PAR7 */
+ sc520_mmcr->par[7] = 0x30af0300;
+
+ /* vga use 3b0-3bb */
+
+ /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+ sc520_mmcr->par[8] = 0x300303bc;
+
+ /* vga use 3c0-3df */
+
+ /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
+ sc520_mmcr->par[9] = 0x301703e0;
+
+ /* com1 use 3f8-3ff */
+
+ return 0;
+}
diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile
index ce125e2b96..55c4d99a8f 100644
--- a/board/tqc/tqm5200/Makefile
+++ b/board/tqc/tqm5200/Makefile
@@ -41,7 +41,7 @@ distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
cam5200_flash.o: cam5200_flash.c
- $(CC) $(CFLAGS) -fno-strict-aliasing -c -o $@ $<
+ $(CC) $(CFLAGS) -c -o $@ $<
#########################################################################
generated by cgit (git 2.34.1) at 2024-12-25 21:44:00 +0000