diff options
Diffstat (limited to 'board')
170 files changed, 1648 insertions, 917 deletions
diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c index 45e78c63a3..cd484fc44b 100644 --- a/board/Arcturus/ucp1020/spl.c +++ b/board/Arcturus/ucp1020/spl.c @@ -110,7 +110,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif - initdram(); + dram_init(); #ifdef CONFIG_SPL_NAND_BOOT puts("Tertiary program loader running in sram..."); #else diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c index 3024a9c681..a00a83a4a5 100644 --- a/board/BuS/eb_cpu5282/eb_cpu5282.c +++ b/board/BuS/eb_cpu5282/eb_cpu5282.c @@ -35,7 +35,7 @@ int checkboard (void) return 0; } -int initdram(void) +int dram_init(void) { int size, i; diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c index c1120c4004..7e16aaf4b2 100644 --- a/board/a3m071/a3m071.c +++ b/board/a3m071/a3m071.c @@ -72,11 +72,11 @@ static void sdram_start(int hi_addr) #endif /* - * ATTENTION: Although partially referenced initdram does NOT make real use + * ATTENTION: Although partially referenced dram_init does NOT make real use * use of CONFIG_SYS_SDRAM_BASE. The code does not work if * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. */ -int initdram(void) +int dram_init(void) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c index d4b30fd147..6f0d4489a2 100644 --- a/board/a4m072/a4m072.c +++ b/board/a4m072/a4m072.c @@ -68,12 +68,12 @@ static void sdram_start (int hi_addr) #endif /* - * ATTENTION: Although partially referenced initdram does NOT make real use + * ATTENTION: Although partially referenced dram_init does NOT make real use * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ -int initdram(void) +int dram_init(void) { ulong dramsize = 0; uint svr, pvr; diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c index 20750fb0ce..91e96ab096 100644 --- a/board/advantech/dms-ba16/dms-ba16.c +++ b/board/advantech/dms-ba16/dms-ba16.c @@ -103,8 +103,9 @@ static void setup_iomux_enet(void) /* Reset AR8033 PHY */ gpio_direction_output(IMX_GPIO_NR(1, 28), 0); - udelay(500); + mdelay(10); gpio_set_value(IMX_GPIO_NR(1, 28), 1); + mdelay(1); } static iomux_v3_cfg_t const usdhc2_pads[] = { @@ -303,7 +304,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev) /* set debug port address: SerDes Test and System Mode Control */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); /* enable rgmii tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + /* set the reserved bits to avoid board specific voltage peak issue*/ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); return 0; } @@ -534,11 +536,61 @@ static const struct boot_mode board_boot_modes[] = { }; #endif +void pmic_init(void) +{ + +#define DA9063_ADDR 0x58 +#define BCORE2_CONF 0x9D +#define BCORE1_CONF 0x9E +#define BPRO_CONF 0x9F +#define BIO_CONF 0xA0 +#define BMEM_CONF 0xA1 +#define BPERI_CONF 0xA2 +#define MODE_BIT_H 7 +#define MODE_BIT_L 6 + + uchar val; + i2c_set_bus_num(2); + + i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1); + val |= (1 << MODE_BIT_H); + val &= ~(1 << MODE_BIT_L); + i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1); + + i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1); + val |= (1 << MODE_BIT_H); + val &= ~(1 << MODE_BIT_L); + i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1); + + i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1); + val |= (1 << MODE_BIT_H); + val &= ~(1 << MODE_BIT_L); + i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1); + + i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1); + val |= (1 << MODE_BIT_H); + val &= ~(1 << MODE_BIT_L); + i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1); + + i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1); + val |= (1 << MODE_BIT_H); + val &= ~(1 << MODE_BIT_L); + i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1); + + i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1); + val |= (1 << MODE_BIT_H); + val &= ~(1 << MODE_BIT_L); + i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1); + +} + int board_late_init(void) { #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif + +#if defined(CONFIG_VIDEO_IPUV3) /* * We need at least 200ms between power on and backlight on * as per specifications from CHI MEI @@ -555,11 +607,15 @@ int board_late_init(void) gpio_direction_output(LVDS_BACKLIGHT_GP, 1); pwm_enable(0); +#endif #ifdef CONFIG_CMD_SATA setup_ba16_sata(); #endif + /* board specific pmic init */ + pmic_init(); + return 0; } diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index cd78a147b1..36500da6f4 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -43,7 +43,7 @@ static void cram_bcr_write(u32 wr_val) return; } -int initdram(void) +int dram_init(void) { int i; u32 val; diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 453677aa66..6a50b393f4 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -438,7 +438,7 @@ int checkboard(void) } -int initdram(void) +int dram_init(void) { gd->ram_size = spd_sdram(); diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c index 725b9ca086..c73424d8c6 100644 --- a/board/amcc/bubinga/bubinga.c +++ b/board/amcc/bubinga/bubinga.c @@ -54,10 +54,10 @@ int checkboard(void) } /* ------------------------------------------------------------------------- - initdram() reads EEPROM via I2c. EEPROM contains all of + dram_init() reads EEPROM via I2c. EEPROM contains all of the necessary info for SDRAM controller configuration ------------------------------------------------------------------------- */ -int initdram(void) +int dram_init(void) { gd->ram_size = spd_sdram(); diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index 9bedb5bc8e..ea987179e7 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -30,10 +30,10 @@ extern void denali_core_search_data_eye(void); /************************************************************************* * - * initdram -- 440EPx's DDR controller is a DENALI Core + * dram_init -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ -int initdram(void) +int dram_init(void) { #if !defined(CONFIG_SYS_RAMBOOT) ulong speed = get_bus_freq(0); diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c index 2a2441e101..b21daa0af8 100644 --- a/board/amcc/walnut/walnut.c +++ b/board/amcc/walnut/walnut.c @@ -73,10 +73,10 @@ int checkboard(void) } /* - * initdram() reads EEPROM via I2c. EEPROM contains all of + * dram_init() reads EEPROM via I2c. EEPROM contains all of * the necessary info for SDRAM controller configuration */ -int initdram(void) +int dram_init(void) { gd->ram_size = spd_sdram(); diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index fde371d919..f46aacfff8 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -205,7 +205,7 @@ int checkboard(void) } /************************************************************************* - * initdram -- doesn't use serial presence detect. + * dram_init -- doesn't use serial presence detect. * * Assumes: 256 MB, ECC, non-registered * PLB @ 133 MHz @@ -286,7 +286,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value) *tr1_value = (first_good + last_bad) / 2; } -int initdram(void) +int dram_init(void) { register uint reg; int tr1_bank1, tr1_bank2; diff --git a/board/denx/m28evk/Kconfig b/board/aries/m28evk/Kconfig index dd4dc4d096..ab5577cf74 100644 --- a/board/denx/m28evk/Kconfig +++ b/board/aries/m28evk/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "m28evk" config SYS_VENDOR - default "denx" + default "aries" config SYS_SOC default "mxs" diff --git a/board/denx/m28evk/MAINTAINERS b/board/aries/m28evk/MAINTAINERS index b0535a9186..f600e7d884 100644 --- a/board/denx/m28evk/MAINTAINERS +++ b/board/aries/m28evk/MAINTAINERS @@ -1,6 +1,6 @@ M28EVK BOARD M: Marek Vasut <marek.vasut@gmail.com> S: Maintained -F: board/denx/m28evk/ +F: board/aries/m28evk/ F: include/configs/m28evk.h F: configs/m28evk_defconfig diff --git a/board/denx/m28evk/Makefile b/board/aries/m28evk/Makefile index 5e890b1eaf..5e890b1eaf 100644 --- a/board/denx/m28evk/Makefile +++ b/board/aries/m28evk/Makefile diff --git a/board/denx/m28evk/README b/board/aries/m28evk/README index cb3ae20f86..9f0d995452 100644 --- a/board/denx/m28evk/README +++ b/board/aries/m28evk/README @@ -1,12 +1,12 @@ -DENX M28EVK -=========== +Aries M28EVK +============ Files of the M28/M28EVK port ---------------------------- arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28 arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28 -board/denx/m28evk/ - M28EVK board specific files +board/aries/m28evk/ - M28EVK board specific files include/configs/m28evk.h - M28EVK configuration file Follow the instructions from doc/README.mxs to generate a bootable SD card or to diff --git a/board/denx/m28evk/m28evk.c b/board/aries/m28evk/m28evk.c index 33d38cfc54..c990ea9fec 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/aries/m28evk/m28evk.c @@ -1,5 +1,5 @@ /* - * DENX M28 module + * Aries M28 module * * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> * on behalf of DENX Software Engineering GmbH @@ -93,7 +93,7 @@ int board_mmc_init(bd_t *bis) int fecmxc_mii_postcall(int phy) { -#if defined(CONFIG_DENX_M28_V11) || defined(CONFIG_DENX_M28_V10) +#if defined(CONFIG_ARIES_M28_V11) || defined(CONFIG_ARIES_M28_V10) /* KZ8031 PHY on old boards. */ const uint32_t freq = 0x0080; #else @@ -123,7 +123,7 @@ int board_eth_init(bd_t *bis) CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, CLKCTRL_ENET_TIME_SEL_RMII_CLK); -#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10) +#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10) /* Reset the new PHY */ gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0); udelay(10000); diff --git a/board/denx/m28evk/spl_boot.c b/board/aries/m28evk/spl_boot.c index 5a1010e595..e27a74e07a 100644 --- a/board/denx/m28evk/spl_boot.c +++ b/board/aries/m28evk/spl_boot.c @@ -1,5 +1,5 @@ /* - * DENX M28 Boot setup + * ARIES M28 Boot setup * * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> * on behalf of DENX Software Engineering GmbH @@ -56,7 +56,7 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, /* UART1 */ -#ifdef CONFIG_DENX_M28_V10 +#ifdef CONFIG_ARIES_M28_V10 MX28_PAD_AUART0_CTS__DUART_RX, MX28_PAD_AUART0_RTS__DUART_TX, #else @@ -132,7 +132,7 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, -#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10) +#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10) MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */ #endif diff --git a/board/denx/m53evk/Kconfig b/board/aries/m53evk/Kconfig index 0696ad7ffb..2d49b40912 100644 --- a/board/denx/m53evk/Kconfig +++ b/board/aries/m53evk/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "m53evk" config SYS_VENDOR - default "denx" + default "aries" config SYS_SOC default "mx5" diff --git a/board/denx/m53evk/MAINTAINERS b/board/aries/m53evk/MAINTAINERS index 5d8c76455c..71137f0802 100644 --- a/board/denx/m53evk/MAINTAINERS +++ b/board/aries/m53evk/MAINTAINERS @@ -1,6 +1,6 @@ M53EVK BOARD M: Marek Vasut <marek.vasut@gmail.com> S: Maintained -F: board/denx/m53evk/ +F: board/aries/m53evk/ F: include/configs/m53evk.h F: configs/m53evk_defconfig diff --git a/board/denx/m53evk/Makefile b/board/aries/m53evk/Makefile index 19b8977ae7..daa0fe4dd9 100644 --- a/board/denx/m53evk/Makefile +++ b/board/aries/m53evk/Makefile @@ -1,5 +1,5 @@ # -# DENX M53EVK +# Aries M53EVK # Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> # # SPDX-License-Identifier: GPL-2.0+ diff --git a/board/denx/m53evk/imximage.cfg b/board/aries/m53evk/imximage.cfg index c0e2602950..ec855c835d 100644 --- a/board/denx/m53evk/imximage.cfg +++ b/board/aries/m53evk/imximage.cfg @@ -1,5 +1,5 @@ /* - * DENX M53 DRAM init values + * Aries M53 DRAM init values * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/denx/m53evk/m53evk.c b/board/aries/m53evk/m53evk.c index 1e4db24c89..14c60fc539 100644 --- a/board/denx/m53evk/m53evk.c +++ b/board/aries/m53evk/m53evk.c @@ -1,5 +1,5 @@ /* - * DENX M53 module + * Aries M53 module * * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> * @@ -381,7 +381,7 @@ int board_init(void) int checkboard(void) { - puts("Board: DENX M53EVK\n"); + puts("Board: Aries M53EVK\n"); return 0; } diff --git a/board/denx/mcvevk/MAINTAINERS b/board/aries/mcvevk/MAINTAINERS index 6787727d84..c3a3a2b87d 100644 --- a/board/denx/mcvevk/MAINTAINERS +++ b/board/aries/mcvevk/MAINTAINERS @@ -1,5 +1,5 @@ -SOCKIT BOARD -M: Marek Vasut <marex@denx.de> +Aries MCVEVK BOARD +M: Marek Vasut <marek.vasut@gmail.com> S: Maintained F: include/configs/socfpga_mcvevk.h F: configs/socfpga_mcvevk_defconfig diff --git a/board/denx/mcvevk/Makefile b/board/aries/mcvevk/Makefile index 86f9b78cad..86f9b78cad 100644 --- a/board/denx/mcvevk/Makefile +++ b/board/aries/mcvevk/Makefile diff --git a/board/denx/mcvevk/qts/iocsr_config.h b/board/aries/mcvevk/qts/iocsr_config.h index 3021830d00..3021830d00 100644 --- a/board/denx/mcvevk/qts/iocsr_config.h +++ b/board/aries/mcvevk/qts/iocsr_config.h diff --git a/board/denx/mcvevk/qts/pinmux_config.h b/board/aries/mcvevk/qts/pinmux_config.h index ea2f7ab3b3..ea2f7ab3b3 100644 --- a/board/denx/mcvevk/qts/pinmux_config.h +++ b/board/aries/mcvevk/qts/pinmux_config.h diff --git a/board/denx/mcvevk/qts/pll_config.h b/board/aries/mcvevk/qts/pll_config.h index b718b39e96..b718b39e96 100644 --- a/board/denx/mcvevk/qts/pll_config.h +++ b/board/aries/mcvevk/qts/pll_config.h diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/aries/mcvevk/qts/sdram_config.h index ff64f555c0..ff64f555c0 100644 --- a/board/denx/mcvevk/qts/sdram_config.h +++ b/board/aries/mcvevk/qts/sdram_config.h diff --git a/board/denx/mcvevk/socfpga.c b/board/aries/mcvevk/socfpga.c index 6be58f047f..6be58f047f 100644 --- a/board/denx/mcvevk/socfpga.c +++ b/board/aries/mcvevk/socfpga.c diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c index da281e87fc..d011ae5723 100644 --- a/board/astro/mcf5373l/mcf5373l.c +++ b/board/astro/mcf5373l/mcf5373l.c @@ -27,7 +27,7 @@ int checkboard(void) return 0; } -int initdram(void) +int dram_init(void) { #if !defined(CONFIG_MONITOR_IS_IN_RAM) sdram_t *sdp = (sdram_t *)(MMAP_SDRAM); diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index fc4f50d219..58da2d27f8 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -71,10 +71,10 @@ static void at91sam9n12ek_nand_hw_init(void) /* Configure ENABLE pin for NandFlash */ at91_set_pio_output(AT91_PIO_PORTD, 4, 1); - at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ - at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ - at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */ - at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */ } #endif @@ -194,7 +194,7 @@ void at91sam9n12ek_ks8851_hw_init(void) &smc->cs[2].mode); /* Configure NCS2 PIN */ - at91_set_b_periph(AT91_PIO_PORTD, 19, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0); } #endif diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index b0d440d728..cc81776f9b 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -77,18 +77,18 @@ static void at91sam9x5ek_nand_hw_init(void) /* Enable NandFlash */ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); - at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ - at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ - at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ - at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ - at91_set_a_periph(AT91_PIO_PORTD, 6, 1); - at91_set_a_periph(AT91_PIO_PORTD, 7, 1); - at91_set_a_periph(AT91_PIO_PORTD, 8, 1); - at91_set_a_periph(AT91_PIO_PORTD, 9, 1); - at91_set_a_periph(AT91_PIO_PORTD, 10, 1); - at91_set_a_periph(AT91_PIO_PORTD, 11, 1); - at91_set_a_periph(AT91_PIO_PORTD, 12, 1); - at91_set_a_periph(AT91_PIO_PORTD, 13, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); } #endif @@ -128,49 +128,49 @@ vidinfo_t panel_info = { void lcd_enable(void) { if (has_lcdc()) - at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */ } void lcd_disable(void) { if (has_lcdc()) - at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */ } static void at91sam9x5ek_lcd_hw_init(void) { if (has_lcdc()) { - at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ - at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */ - at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ - at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */ - - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ - at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ - at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ - at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ - at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */ + + at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ at91_periph_clk_enable(ATMEL_ID_LCDC); } diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index ce67478f0b..134c2fe1eb 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -95,31 +95,31 @@ static void sama5d3xek_nor_hw_init(void) &smc->cs[0].mode); /* Address pin (A1 ~ A23) configuration */ - at91_set_a_periph(AT91_PIO_PORTE, 1, 0); - at91_set_a_periph(AT91_PIO_PORTE, 2, 0); - at91_set_a_periph(AT91_PIO_PORTE, 3, 0); - at91_set_a_periph(AT91_PIO_PORTE, 4, 0); - at91_set_a_periph(AT91_PIO_PORTE, 5, 0); - at91_set_a_periph(AT91_PIO_PORTE, 6, 0); - at91_set_a_periph(AT91_PIO_PORTE, 7, 0); - at91_set_a_periph(AT91_PIO_PORTE, 8, 0); - at91_set_a_periph(AT91_PIO_PORTE, 9, 0); - at91_set_a_periph(AT91_PIO_PORTE, 10, 0); - at91_set_a_periph(AT91_PIO_PORTE, 11, 0); - at91_set_a_periph(AT91_PIO_PORTE, 12, 0); - at91_set_a_periph(AT91_PIO_PORTE, 13, 0); - at91_set_a_periph(AT91_PIO_PORTE, 14, 0); - at91_set_a_periph(AT91_PIO_PORTE, 15, 0); - at91_set_a_periph(AT91_PIO_PORTE, 16, 0); - at91_set_a_periph(AT91_PIO_PORTE, 17, 0); - at91_set_a_periph(AT91_PIO_PORTE, 18, 0); - at91_set_a_periph(AT91_PIO_PORTE, 19, 0); - at91_set_a_periph(AT91_PIO_PORTE, 20, 0); - at91_set_a_periph(AT91_PIO_PORTE, 21, 0); - at91_set_a_periph(AT91_PIO_PORTE, 22, 0); - at91_set_a_periph(AT91_PIO_PORTE, 23, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0); /* CS0 pin configuration */ - at91_set_a_periph(AT91_PIO_PORTE, 26, 0); + at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0); } #endif @@ -170,14 +170,14 @@ static void sama5d3xek_lcd_hw_init(void) gd->fb_base = CONFIG_SAMA5D3_LCD_BASE; /* The higher 8 bit of LCD is board related */ - at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */ - at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */ - at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */ - at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */ - at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */ - at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */ - at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */ - at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */ + at91_pio3_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */ + at91_pio3_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */ + at91_pio3_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */ + at91_pio3_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */ + at91_pio3_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */ + at91_pio3_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */ /* Configure lower 16 bit of LCD and enable clock */ at91_lcd_hw_init(); diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 23ec274468..94ecab28b9 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -10,52 +10,18 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/atmel_mpddrc.h> -#include <asm/arch/atmel_usba_udc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <asm/arch/sama5d3_smc.h> #include <asm/arch/sama5d4.h> #include <atmel_hlcdc.h> -#include <atmel_mci.h> +#include <debug_uart.h> #include <lcd.h> -#include <mmc.h> -#include <net.h> -#include <netdev.h> #include <nand.h> -#include <spi.h> #include <version.h> DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_ATMEL_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - at91_set_pio_output(AT91_PIO_PORTC, 3, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); -} - -static void sama5d4_xplained_spi0_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ - - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_SPI0); -} -#endif /* CONFIG_ATMEL_SPI */ - #ifdef CONFIG_NAND_ATMEL static void sama5d4_xplained_nand_hw_init(void) { @@ -82,20 +48,20 @@ static void sama5d4_xplained_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ - at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ - at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ - at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ - at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ - at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ - at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ - at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ - at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ - at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ } #endif @@ -134,39 +100,39 @@ unsigned int has_lcdc(void) static void sama5d4_xplained_lcd_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ - at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ - at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ - - at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ - - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ - - at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ - at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ - at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ - at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_LCDC); @@ -200,109 +166,46 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD */ -#ifdef CONFIG_GENERIC_ATMEL_MCI -void sama5d4_xplained_mci1_hw_init(void) +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void sama5d4_xplained_serial3_hw_init(void) { - at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ - at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ - at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ - at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ - at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ - at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ - - /* - * As the mci io internal pull down is too strong, so if the io needs - * external pull up, the pull up resistor will be very small, if so - * the power consumption will increase, so disable the interanl pull - * down to save the power. - */ - at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_MCI1); -} - -int board_mmc_init(bd_t *bis) -{ - /* Enable the power supply */ - at91_set_pio_output(AT91_PIO_PORTE, 4, 0); - - return atmel_mci_init((void *)ATMEL_BASE_MCI1); + at91_periph_clk_enable(ATMEL_ID_USART3); } -#endif /* CONFIG_GENERIC_ATMEL_MCI */ -#ifdef CONFIG_MACB -void sama5d4_xplained_macb0_hw_init(void) +void board_debug_uart_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_GMAC0); + sama5d4_xplained_serial3_hw_init(); } #endif -static void sama5d4_xplained_serial3_hw_init(void) -{ - at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ - at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_USART3); -} - +#ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIOD); - at91_periph_clk_enable(ATMEL_ID_PIOE); - - sama5d4_xplained_serial3_hw_init(); - +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif return 0; } +#endif int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -#ifdef CONFIG_ATMEL_SPI - sama5d4_xplained_spi0_hw_init(); -#endif #ifdef CONFIG_NAND_ATMEL sama5d4_xplained_nand_hw_init(); #endif -#ifdef CONFIG_GENERIC_ATMEL_MCI - sama5d4_xplained_mci1_hw_init(); -#endif -#ifdef CONFIG_MACB - sama5d4_xplained_macb0_hw_init(); -#endif #ifdef CONFIG_LCD sama5d4_xplained_lcd_hw_init(); #endif #ifdef CONFIG_CMD_USB sama5d4_xplained_usb_hw_init(); #endif -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - at91_udp_hw_init(); -#endif return 0; } @@ -314,34 +217,12 @@ int dram_init(void) return 0; } -int board_eth_init(bd_t *bis) -{ - int rc = 0; - -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); -#endif - -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - usba_udc_probe(&pdata); -#ifdef CONFIG_USB_ETH_RNDIS - usb_eth_initialize(bis); -#endif -#endif - - return rc; -} - /* SPL */ #ifdef CONFIG_SPL_BUILD void spl_board_init(void) { -#ifdef CONFIG_SYS_USE_MMC - sama5d4_xplained_mci1_hw_init(); -#elif CONFIG_SYS_USE_NANDFLASH +#if CONFIG_SYS_USE_NANDFLASH sama5d4_xplained_nand_hw_init(); -#elif CONFIG_SYS_USE_SERIALFLASH - sama5d4_xplained_spi0_hw_init(); #endif } diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index 72bad23087..ffb4a50a72 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -10,52 +10,18 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/atmel_mpddrc.h> -#include <asm/arch/atmel_usba_udc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <asm/arch/sama5d3_smc.h> #include <asm/arch/sama5d4.h> #include <atmel_hlcdc.h> -#include <atmel_mci.h> +#include <debug_uart.h> #include <lcd.h> -#include <mmc.h> -#include <net.h> -#include <netdev.h> #include <nand.h> -#include <spi.h> #include <version.h> DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_ATMEL_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - at91_set_pio_output(AT91_PIO_PORTC, 3, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); -} - -static void sama5d4ek_spi0_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ - - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_SPI0); -} -#endif /* CONFIG_ATMEL_SPI */ - #ifdef CONFIG_NAND_ATMEL static void sama5d4ek_nand_hw_init(void) { @@ -82,20 +48,20 @@ static void sama5d4ek_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ - at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ - at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ - at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ - at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ - at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ - at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ - at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ - at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ - at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ } #endif @@ -135,33 +101,33 @@ unsigned int has_lcdc(void) static void sama5d4ek_lcd_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ - at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ - at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ - - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ - - at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ - - at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ - at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_LCDC); @@ -196,109 +162,46 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD */ -#ifdef CONFIG_GENERIC_ATMEL_MCI -void sama5d4ek_mci1_hw_init(void) +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void sama5d4ek_serial3_hw_init(void) { - at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ - at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ - at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ - at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ - at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ - at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ - - /* - * As the mci io internal pull down is too strong, so if the io needs - * external pull up, the pull up resistor will be very small, if so - * the power consumption will increase, so disable the interanl pull - * down to save the power. - */ - at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_MCI1); -} - -int board_mmc_init(bd_t *bis) -{ - /* Enable power for MCI1 interface */ - at91_set_pio_output(AT91_PIO_PORTE, 15, 0); - - return atmel_mci_init((void *)ATMEL_BASE_MCI1); + at91_periph_clk_enable(ATMEL_ID_USART3); } -#endif /* CONFIG_GENERIC_ATMEL_MCI */ -#ifdef CONFIG_MACB -void sama5d4ek_macb0_hw_init(void) +void board_debug_uart_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_GMAC0); + sama5d4ek_serial3_hw_init(); } #endif -static void sama5d4ek_serial3_hw_init(void) -{ - at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ - at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_USART3); -} - +#ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIOD); - at91_periph_clk_enable(ATMEL_ID_PIOE); - - sama5d4ek_serial3_hw_init(); - +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif return 0; } +#endif int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -#ifdef CONFIG_ATMEL_SPI - sama5d4ek_spi0_hw_init(); -#endif #ifdef CONFIG_NAND_ATMEL sama5d4ek_nand_hw_init(); #endif -#ifdef CONFIG_GENERIC_ATMEL_MCI - sama5d4ek_mci1_hw_init(); -#endif -#ifdef CONFIG_MACB - sama5d4ek_macb0_hw_init(); -#endif #ifdef CONFIG_LCD sama5d4ek_lcd_hw_init(); #endif #ifdef CONFIG_CMD_USB sama5d4ek_usb_hw_init(); #endif -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - at91_udp_hw_init(); -#endif return 0; } @@ -310,34 +213,12 @@ int dram_init(void) return 0; } -int board_eth_init(bd_t *bis) -{ - int rc = 0; - -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); -#endif - -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - usba_udc_probe(&pdata); -#ifdef CONFIG_USB_ETH_RNDIS - usb_eth_initialize(bis); -#endif -#endif - - return rc; -} - /* SPL */ #ifdef CONFIG_SPL_BUILD void spl_board_init(void) { -#ifdef CONFIG_SYS_USE_MMC - sama5d4ek_mci1_hw_init(); -#elif CONFIG_SYS_USE_NANDFLASH +#if CONFIG_SYS_USE_NANDFLASH sama5d4ek_nand_hw_init(); -#elif CONFIG_SYS_USE_SERIALFLASH - sama5d4ek_spi0_hw_init(); #endif } diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c index 41194ecb7e..54de0e2673 100644 --- a/board/canmb/canmb.c +++ b/board/canmb/canmb.c @@ -62,12 +62,12 @@ static void sdram_start (int hi_addr) #endif /* - * ATTENTION: Although partially referenced initdram does NOT make real use + * ATTENTION: Although partially referenced dram_init does NOT make real use * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ -int initdram(void) +int dram_init(void) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index be0d65c694..7b862355c8 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -97,7 +97,7 @@ static mem_conf_t* get_mem_config(int board_type) /* * Initalize SDRAM - configure SDRAM controller, detect memory size. */ -int initdram(void) +int dram_init(void) { ulong dramsize = 0; #ifndef CONFIG_SYS_RAMBOOT diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c index 48366763c1..0ceaa1f772 100644 --- a/board/cobra5272/cobra5272.c +++ b/board/cobra5272/cobra5272.c @@ -17,7 +17,7 @@ int checkboard (void) return 0; }; -int initdram(void) +int dram_init(void) { volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM); diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index f0be2cbb9b..e3441cad4e 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; -int initdram(void) +int dram_init(void) { gd->ram_size = fixed_sdram(NULL, NULL, 0); diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c index ea7cb744db..81285d7470 100644 --- a/board/dbau1x00/dbau1x00.c +++ b/board/dbau1x00/dbau1x00.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; -int initdram(void) +int dram_init(void) { /* Sdram is setup by assembler code */ /* If memory could be changed, we should return the true value here */ diff --git a/board/denx/ma5d4evk/ma5d4evk.c b/board/denx/ma5d4evk/ma5d4evk.c index ec0fa28f3e..81463712fa 100644 --- a/board/denx/ma5d4evk/ma5d4evk.c +++ b/board/denx/ma5d4evk/ma5d4evk.c @@ -44,9 +44,9 @@ void spi_cs_deactivate(struct spi_slave *slave) static void ma5d4evk_spi0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ @@ -90,39 +90,39 @@ unsigned int has_lcdc(void) static void ma5d4evk_lcd_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */ - at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ - at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */ - - at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ - - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ - - at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ - at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ - at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ - at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_LCDC); @@ -134,16 +134,16 @@ static void ma5d4evk_lcd_hw_init(void) /* On-SoM eMMC */ void ma5d4evk_mci0_hw_init(void) { - at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */ - at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */ - at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */ - at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */ - at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */ - at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */ - at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */ - at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */ - at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */ - at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */ /* * As the mci io internal pull down is too strong, so if the io needs @@ -151,16 +151,16 @@ void ma5d4evk_mci0_hw_init(void) * the power consumption will increase, so disable the internal pull * down to save the power. */ - at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0); /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_MCI0); @@ -169,12 +169,12 @@ void ma5d4evk_mci0_hw_init(void) /* On-board MicroSD slot */ void ma5d4evk_mci1_hw_init(void) { - at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ - at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ - at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ - at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ - at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ - at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ + at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ /* * As the mci io internal pull down is too strong, so if the io needs @@ -182,16 +182,16 @@ void ma5d4evk_mci1_hw_init(void) * the power consumption will increase, so disable the internal pull * down to save the power. */ - at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); /* Deal with WP pin on the microSD slot. */ at91_set_pio_output(AT91_PIO_PORTE, 16, 0); - at91_set_pio_pulldown(AT91_PIO_PORTE, 16, 1); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 16, 1); /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_MCI1); @@ -203,7 +203,7 @@ int board_mmc_init(bd_t *bis) /* De-assert reset on On-SoM eMMC */ at91_set_pio_output(AT91_PIO_PORTE, 15, 1); - at91_set_pio_pulldown(AT91_PIO_PORTE, 15, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 15, 0); ret = atmel_mci_init((void *)ATMEL_BASE_MCI0); if (ret) /* eMMC init failed, skip it. */ @@ -223,16 +223,16 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_MACB void ma5d4evk_macb0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_GMAC0); @@ -242,17 +242,17 @@ void ma5d4evk_macb0_hw_init(void) static void ma5d4evk_serial_hw_init(void) { /* USART0 */ - at91_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */ - at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */ - at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */ at91_periph_clk_enable(ATMEL_ID_USART0); /* USART1 */ - at91_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */ - at91_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */ - at91_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */ at91_periph_clk_enable(ATMEL_ID_USART1); } @@ -273,7 +273,7 @@ int board_early_init_f(void) at91_set_pio_output(AT91_PIO_PORTB, 21, 0); udelay(100); at91_set_pio_output(AT91_PIO_PORTB, 21, 1); - at91_set_pio_pulldown(AT91_PIO_PORTB, 21, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTB, 21, 0); ma5d4evk_serial_hw_init(); diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c index 80963fefa5..66dc407bae 100644 --- a/board/esd/mecp5123/mecp5123.c +++ b/board/esd/mecp5123/mecp5123.c @@ -62,7 +62,7 @@ int board_early_init_f(void) return 0; } -int initdram(void) +int dram_init(void) { gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0)); diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c index e962d4c4bb..c379e7723d 100644 --- a/board/esd/pmc440/sdram.c +++ b/board/esd/pmc440/sdram.c @@ -42,7 +42,7 @@ struct sdram_conf_s sdram_conf[] = { }; /* - * initdram -- 440EPx's DDR controller is a DENALI Core + * dram_init -- 440EPx's DDR controller is a DENALI Core */ int initdram_by_rb(int rows, int banks) { @@ -107,7 +107,7 @@ int initdram_by_rb(int rows, int banks) return 0; } -int initdram(void) +int dram_init(void) { phys_size_t size; int n; diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index 0e7f8b130a..36a55195df 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; void ddr_enable_ecc(unsigned int dram_size); -int initdram(void) +int dram_init(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index 085323132c..5cc2f73a16 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -176,7 +176,7 @@ found: popts->cpo_sample = 0x3e; } -int initdram(void) +int dram_init(void) { phys_size_t dram_size; diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c index a27ad7fa84..60d7f0d48a 100644 --- a/board/freescale/b4860qds/spl.c +++ b/board/freescale/b4860qds/spl.c @@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) puts("\n\n"); - initdram(); + dram_init(); #ifdef CONFIG_SPL_NAND_BOOT nand_boot(); diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c index 86d55bf2ac..94093f11a8 100644 --- a/board/freescale/c29xpcie/spl.c +++ b/board/freescale/c29xpcie/spl.c @@ -67,7 +67,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) i2c_init_all(); - initdram(); + dram_init(); #ifdef CONFIG_SPL_NAND_BOOT puts("TPL\n"); diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index ad93abf9f4..496d8415ec 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -260,7 +260,7 @@ found: popts->ddr_cdr1 = DDR_CDR1_DHC_EN; } -int initdram(void) +int dram_init(void) { phys_size_t dram_size; diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 3bf2e49762..d16a69fc98 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -164,7 +164,7 @@ void board_mem_sleep_setup(void) } #endif -int initdram(void) +int fsl_initdram(void) { phys_size_t dram_size; diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 909fc56275..d81d8abc9b 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -162,7 +162,7 @@ int dram_init(void) * before accessing DDR SPD. */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); - return initdram(); + return fsl_initdram(); } #ifdef CONFIG_FSL_ESDHC diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index db350e27b8..2643f5bf4a 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -108,7 +108,7 @@ found: #endif } -int initdram(void) +int fsl_initdram(void) { phys_size_t dram_size; diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 538bba53da..2df63e468d 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -7,6 +7,7 @@ #include <common.h> #include <i2c.h> #include <fdt_support.h> +#include <fsl_ddr_sdram.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> @@ -153,7 +154,7 @@ int dram_init(void) * before accessing DDR SPD. */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); - initdram(); + fsl_initdram(); #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 2f133db0a6..36d27ecfae 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -170,7 +170,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, } #endif -int initdram(void) +int fsl_initdram(void) { phys_size_t dram_size; diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index 481ed44046..d37af34a9c 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -92,7 +92,7 @@ found: popts->cpo_sample = 0x70; } -int initdram(void) +int fsl_initdram(void) { phys_size_t dram_size; diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 6238852af5..69fc15b681 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -7,6 +7,7 @@ #include <common.h> #include <i2c.h> #include <fdt_support.h> +#include <fsl_ddr_sdram.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> @@ -149,7 +150,7 @@ int dram_init(void) * before accessing DDR SPD. */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); - initdram(); + fsl_initdram(); #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index d1290e27f8..a16f7bc83a 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -96,7 +96,7 @@ found: popts->cpo_sample = 0x70; } -int initdram(void) +int fsl_initdram(void) { phys_size_t dram_size; diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c index d340c4162d..9d176d3851 100644 --- a/board/freescale/ls2080a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -158,7 +158,8 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, return 0; } #endif -int initdram(void) + +int fsl_initdram(void) { puts("Initializing DDR...."); diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index 1e9145d6ab..22a2676a95 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -155,7 +155,7 @@ found: } } -int initdram(void) +int fsl_initdram(void) { #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) gd->ram_size = fsl_ddr_sdram_size(); diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index 029ea61b95..7002dfb236 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -158,7 +158,7 @@ found: } } -int initdram(void) +int fsl_initdram(void) { #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) gd->ram_size = fsl_ddr_sdram_size(); diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c index edf486acc8..4b841c6221 100644 --- a/board/freescale/m5208evbe/m5208evbe.c +++ b/board/freescale/m5208evbe/m5208evbe.c @@ -22,7 +22,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c index 2873643582..e4dfb6fda0 100644 --- a/board/freescale/m52277evb/m52277evb.c +++ b/board/freescale/m52277evb/m52277evb.c @@ -21,7 +21,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { u32 dramsize; diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c index 1d82e93786..93403f6748 100644 --- a/board/freescale/m5235evb/m5235evb.c +++ b/board/freescale/m5235evb/m5235evb.c @@ -22,7 +22,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); gpio_t *gpio = (gpio_t *)(MMAP_GPIO); diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index d3c2acd089..7c9b599d66 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -31,7 +31,7 @@ int checkboard (void) { }; -int initdram(void) +int dram_init(void) { unsigned long junk = 0xa5a59696; diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 1c100e6d8c..c2cc2d76e4 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -22,7 +22,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { u32 dramsize = 0; diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c index eae499fa9d..c1ed431190 100644 --- a/board/freescale/m5253evbe/m5253evbe.c +++ b/board/freescale/m5253evbe/m5253evbe.c @@ -21,7 +21,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { /* * Check to see if the SDRAM has already been initialized diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c index bbe06ba9df..efff465d0f 100644 --- a/board/freescale/m5272c3/m5272c3.c +++ b/board/freescale/m5272c3/m5272c3.c @@ -19,7 +19,7 @@ int checkboard (void) { return 0; }; -int initdram(void) +int dram_init(void) { sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c index 48ad4a86b9..5a9831d619 100644 --- a/board/freescale/m5275evb/m5275evb.c +++ b/board/freescale/m5275evb/m5275evb.c @@ -25,7 +25,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM); gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c index 7f3c04c379..eb618b54f4 100644 --- a/board/freescale/m5282evb/m5282evb.c +++ b/board/freescale/m5282evb/m5282evb.c @@ -16,7 +16,7 @@ int checkboard (void) return 0; } -int initdram(void) +int dram_init(void) { u32 dramsize, i, dramclk; diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c index b0c27b4967..71cca35e02 100644 --- a/board/freescale/m53017evb/m53017evb.c +++ b/board/freescale/m53017evb/m53017evb.c @@ -22,7 +22,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index 5609a7b376..4e0b4e4bd8 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -22,7 +22,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c index 48a262c12f..f2ed298f0f 100644 --- a/board/freescale/m5373evb/m5373evb.c +++ b/board/freescale/m5373evb/m5373evb.c @@ -22,7 +22,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c index 3f1100c355..433539486e 100644 --- a/board/freescale/m54418twr/m54418twr.c +++ b/board/freescale/m54418twr/m54418twr.c @@ -25,7 +25,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { u32 dramsize; diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c index 653a11352c..050624bf92 100644 --- a/board/freescale/m54451evb/m54451evb.c +++ b/board/freescale/m54451evb/m54451evb.c @@ -26,7 +26,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { u32 dramsize; #ifdef CONFIG_CF_SBF diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index b9850c1a2a..d6b0650b99 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -22,7 +22,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { u32 dramsize; #ifdef CONFIG_CF_SBF diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c index fc674522f6..d28f43da04 100644 --- a/board/freescale/m547xevb/m547xevb.c +++ b/board/freescale/m547xevb/m547xevb.c @@ -23,7 +23,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { siu_t *siu = (siu_t *) (MMAP_SIU); sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c index c268ec6a60..56060b68b6 100644 --- a/board/freescale/m548xevb/m548xevb.c +++ b/board/freescale/m548xevb/m548xevb.c @@ -23,7 +23,7 @@ int checkboard(void) return 0; }; -int initdram(void) +int dram_init(void) { siu_t *siu = (siu_t *) (MMAP_SIU); sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index a0e5d91c8f..f87579f193 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -95,7 +95,7 @@ int is_micron(void){ return(ismicron); } -int initdram(void) +int dram_init(void) { u32 msize = 0; /* diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c index aac56c3983..81e155a401 100644 --- a/board/freescale/mpc8308rdb/sdram.c +++ b/board/freescale/mpc8308rdb/sdram.c @@ -65,7 +65,7 @@ static long fixed_sdram(void) return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); } -int initdram(void) +int dram_init(void) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize; diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index e3a5941f20..8974378326 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -134,7 +134,7 @@ void board_init_f(ulong bootflag) CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); puts("NAND boot... "); timer_init(); - initdram(); + dram_init(); relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd, CONFIG_SYS_NAND_U_BOOT_RELOC); } diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 4e5dfe6f15..a4128cbd11 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -97,7 +97,7 @@ static long fixed_sdram(void) return msize; } -int initdram(void) +int dram_init(void) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; volatile fsl_lbc_t *lbc = &im->im_lbc; diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index 7779b6daed..22f1565b4c 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -222,7 +222,7 @@ void board_init_f(ulong bootflag) CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); puts("NAND boot... "); timer_init(); - initdram(); + dram_init(); relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, CONFIG_SYS_NAND_U_BOOT_RELOC); } diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index 947ffabbb5..b69c86bb81 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -92,7 +92,7 @@ static long fixed_sdram(void) } #endif /* CONFIG_SYS_RAMBOOT */ -int initdram(void) +int dram_init(void) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; u32 msize; diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index e7d8b99738..f30a1510ee 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -70,7 +70,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { int fixed_sdram(void); -int initdram(void) +int dram_init(void) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c index 907ad09dc8..b49e03e4f9 100644 --- a/board/freescale/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -90,7 +90,7 @@ int board_early_init_r(void) int fixed_sdram(void); -int initdram(void) +int dram_init(void) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 595bce16d1..5f502e2a65 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -48,7 +48,7 @@ int board_early_init_f (void) #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) -int initdram(void) +int dram_init(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; phys_size_t msize = 0; diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 27f0ccd9a6..895e9ffda6 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -118,7 +118,7 @@ volatile static struct pci_controller hose[] = { }; #endif /* CONFIG_PCI */ -int initdram(void) +int dram_init(void) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index a3af246854..233049227f 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -218,7 +218,7 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif int fixed_sdram(void); -int initdram(void) +int dram_init(void) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 2f5431ee21..319f0479e2 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -62,7 +62,7 @@ void ddr_enable_ecc(unsigned int dram_size); #endif int fixed_sdram(void); -int initdram(void) +int dram_init(void) { immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 0422208133..d97562c849 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -118,7 +118,7 @@ int checkboard(void) } -int initdram(void) +int dram_init(void) { phys_size_t dram_size = 0; diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 07cb08b6b8..2604a51e91 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -39,7 +39,7 @@ int checkboard(void) return 0; } -int initdram(void) +int dram_init(void) { phys_size_t dram_size = 0; diff --git a/board/freescale/mx6sabresd/README b/board/freescale/mx6sabresd/README index 5814b9d380..bc0c0d0d16 100644 --- a/board/freescale/mx6sabresd/README +++ b/board/freescale/mx6sabresd/README @@ -1,17 +1,19 @@ How to use and build U-Boot on mx6sabresd: ---------------------------------- -Currently there are three methods for booting mx6sabresd boards: +Currently there are four methods for booting mx6sabresd boards: -1. Booting via Normal U-Boot (u-boot.imx) +1. Booting from SD card via normal U-Boot (u-boot.imx) -2. Booting via SPL (SPL and u-boot.img) +2. Booting from eMMC via normal U-Boot -3. Booting via Falcon mode (SPL launches the kernel directly) +3. Booting via SPL (SPL and u-boot.img) +4. Booting via Falcon mode (SPL launches the kernel directly) -1. Booting via Normal U-Boot ----------------------------- + +1. Booting from SD card via normal U-Boot +----------------------------------------- $ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd) @@ -28,7 +30,44 @@ This will generate the image called u-boot.imx. $ sudo dd if=u-boot.imx of=/dev/sdb bs=1K seek=1 && sync -2. Booting via SPL +2. Booting from eMMC via normal U-Boot +-------------------------------------- + +$ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd) + +or + +$ make mx6dlsabresd_defconfig (If you want to build for mx6dlsabresd) + +$ make + +This will generate the image called u-boot.imx. + +- Flash the u-boot.imx binary into the eMMC: + +Set SW6 to download mode: 00001100 + +Plug a usb cable to USB-OTG and load the u-boot image using the imx_usb_loader +tool (https://github.com/boundarydevices/imx_usb_loader): + +$ sudo ./imx_usb u-boot.imx + +In U-boot change the eMMC partition config: + +=> mmc partconf 2 1 0 0 + +Mount the eMMC in the host PC: + +=> ums 0 mmc 2 + +Flash the u-boot.imx binary + +$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1 && sync + +Set SW6 to eMMC 8-bit boot: 11010110 + + +3. Booting via SPL ------------------ Other method for building U-Boot on mx6qsabresd and mx6qpsabresd is @@ -48,7 +87,7 @@ $ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync $ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 && sync -3. Booting via Falcon mode +4. Booting via Falcon mode -------------------------- $ make mx6sabresd_spl_defconfig diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 96c0e8cfc7..d49543315b 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -47,11 +47,6 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ @@ -155,157 +150,55 @@ static void setup_iomux_fec(void) imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); /* Power up LAN8720 PHY */ + gpio_request(ETH_PHY_POWER, "eth_pwr"); gpio_direction_output(ETH_PHY_POWER , 1); udelay(15000); } -#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) -#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) -#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) - -static struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC1_BASE_ADDR}, - {USDHC2_BASE_ADDR, 0, 4}, - {USDHC3_BASE_ADDR, 0, 4}, -}; - int board_mmc_get_env_dev(int devno) { return devno; } -int board_mmc_getcd(struct mmc *mmc) +#ifdef CONFIG_DM_PMIC_PFUZE100 +int power_init_board(void) { - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; + struct udevice *dev; + int ret; + u32 dev_id, rev_id, i; + u32 switch_num = 6; + u32 offset = PFUZE100_SW1CMODE; - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = !gpio_get_value(USDHC3_CD_GPIO); - break; - } - - return ret; -} + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) + return 0; -int board_mmc_init(bd_t *bis) -{ -#ifndef CONFIG_SPL_BUILD - int i, ret; - - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - * mmc2 USDHC3 - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - gpio_direction_input(USDHC3_CD_GPIO); - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) { - printf("Warning: failed to initialize " - "mmc dev %d\n", i); - return ret; - } - } + if (ret != 0) + return ret; - return 0; -#else - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - u32 val; - u32 port; + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - val = readl(&src_regs->sbmr1); + /* set SW1AB staby volatage 0.975V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); - /* Boot from USDHC */ - port = (val >> 11) & 0x3; - switch (port) { - case 0: - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_direction_input(USDHC2_CD_GPIO); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - usdhc_cfg[0].max_bus_width = 4; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - break; - case 2: - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, - ARRAY_SIZE(usdhc3_pads)); - gpio_direction_input(USDHC3_CD_GPIO); - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; - usdhc_cfg[0].max_bus_width = 4; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - } + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif -} + /* set SW1C staby volatage 0.975V */ + pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -struct i2c_pads_info i2c_pad_info1 = { - .sda = { - .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC, - .gp = IMX_GPIO_NR(3, 13), - }, - .scl = { - .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC, - .gp = IMX_GPIO_NR(3, 12), - }, -}; + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); -int power_init_board(void) -{ - struct pmic *p; + /* Init mode to APS_PFM */ + pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); - p = pfuze_common_init(I2C_PMIC); - if (!p) - return -ENODEV; + for (i = 0; i < switch_num - 1; i++) + pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); - return pfuze_mode_init(p, APS_PFM); + return 0; } #endif @@ -374,9 +267,7 @@ int board_ehci_hcd_init(int port) int board_early_init_f(void) { setup_iomux_uart(); -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif + return 0; } @@ -385,8 +276,9 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#ifdef CONFIG_MXC_SPI + gpio_request(IMX_GPIO_NR(4, 11), "spi_cs"); + setup_spi(); #endif #ifdef CONFIG_FEC_MXC @@ -411,6 +303,76 @@ int checkboard(void) #include <spl.h> #include <libfdt.h> +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) +#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0) +#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + /* Boot from USDHC */ + port = (val >> 11) & 0x3; + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, + ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + } + + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = { .dram_sdqs0 = 0x00003030, .dram_sdqs1 = 0x00003030, diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 0565367937..2cebc2c002 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -94,7 +94,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) i2c_init_all(); - initdram(); + dram_init(); #ifdef CONFIG_SPL_NAND_BOOT puts("\nTertiary program loader running in sram..."); #else diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index 1f490dc943..a117dc3a2c 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -111,7 +111,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif - initdram(); + dram_init(); #ifdef CONFIG_SPL_NAND_BOOT puts("Tertiary program loader running in sram..."); #else diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 67637390be..1cf3497aa6 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif - initdram(); + dram_init(); #ifdef CONFIG_SPL_NAND_BOOT puts("Tertiary program loader running in sram..."); #else diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c index 3df8d21725..1ab98fc089 100644 --- a/board/freescale/p2041rdb/ddr.c +++ b/board/freescale/p2041rdb/ddr.c @@ -118,7 +118,7 @@ found: popts->ddr_cdr1 = DDR_CDR1_DHC_EN; } -int initdram(void) +int dram_init(void) { phys_size_t dram_size = 0; diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c index 93003c25d8..d822d3f806 100644 --- a/board/freescale/t102xqds/ddr.c +++ b/board/freescale/t102xqds/ddr.c @@ -169,7 +169,7 @@ void board_mem_sleep_setup(void) } #endif -int initdram(void) +int dram_init(void) { phys_size_t dram_size; diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c index c847b01e7e..b987ecea1d 100644 --- a/board/freescale/t102xqds/spl.c +++ b/board/freescale/t102xqds/spl.c @@ -142,7 +142,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) i2c_init_all(); - initdram(); + dram_init(); #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index 773aa77781..49460a02d1 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -229,7 +229,7 @@ void board_mem_sleep_setup(void) } #endif -int initdram(void) +int dram_init(void) { phys_size_t dram_size; diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index 5be71628af..dc6d9eeef6 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -129,7 +129,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) i2c_init_all(); - initdram(); + dram_init(); #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index d23787d43a..8f7909dc68 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -117,7 +117,7 @@ void board_mem_sleep_setup(void) } #endif -int initdram(void) +int dram_init(void) { phys_size_t dram_size; diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index b99ab95397..4e55844abe 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -120,7 +120,7 @@ void board_mem_sleep_setup(void) } #endif -int initdram(void) +int dram_init(void) { phys_size_t dram_size; diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index 899691a779..2e43307b2d 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -125,7 +125,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) puts("\n\n"); - initdram(); + dram_init(); #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index adc109042b..ba65049709 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -104,7 +104,7 @@ found: popts->cpo_sample = 0x64; } -int initdram(void) +int dram_init(void) { phys_size_t dram_size; diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index 3e713dc2c3..d7d716b690 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -128,7 +128,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) i2c_init_all(); - initdram(); + dram_init(); #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c index b4ad615846..50dc69a443 100644 --- a/board/freescale/t208xrdb/ddr.c +++ b/board/freescale/t208xrdb/ddr.c @@ -97,7 +97,7 @@ found: popts->cpo_sample = 0x54; } -int initdram(void) +int dram_init(void) { phys_size_t dram_size; diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index a5f940c6f6..b43140148b 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -98,7 +98,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) i2c_init_all(); - initdram(); + dram_init(); #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 84ff792225..740897015e 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -112,7 +112,7 @@ found: popts->cpo_sample = 0x63; } -int initdram(void) +int dram_init(void) { phys_size_t dram_size; diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c index 05feedecc2..9ecdaedda3 100644 --- a/board/freescale/t4qds/spl.c +++ b/board/freescale/t4qds/spl.c @@ -133,7 +133,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) i2c_init_all(); - initdram(); + dram_init(); #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c index d03baa3f45..8415527ec2 100644 --- a/board/freescale/t4rdb/ddr.c +++ b/board/freescale/t4rdb/ddr.c @@ -105,7 +105,7 @@ found: popts->cpo_sample = 0x64; } -int initdram(void) +int dram_init(void) { phys_size_t dram_size; diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index e96f3d38c5..5feab1cfcd 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -91,7 +91,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) i2c_init_all(); - initdram(); + dram_init(); mmc_boot(); } diff --git a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c index 4ceb48b09d..f1868550c7 100644 --- a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c +++ b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c @@ -10,7 +10,7 @@ #include <config.h> #include <asm/leon.h> -int initdram(void) +int dram_init(void) { /* Does not set gd->ram_size here */ diff --git a/board/gaisler/gr_ep2s60/gr_ep2s60.c b/board/gaisler/gr_ep2s60/gr_ep2s60.c index 12d8c1025c..a73d89db2f 100644 --- a/board/gaisler/gr_ep2s60/gr_ep2s60.c +++ b/board/gaisler/gr_ep2s60/gr_ep2s60.c @@ -10,7 +10,7 @@ #include <config.h> #include <asm/leon.h> -int initdram(void) +int dram_init(void) { /* Does not set gd->ram_size here */ diff --git a/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c b/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c index 02beb5c926..d86047a785 100644 --- a/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c +++ b/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c @@ -9,7 +9,7 @@ #include <config.h> #include <asm/leon.h> -int initdram(void) +int dram_init(void) { /* Does not set gd->ram_size here */ diff --git a/board/gaisler/grsim/grsim.c b/board/gaisler/grsim/grsim.c index aa9ba50877..99262b0813 100644 --- a/board/gaisler/grsim/grsim.c +++ b/board/gaisler/grsim/grsim.c @@ -10,7 +10,7 @@ #include <common.h> #include <asm/leon.h> -int initdram(void) +int dram_init(void) { /* Does not set gd->ram_size here */ diff --git a/board/gaisler/grsim_leon2/grsim_leon2.c b/board/gaisler/grsim_leon2/grsim_leon2.c index 384db3d84b..c6c4bb4270 100644 --- a/board/gaisler/grsim_leon2/grsim_leon2.c +++ b/board/gaisler/grsim_leon2/grsim_leon2.c @@ -10,7 +10,7 @@ #include <common.h> #include <asm/leon.h> -int initdram(void) +int dram_init(void) { /* Does not set gd->ram_size here */ diff --git a/board/gateworks/gw_ventana/MAINTAINERS b/board/gateworks/gw_ventana/MAINTAINERS index b44fb4dc4b..265ddac1c0 100644 --- a/board/gateworks/gw_ventana/MAINTAINERS +++ b/board/gateworks/gw_ventana/MAINTAINERS @@ -3,4 +3,6 @@ M: Tim Harvey <tharvey@gateworks.com> S: Maintained F: board/gateworks/gw_ventana/ F: include/configs/gw_ventana.h -F: configs/gwventana_defconfig +F: configs/gwventana_nand_defconfig +F: configs/gwventana_emmc_defconfig +F: configs/gwventana_gw5904_defconfig diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 3dc5f88102..56a7b3e7fd 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -38,6 +38,44 @@ void setup_iomux_uart(void) } /* MMC */ +static iomux_v3_cfg_t const gw5904_emmc_pads[] = { + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; +/* 4-bit microSD on SD2 */ +static iomux_v3_cfg_t const gw5904_mmc_pads[] = { + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + /* CD */ + IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; +/* 8-bit eMMC on SD2/NAND */ +static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = { + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -352,6 +390,107 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = { IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; +static iomux_v3_cfg_t const gw560x_gpio_pads[] = { + /* RS232_EN# */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), + /* CAN_STBY */ + IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), + /* USB_HUBRST# */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + /* DIOI2C_DIS# */ + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), + /* VID_EN */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG), + /* RS485_EN */ + IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), + /* USBH2_PEN (OTG) */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* 12V0_PWR_EN */ + IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw5903_gpio_pads[] = { + /* BKLT_12VEN */ + IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), + /* EMMY_PDN# */ + IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG), + /* EMMY_CFG1# */ + IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG), + /* EMMY_CFG1# */ + IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG), + /* USBH1_PEN (EHCI) */ + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), + /* USBH2_PEN (OTG) */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* USBDPC_PEN */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* TOUCH_RST */ + IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG), + /* AUDIO_RST# */ + IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), + /* UART1_TEN# */ + IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), + /* LVDS_BKLEN # */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), + /* RGMII_PDWN# */ + IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG), + /* TOUCH_IRQ# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* TOUCH_RST# */ + IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw5904_gpio_pads[] = { + /* USB_HUBRST# */ + IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* MX6_LOCLED# */ + IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), + /* IOEXP_PWREN# */ + IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), + /* IOEXP_IRQ# */ + IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + /* DIOI2C_DIS# */ + IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), + /* UART_RS485 */ + IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG), + /* UART_HALF */ + IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG), + /* SKT1_WDIS# */ + IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG), + /* SKT1_RST# */ + IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG), + /* SKT2_WDIS# */ + IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG), + /* SKT2_RST# */ + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), + /* M2_OFF# */ + IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG), + /* M2_WDIS# */ + IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG), + /* M2_RST# */ + IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG), +}; + /* Digital I/O */ struct dio_cfg gw51xx_dio[] = { { @@ -566,6 +705,111 @@ struct dio_cfg gw553x_dio[] = { }, }; +struct dio_cfg gw560x_dio[] = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, +}; + +struct dio_cfg gw5903_dio[] = { +}; + +struct dio_cfg gw5904_dio[] = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) }, + IMX_GPIO_NR(2, 0), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) }, + IMX_GPIO_NR(2, 1), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) }, + IMX_GPIO_NR(2, 2), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) }, + IMX_GPIO_NR(2, 3), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) }, + IMX_GPIO_NR(2, 4), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) }, + IMX_GPIO_NR(2, 5), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) }, + IMX_GPIO_NR(2, 6), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) }, + IMX_GPIO_NR(2, 7), + { 0, 0 }, + 0 + }, +}; + /* * Board Specific GPIO */ @@ -588,6 +832,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .dioi2c_en = IMX_GPIO_NR(4, 5), .pcie_sson = IMX_GPIO_NR(1, 20), .otgpwr_en = IMX_GPIO_NR(3, 22), + .mmc_cd = IMX_GPIO_NR(7, 0), }, /* GW51xx */ @@ -631,6 +876,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .rs232_en = GP_RS232_EN, .otgpwr_en = IMX_GPIO_NR(3, 22), .vsel_pin = IMX_GPIO_NR(6, 14), + .mmc_cd = IMX_GPIO_NR(7, 0), }, /* GW53xx */ @@ -654,6 +900,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .rs232_en = GP_RS232_EN, .otgpwr_en = IMX_GPIO_NR(3, 22), .vsel_pin = IMX_GPIO_NR(6, 14), + .mmc_cd = IMX_GPIO_NR(7, 0), }, /* GW54xx */ @@ -679,6 +926,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .rs232_en = GP_RS232_EN, .otgpwr_en = IMX_GPIO_NR(3, 22), .vsel_pin = IMX_GPIO_NR(6, 14), + .mmc_cd = IMX_GPIO_NR(7, 0), }, /* GW551x */ @@ -726,6 +974,58 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .wdis = IMX_GPIO_NR(7, 12), .otgpwr_en = IMX_GPIO_NR(3, 22), .vsel_pin = IMX_GPIO_NR(6, 14), + .mmc_cd = IMX_GPIO_NR(7, 0), + }, + + /* GW560x */ + { + .gpio_pads = gw560x_gpio_pads, + .num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2, + .dio_cfg = gw560x_dio, + .dio_num = ARRAY_SIZE(gw560x_dio), + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(4, 31), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .rs232_en = GP_RS232_EN, + .vidin_en = IMX_GPIO_NR(3, 31), + .wdis = IMX_GPIO_NR(7, 12), + .otgpwr_en = IMX_GPIO_NR(4, 15), + .mmc_cd = IMX_GPIO_NR(7, 0), + }, + + /* GW5903 */ + { + .gpio_pads = gw5903_gpio_pads, + .num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2, + .dio_cfg = gw5903_dio, + .dio_num = ARRAY_SIZE(gw5903_dio), + .leds = { + IMX_GPIO_NR(6, 14), + }, + .otgpwr_en = IMX_GPIO_NR(4, 15), + .mmc_cd = IMX_GPIO_NR(6, 11), + }, + + /* GW5904 */ + { + .gpio_pads = gw5904_gpio_pads, + .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2, + .dio_cfg = gw5904_dio, + .dio_num = ARRAY_SIZE(gw5904_dio), + .leds = { + IMX_GPIO_NR(4, 6), + IMX_GPIO_NR(4, 7), + IMX_GPIO_NR(4, 15), + }, + .pcie_rst = IMX_GPIO_NR(1, 0), + .mezz_pwren = IMX_GPIO_NR(2, 19), + .mezz_irq = IMX_GPIO_NR(2, 18), + .otgpwr_en = IMX_GPIO_NR(3, 22), }, }; @@ -834,6 +1134,50 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) gpio_direction_input(gpio_cfg[board].vsel_pin); gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin); } + + /* microSD CD */ + if (gpio_cfg[board].mmc_cd) { + gpio_request(gpio_cfg[board].mmc_cd, "sd_cd"); + gpio_direction_input(gpio_cfg[board].mmc_cd); + } + + /* Anything else board specific */ + switch(board) { + case GW560x: + gpio_request(IMX_GPIO_NR(4, 26), "12p0_en"); + gpio_direction_output(IMX_GPIO_NR(4, 26), 1); + break; + case GW5903: + gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr"); + gpio_direction_output(IMX_GPIO_NR(3, 31), 1); + gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr"); + gpio_direction_output(IMX_GPIO_NR(4, 15), 1); + gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr"); + gpio_direction_output(IMX_GPIO_NR(4, 15), 1); + gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en"); + gpio_direction_output(IMX_GPIO_NR(1, 25), 1); + gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#"); + gpio_direction_input(IMX_GPIO_NR(4, 6)); + gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst"); + gpio_direction_output(IMX_GPIO_NR(4, 8), 1); + gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven"); + gpio_direction_output(IMX_GPIO_NR(1, 7), 1); + break; + case GW5904: + gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#"); + gpio_direction_output(IMX_GPIO_NR(5, 11), 1); + gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#"); + gpio_direction_output(IMX_GPIO_NR(5, 12), 1); + gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#"); + gpio_direction_output(IMX_GPIO_NR(5, 13), 1); + gpio_request(IMX_GPIO_NR(1, 15), "m2_off#"); + gpio_direction_output(IMX_GPIO_NR(1, 15), 1); + gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#"); + gpio_direction_output(IMX_GPIO_NR(1, 14), 1); + gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#"); + gpio_direction_output(IMX_GPIO_NR(1, 13), 1); + break; + } } /* setup GPIO pinmux and default configuration per baseboard and env */ @@ -926,6 +1270,8 @@ void setup_board_gpio(int board, struct ventana_board_info *info) void setup_pmic(void) { struct pmic *p; + struct ventana_board_info ventana_info; + int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info); u32 reg; i2c_set_bus_num(CONFIG_I2C_PMIC); @@ -958,23 +1304,40 @@ void setup_pmic(void) debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR); power_ltc3676_init(CONFIG_I2C_PMIC); p = pmic_get("LTC3676_PMIC"); - if (p && !pmic_probe(p)) { - puts("PMIC: LTC3676\n"); - /* - * set board-specific scalar for max CPU frequency - * per CPU based on the LDO enabled Operating Ranges - * defined in the respective IMX6DQ and IMX6SDL - * datasheets. The voltage resulting from the R1/R2 - * feedback inputs on Ventana is 1308mV. Note that this - * is a bit shy of the Vmin of 1350mV in the datasheet - * for LDO enabled mode but is as high as we can go. - * - * We will rely on an OS kernel driver to properly - * regulate these per CPU operating point and use LDO - * bypass mode when using the higher frequency - * operating points to compensate as LDO bypass mode - * allows the rails be 125mV lower. - */ + if (!p || pmic_probe(p)) + return; + puts("PMIC: LTC3676\n"); + /* + * set board-specific scalar for max CPU frequency + * per CPU based on the LDO enabled Operating Ranges + * defined in the respective IMX6DQ and IMX6SDL + * datasheets. The voltage resulting from the R1/R2 + * feedback inputs on Ventana is 1308mV. Note that this + * is a bit shy of the Vmin of 1350mV in the datasheet + * for LDO enabled mode but is as high as we can go. + */ + switch (board) { + case GW560x: + /* mask PGOOD during SW3 transition */ + pmic_reg_write(p, LTC3676_DVB3B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW3 (VDD_ARM) */ + pmic_reg_write(p, LTC3676_DVB3A, 0x1f); + break; + case GW5903: + /* mask PGOOD during SW1 transition */ + pmic_reg_write(p, LTC3676_DVB3B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW3 (VDD_ARM) */ + pmic_reg_write(p, LTC3676_DVB3A, 0x1f); + + /* mask PGOOD during SW4 transition */ + pmic_reg_write(p, LTC3676_DVB4B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW4 (VDD_SOC) */ + pmic_reg_write(p, LTC3676_DVB4A, 0x1f); + break; + default: /* mask PGOOD during SW1 transition */ pmic_reg_write(p, LTC3676_DVB1B, 0x1f | LTC3676_PGOOD_MASK); @@ -991,23 +1354,96 @@ void setup_pmic(void) } #ifdef CONFIG_FSL_ESDHC -static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; +static struct fsl_esdhc_cfg usdhc_cfg[2]; int board_mmc_init(bd_t *bis) { - /* Only one USDHC controller on Ventana */ - SETUP_IOMUX_PADS(usdhc3_pads); - usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg.max_bus_width = 4; - - return fsl_esdhc_initialize(bis, &usdhc_cfg); + struct ventana_board_info ventana_info; + int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); + int ret; + + switch (board_type) { + case GW52xx: + case GW53xx: + case GW54xx: + case GW553x: + /* usdhc3: 4bit microSD */ + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + case GW560x: + /* usdhc2: 8-bit eMMC */ + SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[0].max_bus_width = 8; + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + if (ret) + return ret; + /* usdhc3: 4-bit microSD */ + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].max_bus_width = 4; + return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); + case GW5903: + /* usdhc3: 8-bit eMMC */ + SETUP_IOMUX_PADS(gw5904_emmc_pads); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 8; + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + if (ret) + return ret; + /* usdhc2: 4-bit microSD */ + SETUP_IOMUX_PADS(gw5904_mmc_pads); + usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[1].max_bus_width = 4; + return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); + case GW5904: + /* usdhc3: 8bit eMMC */ + SETUP_IOMUX_PADS(gw5904_emmc_pads); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 8; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + default: + /* doesn't have MMC */ + return -1; + } } int board_mmc_getcd(struct mmc *mmc) { + struct ventana_board_info ventana_info; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info); + int gpio = gpio_cfg[board].mmc_cd; + /* Card Detect */ - gpio_request(GP_SD3_CD, "sd_cd"); - gpio_direction_input(GP_SD3_CD); - return !gpio_get_value(GP_SD3_CD); + switch (board) { + case GW560x: + /* emmc is always present */ + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + return 1; + break; + case GW5903: + case GW5904: + /* emmc is always present */ + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + return 1; + break; + } + + if (gpio) { + debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio)); + return !gpio_get_value(gpio); + } + + return -1; } + #endif /* CONFIG_FSL_ESDHC */ diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index 18909a02b5..3eb4c59400 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -13,7 +13,6 @@ /* GPIO's common to all baseboards */ #define GP_PHY_RST IMX_GPIO_NR(1, 30) -#define GP_SD3_CD IMX_GPIO_NR(7, 0) #define GP_RS232_EN IMX_GPIO_NR(2, 11) #define GP_MSATA_SEL IMX_GPIO_NR(2, 8) @@ -79,6 +78,7 @@ struct ventana { int rs232_en; int otgpwr_en; int vsel_pin; + int mmc_cd; /* various features */ bool usd_vsel; }; diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c index 1382e5debe..2c07a84fff 100644 --- a/board/gateworks/gw_ventana/eeprom.c +++ b/board/gateworks/gw_ventana/eeprom.c @@ -64,6 +64,7 @@ read_eeprom(int bus, struct ventana_board_info *info) if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0) baseboard = '0'; + type = GW_UNKNOWN; switch (baseboard) { case '0': /* original GW5400-A prototype */ type = GW54proto; @@ -91,10 +92,16 @@ read_eeprom(int bus, struct ventana_board_info *info) type = GW553x; break; } - /* fall through */ - default: - printf("EEPROM: Unknown model in EEPROM: %s\n", info->model); - type = GW_UNKNOWN; + break; + case '6': + if (info->model[4] == '0') + type = GW560x; + break; + case '9': + if (info->model[4] == '0' && info->model[5] == '3') + type = GW5903; + if (info->model[4] == '0' && info->model[5] == '4') + type = GW5904; break; } return type; diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c index 613a275a8f..68b1ddb532 100644 --- a/board/gateworks/gw_ventana/gsc.c +++ b/board/gateworks/gw_ventana/gsc.c @@ -137,6 +137,10 @@ int gsc_info(int verbose) break; case '5': /* GW55xx */ break; + case '6': /* GW560x */ + read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); + read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); + break; } return 0; } diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 3f9d2f7010..dc8cd883e9 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -132,8 +132,9 @@ static void setup_iomux_enet(int gpio) /* toggle PHY_RST# */ gpio_request(gpio, "phy_rst#"); gpio_direction_output(gpio, 0); - mdelay(2); + mdelay(10); gpio_set_value(gpio, 1); + mdelay(100); } #ifdef CONFIG_USB_EHCI_MX6 @@ -226,12 +227,56 @@ int board_phy_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); } + /* TI DP83867 */ + else if (phydev->phy_id == 0x2000a231) { + /* configure register 0x170 for ref CLKOUT */ + phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f); + phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170); + phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f); + val = phy_read(phydev, MDIO_DEVAD_NONE, 14); + val &= ~0x1f00; + val |= 0x0b00; /* chD tx clock*/ + phy_write(phydev, MDIO_DEVAD_NONE, 14, val); + } + if (phydev->drv->config) phydev->drv->config(phydev); return 0; } +#ifdef CONFIG_MV88E61XX_SWITCH +int mv88e61xx_hw_reset(struct phy_device *phydev) +{ + struct mii_dev *bus = phydev->bus; + + /* GPIO[0] output, CLK125 */ + debug("enabling RGMII_REFCLK\n"); + bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0, + 0x1a /*MV_SCRATCH_MISC*/, + (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe); + bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0, + 0x1a /*MV_SCRATCH_MISC*/, + (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7); + + /* RGMII delay - Physical Control register bit[15:14] */ + debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT); + /* forced 1000mbps full-duplex link */ + bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe); + phydev->autoneg = AUTONEG_DISABLE; + phydev->speed = SPEED_1000; + phydev->duplex = DUPLEX_FULL; + + /* LED configuration: 7:4-green (8=Activity) 3:0 amber (9=10Link) */ + bus->write(bus, 0x10, 0, 0x16, 0x8089); + bus->write(bus, 0x11, 0, 0x16, 0x8089); + bus->write(bus, 0x12, 0, 0x16, 0x8089); + bus->write(bus, 0x13, 0, 0x16, 0x8089); + + return 0; +} +#endif // CONFIG_MV88E61XX_SWITCH + int board_eth_init(bd_t *bis) { #ifdef CONFIG_FEC_MXC @@ -661,6 +706,8 @@ int checkboard(void) static const struct boot_mode board_boot_modes[] = { /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */ + { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/GW5904 */ { NULL, 0 }, }; #endif @@ -712,7 +759,8 @@ int misc_init_r(void) setenv("fdt_file1", fdt); if (board_type != GW551x && board_type != GW552x && - board_type != GW553x) + board_type != GW553x && + board_type != GW560x) str[4] = 'x'; str[5] = 'x'; str[6] = 0; diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 8cc2a571d3..6060b44216 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -374,6 +374,25 @@ static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = { .p1_mpwrdlctl = 0x383A3930, }; +static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x001F003F, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x001F004E, + .p1_mpwldectrl1 = 0x0059001F, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x42220225, + .p0_mpdgctrl1 = 0x0213021F, + .p1_mpdgctrl0 = 0x022C0242, + .p1_mpdgctrl1 = 0x022C0244, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x474A4C4A, + .p1_mprddlctl = 0x48494C45, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x3F3F3F36, + .p1_mpwrdlctl = 0x3F36363F, +}; + static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0x002A0025, @@ -510,10 +529,25 @@ static void spl_dram_init(int width, int size_mb, int board_model) calib = &mx6sdl_256x64_mmdc_calib; debug("4gB density\n"); } else if (width == 64 && size_mb == 4096) { - mem = &mt41k512m16ha_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_512x64_mmdc_calib; - debug("8gB density\n"); + switch(board_model) { + case GW5903: + /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */ + mem = &mt41k256m16ha_125; + debug("4gB density\n"); + if (!is_cpu_type(MXC_CPU_MX6Q)) { + calib = &mx6sdl_256x64x2_mmdc_calib; + sysinfo.ncs = 2; + sysinfo.cs_density = 18; /* CS0_END=71 */ + sysinfo.cs1_mirror = 1; /* mirror enabled */ + } + break; + default: + mem = &mt41k512m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_512x64_mmdc_calib; + debug("8gB density\n"); + break; + } } if (!(mem && calib)) { @@ -608,6 +642,20 @@ void board_init_f(ulong dummy) memset(__bss_start, 0, __bss_end - __bss_start); } +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + switch (spl_boot_list[0]) { + case BOOT_DEVICE_NAND: + spl_boot_list[1] = BOOT_DEVICE_MMC1; + spl_boot_list[2] = BOOT_DEVICE_UART; + break; + case BOOT_DEVICE_MMC1: + spl_boot_list[1] = BOOT_DEVICE_UART; + break; + } +} + /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */ /* its our chance to print info about boot device */ void spl_board_init(void) diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h index 9ffad58e03..8a42d67ba1 100644 --- a/board/gateworks/gw_ventana/ventana_eeprom.h +++ b/board/gateworks/gw_ventana/ventana_eeprom.h @@ -112,6 +112,9 @@ enum { GW551x, GW552x, GW553x, + GW560x, + GW5903, + GW5904, GW_UNKNOWN, GW_BADCRC, }; diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 5b67a013da..5d2ec89b8c 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -66,7 +66,7 @@ static long fixed_sdram(void) return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); } -int initdram(void) +int dram_init(void) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize; diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index d8e6701fac..4433e8c77e 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -119,7 +119,7 @@ static int setup_sdram(void) return msize; } -int initdram(void) +int dram_init(void) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; fsl_lbc_t *lbc = &im->im_lbc; diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c index 129eb47b0e..348613736d 100644 --- a/board/ifm/ac14xx/ac14xx.c +++ b/board/ifm/ac14xx/ac14xx.c @@ -310,7 +310,7 @@ u32 sdram_init_seq[] = { /* EMPTY, optional, we don't do it */ }; -int initdram(void) +int dram_init(void) { gd->ram_size = fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq)); diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c index 4f81007ead..7770806bd2 100644 --- a/board/ifm/o2dnt2/o2dnt2.c +++ b/board/ifm/o2dnt2/o2dnt2.c @@ -62,11 +62,11 @@ static void sdram_start(int hi_addr) #endif /* - * ATTENTION: Although partially referenced initdram does NOT make real use + * ATTENTION: Although partially referenced dram_init does NOT make real use * use of CONFIG_SYS_SDRAM_BASE. The code does not work if * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. */ -int initdram(void) +int dram_init(void) { struct mpc5xxx_mmap_ctl *mmap_ctl = (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c index b92ff2aa88..3479b98b88 100644 --- a/board/imgtec/boston/ddr.c +++ b/board/imgtec/boston/ddr.c @@ -12,7 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; -int initdram(void) +int dram_init(void) { u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0); diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index f8c65b0e46..de81aa01f0 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -85,7 +85,7 @@ static enum sys_con malta_sys_con(void) } } -int initdram(void) +int dram_init(void) { gd->ram_size = CONFIG_SYS_MEM_SIZE; diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c index 8aa7c10bff..841d61459d 100644 --- a/board/imgtec/xilfpga/xilfpga.c +++ b/board/imgtec/xilfpga/xilfpga.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; /* initialize the DDR Controller and PHY */ -int initdram(void) +int dram_init(void) { /* MIG IP block is smart and doesn't need SW * to do any init */ diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index 2dd9799ea7..88cae59e8f 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -74,12 +74,12 @@ static void sdram_start (int hi_addr) #endif /* - * ATTENTION: Although partially referenced initdram does NOT make real use + * ATTENTION: Although partially referenced dram_init does NOT make real use * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ -int initdram(void) +int dram_init(void) { volatile struct mpc5xxx_mmap_ctl *mm = (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c index 922d9ef0a1..b8bc0459f8 100644 --- a/board/intercontrol/digsy_mtc/digsy_mtc.c +++ b/board/intercontrol/digsy_mtc/digsy_mtc.c @@ -74,12 +74,12 @@ static void sdram_start(int hi_addr) #endif /* - * ATTENTION: Although partially referenced initdram does NOT make real use + * ATTENTION: Although partially referenced dram_init does NOT make real use * use of CONFIG_SYS_SDRAM_BASE. The code does not work if * CONFIG_SYS_SDRAM_BASE is something other than 0x00000000. */ -int initdram(void) +int dram_init(void) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c index ca99332e51..133db8c6bd 100644 --- a/board/ipek01/ipek01.c +++ b/board/ipek01/ipek01.c @@ -75,12 +75,12 @@ static void sdram_start (int hi_addr) } /* - * ATTENTION: Although partially referenced initdram does NOT make real + * ATTENTION: Although partially referenced dram_init does NOT make real * use of CONFIG_SYS_SDRAM_BASE. The code does not work if * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. */ -int initdram(void) +int dram_init(void) { struct mpc5xxx_mmap_ctl *mmap_ctl = (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index d134691361..ea24eaa5c0 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -73,12 +73,12 @@ static void sdram_start (int hi_addr) #endif /* - * ATTENTION: Although partially referenced initdram does NOT make real use + * ATTENTION: Although partially referenced dram_init does NOT make real use * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ -int initdram(void) +int dram_init(void) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c index bbabbcfc0b..51b4571d40 100644 --- a/board/keymile/km82xx/km82xx.c +++ b/board/keymile/km82xx/km82xx.c @@ -291,7 +291,7 @@ static long probe_sdram(memctl8260_t *memctl) #endif /* CONFIG_SYS_SDRAM_LIST */ -int initdram(void) +int dram_init(void) { immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index f83fa06e93..8020c379fd 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -330,7 +330,7 @@ static int fixed_sdram(void) return msize; } -int initdram(void) +int dram_init(void) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c index 006b809654..6f82e15f82 100644 --- a/board/keymile/kmp204x/ddr.c +++ b/board/keymile/kmp204x/ddr.c @@ -50,7 +50,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm; } -int initdram(void) +int dram_init(void) { phys_size_t dram_size = 0; diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c index 3d7af092e8..a938a2c2e1 100644 --- a/board/l+g/vinco/vinco.c +++ b/board/l+g/vinco/vinco.c @@ -51,9 +51,9 @@ void spi_cs_deactivate(struct spi_slave *slave) static void vinco_spi0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ + at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ @@ -76,16 +76,16 @@ static void vinco_usb_hw_init(void) #ifdef CONFIG_GENERIC_ATMEL_MCI void vinco_mci0_hw_init(void) { - at91_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI0 CDA */ - at91_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI0 DA0 */ - at91_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI0 DA1 */ - at91_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI0 DA2 */ - at91_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI0 DA3 */ - at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */ - at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */ - at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */ - at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */ - at91_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI0 CLK */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI0 CDA */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI0 DA0 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI0 DA1 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI0 DA2 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI0 DA3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */ + at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI0 CLK */ /* * As the mci io internal pull down is too strong, so if the io needs @@ -93,16 +93,16 @@ void vinco_mci0_hw_init(void) * the power consumption will increase, so disable the interanl pull * down to save the power. */ - at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0); - at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0); + at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0); /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_MCI0); @@ -120,16 +120,16 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_MACB void vinco_macb0_hw_init(void) { - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_GMAC0); @@ -141,8 +141,8 @@ void vinco_macb0_hw_init(void) static void vinco_serial3_hw_init(void) { - at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ - at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_USART3); diff --git a/board/liebherr/lwmon5/sdram.c b/board/liebherr/lwmon5/sdram.c index f7251e567f..4a65d74443 100644 --- a/board/liebherr/lwmon5/sdram.c +++ b/board/liebherr/lwmon5/sdram.c @@ -144,10 +144,10 @@ static void program_ecc(u32 start_address, /************************************************************************* * - * initdram -- 440EPx's DDR controller is a DENALI Core + * dram_init -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ -int initdram(void) +int dram_init(void) { /* CL=4 */ mtsdram(DDR0_02, 0x00000000); diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig new file mode 100644 index 0000000000..f5e2f58b12 --- /dev/null +++ b/board/logicpd/imx6/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6LOGICPD + +config SYS_BOARD + default "imx6" + +config SYS_VENDOR + default "logicpd" + +config SYS_CONFIG_NAME + default "imx6_logic" + +endif diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS new file mode 100644 index 0000000000..5db7d2cadd --- /dev/null +++ b/board/logicpd/imx6/MAINTAINERS @@ -0,0 +1,6 @@ +MX6LOGICPD BOARD +M: Adam Ford <aford173@gmail.com> +S: Maintained +F: board/logicpd/imx6/ +F: include/configs/imx6_logic.h +F: configs/imx6q_logic_defconfig diff --git a/board/logicpd/imx6/Makefile b/board/logicpd/imx6/Makefile new file mode 100644 index 0000000000..337df9247d --- /dev/null +++ b/board/logicpd/imx6/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := imx6logic.o + diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README new file mode 100644 index 0000000000..df43b55d6b --- /dev/null +++ b/board/logicpd/imx6/README @@ -0,0 +1,37 @@ +U-Boot for LogicPD i.MX6 Development Kit +---------------------------------------- + +This file contains information for the port of U-Boot to the Logic PD Development kit. + +Logic PD has an i.MX6 System On Module (SOM) and a correspondong development +board. SOM has a built-in microSD socket, DDR and NAND flash. The development kit has +an SMSC Ethernet PHY, serial debug port and a variety of peripherals. + +On the intial release, the SOM came with either an i.MX6D or i.MX6Q. + +For more details about Logic PD i.MX6 Development kit, visit: +https://www.logicpd.com/ + +Building U-Boot for Logic PD Development Kit +-------------------------------------------- +To build U-Boot for the Dual and Quad variants: + + make imx6q_logic_defconfig + make u-boot.imx ARCH=arm CROSS_COMPILE=arm-linux- + + +Flashing U-Boot into the SD card +-------------------------------- + +See README.imximage for details on booting from SD + +Flashing U-Boot into NAND +------------------------- +Once in Linux with MTD support for the NAND on /dev/mtd0, program U-Boot with the following: +with: + + kobs-ng init -v -x u-boot-dtb.imx + +Additional Support Documentation can be found at: +https://support.logicpd.com/ + diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c new file mode 100644 index 0000000000..55767996a0 --- /dev/null +++ b/board/logicpd/imx6/imx6logic.c @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2017 Logic PD, Inc. + * + * Author: Adam Ford <aford173@gmail.com> + * + * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com> + * and updates by Jagan Teki <jagan@amarulasolutions.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/sizes.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/iomux-v3.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart3_pads[] = { + MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void fixup_enet_clock(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct gpio_desc nint; + struct gpio_desc reset; + int ret; + + /* Set Ref Clock to 50 MHz */ + enable_fec_anatop_clock(0, ENET_50MHZ); + + /* Set GPIO_16 as ENET_REF_CLK_OUT */ + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + /* Request GPIO Pins to reset Ethernet with new clock */ + ret = dm_gpio_lookup_name("GPIO4_7", &nint); + if (ret) { + printf("Unable to lookup GPIO4_7\n"); + return; + } + + ret = dm_gpio_request(&nint, "eth0_nInt"); + if (ret) { + printf("Unable to request eth0_nInt\n"); + return; + } + + /* Ensure nINT is input or PHY won't startup */ + dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN); + + ret = dm_gpio_lookup_name("GPIO4_9", &reset); + if (ret) { + printf("Unable to lookup GPIO4_9\n"); + return; + } + + ret = dm_gpio_request(&reset, "eth0_reset"); + if (ret) { + printf("Unable to request eth0_reset\n"); + return; + } + + /* Reset LAN8710A PHY */ + dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT); + dm_gpio_set_value(&reset, 0); + udelay(150); + dm_gpio_set_value(&reset, 1); + mdelay(50); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); +} + +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; + +static void setup_nand_pins(void) +{ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_early_init_f(void) +{ + fixup_enet_clock(); + setup_iomux_uart(); + setup_nand_pins(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + return 0; +} + +int board_late_init(void) +{ + setenv("board_name", "imx6logic"); + + if (is_mx6dq()) { + setenv("board_rev", "MX6DQ"); + setenv("fdt_file", "imx6q-logicpd.dtb"); + } + + return 0; +} diff --git a/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg new file mode 100644 index 0000000000..b20654870a --- /dev/null +++ b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2017 Logic PD, Inc. + * Adam Ford <aford173@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#include <asm/imx-common/imximage.cfg> + +/* image version */ +IMAGE_VERSION 2 + +BOOT_OFFSET FLASH_OFFSET_STANDARD + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch-mx6/mx6-ddr.h" +#include "asm/arch-mx6/iomux.h" +#include "asm/arch-mx6/crm_regs.h" + +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038 +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0xFFFFF300 +DATA 4, CCM_CCGR5, 0x0F0000F3 +DATA 4, CCM_CCGR6, 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 MX6_IOMUXC_GPR4 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 MX6_IOMUXC_GPR6 0x007F007F +DATA 4 MX6_IOMUXC_GPR7 0x007F007F diff --git a/board/micronas/vct/vct.c b/board/micronas/vct/vct.c index 02824eaf4f..8bf8d5f4e8 100644 --- a/board/micronas/vct/vct.c +++ b/board/micronas/vct/vct.c @@ -61,7 +61,7 @@ void _machine_restart(void) * SDRAM is already configured by the bootstrap code, only return the * auto-detected size here */ -int initdram(void) +int dram_init(void) { gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20); diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index a2520bc3bc..7883a179e8 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -118,7 +118,7 @@ static void sdram_start(int hi_addr) /* * Initalize SDRAM - configure SDRAM controller, detect memory size. */ -int initdram(void) +int dram_init(void) { ulong dramsize = 0; #ifndef CONFIG_SYS_RAMBOOT diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c index e0f4671b17..05c477d389 100644 --- a/board/mpc8308_p1m/sdram.c +++ b/board/mpc8308_p1m/sdram.c @@ -61,7 +61,7 @@ static long fixed_sdram(void) return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); } -int initdram(void) +int dram_init(void) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize; diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index e6422965f9..4d8671fe67 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -615,14 +615,14 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ /* ------------------------------------------------------------------------- */ /* - initdram() reads EEPROM via I2c. EEPROM contains all of + dram_init() reads EEPROM via I2c. EEPROM contains all of the necessary info for SDRAM controller configuration */ /* ------------------------------------------------------------------------- */ /* ------------------------------------------------------------------------- */ static int test_dram (unsigned long ramsize); -int initdram(void) +int dram_init(void) { unsigned long bank_reg[4], tmp, bank_size; diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c index 7b7b93f682..1288f743cc 100644 --- a/board/mpl/pati/pati.c +++ b/board/mpl/pati/pati.c @@ -135,7 +135,7 @@ extern int mem_test (unsigned long start, unsigned long ramsize, int quiet); /* * Get RAM size. */ -int initdram(void) +int dram_init(void) { unsigned char board_rev; unsigned long reg; diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index c07d8f88b9..408518d648 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -605,14 +605,14 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ /* ------------------------------------------------------------------------- */ /* - initdram() reads EEPROM via I2c. EEPROM contains all of + dram_init() reads EEPROM via I2c. EEPROM contains all of the necessary info for SDRAM controller configuration */ /* ------------------------------------------------------------------------- */ /* ------------------------------------------------------------------------- */ static int test_dram (unsigned long ramsize); -int initdram(void) +int dram_init(void) { unsigned long bank_reg[4], tmp, bank_size; int i, ds; diff --git a/board/munices/munices.c b/board/munices/munices.c index 8f1a5a8341..468eb3723e 100644 --- a/board/munices/munices.c +++ b/board/munices/munices.c @@ -55,12 +55,12 @@ static void sdram_start (int hi_addr) #endif /* - * ATTENTION: Although partially referenced initdram does NOT make real use + * ATTENTION: Although partially referenced dram_init does NOT make real use * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ -int initdram(void) +int dram_init(void) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c index e473531fd3..1c0540a989 100644 --- a/board/pb1x00/pb1x00.c +++ b/board/pb1x00/pb1x00.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; -int initdram(void) +int dram_init(void) { /* Sdram is setup by assembler code */ /* If memory could be changed, we should return the true value here */ diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c index c833aec9b2..9db31d3312 100644 --- a/board/pdm360ng/pdm360ng.c +++ b/board/pdm360ng/pdm360ng.c @@ -48,7 +48,7 @@ sdram_conf_t mddrc_config[] = { }, }; -int initdram(void) +int dram_init(void) { int i; u32 msize = 0; diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c index 19d87169ee..983559e81e 100644 --- a/board/phytec/pcm030/pcm030.c +++ b/board/phytec/pcm030/pcm030.c @@ -69,13 +69,13 @@ static void sdram_start(int hi_addr) #endif /* - * ATTENTION: Although partially referenced initdram does NOT make + * ATTENTION: Although partially referenced dram_init does NOT make * real use of CONFIG_SYS_SDRAM_BASE. The code does not * work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ -int initdram(void) +int dram_init(void) { volatile struct mpc5xxx_mmap_ctl *mm = (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; diff --git a/board/qemu-mips/qemu-mips.c b/board/qemu-mips/qemu-mips.c index 2638ea67d3..583acc2e44 100644 --- a/board/qemu-mips/qemu-mips.c +++ b/board/qemu-mips/qemu-mips.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR; -int initdram(void) +int dram_init(void) { /* Sdram is setup by assembler code */ /* If memory could be changed, we should return the true value here */ diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index f01cd7ed52..a3395ed680 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -37,7 +37,7 @@ int board_early_init_f (void) #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) -int initdram(void) +int dram_init(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 44842d5af1..08ced102b6 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -39,7 +39,7 @@ int checkboard (void) return 0; } -int initdram(void) +int dram_init(void) { long dram_size = 0; diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c index e2b9123bac..3bfe511a98 100644 --- a/board/sysam/amcore/amcore.c +++ b/board/sysam/amcore/amcore.c @@ -40,7 +40,7 @@ int checkboard(void) } /* - * in initdram we are here executing from flash + * in dram_init we are here executing from flash * case 1: * is with no ACR/flash cache enabled * nop = 40ns (scope measured) @@ -51,7 +51,7 @@ void fudelay(int usec) asm volatile ("nop"); } -int initdram(void) +int dram_init(void) { u32 dramsize, RC; diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index baf3208740..92db093dbf 100644 --- a/board/tqc/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -128,12 +128,12 @@ static void sdram_start (int hi_addr) #endif /* - * ATTENTION: Although partially referenced initdram does NOT make real use + * ATTENTION: Although partially referenced dram_init does NOT make real use * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ -int initdram(void) +int dram_init(void) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index 0968e494a5..4642342bfb 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -66,7 +66,7 @@ int board_early_init_r (void) { /************************************************************************** * DRAM initalization and size detection */ -int initdram(void) +int dram_init(void) { long bank_size; long size; diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 489a22c161..58bd7fae47 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -126,7 +126,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -int initdram(void) +int dram_init(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c index c271fb5873..73227c1b15 100644 --- a/board/v38b/v38b.c +++ b/board/v38b/v38b.c @@ -57,7 +57,7 @@ static void sdram_start(int hi_addr) #endif /* !CONFIG_SYS_RAMBOOT */ -int initdram(void) +int dram_init(void) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/varisys/cyrus/ddr.c b/board/varisys/cyrus/ddr.c index abf4e93265..2ba7b3a3ea 100644 --- a/board/varisys/cyrus/ddr.c +++ b/board/varisys/cyrus/ddr.c @@ -168,7 +168,7 @@ found: popts->ddr_cdr1 = DDR_CDR1_DHC_EN; } -int initdram(void) +int dram_init(void) { phys_size_t dram_size; diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index 37441c7a46..3818ab96b3 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -88,7 +88,7 @@ static long fixed_sdram(void) return msize; } -int initdram(void) +int dram_init(void) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; volatile fsl_lbc_t *lbc = &im->im_lbc; diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c index df5a7a0539..ef646fa4a1 100644 --- a/board/xes/xpedite1000/xpedite1000.c +++ b/board/xes/xpedite1000/xpedite1000.c @@ -116,7 +116,7 @@ int checkboard(void) return 0; } -int initdram(void) +int dram_init(void) { gd->ram_size = spd_sdram(); diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c index e436c28f78..19b96f636d 100644 --- a/board/xes/xpedite517x/xpedite517x.c +++ b/board/xes/xpedite517x/xpedite517x.c @@ -58,7 +58,7 @@ int board_early_init_r(void) return 0; } -int initdram(void) +int dram_init(void) { phys_size_t dram_size = fsl_ddr_sdram(); diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c index 6148a4b69c..be6b4dc5b9 100644 --- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c +++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c @@ -23,7 +23,7 @@ int checkboard(void) return 0; } -int initdram(void) +int dram_init(void) { gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c index d7e6aee706..07a3ab7f82 100644 --- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c +++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c @@ -19,7 +19,7 @@ int checkboard(void) return 0; } -int initdram(void) +int dram_init(void) { gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); |