diff options
Diffstat (limited to 'board')
90 files changed, 2511 insertions, 1841 deletions
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 876150402c..5cc82c9473 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -264,13 +264,13 @@ static int load_devicetree(void) #else char *dtbname = getenv("dtb"); char *dtbdev = getenv("dtbdev"); - char *dtppart = getenv("dtbpart"); - if (!dtbdev || !dtbdev || !dtbname) { + char *dtbpart = getenv("dtbpart"); + if (!dtbdev || !dtbpart || !dtbname) { printf("%s: <dtbdev>/<dtbpart>/<dtb> missing.\n", __func__); return -1; } - if (fs_set_blk_dev(dtbdev, dtppart, FS_TYPE_EXT)) { + if (fs_set_blk_dev(dtbdev, dtbpart, FS_TYPE_EXT)) { puts("load_devicetree: set_blk_dev failed.\n"); return -1; } diff --git a/board/amlogic/odroid-c2/README b/board/amlogic/odroid-c2/README index d6d266a5ce..b407c04952 100644 --- a/board/amlogic/odroid-c2/README +++ b/board/amlogic/odroid-c2/README @@ -18,6 +18,7 @@ Schematics are available on the manufacturer website. Currently the u-boot port supports the following devices: - serial + - eMMC, microSD - Ethernet u-boot compilation diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index 2b9da91b2d..ba7f9f2443 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -6,16 +6,13 @@ */ #include <common.h> -#include <mmc.h> #include <asm/io.h> #include <asm/arch/sama5d3_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> -#include <atmel_mci.h> -#include <net.h> -#include <netdev.h> +#include <debug_uart.h> #include <spl.h> #include <asm/arch/atmel_mpddrc.h> #include <asm/arch/at91_wdt.h> @@ -65,24 +62,26 @@ static void sama5d3_xplained_usb_hw_init(void) #ifdef CONFIG_GENERIC_ATMEL_MCI static void sama5d3_xplained_mci0_hw_init(void) { - at91_mci_hw_init(); - at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */ } #endif -int board_early_init_f(void) +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) { - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIOD); - at91_periph_clk_enable(ATMEL_ID_PIOE); - at91_seriald_hw_init(); +} +#endif +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif return 0; } +#endif int board_init(void) { @@ -98,10 +97,6 @@ int board_init(void) #ifdef CONFIG_GENERIC_ATMEL_MCI sama5d3_xplained_mci0_hw_init(); #endif -#ifdef CONFIG_MACB - at91_gmac_hw_init(); - at91_macb_hw_init(); -#endif return 0; } @@ -113,30 +108,14 @@ int dram_init(void) return 0; } -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_MACB - macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); - macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); -#endif - return 0; -} - -#ifdef CONFIG_GENERIC_ATMEL_MCI -int board_mmc_init(bd_t *bis) -{ - atmel_mci_init((void *)ATMEL_BASE_MCI0); - - return 0; -} -#endif - /* SPL */ #ifdef CONFIG_SPL_BUILD void spl_board_init(void) { #ifdef CONFIG_SYS_USE_MMC +#ifdef CONFIG_GENERIC_ATMEL_MCI sama5d3_xplained_mci0_hw_init(); +#endif #elif CONFIG_SYS_USE_NANDFLASH sama5d3_xplained_nand_hw_init(); #endif diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 134c2fe1eb..cae6e245dd 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -6,29 +6,22 @@ */ #include <common.h> -#include <mmc.h> #include <asm/io.h> #include <asm/arch/sama5d3_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> +#include <debug_uart.h> #include <lcd.h> #include <linux/ctype.h> #include <atmel_hlcdc.h> -#include <atmel_mci.h> #include <phy.h> #include <micrel.h> -#include <net.h> -#include <netdev.h> #include <spl.h> #include <asm/arch/atmel_mpddrc.h> #include <asm/arch/at91_wdt.h> -#ifdef CONFIG_USB_GADGET_ATMEL_USBA -#include <asm/arch/atmel_usba_udc.h> -#endif - DECLARE_GLOBAL_DATA_PTR; /* ------------------------------------------------------------------------- */ @@ -135,8 +128,6 @@ static void sama5d3xek_usb_hw_init(void) #ifdef CONFIG_GENERIC_ATMEL_MCI static void sama5d3xek_mci_hw_init(void) { - at91_mci_hw_init(); - at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */ } #endif @@ -215,18 +206,22 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_LCD */ -int board_early_init_f(void) +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) { - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - at91_periph_clk_enable(ATMEL_ID_PIOD); - at91_periph_clk_enable(ATMEL_ID_PIOE); - at91_seriald_hw_init(); +} +#endif +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif return 0; } +#endif int board_init(void) { @@ -242,21 +237,9 @@ int board_init(void) #ifdef CONFIG_CMD_USB sama5d3xek_usb_hw_init(); #endif -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - at91_udp_hw_init(); -#endif #ifdef CONFIG_GENERIC_ATMEL_MCI sama5d3xek_mci_hw_init(); #endif -#ifdef CONFIG_ATMEL_SPI - at91_spi0_hw_init(1 << 0); -#endif -#ifdef CONFIG_MACB - if (has_emac()) - at91_macb_hw_init(); - if (has_gmac()) - at91_gmac_hw_init(); -#endif #ifdef CONFIG_LCD if (has_lcdc()) sama5d3xek_lcd_hw_init(); @@ -271,104 +254,6 @@ int dram_init(void) return 0; } -int board_phy_config(struct phy_device *phydev) -{ - /* board specific timings for GMAC */ - if (has_gmac()) { - /* rx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, - 0x2222); - /* tx data delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, - 0x2222); - /* rx/tx clock delay */ - ksz9021_phy_extended_write(phydev, - MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, - 0xf2f4); - } - - /* always run the PHY's config routine */ - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; - -#ifdef CONFIG_MACB - if (has_emac()) - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); - if (has_gmac()) - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); -#endif -#ifdef CONFIG_USB_GADGET_ATMEL_USBA - usba_udc_probe(&pdata); -#ifdef CONFIG_USB_ETH_RNDIS - usb_eth_initialize(bis); -#endif -#endif - - return rc; -} - -#ifdef CONFIG_GENERIC_ATMEL_MCI -int board_mmc_init(bd_t *bis) -{ - int rc = 0; - - rc = atmel_mci_init((void *)ATMEL_BASE_MCI0); - - return rc; -} -#endif - -/* SPI chip select control */ -#ifdef CONFIG_ATMEL_SPI -#include <spi.h> - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs < 4; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - switch (slave->cs) { - case 0: - at91_set_pio_output(AT91_PIO_PORTD, 13, 0); - case 1: - at91_set_pio_output(AT91_PIO_PORTD, 14, 0); - case 2: - at91_set_pio_output(AT91_PIO_PORTD, 15, 0); - case 3: - at91_set_pio_output(AT91_PIO_PORTD, 16, 0); - default: - break; - } -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - switch (slave->cs) { - case 0: - at91_set_pio_output(AT91_PIO_PORTD, 13, 1); - case 1: - at91_set_pio_output(AT91_PIO_PORTD, 14, 1); - case 2: - at91_set_pio_output(AT91_PIO_PORTD, 15, 1); - case 3: - at91_set_pio_output(AT91_PIO_PORTD, 16, 1); - default: - break; - } -} -#endif /* CONFIG_ATMEL_SPI */ - #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -392,12 +277,8 @@ int board_late_init(void) #ifdef CONFIG_SPL_BUILD void spl_board_init(void) { -#ifdef CONFIG_SYS_USE_MMC - sama5d3xek_mci_hw_init(); -#elif CONFIG_SYS_USE_NANDFLASH +#if CONFIG_SYS_USE_NANDFLASH sama5d3xek_nand_hw_init(); -#elif CONFIG_SYS_USE_SERIALFLASH - at91_spi0_hw_init(1 << 0); #endif } diff --git a/board/compulab/cl-som-am57x/cl-som-am57x.c b/board/compulab/cl-som-am57x/cl-som-am57x.c index bdd0a2ba19..4701b71102 100644 --- a/board/compulab/cl-som-am57x/cl-som-am57x.c +++ b/board/compulab/cl-som-am57x/cl-som-am57x.c @@ -53,16 +53,6 @@ int board_mmc_init(bd_t *bis) } #endif /* CONFIG_GENERIC_MMC */ -#ifdef CONFIG_USB_XHCI_OMAP -int board_usb_init(int index, enum usb_init_type init) -{ - setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, - OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M); - - return 0; -} -#endif /* CONFIG_USB_XHCI_OMAP */ - int misc_init_r(void) { cl_print_pcb_info(); diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index f5190ac178..8a9a9be8ce 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -1,5 +1,6 @@ config CHAIN_OF_TRUST depends on !FIT_SIGNATURE && SECURE_BOOT + imply CMD_BLOB select FSL_CAAM bool default y diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index 16fd445306..6ed5d9ef1f 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -13,7 +13,7 @@ #endif #include <asm/armv7.h> -#if defined(CONFIG_LS102XA) +#if defined(CONFIG_ARCH_LS1021A) #include <asm/arch/immap_ls102xa.h> #endif @@ -66,7 +66,7 @@ static void dp_ddr_restore(void) *dst++ = *src++; } -#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA) +#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A) void ls1_psci_resume_fixup(void) { u32 tmp; @@ -104,7 +104,7 @@ static void dp_resume_prepare(void) #ifdef CONFIG_U_QE u_qe_resume(); #endif -#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA) +#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A) ls1_psci_resume_fixup(); #endif } diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 438e781957..aad1b93d14 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -22,7 +22,7 @@ #include <asm/fsl_pamu.h> #endif -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A #include <asm/arch/immap_ls102xa.h> #endif diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 7396aa2f69..ed48c5c8bd 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -15,7 +15,7 @@ #include <u-boot/rsa-mod-exp.h> #include <hash.h> #include <fsl_secboot_err.h> -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A #include <asm/arch/immap_ls102xa.h> #endif @@ -393,6 +393,7 @@ static void fsl_secboot_bootscript_parse_failure(void) */ void fsl_secboot_handle_error(int error) { +#ifndef CONFIG_SPL_BUILD const struct fsl_secboot_errcode *e; for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX; @@ -400,6 +401,9 @@ void fsl_secboot_handle_error(int error) if (e->errcode == error) printf("ERROR :: %x :: %s\n", error, e->name); } +#else + printf("ERROR :: %x\n", error); +#endif /* If Boot Mode is secure, transition the SNVS state and issue * reset based on type of failure and ITS setting. diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS index 79a2a7dd24..2cb38e7405 100644 --- a/board/freescale/ls1012ardb/MAINTAINERS +++ b/board/freescale/ls1012ardb/MAINTAINERS @@ -4,3 +4,7 @@ S: Maintained F: board/freescale/ls1012ardb/ F: include/configs/ls1012ardb.h F: configs/ls1012ardb_qspi_defconfig + +M: Sumit Garg <sumit.garg@nxp.com> +S: Maintained +F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index a23a23be1f..a21e4c4aeb 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -22,6 +22,7 @@ #include <environment.h> #include <fsl_mmdc.h> #include <netdev.h> +#include <fsl_sec.h> DECLARE_GLOBAL_DATA_PTR; @@ -118,6 +119,10 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index d96fd774d3..ff32d5cb28 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -273,6 +273,7 @@ int board_eth_init(bd_t *bis) #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; num++; #endif if (!num) { diff --git a/board/freescale/ls1043aqds/Makefile b/board/freescale/ls1043aqds/Makefile index f727bfd622..49d8d7d9b9 100644 --- a/board/freescale/ls1043aqds/Makefile +++ b/board/freescale/ls1043aqds/Makefile @@ -5,5 +5,7 @@ # obj-y += ddr.o +ifndef CONFIG_SPL_BUILD obj-y += eth.o +endif obj-y += ls1043aqds.o diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 2643f5bf4a..b22d3784dc 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -113,7 +113,9 @@ int fsl_initdram(void) phys_size_t dram_size; #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - return fsl_ddr_sdram_size(); + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; #else puts("Initializing DDR....using SPD\n"); diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 2df63e468d..8fbd3a74bd 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -11,6 +11,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#include <asm/arch/ppa.h> #include <asm/arch/fdt.h> #include <asm/arch/mmu.h> #include <asm/arch/soc.h> @@ -325,6 +326,10 @@ int board_init(void) config_serdes_mux(); #endif +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + return 0; } diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS index 0503a3fcc9..87aa006455 100644 --- a/board/freescale/ls1043ardb/MAINTAINERS +++ b/board/freescale/ls1043ardb/MAINTAINERS @@ -12,3 +12,5 @@ LS1043A_SECURE_BOOT BOARD M: Ruchika Gupta <ruchika.gupta@nxp.com> S: Maintained F: configs/ls1043ardb_SECURE_BOOT_defconfig +F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile index 5fe1cc9393..2a4452e5ec 100644 --- a/board/freescale/ls1043ardb/Makefile +++ b/board/freescale/ls1043ardb/Makefile @@ -4,7 +4,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpld.o obj-y += ddr.o obj-y += ls1043ardb.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o +obj-y += cpld.o +endif diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 728de2e3f1..9dc1cbc343 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -27,6 +27,15 @@ DECLARE_GLOBAL_DATA_PTR; +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +#ifndef CONFIG_SPL_BUILD + int checkboard(void) { static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; @@ -65,13 +74,6 @@ int checkboard(void) return 0; } -int board_early_init_f(void) -{ - fsl_lsch2_early_init_f(); - - return 0; -} - int board_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; @@ -213,3 +215,5 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } + +#endif diff --git a/board/freescale/ls1046aqds/MAINTAINERS b/board/freescale/ls1046aqds/MAINTAINERS index b4549ae138..6737d558ce 100644 --- a/board/freescale/ls1046aqds/MAINTAINERS +++ b/board/freescale/ls1046aqds/MAINTAINERS @@ -8,3 +8,7 @@ F: configs/ls1046aqds_nand_defconfig F: configs/ls1046aqds_sdcard_ifc_defconfig F: configs/ls1046aqds_sdcard_qspi_defconfig F: configs/ls1046aqds_qspi_defconfig + +M: Sumit Garg <sumit.garg@nxp.com> +S: Maintained +F: configs/ls1046aqds_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1046aqds/Makefile b/board/freescale/ls1046aqds/Makefile index df6e5461db..6267522cc2 100644 --- a/board/freescale/ls1046aqds/Makefile +++ b/board/freescale/ls1046aqds/Makefile @@ -5,5 +5,7 @@ # obj-y += ddr.o +ifndef CONFIG_SPL_BUILD obj-y += eth.o +endif obj-y += ls1046aqds.o diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index d37af34a9c..5fcfa0f701 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -97,7 +97,9 @@ int fsl_initdram(void) phys_size_t dram_size; #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - return fsl_ddr_sdram_size(); + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; #else puts("Initializing DDR....using SPD\n"); diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 69fc15b681..057a11daa8 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -11,6 +11,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#include <asm/arch/ppa.h> #include <asm/arch/fdt.h> #include <asm/arch/mmu.h> #include <asm/arch/soc.h> @@ -22,6 +23,7 @@ #include <fsl_csu.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> +#include <fsl_sec.h> #include <spl.h> #include "../common/vid.h" @@ -266,6 +268,28 @@ int board_init(void) if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n"); +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + +#ifdef CONFIG_SECURE_BOOT + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + return 0; } diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig index a62255c78d..b9f2ed7e4b 100644 --- a/board/freescale/ls1046ardb/Kconfig +++ b/board/freescale/ls1046ardb/Kconfig @@ -12,5 +12,5 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1046ardb" - +source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS index ff42bef090..79a2290974 100644 --- a/board/freescale/ls1046ardb/MAINTAINERS +++ b/board/freescale/ls1046ardb/MAINTAINERS @@ -7,3 +7,13 @@ F: include/configs/ls1046ardb.h F: configs/ls1046ardb_qspi_defconfig F: configs/ls1046ardb_sdcard_defconfig F: configs/ls1046ardb_emmc_defconfig + +LS1046A_SECURE_BOOT BOARD +M: Ruchika Gupta <ruchika.gupta@nxp.com> +S: Maintained +F: configs/ls1046ardb_SECURE_BOOT_defconfig +F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig + +M: Sumit Garg <sumit.garg@nxp.com> +S: Maintained +F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1046ardb/Makefile b/board/freescale/ls1046ardb/Makefile index 348eb76ea7..b92ed0b3ec 100644 --- a/board/freescale/ls1046ardb/Makefile +++ b/board/freescale/ls1046ardb/Makefile @@ -4,7 +4,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpld.o obj-y += ddr.o obj-y += ls1046ardb.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o +obj-y += cpld.o +endif diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index a16f7bc83a..ae5046cab6 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -101,7 +101,9 @@ int fsl_initdram(void) phys_size_t dram_size; #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - return fsl_ddr_sdram_size(); + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; #else puts("Initializing DDR....using SPD\n"); diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 02b6c4c375..1dd5e69882 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -21,9 +21,18 @@ #include <fsl_esdhc.h> #include <power/mc34vr500_pmic.h> #include "cpld.h" +#include <fsl_sec.h> DECLARE_GLOBAL_DATA_PTR; +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +#ifndef CONFIG_SPL_BUILD int checkboard(void) { static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; @@ -56,13 +65,6 @@ int checkboard(void) return 0; } -int board_early_init_f(void) -{ - fsl_lsch2_early_init_f(); - - return 0; -} - int board_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; @@ -71,6 +73,24 @@ int board_init(void) enable_layerscape_ns_access(); #endif +#ifdef CONFIG_SECURE_BOOT + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif @@ -161,3 +181,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } +#endif diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index 799799c251..ba584c8a76 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -62,6 +62,13 @@ int board_eth_init(bd_t *bis) wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4); break; + case 0x4B: + wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); + + break; default: printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n", srds_s1); diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 1cf3497aa6..ca7ba5754e 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -17,11 +17,6 @@ DECLARE_GLOBAL_DATA_PTR; -static const u32 sysclk_tbl[] = { - 66666000, 7499900, 83332500, 8999900, - 99999000, 11111000, 12499800, 13333200 -}; - phys_size_t get_effective_memsize(void) { return CONFIG_SYS_L2_SIZE; diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index 56f7c1a909..f370f72baa 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -167,6 +167,13 @@ unsigned long get_board_ddr_clk(void) return CONFIG_DDR_CLK_FREQ; } +#ifdef CONFIG_TARGET_T1024RDB +void board_reset(void) +{ + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} +#endif + int misc_init_r(void) { return 0; diff --git a/board/gaisler/gr_cpci_ax2000/Kconfig b/board/gaisler/gr_cpci_ax2000/Kconfig deleted file mode 100644 index c12a002179..0000000000 --- a/board/gaisler/gr_cpci_ax2000/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_GR_CPCI_AX2000 - -config SYS_BOARD - default "gr_cpci_ax2000" - -config SYS_CONFIG_NAME - default "gr_cpci_ax2000" - -endif diff --git a/board/gaisler/gr_cpci_ax2000/MAINTAINERS b/board/gaisler/gr_cpci_ax2000/MAINTAINERS deleted file mode 100644 index df55a4cc41..0000000000 --- a/board/gaisler/gr_cpci_ax2000/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -GR_CPCI_AX2000 BOARD -#M: - -S: Maintained -F: board/gaisler/gr_cpci_ax2000/ -F: include/configs/gr_cpci_ax2000.h -F: configs/gr_cpci_ax2000_defconfig diff --git a/board/gaisler/gr_cpci_ax2000/Makefile b/board/gaisler/gr_cpci_ax2000/Makefile deleted file mode 100644 index a08e04dbe8..0000000000 --- a/board/gaisler/gr_cpci_ax2000/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := gr_cpci_ax2000.o diff --git a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c deleted file mode 100644 index f1868550c7..0000000000 --- a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2008 - * Daniel Hellstrom, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <config.h> -#include <asm/leon.h> - -int dram_init(void) -{ - /* Does not set gd->ram_size here */ - - return 0; -} - -int checkboard(void) -{ - puts("Board: GR-CPCI-AX2000\n"); - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/gaisler/gr_ep2s60/Kconfig b/board/gaisler/gr_ep2s60/Kconfig deleted file mode 100644 index f49937c55a..0000000000 --- a/board/gaisler/gr_ep2s60/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_GR_EP2S60 - -config SYS_BOARD - default "gr_ep2s60" - -config SYS_CONFIG_NAME - default "gr_ep2s60" - -endif diff --git a/board/gaisler/gr_ep2s60/MAINTAINERS b/board/gaisler/gr_ep2s60/MAINTAINERS deleted file mode 100644 index 7acd5f44c6..0000000000 --- a/board/gaisler/gr_ep2s60/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -GR_EP2S60 BOARD -#M: - -S: Maintained -F: board/gaisler/gr_ep2s60/ -F: include/configs/gr_ep2s60.h -F: configs/gr_ep2s60_defconfig diff --git a/board/gaisler/gr_ep2s60/Makefile b/board/gaisler/gr_ep2s60/Makefile deleted file mode 100644 index 059a9c03c4..0000000000 --- a/board/gaisler/gr_ep2s60/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := gr_ep2s60.o diff --git a/board/gaisler/gr_ep2s60/gr_ep2s60.c b/board/gaisler/gr_ep2s60/gr_ep2s60.c deleted file mode 100644 index a73d89db2f..0000000000 --- a/board/gaisler/gr_ep2s60/gr_ep2s60.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2008 - * Daniel Hellstrom, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <config.h> -#include <asm/leon.h> - -int dram_init(void) -{ - /* Does not set gd->ram_size here */ - - return 0; -} - -int checkboard(void) -{ - puts("Board: EP2S60 GRLIB\n"); - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/gaisler/gr_xc3s_1500/Kconfig b/board/gaisler/gr_xc3s_1500/Kconfig deleted file mode 100644 index e695ba2cdd..0000000000 --- a/board/gaisler/gr_xc3s_1500/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_GR_XC3S_1500 - -config SYS_BOARD - default "gr_xc3s_1500" - -config SYS_CONFIG_NAME - default "gr_xc3s_1500" - -endif diff --git a/board/gaisler/gr_xc3s_1500/MAINTAINERS b/board/gaisler/gr_xc3s_1500/MAINTAINERS deleted file mode 100644 index c4179d29c0..0000000000 --- a/board/gaisler/gr_xc3s_1500/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -GR_XC3S_1500 BOARD -#M: - -S: Maintained -F: board/gaisler/gr_xc3s_1500/ -F: include/configs/gr_xc3s_1500.h -F: configs/gr_xc3s_1500_defconfig diff --git a/board/gaisler/gr_xc3s_1500/Makefile b/board/gaisler/gr_xc3s_1500/Makefile deleted file mode 100644 index 302c4611e0..0000000000 --- a/board/gaisler/gr_xc3s_1500/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := gr_xc3s_1500.o diff --git a/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c b/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c deleted file mode 100644 index d86047a785..0000000000 --- a/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2007 - * Daniel Hellstrom, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <config.h> -#include <asm/leon.h> - -int dram_init(void) -{ - /* Does not set gd->ram_size here */ - - return 0; -} - -int checkboard(void) -{ - puts("Board: GR-XC3S-1500\n"); - return 0; -} - -int misc_init_r(void) -{ - return 0; -} diff --git a/board/gaisler/grsim/Kconfig b/board/gaisler/grsim/Kconfig deleted file mode 100644 index 18598d3c2a..0000000000 --- a/board/gaisler/grsim/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_GRSIM - -config SYS_BOARD - default "grsim" - -config SYS_CONFIG_NAME - default "grsim" - -endif diff --git a/board/gaisler/grsim/MAINTAINERS b/board/gaisler/grsim/MAINTAINERS deleted file mode 100644 index 4b3312ef72..0000000000 --- a/board/gaisler/grsim/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -GRSIM BOARD -#M: - -S: Maintained -F: board/gaisler/grsim/ -F: include/configs/grsim.h -F: configs/grsim_defconfig diff --git a/board/gaisler/grsim/Makefile b/board/gaisler/grsim/Makefile deleted file mode 100644 index 4c93bdae83..0000000000 --- a/board/gaisler/grsim/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := grsim.o diff --git a/board/gaisler/grsim/grsim.c b/board/gaisler/grsim/grsim.c deleted file mode 100644 index 99262b0813..0000000000 --- a/board/gaisler/grsim/grsim.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * GRSIM/TSIM board - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/leon.h> - -int dram_init(void) -{ - /* Does not set gd->ram_size here */ - - return 0; -} - -int checkboard(void) -{ - puts("Board: GRSIM/TSIM\n"); - return 0; -} - -int misc_init_r(void) -{ - return 0; -} diff --git a/board/gaisler/grsim_leon2/Kconfig b/board/gaisler/grsim_leon2/Kconfig deleted file mode 100644 index 0d21a0a985..0000000000 --- a/board/gaisler/grsim_leon2/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_GRSIM_LEON2 - -config SYS_BOARD - default "grsim_leon2" - -config SYS_CONFIG_NAME - default "grsim_leon2" - -endif diff --git a/board/gaisler/grsim_leon2/MAINTAINERS b/board/gaisler/grsim_leon2/MAINTAINERS deleted file mode 100644 index bf4a95001b..0000000000 --- a/board/gaisler/grsim_leon2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -GRSIM_LEON2 BOARD -#M: - -S: Maintained -F: board/gaisler/grsim_leon2/ -F: include/configs/grsim_leon2.h -F: configs/grsim_leon2_defconfig diff --git a/board/gaisler/grsim_leon2/Makefile b/board/gaisler/grsim_leon2/Makefile deleted file mode 100644 index 5468305caa..0000000000 --- a/board/gaisler/grsim_leon2/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := grsim_leon2.o diff --git a/board/gaisler/grsim_leon2/grsim_leon2.c b/board/gaisler/grsim_leon2/grsim_leon2.c deleted file mode 100644 index c6c4bb4270..0000000000 --- a/board/gaisler/grsim_leon2/grsim_leon2.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * GRSIM/TSIM board - * - * (C) Copyright 2007 - * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/leon.h> - -int dram_init(void) -{ - /* Does not set gd->ram_size here */ - - return 0; -} - -int checkboard(void) -{ - puts("Board: GRSIM/TSIM LEON2\n"); - return 0; -} - -int misc_init_r(void) -{ - return 0; -} diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 56a7b3e7fd..d27bd57648 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -1272,14 +1272,15 @@ void setup_pmic(void) struct pmic *p; struct ventana_board_info ventana_info; int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info); + const int i2c_pmic = 1; u32 reg; - i2c_set_bus_num(CONFIG_I2C_PMIC); + i2c_set_bus_num(i2c_pmic); /* configure PFUZE100 PMIC */ if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) { debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR); - power_pfuze100_init(CONFIG_I2C_PMIC); + power_pfuze100_init(i2c_pmic); p = pmic_get("PFUZE100"); if (p && !pmic_probe(p)) { pmic_reg_read(p, PFUZE100_DEVICEID, ®); @@ -1302,7 +1303,7 @@ void setup_pmic(void) /* configure LTC3676 PMIC */ else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) { debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR); - power_ltc3676_init(CONFIG_I2C_PMIC); + power_ltc3676_init(i2c_pmic); p = pmic_get("LTC3676_PMIC"); if (!p || pmic_probe(p)) return; diff --git a/board/ibf-dsp561/Kconfig b/board/ibf-dsp561/Kconfig deleted file mode 100644 index acf5d7c6f9..0000000000 --- a/board/ibf-dsp561/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_IBF_DSP561 - -config SYS_BOARD - default "ibf-dsp561" - -config SYS_CONFIG_NAME - default "ibf-dsp561" - -endif diff --git a/board/ibf-dsp561/MAINTAINERS b/board/ibf-dsp561/MAINTAINERS deleted file mode 100644 index dfd0f9095f..0000000000 --- a/board/ibf-dsp561/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -IBF-DSP561 BOARD -M: I-SYST Micromodule <support@i-syst.com> -S: Maintained -F: board/ibf-dsp561/ -F: include/configs/ibf-dsp561.h -F: configs/ibf-dsp561_defconfig diff --git a/board/ibf-dsp561/Makefile b/board/ibf-dsp561/Makefile deleted file mode 100644 index cbf16121df..0000000000 --- a/board/ibf-dsp561/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# U-Boot - Makefile -# -# Copyright (c) 2005-2007 Analog Device Inc. -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ibf-dsp561.o diff --git a/board/ibf-dsp561/config.mk b/board/ibf-dsp561/config.mk deleted file mode 100644 index 854d7dbb86..0000000000 --- a/board/ibf-dsp561/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2005-2008 Analog Device Inc. -# -# (C) Copyright 2001 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Set some default LDR flags based on boot mode. -LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/ibf-dsp561/ibf-dsp561.c b/board/ibf-dsp561/ibf-dsp561.c deleted file mode 100644 index 8475fda1a4..0000000000 --- a/board/ibf-dsp561/ibf-dsp561.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * U-Boot - main board file - * - * Copyright (c) 2008-2009 I-SYST. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - printf("Board: I-SYST IBF-DSP561 Micromodule\n"); - printf(" Support: http://www.i-syst.com/\n"); - return 0; -} - -#ifdef CONFIG_DRIVER_AX88180 -int board_eth_init(bd_t *bis) -{ - return ax88180_initialize(bis); -} -#endif diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c deleted file mode 100644 index 5fea7ffaef..0000000000 --- a/board/isee/igep0033/board.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Board functions for IGEP COM AQUILA based boards - * - * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <errno.h> -#include <spl.h> -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> -#include <asm/arch/omap.h> -#include <asm/arch/ddr_defs.h> -#include <asm/arch/clock.h> -#include <asm/arch/gpio.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/sys_proto.h> -#include <asm/io.h> -#include <asm/emif.h> -#include <asm/gpio.h> -#include <i2c.h> -#include <miiphy.h> -#include <cpsw.h> -#include "board.h" - -DECLARE_GLOBAL_DATA_PTR; - -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - -#ifdef CONFIG_SPL_BUILD -static const struct ddr_data ddr3_data = { - .datardsratio0 = K4B2G1646EBIH9_RD_DQS, - .datawdsratio0 = K4B2G1646EBIH9_WR_DQS, - .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE, - .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA, -}; - -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = K4B2G1646EBIH9_RATIO, - .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, - - .cmd1csratio = K4B2G1646EBIH9_RATIO, - .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, - - .cmd2csratio = K4B2G1646EBIH9_RATIO, - .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG, - .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF, - .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1, - .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2, - .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3, - .zq_config = K4B2G1646EBIH9_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY, -}; - -#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr = { - 400, OSC-1, 1, -1, -1, -1, -1}; - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - -void set_uart_mux_conf(void) -{ - enable_uart0_pin_mux(); -} - -void set_mux_conf_regs(void) -{ - enable_board_pin_mux(); -} - -const struct ctrl_ioregs ioregs = { - .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, - .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, - .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, - .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, - .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, -}; - -void sdram_init(void) -{ - config_ddr(400, &ioregs, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -} -#endif - -/* - * Basic board specific setup. Pinmux has been handled already. - */ -int board_init(void) -{ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - gpmc_init(); - - return 0; -} - -#if defined(CONFIG_DRIVER_TI_CPSW) -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_RMII, - }, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -int board_eth_init(bd_t *bis) -{ - int rv, ret = 0; - uint8_t mac_addr[6]; - uint32_t mac_hi, mac_lo; - - if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { - /* try reading mac address from efuse */ - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; - if (is_valid_ethaddr(mac_addr)) - eth_setenv_enetaddr("ethaddr", mac_addr); - } - - writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN), - &cdev->miisel); - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - else - ret += rv; - - return ret; -} -#endif diff --git a/board/isee/igep0033/Kconfig b/board/isee/igep003x/Kconfig index e989e4b15c..68a68fc52f 100644 --- a/board/isee/igep0033/Kconfig +++ b/board/isee/igep003x/Kconfig @@ -1,7 +1,7 @@ -if TARGET_AM335X_IGEP0033 +if TARGET_AM335X_IGEP003X config SYS_BOARD - default "igep0033" + default "igep003x" config SYS_VENDOR default "isee" @@ -10,6 +10,6 @@ config SYS_SOC default "am33xx" config SYS_CONFIG_NAME - default "am335x_igep0033" + default "am335x_igep003x" endif diff --git a/board/isee/igep0033/MAINTAINERS b/board/isee/igep003x/MAINTAINERS index bd8a1f2eb4..748b189c4e 100644 --- a/board/isee/igep0033/MAINTAINERS +++ b/board/isee/igep003x/MAINTAINERS @@ -1,6 +1,6 @@ -IGEP0033 BOARD +IGEP003X BOARD M: Enric Balletbo i Serra <eballetbo@gmail.com> S: Maintained -F: board/isee/igep0033/ -F: include/configs/am335x_igep0033.h +F: board/isee/igep003x/ +F: include/configs/am335x_igep003x.h F: configs/am335x_igep0033_defconfig diff --git a/board/isee/igep0033/Makefile b/board/isee/igep003x/Makefile index fc985b45b6..fc985b45b6 100644 --- a/board/isee/igep0033/Makefile +++ b/board/isee/igep003x/Makefile diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c new file mode 100644 index 0000000000..2d0ebbf5ef --- /dev/null +++ b/board/isee/igep003x/board.c @@ -0,0 +1,287 @@ +/* + * Board functions for IGEP COM AQUILA and SMARC AM335x based boards + * + * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <fdt_support.h> +#include <mtd_node.h> +#include <jffs2/load_kernel.h> +#include <environment.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards + * and control IGEP0034 green and red LEDs. + * U-boot configures these pins as input pullup to detect board revision: + * IGEP0034-LITE = 0b00 + * IGEP0034 (FULL) = 0b01 + * IGEP0033 = 0b1X + */ +#define GPIO_GREEN_REVISION 27 +#define GPIO_RED_REVISION 26 + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* + * Routine: get_board_revision + * Description: Returns the board revision + */ +static int get_board_revision(void) +{ + int revision; + + gpio_request(GPIO_GREEN_REVISION, "green_revision"); + gpio_direction_input(GPIO_GREEN_REVISION); + revision = 2 * gpio_get_value(GPIO_GREEN_REVISION); + gpio_free(GPIO_GREEN_REVISION); + + gpio_request(GPIO_RED_REVISION, "red_revision"); + gpio_direction_input(GPIO_RED_REVISION); + revision = revision + gpio_get_value(GPIO_RED_REVISION); + gpio_free(GPIO_RED_REVISION); + + return revision; +} + +#ifdef CONFIG_SPL_BUILD +/* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/ +static const struct ddr_data ddr3_igep0034_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; + +static const struct ddr_data ddr3_igep0034_lite_data = { + .datardsratio0 = K4B2G1646EBIH9_RD_DQS, + .datawdsratio0 = K4B2G1646EBIH9_WR_DQS, + .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE, + .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA, +}; + +static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + +static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = { + .cmd0csratio = K4B2G1646EBIH9_RATIO, + .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, + + .cmd1csratio = K4B2G1646EBIH9_RATIO, + .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, + + .cmd2csratio = K4B2G1646EBIH9_RATIO, + .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, +}; + +static struct emif_regs ddr3_igep0034_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; + +static struct emif_regs ddr3_igep0034_lite_emif_reg_data = { + .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG, + .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF, + .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1, + .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2, + .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3, + .zq_config = K4B2G1646EBIH9_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY, +}; + +const struct ctrl_ioregs ioregs_igep0034 = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; + +const struct ctrl_ioregs ioregs_igep0034_lite = { + .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, + .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE, +}; + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +void sdram_init(void) +{ + if (get_board_revision() == 1) + config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data, + &ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0); + else + config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data, + &ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0); +} +#endif + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + gpmc_init(); + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + switch (get_board_revision()) { + case 0: + setenv("board_name", "igep0034-lite"); + break; + case 1: + setenv("board_name", "igep0034"); + break; + default: + setenv("board_name", "igep0033"); + break; + } +#endif + return 0; +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + static struct node_info nodes[] = { + { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, + }; + + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif + return 0; +} +#endif + +#if defined(CONFIG_DRIVER_TI_CPSW) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int rv, ret = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN), + &cdev->miisel); + + if (get_board_revision() == 1) + cpsw_slaves[0].phy_addr = 1; + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + ret += rv; + + return ret; +} +#endif diff --git a/board/isee/igep0033/board.h b/board/isee/igep003x/board.h index a11d7ab86d..a11d7ab86d 100644 --- a/board/isee/igep0033/board.h +++ b/board/isee/igep003x/board.h diff --git a/board/isee/igep0033/mux.c b/board/isee/igep003x/mux.c index e86277663d..550e3b3197 100644 --- a/board/isee/igep0033/mux.c +++ b/board/isee/igep003x/mux.c @@ -32,7 +32,7 @@ static struct module_pin_mux mmc0_pin_mux[] = { {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ - {OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)}, /* MMC0_CD */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ {-1}, }; @@ -69,6 +69,12 @@ static struct module_pin_mux rmii1_pin_mux[] = { {-1}, }; +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(gpmc_ad10), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_26 */ + {OFFSET(gpmc_ad11), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_27 */ + {-1}, +}; + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -85,4 +91,6 @@ void enable_board_pin_mux(void) configure_module_pin_mux(mmc0_pin_mux); /* Ethernet pinmux. */ configure_module_pin_mux(rmii1_pin_mux); + /* GPIO pinmux. */ + configure_module_pin_mux(gpio_pin_mux); } diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index fdad8d13a7..dc3a9dcade 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -6,268 +6,83 @@ */ #include <common.h> +#include <dm.h> +#include <ram.h> #include <asm/io.h> #include <asm/armv7m.h> #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> -#include <asm/arch/fmc.h> #include <dm/platdata.h> #include <dm/platform_data/serial_stm32x7.h> #include <asm/arch/stm32_periph.h> #include <asm/arch/stm32_defs.h> #include <asm/arch/syscfg.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; -const struct stm32_gpio_ctl gpio_ctl_gpout = { - .mode = STM32_GPIO_MODE_OUT, - .otype = STM32_GPIO_OTYPE_PP, - .speed = STM32_GPIO_SPEED_50M, - .pupd = STM32_GPIO_PUPD_NO, - .af = STM32_GPIO_AF0 -}; - -const struct stm32_gpio_ctl gpio_ctl_fmc = { - .mode = STM32_GPIO_MODE_AF, - .otype = STM32_GPIO_OTYPE_PP, - .speed = STM32_GPIO_SPEED_100M, - .pupd = STM32_GPIO_PUPD_NO, - .af = STM32_GPIO_AF12 -}; - -static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { - /* Chip is LQFP144, see DM00077036.pdf for details */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ - {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ - - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ - {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ - - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ - - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ - - {STM32_GPIO_PORT_H, STM32_GPIO_PIN_3}, /* 136, SDRAM_NE */ - {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ - {STM32_GPIO_PORT_H, STM32_GPIO_PIN_5}, /* 26, SDRAM_NWE */ - {STM32_GPIO_PORT_C, STM32_GPIO_PIN_3}, /* 135, SDRAM_CKE */ - - {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ -}; - -static int fmc_setup_gpio(void) +int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size) { - int rv = 0; - int i; - - clock_setup(GPIO_B_CLOCK_CFG); - clock_setup(GPIO_C_CLOCK_CFG); - clock_setup(GPIO_D_CLOCK_CFG); - clock_setup(GPIO_E_CLOCK_CFG); - clock_setup(GPIO_F_CLOCK_CFG); - clock_setup(GPIO_G_CLOCK_CFG); - clock_setup(GPIO_H_CLOCK_CFG); + int mr_node; - for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { - rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], - &gpio_ctl_fmc); - if (rv) - goto out; - } + mr_node = fdt_path_offset(gd->fdt_blob, "/memory"); + if (mr_node < 0) + return mr_node; + *mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node, + "reg", 0, mr_size, false); + debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size); -out: - return rv; -} - -static inline u32 _ns2clk(u32 ns, u32 freq) -{ - u32 tmp = freq/1000000; - return (tmp * ns) / 1000; + return 0; } - -#define NS2CLK(ns) (_ns2clk(ns, freq)) - -/* - * Following are timings for IS42S16400J, from corresponding datasheet - */ -#define SDRAM_CAS 3 /* 3 cycles */ -#define SDRAM_NB 1 /* Number of banks */ -#define SDRAM_MWID 1 /* 16 bit memory */ - -#define SDRAM_NR 0x1 /* 12-bit row */ -#define SDRAM_NC 0x0 /* 8-bit col */ -#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ -#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ - -#define SDRAM_TRRD NS2CLK(12) -#define SDRAM_TRCD NS2CLK(18) -#define SDRAM_TRP NS2CLK(18) -#define SDRAM_TRAS NS2CLK(42) -#define SDRAM_TRC NS2CLK(60) -#define SDRAM_TRFC NS2CLK(60) -#define SDRAM_TCDL (1 - 1) -#define SDRAM_TRDL NS2CLK(12) -#define SDRAM_TBDL (1 - 1) -#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) -#define SDRAM_TCCD (1 - 1) - -#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */ -#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */ - - -/* Last data in to row precharge, need also comply ineq on page 1648 */ -#define SDRAM_TWR max(\ - (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \ - (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\ -) - - -#define SDRAM_MODE_BL_SHIFT 0 -#define SDRAM_MODE_CAS_SHIFT 4 -#define SDRAM_MODE_BL 0 -#define SDRAM_MODE_CAS SDRAM_CAS - int dram_init(void) { - u32 freq; + struct udevice *dev; int rv; + fdt_addr_t mr_base, mr_size; - rv = fmc_setup_gpio(); - if (rv) + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) { + debug("DRAM init failed: %d\n", rv); return rv; + } - clock_setup(FMC_CLOCK_CFG); - - /* - * Get frequency for NS2CLK calculation. - */ - freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; - - writel( - CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT - | SDRAM_CAS << FMC_SDCR_CAS_SHIFT - | SDRAM_NB << FMC_SDCR_NB_SHIFT - | SDRAM_MWID << FMC_SDCR_MWID_SHIFT - | SDRAM_NR << FMC_SDCR_NR_SHIFT - | SDRAM_NC << FMC_SDCR_NC_SHIFT - | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT - | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, - &STM32_SDRAM_FMC->sdcr1); - - writel( - SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT - | SDRAM_TRP << FMC_SDTR_TRP_SHIFT - | SDRAM_TWR << FMC_SDTR_TWR_SHIFT - | SDRAM_TRC << FMC_SDTR_TRC_SHIFT - | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT - | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT - | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, - &STM32_SDRAM_FMC->sdtr1); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, - &STM32_SDRAM_FMC->sdcmr); - - udelay(200); /* 200 us delay, page 10, "Power-Up" */ - FMC_BUSY_WAIT(); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, - &STM32_SDRAM_FMC->sdcmr); - - udelay(100); - FMC_BUSY_WAIT(); - - writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH - | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); - - udelay(100); - FMC_BUSY_WAIT(); - - writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT - | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) - << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, - &STM32_SDRAM_FMC->sdcmr); - - udelay(100); - - FMC_BUSY_WAIT(); - - writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, - &STM32_SDRAM_FMC->sdcmr); - - FMC_BUSY_WAIT(); + rv = get_memory_base_size(&mr_base, &mr_size); + if (rv) + return rv; + gd->ram_size = mr_size; + gd->ram_top = mr_base; - /* Refresh timer */ - writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); + return rv; +} +int dram_init_banksize(void) +{ + fdt_addr_t mr_base, mr_size; + get_memory_base_size(&mr_base, &mr_size); /* * Fill in global info with description of SRAM configuration */ - gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; - gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; - - gd->ram_size = CONFIG_SYS_RAM_SIZE; - - return rv; -} + gd->bd->bi_dram[0].start = mr_base; + gd->bd->bi_dram[0].size = mr_size; -int uart_setup_gpio(void) -{ - clock_setup(GPIO_A_CLOCK_CFG); - clock_setup(GPIO_B_CLOCK_CFG); return 0; } #ifdef CONFIG_ETH_DESIGNWARE - static int stmmac_setup(void) { clock_setup(SYSCFG_CLOCK_CFG); /* Set >RMII mode */ STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; - - clock_setup(GPIO_A_CLOCK_CFG); - clock_setup(GPIO_C_CLOCK_CFG); - clock_setup(GPIO_G_CLOCK_CFG); clock_setup(STMMAC_CLOCK_CFG); return 0; } -#endif - -#ifdef CONFIG_STM32_QSPI -static int qspi_setup(void) +int board_early_init_f(void) { - clock_setup(GPIO_B_CLOCK_CFG); - clock_setup(GPIO_D_CLOCK_CFG); - clock_setup(GPIO_E_CLOCK_CFG); + stmmac_setup(); + return 0; } #endif @@ -277,32 +92,44 @@ u32 get_board_rev(void) return 0; } -int board_early_init_f(void) +int board_late_init(void) { - int res; + struct gpio_desc gpio = {}; + int node; - res = uart_setup_gpio(); - if (res) - return res; + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1"); + if (node < 0) + return -1; -#ifdef CONFIG_ETH_DESIGNWARE - res = stmmac_setup(); - if (res) - return res; -#endif + gpio_request_by_name_nodev(gd->fdt_blob, node, "led-gpio", 0, &gpio, + GPIOD_IS_OUT); -#ifdef CONFIG_STM32_QSPI - res = qspi_setup(); - if (res) - return res; -#endif + if (dm_gpio_is_valid(&gpio)) { + dm_gpio_set_value(&gpio, 0); + mdelay(10); + dm_gpio_set_value(&gpio, 1); + } + + /* read button 1*/ + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1"); + if (node < 0) + return -1; + + gpio_request_by_name_nodev(gd->fdt_blob, node, "button-gpio", 0, &gpio, + GPIOD_IS_IN); + + if (dm_gpio_is_valid(&gpio)) { + if (dm_gpio_get_value(&gpio)) + puts("usr button is at HIGH LEVEL\n"); + else + puts("usr button is at LOW LEVEL\n"); + } return 0; } int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; return 0; } diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig deleted file mode 100644 index a667c9e5c5..0000000000 --- a/board/sunxi/Kconfig +++ /dev/null @@ -1,720 +0,0 @@ -if ARCH_SUNXI - -config IDENT_STRING - default " Allwinner Technology" - -# FIXME: Should not redefine these Kconfig symbols -config PRE_CONSOLE_BUFFER - default y - -config SPL_GPIO_SUPPORT - default y - -config SPL_LIBCOMMON_SUPPORT - default y - -config SPL_LIBDISK_SUPPORT - default y - -config SPL_LIBGENERIC_SUPPORT - default y - -config SPL_MMC_SUPPORT - depends on SPL && GENERIC_MMC - default y - -config SPL_POWER_SUPPORT - default y - -config SPL_SERIAL_SUPPORT - default y - -config SUNXI_HIGH_SRAM - bool - default n - ---help--- - Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, - with the first SRAM region being located at address 0. - Some newer SoCs map the boot ROM at address 0 instead and move the - SRAM to 64KB, just behind the mask ROM. - Chips using the latter setup are supposed to select this option to - adjust the addresses accordingly. - -# Note only one of these may be selected at a time! But hidden choices are -# not supported by Kconfig -config SUNXI_GEN_SUN4I - bool - ---help--- - Select this for sunxi SoCs which have resets and clocks set up - as the original A10 (mach-sun4i). - -config SUNXI_GEN_SUN6I - bool - ---help--- - Select this for sunxi SoCs which have sun6i like periphery, like - separate ahb reset control registers, custom pmic bus, new style - watchdog, etc. - - -config MACH_SUNXI_H3_H5 - bool - select SUNXI_GEN_SUN6I - select SUPPORT_SPL - -choice - prompt "Sunxi SoC Variant" - optional - -config MACH_SUN4I - bool "sun4i (Allwinner A10)" - select CPU_V7 - select ARM_CORTEX_CPU_IS_UP - select SUNXI_GEN_SUN4I - select SUPPORT_SPL - -config MACH_SUN5I - bool "sun5i (Allwinner A13)" - select CPU_V7 - select ARM_CORTEX_CPU_IS_UP - select SUNXI_GEN_SUN4I - select SUPPORT_SPL - -config MACH_SUN6I - bool "sun6i (Allwinner A31)" - select CPU_V7 - select CPU_V7_HAS_NONSEC - select CPU_V7_HAS_VIRT - select ARCH_SUPPORT_PSCI - select SUNXI_GEN_SUN6I - select SUPPORT_SPL - select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - -config MACH_SUN7I - bool "sun7i (Allwinner A20)" - select CPU_V7 - select CPU_V7_HAS_NONSEC - select CPU_V7_HAS_VIRT - select ARCH_SUPPORT_PSCI - select SUNXI_GEN_SUN4I - select SUPPORT_SPL - select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - -config MACH_SUN8I_A23 - bool "sun8i (Allwinner A23)" - select CPU_V7 - select CPU_V7_HAS_NONSEC - select CPU_V7_HAS_VIRT - select ARCH_SUPPORT_PSCI - select SUNXI_GEN_SUN6I - select SUPPORT_SPL - select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - -config MACH_SUN8I_A33 - bool "sun8i (Allwinner A33)" - select CPU_V7 - select CPU_V7_HAS_NONSEC - select CPU_V7_HAS_VIRT - select ARCH_SUPPORT_PSCI - select SUNXI_GEN_SUN6I - select SUPPORT_SPL - select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - -config MACH_SUN8I_A83T - bool "sun8i (Allwinner A83T)" - select CPU_V7 - select SUNXI_GEN_SUN6I - select SUPPORT_SPL - -config MACH_SUN8I_H3 - bool "sun8i (Allwinner H3)" - select CPU_V7 - select CPU_V7_HAS_NONSEC - select CPU_V7_HAS_VIRT - select ARCH_SUPPORT_PSCI - select MACH_SUNXI_H3_H5 - select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - -config MACH_SUN9I - bool "sun9i (Allwinner A80)" - select CPU_V7 - select SUNXI_HIGH_SRAM - select SUNXI_GEN_SUN6I - select SUPPORT_SPL - -config MACH_SUN50I - bool "sun50i (Allwinner A64)" - select ARM64 - select SUNXI_GEN_SUN6I - select SUNXI_HIGH_SRAM - select SUPPORT_SPL - -config MACH_SUN50I_H5 - bool "sun50i (Allwinner H5)" - select ARM64 - select MACH_SUNXI_H3_H5 - select SUNXI_HIGH_SRAM - -endchoice - -# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" -config MACH_SUN8I - bool - default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUNXI_H3_H5 || MACH_SUN8I_A83T - -config RESERVE_ALLWINNER_BOOT0_HEADER - bool "reserve space for Allwinner boot0 header" - select ENABLE_ARM_SOC_BOOT0_HOOK - ---help--- - Prepend a 1536 byte (empty) header to the U-Boot image file, to be - filled with magic values post build. The Allwinner provided boot0 - blob relies on this information to load and execute U-Boot. - Only needed on 64-bit Allwinner boards so far when using boot0. - -config ARM_BOOT_HOOK_RMR - bool - depends on ARM64 - default y - select ENABLE_ARM_SOC_BOOT0_HOOK - ---help--- - Insert some ARM32 code at the very beginning of the U-Boot binary - which uses an RMR register write to bring the core into AArch64 mode. - The very first instruction acts as a switch, since it's carefully - chosen to be a NOP in one mode and a branch in the other, so the - code would only be executed if not already in AArch64. - This allows both the SPL and the U-Boot proper to be entered in - either mode and switch to AArch64 if needed. - -config DRAM_TYPE - int "sunxi dram type" - depends on MACH_SUN8I_A83T - default 3 - ---help--- - Set the dram type, 3: DDR3, 7: LPDDR3 - -config DRAM_CLK - int "sunxi dram clock speed" - default 792 if MACH_SUN9I - default 312 if MACH_SUN6I || MACH_SUN8I - default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I - default 672 if MACH_SUN50I - ---help--- - Set the dram clock speed, valid range 240 - 480 (prior to sun9i), - must be a multiple of 24. For the sun9i (A80), the tested values - (for DDR3-1600) are 312 to 792. - -if MACH_SUN5I || MACH_SUN7I -config DRAM_MBUS_CLK - int "sunxi mbus clock speed" - default 300 - ---help--- - Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. - -endif - -config DRAM_ZQ - int "sunxi dram zq value" - default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I - default 127 if MACH_SUN7I - default 4145117 if MACH_SUN9I - default 3881915 if MACH_SUN50I - ---help--- - Set the dram zq value. - -config DRAM_ODT_EN - bool "sunxi dram odt enable" - default n if !MACH_SUN8I_A23 - default y if MACH_SUN8I_A23 - default y if MACH_SUN50I - ---help--- - Select this to enable dram odt (on die termination). - -if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I -config DRAM_EMR1 - int "sunxi dram emr1 value" - default 0 if MACH_SUN4I - default 4 if MACH_SUN5I || MACH_SUN7I - ---help--- - Set the dram controller emr1 value. - -config DRAM_TPR3 - hex "sunxi dram tpr3 value" - default 0 - ---help--- - Set the dram controller tpr3 parameter. This parameter configures - the delay on the command lane and also phase shifts, which are - applied for sampling incoming read data. The default value 0 - means that no phase/delay adjustments are necessary. Properly - configuring this parameter increases reliability at high DRAM - clock speeds. - -config DRAM_DQS_GATING_DELAY - hex "sunxi dram dqs_gating_delay value" - default 0 - ---help--- - Set the dram controller dqs_gating_delay parmeter. Each byte - encodes the DQS gating delay for each byte lane. The delay - granularity is 1/4 cycle. For example, the value 0x05060606 - means that the delay is 5 quarter-cycles for one lane (1.25 - cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. - The default value 0 means autodetection. The results of hardware - autodetection are not very reliable and depend on the chip - temperature (sometimes producing different results on cold start - and warm reboot). But the accuracy of hardware autodetection - is usually good enough, unless running at really high DRAM - clocks speeds (up to 600MHz). If unsure, keep as 0. - -choice - prompt "sunxi dram timings" - default DRAM_TIMINGS_VENDOR_MAGIC - ---help--- - Select the timings of the DDR3 chips. - -config DRAM_TIMINGS_VENDOR_MAGIC - bool "Magic vendor timings from Android" - ---help--- - The same DRAM timings as in the Allwinner boot0 bootloader. - -config DRAM_TIMINGS_DDR3_1066F_1333H - bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" - ---help--- - Use the timings of the standard JEDEC DDR3-1066F speed bin for - DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin - for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips - used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 - or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm - that down binning to DDR3-1066F is supported (because DDR3-1066F - uses a bit faster timings than DDR3-1333H). - -config DRAM_TIMINGS_DDR3_800E_1066G_1333J - bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" - ---help--- - Use the timings of the slowest possible JEDEC speed bin for the - selected DRAM_CLK. Depending on the DRAM_CLK value, it may be - DDR3-800E, DDR3-1066G or DDR3-1333J. - -endchoice - -endif - -if MACH_SUN8I_A23 -config DRAM_ODT_CORRECTION - int "sunxi dram odt correction value" - default 0 - ---help--- - Set the dram odt correction value (range -255 - 255). In allwinner - fex files, this option is found in bits 8-15 of the u32 odt_en variable - in the [dram] section. When bit 31 of the odt_en variable is set - then the correction is negative. Usually the value for this is 0. -endif - -config SYS_CLK_FREQ - default 816000000 if MACH_SUN50I - default 912000000 if MACH_SUN7I - default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I - -config SYS_CONFIG_NAME - default "sun4i" if MACH_SUN4I - default "sun5i" if MACH_SUN5I - default "sun6i" if MACH_SUN6I - default "sun7i" if MACH_SUN7I - default "sun8i" if MACH_SUN8I - default "sun9i" if MACH_SUN9I - default "sun50i" if MACH_SUN50I - -config SYS_BOARD - default "sunxi" - -config SYS_SOC - default "sunxi" - -config UART0_PORT_F - bool "UART0 on MicroSD breakout board" - default n - ---help--- - Repurpose the SD card slot for getting access to the UART0 serial - console. Primarily useful only for low level u-boot debugging on - tablets, where normal UART0 is difficult to access and requires - device disassembly and/or soldering. As the SD card can't be used - at the same time, the system can be only booted in the FEL mode. - Only enable this if you really know what you are doing. - -config OLD_SUNXI_KERNEL_COMPAT - bool "Enable workarounds for booting old kernels" - default n - ---help--- - Set this to enable various workarounds for old kernels, this results in - sub-optimal settings for newer kernels, only enable if needed. - -config MMC0_CD_PIN - string "Card detect pin for mmc0" - default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I - default "" - ---help--- - Set the card detect pin for mmc0, leave empty to not use cd. This - takes a string in the format understood by sunxi_name_to_gpio, e.g. - PH1 for pin 1 of port H. - -config MMC1_CD_PIN - string "Card detect pin for mmc1" - default "" - ---help--- - See MMC0_CD_PIN help text. - -config MMC2_CD_PIN - string "Card detect pin for mmc2" - default "" - ---help--- - See MMC0_CD_PIN help text. - -config MMC3_CD_PIN - string "Card detect pin for mmc3" - default "" - ---help--- - See MMC0_CD_PIN help text. - -config MMC1_PINS - string "Pins for mmc1" - default "" - ---help--- - Set the pins used for mmc1, when applicable. This takes a string in the - format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. - -config MMC2_PINS - string "Pins for mmc2" - default "" - ---help--- - See MMC1_PINS help text. - -config MMC3_PINS - string "Pins for mmc3" - default "" - ---help--- - See MMC1_PINS help text. - -config MMC_SUNXI_SLOT_EXTRA - int "mmc extra slot number" - default -1 - ---help--- - sunxi builds always enable mmc0, some boards also have a second sdcard - slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable - support for this. - -config INITIAL_USB_SCAN_DELAY - int "delay initial usb scan by x ms to allow builtin devices to init" - default 0 - ---help--- - Some boards have on board usb devices which need longer than the - USB spec's 1 second to connect from board powerup. Set this config - option to a non 0 value to add an extra delay before the first usb - bus scan. - -config USB0_VBUS_PIN - string "Vbus enable pin for usb0 (otg)" - default "" - ---help--- - Set the Vbus enable pin for usb0 (otg). This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config USB0_VBUS_DET - string "Vbus detect pin for usb0 (otg)" - default "" - ---help--- - Set the Vbus detect pin for usb0 (otg). This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config USB0_ID_DET - string "ID detect pin for usb0 (otg)" - default "" - ---help--- - Set the ID detect pin for usb0 (otg). This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config USB1_VBUS_PIN - string "Vbus enable pin for usb1 (ehci0)" - default "PH6" if MACH_SUN4I || MACH_SUN7I - default "PH27" if MACH_SUN6I - ---help--- - Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes - a string in the format understood by sunxi_name_to_gpio, e.g. - PH1 for pin 1 of port H. - -config USB2_VBUS_PIN - string "Vbus enable pin for usb2 (ehci1)" - default "PH3" if MACH_SUN4I || MACH_SUN7I - default "PH24" if MACH_SUN6I - ---help--- - See USB1_VBUS_PIN help text. - -config USB3_VBUS_PIN - string "Vbus enable pin for usb3 (ehci2)" - default "" - ---help--- - See USB1_VBUS_PIN help text. - -config I2C0_ENABLE - bool "Enable I2C/TWI controller 0" - default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I - default n if MACH_SUN6I || MACH_SUN8I - select CMD_I2C - ---help--- - This allows enabling I2C/TWI controller 0 by muxing its pins, enabling - its clock and setting up the bus. This is especially useful on devices - with slaves connected to the bus or with pins exposed through e.g. an - expansion port/header. - -config I2C1_ENABLE - bool "Enable I2C/TWI controller 1" - default n - select CMD_I2C - ---help--- - See I2C0_ENABLE help text. - -config I2C2_ENABLE - bool "Enable I2C/TWI controller 2" - default n - select CMD_I2C - ---help--- - See I2C0_ENABLE help text. - -if MACH_SUN6I || MACH_SUN7I -config I2C3_ENABLE - bool "Enable I2C/TWI controller 3" - default n - select CMD_I2C - ---help--- - See I2C0_ENABLE help text. -endif - -if SUNXI_GEN_SUN6I -config R_I2C_ENABLE - bool "Enable the PRCM I2C/TWI controller" - # This is used for the pmic on H3 - default y if SY8106A_POWER - select CMD_I2C - ---help--- - Set this to y to enable the I2C controller which is part of the PRCM. -endif - -if MACH_SUN7I -config I2C4_ENABLE - bool "Enable I2C/TWI controller 4" - default n - select CMD_I2C - ---help--- - See I2C0_ENABLE help text. -endif - -config AXP_GPIO - bool "Enable support for gpio-s on axp PMICs" - default n - ---help--- - Say Y here to enable support for the gpio pins of the axp PMIC ICs. - -config VIDEO - bool "Enable graphical uboot console on HDMI, LCD or VGA" - depends on !MACH_SUN8I_A83T && !MACH_SUNXI_H3_H5 && !MACH_SUN9I && !MACH_SUN50I - default y - ---help--- - Say Y here to add support for using a cfb console on the HDMI, LCD - or VGA output found on most sunxi devices. See doc/README.video for - info on how to select the video output and mode. - -config VIDEO_HDMI - bool "HDMI output support" - depends on VIDEO && !MACH_SUN8I - default y - ---help--- - Say Y here to add support for outputting video over HDMI. - -config VIDEO_VGA - bool "VGA output support" - depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) - default n - ---help--- - Say Y here to add support for outputting video over VGA. - -config VIDEO_VGA_VIA_LCD - bool "VGA via LCD controller support" - depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) - default n - ---help--- - Say Y here to add support for external DACs connected to the parallel - LCD interface driving a VGA connector, such as found on the - Olimex A13 boards. - -config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH - bool "Force sync active high for VGA via LCD controller support" - depends on VIDEO_VGA_VIA_LCD - default n - ---help--- - Say Y here if you've a board which uses opendrain drivers for the vga - hsync and vsync signals. Opendrain drivers cannot generate steep enough - positive edges for a stable video output, so on boards with opendrain - drivers the sync signals must always be active high. - -config VIDEO_VGA_EXTERNAL_DAC_EN - string "LCD panel power enable pin" - depends on VIDEO_VGA_VIA_LCD - default "" - ---help--- - Set the enable pin for the external VGA DAC. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config VIDEO_COMPOSITE - bool "Composite video output support" - depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) - default n - ---help--- - Say Y here to add support for outputting composite video. - -config VIDEO_LCD_MODE - string "LCD panel timing details" - depends on VIDEO - default "" - ---help--- - LCD panel timing details string, leave empty if there is no LCD panel. - This is in drivers/video/videomodes.c: video_get_params() format, e.g. - x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 - Also see: http://linux-sunxi.org/LCD - -config VIDEO_LCD_DCLK_PHASE - int "LCD panel display clock phase" - depends on VIDEO - default 1 - ---help--- - Select LCD panel display clock phase shift, range 0-3. - -config VIDEO_LCD_POWER - string "LCD panel power enable pin" - depends on VIDEO - default "" - ---help--- - Set the power enable pin for the LCD panel. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config VIDEO_LCD_RESET - string "LCD panel reset pin" - depends on VIDEO - default "" - ---help--- - Set the reset pin for the LCD panel. This takes a string in the format - understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config VIDEO_LCD_BL_EN - string "LCD panel backlight enable pin" - depends on VIDEO - default "" - ---help--- - Set the backlight enable pin for the LCD panel. This takes a string in the - the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of - port H. - -config VIDEO_LCD_BL_PWM - string "LCD panel backlight pwm pin" - depends on VIDEO - default "" - ---help--- - Set the backlight pwm pin for the LCD panel. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config VIDEO_LCD_BL_PWM_ACTIVE_LOW - bool "LCD panel backlight pwm is inverted" - depends on VIDEO - default y - ---help--- - Set this if the backlight pwm output is active low. - -config VIDEO_LCD_PANEL_I2C - bool "LCD panel needs to be configured via i2c" - depends on VIDEO - default n - select CMD_I2C - ---help--- - Say y here if the LCD panel needs to be configured via i2c. This - will add a bitbang i2c controller using gpios to talk to the LCD. - -config VIDEO_LCD_PANEL_I2C_SDA - string "LCD panel i2c interface SDA pin" - depends on VIDEO_LCD_PANEL_I2C - default "PG12" - ---help--- - Set the SDA pin for the LCD i2c interface. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config VIDEO_LCD_PANEL_I2C_SCL - string "LCD panel i2c interface SCL pin" - depends on VIDEO_LCD_PANEL_I2C - default "PG10" - ---help--- - Set the SCL pin for the LCD i2c interface. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - - -# Note only one of these may be selected at a time! But hidden choices are -# not supported by Kconfig -config VIDEO_LCD_IF_PARALLEL - bool - -config VIDEO_LCD_IF_LVDS - bool - - -choice - prompt "LCD panel support" - depends on VIDEO - ---help--- - Select which type of LCD panel to support. - -config VIDEO_LCD_PANEL_PARALLEL - bool "Generic parallel interface LCD panel" - select VIDEO_LCD_IF_PARALLEL - -config VIDEO_LCD_PANEL_LVDS - bool "Generic lvds interface LCD panel" - select VIDEO_LCD_IF_LVDS - -config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 - bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" - select VIDEO_LCD_SSD2828 - select VIDEO_LCD_IF_PARALLEL - ---help--- - 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 - -config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 - bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" - select VIDEO_LCD_ANX9804 - select VIDEO_LCD_IF_PARALLEL - select VIDEO_LCD_PANEL_I2C - ---help--- - Select this for eDP LCD panels with 4 lanes running at 1.62G, - connected via an ANX9804 bridge chip. - -config VIDEO_LCD_PANEL_HITACHI_TX18D42VM - bool "Hitachi tx18d42vm LCD panel" - select VIDEO_LCD_HITACHI_TX18D42VM - select VIDEO_LCD_IF_LVDS - ---help--- - 7.85" 1024x768 Hitachi tx18d42vm LCD panel support - -config VIDEO_LCD_TL059WV5C0 - bool "tl059wv5c0 LCD panel" - select VIDEO_LCD_PANEL_I2C - select VIDEO_LCD_IF_PARALLEL - ---help--- - 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and - Aigo M60/M608/M606 tablets. - -endchoice - - -config GMAC_TX_DELAY - int "GMAC Transmit Clock Delay Chain" - default 0 - ---help--- - Set the GMAC Transmit Clock Delay Chain value. - -config SPL_STACK_R_ADDR - default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I - default 0x2fe00000 if MACH_SUN9I - -endif diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 91ca6eaf7a..1c8817375d 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -109,6 +109,12 @@ M: Paul Kocialkowski <contact@paulk.fr> S: Maintained F: configs/Ampe_A76_defconfig +BANANAPI M2 ULTRA BOARD +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/Bananapi_M2_Ultra_defconfig +F: arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts + COLOMBUS BOARD M: Maxime Ripard <maxime.ripard@free-electrons.com> S: Maintained @@ -182,6 +188,11 @@ M: Jelle de Jong <jelledejong@powercraft.nl> S: Maintained F: configs/Lamobo_R1_defconfig +LICHEEPI-ZERO BOARD +M: Icenowy Zheng <icenowy@aosc.xyz> +S: Maintained +F: configs/LicheePi_Zero_defconfig + LINKSPRITE-PCDUINO BOARD M: Zoltan Herpai <wigyori@uid0.hu> S: Maintained @@ -232,6 +243,11 @@ M: Jelle van der Waa <jelle@vdwaa.nl> S: Maintained F: configs/nanopi_neo_defconfig +NANOPI-NEO-AIR BOARD +M: Jelle van der Waa <jelle@vdwaa.nl> +S: Maintained +F: configs/nanopi_neo_air_defconfig + NINTENDO NES CLASSIC EDITION BOARD M: FUKAUMI Naoki <naobsd@gmail.com> S: Maintained @@ -264,6 +280,11 @@ S: Maintained F: configs/Sinlinx_SinA33_defconfig W: http://linux-sunxi.org/Sinlinx_SinA33 +SINOVOIP BPI M2 PLUS H3 BOARD +M: Icenowy Zheng <icenowy@aosc.io> +S: Maintained +F: configs/Sinovoip_BPI_M2_Plus_defconfig + SINOVOIP BPI M3 A83T BOARD M: VishnuPatekar <vishnupatekar0510@gmail.com> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index b9660128e5..01de42d031 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -77,10 +77,104 @@ static int soft_i2c_board_init(void) { return 0; } DECLARE_GLOBAL_DATA_PTR; +void i2c_init_board(void) +{ +#ifdef CONFIG_I2C0_ENABLE +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN5I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); + clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); + clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); + clock_twi_onoff(0, 1); +#endif +#endif + +#ifdef CONFIG_I2C1_ENABLE +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); + clock_twi_onoff(1, 1); +#endif +#endif + +#ifdef CONFIG_I2C2_ENABLE +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); + clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); + clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); + clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); + clock_twi_onoff(2, 1); +#endif +#endif + +#ifdef CONFIG_I2C3_ENABLE +#if defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); + sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); + clock_twi_onoff(3, 1); +#elif defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); + sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); + clock_twi_onoff(3, 1); +#endif +#endif + +#ifdef CONFIG_I2C4_ENABLE +#if defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); + sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); + clock_twi_onoff(4, 1); +#endif +#endif + +#ifdef CONFIG_R_I2C_ENABLE + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); +#endif +} + /* add board specific code here */ int board_init(void) { - __maybe_unused int id_pfr1, ret; + __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin; gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); @@ -118,12 +212,22 @@ int board_init(void) return ret; #ifdef CONFIG_SATAPWR - gpio_request(CONFIG_SATAPWR, "satapwr"); - gpio_direction_output(CONFIG_SATAPWR, 1); + satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR); + gpio_request(satapwr_pin, "satapwr"); + gpio_direction_output(satapwr_pin, 1); #endif #ifdef CONFIG_MACPWR - gpio_request(CONFIG_MACPWR, "macpwr"); - gpio_direction_output(CONFIG_MACPWR, 1); + macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR); + gpio_request(macpwr_pin, "macpwr"); + gpio_direction_output(macpwr_pin, 1); +#endif + +#ifdef CONFIG_DM_I2C + /* + * Temporary workaround for enabling I2C clocks until proper sunxi DM + * clk, reset and pinctrl drivers land. + */ + i2c_init_board(); #endif /* Uses dm gpio code so do this here and not in i2c_init_board() */ @@ -199,7 +303,8 @@ static void mmc_pinmux_setup(int sdc) case 1: pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) if (pins == SUNXI_GPIO_H) { /* SDC1: PH22-PH-27 */ for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { @@ -294,6 +399,17 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(SUNXI_GPC(24), 2); } +#elif defined(CONFIG_MACH_SUN8I_R40) + /* SDC2: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) /* SDC2: PC5-PC6, PC8-PC16 */ for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { @@ -320,7 +436,8 @@ static void mmc_pinmux_setup(int sdc) case 3: pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) /* SDC3: PI4-PI9 */ for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); @@ -391,91 +508,6 @@ int board_mmc_init(bd_t *bis) } #endif -void i2c_init_board(void) -{ -#ifdef CONFIG_I2C0_ENABLE -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); - clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); - clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); - clock_twi_onoff(0, 1); -#endif -#endif - -#ifdef CONFIG_I2C1_ENABLE -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); - clock_twi_onoff(1, 1); -#endif -#endif - -#ifdef CONFIG_I2C2_ENABLE -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); - sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); - clock_twi_onoff(2, 1); -#elif defined(CONFIG_MACH_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); - sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); - clock_twi_onoff(2, 1); -#elif defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); - sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); - clock_twi_onoff(2, 1); -#elif defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); - sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); - clock_twi_onoff(2, 1); -#endif -#endif - -#ifdef CONFIG_I2C3_ENABLE -#if defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); - sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); - clock_twi_onoff(3, 1); -#elif defined(CONFIG_MACH_SUN7I) - sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); - sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); - clock_twi_onoff(3, 1); -#endif -#endif - -#ifdef CONFIG_I2C4_ENABLE -#if defined(CONFIG_MACH_SUN7I) - sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); - sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); - clock_twi_onoff(4, 1); -#endif -#endif - -#ifdef CONFIG_R_I2C_ENABLE - clock_twi_onoff(5, 1); - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); -#endif -} - #ifdef CONFIG_SPL_BUILD void sunxi_board_init(void) { diff --git a/board/terasic/de10-nano/MAINTAINERS b/board/terasic/de10-nano/MAINTAINERS new file mode 100644 index 0000000000..f4dd0dff3b --- /dev/null +++ b/board/terasic/de10-nano/MAINTAINERS @@ -0,0 +1,5 @@ +DE10-NANO BOARD +M: Dalon Westergreen <dwesterg@gmail.com> +S: Maintained +F: include/configs/socfpga_de10_nano.h +F: configs/socfpga_de10_nano_defconfig diff --git a/board/terasic/de10-nano/Makefile b/board/terasic/de10-nano/Makefile new file mode 100644 index 0000000000..ab38f4264f --- /dev/null +++ b/board/terasic/de10-nano/Makefile @@ -0,0 +1,9 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2017, Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o diff --git a/board/terasic/de10-nano/qts/iocsr_config.h b/board/terasic/de10-nano/qts/iocsr_config.h new file mode 100644 index 0000000000..7e049bf81e --- /dev/null +++ b/board/terasic/de10-nano/qts/iocsr_config.h @@ -0,0 +1,660 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00020080, + 0x18060000, + 0x08000000, + 0x00018020, + 0x00000000, + 0x00004000, + 0x00010040, + 0x04010000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x00020000, + 0x02008000, + 0x02000000, + 0x00000008, + 0x00002008, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00100000, + 0x10040000, + 0x100000C0, + 0x00000040, + 0x00010040, + 0x00008000, + 0x00060180, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x00010040, + 0x10000000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x00020000, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00010000, + 0x04000000, + 0x00000000, + 0x00000010, + 0x00004000, + 0x00000800, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000008, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00401000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00600802, + 0x00000000, + 0x80200000, + 0x80000600, + 0x00000200, + 0x00000100, + 0x00300401, + 0xC0100400, + 0x40100000, + 0x40000300, + 0x000C0100, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x300C0300, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C0300C0, + 0x00008000, + 0x00080000, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00020000, + 0x00004000, + 0x200300C0, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x00002000, + 0x10018060, + 0x06018000, + 0x06000000, + 0x00010018, + 0x00006018, + 0x00001000, + 0x00010000, + 0x00000000, + 0x03000000, + 0x0000800C, + 0x00C01004, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x45034071, + 0x0A281A01, + 0x806180D0, + 0x34071C06, + 0x01A034D0, + 0x180D0000, + 0x71C06806, + 0x01450340, + 0xD000001A, + 0x0680E380, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x45034071, + 0x0A281A01, + 0x806180D0, + 0x34071C06, + 0x01A00040, + 0x180D0002, + 0x71C06806, + 0x01450340, + 0xD00A281A, + 0x06806180, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x79E47A03, + 0xCAAAA3DD, + 0xF6D5551E, + 0x0352D348, + 0x821A0000, + 0x0000D000, + 0x030C0680, + 0xD559647A, + 0x1ECAAAA3, + 0xC8F6D965, + 0x00034AB2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x79E47A03, + 0x8B2CA3DD, + 0xF6D9651E, + 0x034AB2C8, + 0x821A0041, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8B2CA3, + 0xC8F6D965, + 0x00034AB2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8AAAA3D5, + 0xF6D9651E, + 0x034AB2C8, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8B2CA3, + 0xC8F6D965, + 0x00034AB2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8B2CA3D5, + 0xF6D9651E, + 0x0352D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8B2CA3, + 0x48F6D965, + 0x000352D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/terasic/de10-nano/qts/pinmux_config.h b/board/terasic/de10-nano/qts/pinmux_config.h new file mode 100644 index 0000000000..b8f5ea1413 --- /dev/null +++ b/board/terasic/de10-nano/qts/pinmux_config.h @@ -0,0 +1,219 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 1, /* GENERALIO15 */ + 1, /* GENERALIO16 */ + 1, /* GENERALIO17 */ + 1, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 0, /* MIXED1IO15 */ + 0, /* MIXED1IO16 */ + 0, /* MIXED1IO17 */ + 0, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 1, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 1, /* I2C3USEFPGA */ + 1, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 1 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/terasic/de10-nano/qts/pll_config.h b/board/terasic/de10-nano/qts/pll_config.h new file mode 100644 index 0000000000..3a46047d1c --- /dev/null +++ b/board/terasic/de10-nano/qts/pll_config.h @@ -0,0 +1,85 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 50000000 +#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 +#define CONFIG_HPS_CLK_QSPI_HZ 3125000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 12500000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/terasic/de10-nano/qts/sdram_config.h b/board/terasic/de10-nano/qts/sdram_config.h new file mode 100644 index 0000000000..34dacc717e --- /dev/null +++ b/board/terasic/de10-nano/qts/sdram_config.h @@ -0,0 +1,344 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 8 +#define CALIB_VFIFO_OFFSET 6 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504a1 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080431, + 0x10080530, + 0x10090044, + 0x100a0010, + 0x100b0000, + 0x10380400, + 0x10080449, + 0x100804c8, + 0x100a0024, + 0x10090008, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/terasic/de10-nano/socfpga.c b/board/terasic/de10-nano/socfpga.c new file mode 100644 index 0000000000..c5852e7cb4 --- /dev/null +++ b/board/terasic/de10-nano/socfpga.c @@ -0,0 +1,6 @@ +/* + * Copyright (C) 2017, Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> diff --git a/board/theobroma-systems/puma_rk3399/Kconfig b/board/theobroma-systems/puma_rk3399/Kconfig new file mode 100644 index 0000000000..a645590d78 --- /dev/null +++ b/board/theobroma-systems/puma_rk3399/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PUMA_RK3399 + +config SYS_BOARD + default "puma_rk3399" + +config SYS_VENDOR + default "theobroma-systems" + +config SYS_CONFIG_NAME + default "puma_rk3399" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS b/board/theobroma-systems/puma_rk3399/MAINTAINERS new file mode 100644 index 0000000000..ccec09c386 --- /dev/null +++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS @@ -0,0 +1,10 @@ +PUMA-RK3399 +M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> +M: Klaus Goger <klaus.goger@theobroma-systems.com> +S: Maintained +F: board/theobroma-systems/puma_rk3399 +F: include/configs/puma_rk3399.h +F: arch/arm/dts/rk3399-puma.dts +F: configs/puma-rk3399_defconfig +W: https://www.theobroma-systems.com/rk3399-q7/tech-specs +T: git git://git.theobroma-systems.com/puma-u-boot.git diff --git a/board/theobroma-systems/puma_rk3399/Makefile b/board/theobroma-systems/puma_rk3399/Makefile new file mode 100644 index 0000000000..d962b56f11 --- /dev/null +++ b/board/theobroma-systems/puma_rk3399/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += puma-rk3399.o diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README new file mode 100644 index 0000000000..1a8d02b480 --- /dev/null +++ b/board/theobroma-systems/puma_rk3399/README @@ -0,0 +1,73 @@ +Introduction +============ + +The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip +RK3399 in a Qseven-compatible form-factor. + +RK3399-Q7 features: + * CPU: ARMv8 64bit Big-Little architecture, + * Big: dual-core Cortex-A72 + * Little: quad-core Cortex-A53 + * IRAM: 200KB + * DRAM: 4GB-128MB dual-channel + * eMMC: onboard eMMC + * SD/MMC + * GbE (onboard Micrel KSZ9031) Gigabit ethernet PHY + * USB: + * USB3.0 dual role port + * 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub + * Display: HDMI/eDP/MIPI + * Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF) + * NOR Flash: onboard SPI NOR + * Companion Controller: onboard additional Cortex-M0 microcontroller + * RTC + * fan controller + * CAN + +Here is the step-by-step to boot to U-Boot on rk3399. + +Get the Source and build ATF/Cortex-M0 binaries +=============================================== + + > git clone git://git.theobroma-systems.com/arm-trusted-firmware.git + > git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git + +Compile the ATF +=============== + + > cd arm-trusted-firmware + > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 + > cp build/rk3399/release/bl31.bin ../u-boot + +Compile the M0 firmware +======================= + + > cd ../rk3399-cortex-m0 + > make CROSS_COMPILE=arm-cortex_m0-eabi- + > cp rk3399m0.bin ../u-boot + +Compile the U-Boot +================== + + > cd ../u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- puma-rk3399_defconfig all + +Package the image +================= + + > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl.img + > tools/mkimage -f board/theobroma/puma_rk3399/fit_spl_atf.its \ + -E rk3399_bl3x.itb + +Flash the image +=============== + +Copy the SPL to offset 32k and the FIT image containing the payloads +(U-Boot proper, ATF, M0 Firmware, devicetree) to offset 256k on a SD +card. + + > dd if=spl.img of=/dev/sdb seek=64 + > dd if=rk3399_bl3x.itb of=/dev/sdb seek=512 + +After powering up the board (with the inserted SD card), you should see +a U-Boot console on UART0 (115200n8). diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its new file mode 100644 index 0000000000..f93c251927 --- /dev/null +++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * Minimal dts for a SPL FIT image payload. + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; + +/ { + description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB"; + #address-cells = <1>; + + images { + uboot@1 { + description = "U-Boot (64-bit)"; + data = /incbin/("../../../u-boot-nodtb.bin"); + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x00200000>; + }; + atf@1 { + description = "ARM Trusted Firmware"; + data = /incbin/("../../../bl31.bin"); + type = "firmware"; + arch = "arm64"; + compression = "none"; + load = <0x00001000>; + entry = <0x00001000>; + }; + pmu@1 { + description = "Cortex-M0 firmware"; + data = /incbin/("../../../rk3399m0.bin"); + type = "pmu-firmware"; + compression = "none"; + load = <0xff8c0000>; + }; + fdt@1 { + description = "RK3399-Q7 (Puma) flat device-tree"; + data = /incbin/("../../../u-boot.dtb"); + type = "flat_dt"; + compression = "none"; + }; + }; + + configurations { + default = "conf@1"; + conf@1 { + description = "Theobroma Systems RK3399-Q7 (Puma) SoM"; + firmware = "uboot@1"; + loadables = "atf@1"; + fdt = "fdt@1"; + }; + }; +}; diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c new file mode 100644 index 0000000000..fb4d31e01d --- /dev/null +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <dm/uclass-internal.h> +#include <asm/arch/periph.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + struct udevice *pinctrl, *regulator; + int ret; + + /* + * The PWM does not have decicated interrupt number in dts and can + * not get periph_id by pinctrl framework, so let's init them here. + * The PWM2 and PWM3 are for pwm regulators. + */ + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto out; + } + + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2); + if (ret) { + debug("%s PWM2 pinctrl init fail!\n", __func__); + goto out; + } + + /* rk3399 need to init vdd_center to get the correct output voltage */ + ret = regulator_get_by_platname("vdd_center", ®ulator); + if (ret) + debug("%s: Cannot get vdd_center regulator\n", __func__); + + ret = regulator_get_by_platname("vcc5v0_host", ®ulator); + if (ret) { + debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret); + goto out; + } + + ret = regulator_set_enable(regulator, true); + if (ret) { + debug("%s vcc5v0-host-en set fail!\n", __func__); + goto out; + } + +out: + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x80000000; + return 0; +} + +int dram_init_banksize(void) +{ + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = 0x7e000000; + + return 0; +} diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 390cc168cd..2572029a25 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -694,7 +694,7 @@ int usb_gadget_handle_interrupts(int index) #endif /* CONFIG_USB_DWC3 */ #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) -int board_usb_init(int index, enum usb_init_type init) +int omap_xhci_board_usb_init(int index, enum usb_init_type init) { enable_usb_clocks(index); #ifdef CONFIG_USB_DWC3 @@ -725,7 +725,7 @@ int board_usb_init(int index, enum usb_init_type init) return 0; } -int board_usb_cleanup(int index, enum usb_init_type init) +int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init) { #ifdef CONFIG_USB_DWC3 switch (index) { diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 1cfc08bc9c..6d444e09fa 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -720,7 +720,7 @@ int usb_gadget_handle_interrupts(int index) #endif /* CONFIG_USB_DWC3 */ #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) -int board_usb_init(int index, enum usb_init_type init) +int omap_xhci_board_usb_init(int index, enum usb_init_type init) { enable_usb_clocks(index); switch (index) { @@ -754,7 +754,7 @@ int board_usb_init(int index, enum usb_init_type init) return 0; } -int board_usb_cleanup(int index, enum usb_init_type init) +int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init) { #ifdef CONFIG_USB_DWC3 switch (index) { diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index 15b5ccf741..08c39d9409 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -13,3 +13,29 @@ config EEPROM_CHIP_ADDRESS hex "Board EEPROM's I2C chip address" range 0 0xff default 0x50 + +config TI_COMMON_CMD_OPTIONS + bool "Enable cmd options on TI platforms" + imply CMD_ASKENV + imply CMD_BOOTZ + imply CMD_DFU if USB_GADGET_DOWNLOAD + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_EXT4_WRITE + imply CMD_FASTBOOT if FASTBOOT + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_GPIO + imply CMD_GPT + imply CMD_I2C + imply CMD_MII + imply CMD_MMC + imply CMD_PART + imply CMD_PING + imply CMD_PMIC if DM_PMIC + imply CMD_REGULATOR if DM_REGULATOR + imply CMD_SF if SPI_FLASH + imply CMD_SPI + imply CMD_TIME + imply CMD_USB if USB diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index ae2d59da43..d8e48dd3f8 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -438,14 +438,18 @@ struct vcores_data dra718_volts = { * and are powered by BUCK1 of LP873X PMIC */ .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, + .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = LP873X_REG_ADDR_BUCK1, .eve.pmic = &lp8733, .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, + .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = LP873X_REG_ADDR_BUCK1, .iva.pmic = &lp8733, @@ -456,27 +460,44 @@ int get_voltrail_opp(int rail_offset) { int opp; - /* - * DRA71x supports only OPP_NOM. - */ - if (board_is_dra71x_evm()) - return OPP_NOM; - switch (rail_offset) { case VOLT_MPU: opp = DRA7_MPU_OPP; + /* DRA71x supports only OPP_NOM for MPU */ + if (board_is_dra71x_evm()) + opp = OPP_NOM; break; case VOLT_CORE: opp = DRA7_CORE_OPP; + /* DRA71x supports only OPP_NOM for CORE */ + if (board_is_dra71x_evm()) + opp = OPP_NOM; break; case VOLT_GPU: opp = DRA7_GPU_OPP; + /* DRA71x supports only OPP_NOM for GPU */ + if (board_is_dra71x_evm()) + opp = OPP_NOM; break; case VOLT_EVE: opp = DRA7_DSPEVE_OPP; + /* + * DRA71x does not support OPP_OD for EVE. + * If OPP_OD is selected by menuconfig, fallback + * to OPP_NOM. + */ + if (board_is_dra71x_evm() && opp == OPP_OD) + opp = OPP_NOM; break; case VOLT_IVA: opp = DRA7_IVA_OPP; + /* + * DRA71x does not support OPP_OD for IVA. + * If OPP_OD is selected by menuconfig, fallback + * to OPP_NOM. + */ + if (board_is_dra71x_evm() && opp == OPP_OD) + opp = OPP_NOM; break; default: opp = OPP_NOM; @@ -729,7 +750,7 @@ static struct ti_usb_phy_device usb_phy2_device = { .index = 1, }; -int board_usb_init(int index, enum usb_init_type init) +int omap_xhci_board_usb_init(int index, enum usb_init_type init) { enable_usb_clocks(index); switch (index) { @@ -766,7 +787,7 @@ int board_usb_init(int index, enum usb_init_type init) return 0; } -int board_usb_cleanup(int index, enum usb_init_type init) +int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init) { switch (index) { case 0: diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index cbb3077bc3..64f0c9cd5b 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -14,12 +14,30 @@ DECLARE_GLOBAL_DATA_PTR; -unsigned int external_clk[ext_clk_count] = { - [sys_clk] = 100000000, - [alt_core_clk] = 100000000, - [pa_clk] = 100000000, - [ddr3a_clk] = 100000000, -}; +unsigned int get_external_clk(u32 clk) +{ + unsigned int clk_freq; + + switch (clk) { + case sys_clk: + clk_freq = 100000000; + break; + case alt_core_clk: + clk_freq = 100000000; + break; + case pa_clk: + clk_freq = 100000000; + break; + case ddr3a_clk: + clk_freq = 100000000; + break; + default: + clk_freq = 0; + break; + } + + return clk_freq; +} static struct pll_init_data core_pll_config[NUM_SPDS] = { [SPD800] = CORE_PLL_800, diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 79e110ef48..6e03f6bcd0 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -14,16 +14,42 @@ #include "mux-k2g.h" #include "../common/board_detect.h" -#define SYS_CLK 24000000 - -unsigned int external_clk[ext_clk_count] = { - [sys_clk] = SYS_CLK, - [pa_clk] = SYS_CLK, - [tetris_clk] = SYS_CLK, - [ddr3a_clk] = SYS_CLK, - [uart_clk] = SYS_CLK, +const unsigned int sysclk_array[MAX_SYSCLK] = { + 19200000, + 24000000, + 25000000, + 26000000, }; +unsigned int get_external_clk(u32 clk) +{ + unsigned int clk_freq; + u8 sysclk_index = get_sysclk_index(); + + switch (clk) { + case sys_clk: + clk_freq = sysclk_array[sysclk_index]; + break; + case pa_clk: + clk_freq = sysclk_array[sysclk_index]; + break; + case tetris_clk: + clk_freq = sysclk_array[sysclk_index]; + break; + case ddr3a_clk: + clk_freq = sysclk_array[sysclk_index]; + break; + case uart_clk: + clk_freq = sysclk_array[sysclk_index]; + break; + default: + clk_freq = 0; + break; + } + + return clk_freq; +} + static int arm_speeds[DEVSPEED_NUMSPDS] = { SPD400, SPD600, @@ -48,49 +74,116 @@ static int dev_speeds[DEVSPEED_NUMSPDS] = { SPD400, }; -static struct pll_init_data main_pll_config[NUM_SPDS] = { - [SPD400] = {MAIN_PLL, 100, 3, 2}, - [SPD600] = {MAIN_PLL, 300, 6, 2}, - [SPD800] = {MAIN_PLL, 200, 3, 2}, - [SPD900] = {TETRIS_PLL, 75, 1, 2}, - [SPD1000] = {TETRIS_PLL, 250, 3, 2}, +static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = { + [SYSCLK_19MHz] = { + [SPD400] = {MAIN_PLL, 125, 3, 2}, + [SPD600] = {MAIN_PLL, 125, 2, 2}, + [SPD800] = {MAIN_PLL, 250, 3, 2}, + [SPD900] = {TETRIS_PLL, 187, 2, 2}, + [SPD1000] = {TETRIS_PLL, 104, 1, 2}, + }, + [SYSCLK_24MHz] = { + [SPD400] = {MAIN_PLL, 100, 3, 2}, + [SPD600] = {MAIN_PLL, 300, 6, 2}, + [SPD800] = {MAIN_PLL, 200, 3, 2}, + [SPD900] = {TETRIS_PLL, 75, 1, 2}, + [SPD1000] = {TETRIS_PLL, 250, 3, 2}, + }, + [SYSCLK_25MHz] = { + [SPD400] = {MAIN_PLL, 32, 1, 2}, + [SPD600] = {MAIN_PLL, 48, 1, 2}, + [SPD800] = {MAIN_PLL, 64, 1, 2}, + [SPD900] = {TETRIS_PLL, 72, 1, 2}, + [SPD1000] = {TETRIS_PLL, 80, 1, 2}, + }, + [SYSCLK_26MHz] = { + [SPD400] = {MAIN_PLL, 400, 13, 2}, + [SPD600] = {MAIN_PLL, 230, 5, 2}, + [SPD800] = {MAIN_PLL, 123, 2, 2}, + [SPD900] = {TETRIS_PLL, 69, 1, 2}, + [SPD1000] = {TETRIS_PLL, 384, 5, 2}, + }, }; -static struct pll_init_data tetris_pll_config[NUM_SPDS] = { - [SPD200] = {TETRIS_PLL, 250, 3, 10}, - [SPD400] = {TETRIS_PLL, 100, 1, 6}, - [SPD600] = {TETRIS_PLL, 100, 1, 4}, - [SPD800] = {TETRIS_PLL, 400, 3, 4}, - [SPD900] = {TETRIS_PLL, 75, 1, 2}, - [SPD1000] = {TETRIS_PLL, 250, 3, 2}, +static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = { + [SYSCLK_19MHz] = { + [SPD200] = {TETRIS_PLL, 625, 6, 10}, + [SPD400] = {TETRIS_PLL, 125, 1, 6}, + [SPD600] = {TETRIS_PLL, 125, 1, 4}, + [SPD800] = {TETRIS_PLL, 333, 2, 4}, + [SPD900] = {TETRIS_PLL, 187, 2, 2}, + [SPD1000] = {TETRIS_PLL, 104, 1, 2}, + }, + [SYSCLK_24MHz] = { + [SPD200] = {TETRIS_PLL, 250, 3, 10}, + [SPD400] = {TETRIS_PLL, 100, 1, 6}, + [SPD600] = {TETRIS_PLL, 100, 1, 4}, + [SPD800] = {TETRIS_PLL, 400, 3, 4}, + [SPD900] = {TETRIS_PLL, 75, 1, 2}, + [SPD1000] = {TETRIS_PLL, 250, 3, 2}, + }, + [SYSCLK_25MHz] = { + [SPD200] = {TETRIS_PLL, 80, 1, 10}, + [SPD400] = {TETRIS_PLL, 96, 1, 6}, + [SPD600] = {TETRIS_PLL, 96, 1, 4}, + [SPD800] = {TETRIS_PLL, 128, 1, 4}, + [SPD900] = {TETRIS_PLL, 72, 1, 2}, + [SPD1000] = {TETRIS_PLL, 80, 1, 2}, + }, + [SYSCLK_26MHz] = { + [SPD200] = {TETRIS_PLL, 307, 4, 10}, + [SPD400] = {TETRIS_PLL, 369, 4, 6}, + [SPD600] = {TETRIS_PLL, 369, 4, 4}, + [SPD800] = {TETRIS_PLL, 123, 1, 4}, + [SPD900] = {TETRIS_PLL, 69, 1, 2}, + [SPD1000] = {TETRIS_PLL, 384, 5, 2}, + }, +}; + +static struct pll_init_data uart_pll_config[MAX_SYSCLK] = { + [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8}, + [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8}, + [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10}, + [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2}, }; -static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; -static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; -static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 133, 1, 16}; +static struct pll_init_data nss_pll_config[MAX_SYSCLK] = { + [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2}, + [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2}, + [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2}, + [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2}, +}; + +static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = { + [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16}, + [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16}, + [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16}, + [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16}, +}; struct pll_init_data *get_pll_init_data(int pll) { int speed; struct pll_init_data *data = NULL; + u8 sysclk_index = get_sysclk_index(); switch (pll) { case MAIN_PLL: speed = get_max_dev_speed(dev_speeds); - data = &main_pll_config[speed]; + data = &main_pll_config[sysclk_index][speed]; break; case TETRIS_PLL: speed = get_max_arm_speed(arm_speeds); - data = &tetris_pll_config[speed]; + data = &tetris_pll_config[sysclk_index][speed]; break; case NSS_PLL: - data = &nss_pll_config; + data = &nss_pll_config[sysclk_index]; break; case UART_PLL: - data = &uart_pll_config; + data = &uart_pll_config[sysclk_index]; break; case DDR3_PLL: - data = &ddr3_pll_config; + data = &ddr3_pll_config[sysclk_index]; break; default: data = NULL; diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index e217beaed5..b35f24d7b5 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -23,6 +23,37 @@ unsigned int external_clk[ext_clk_count] = { [ddr3b_clk] = 100000000, }; +unsigned int get_external_clk(u32 clk) +{ + unsigned int clk_freq; + + switch (clk) { + case sys_clk: + clk_freq = 122880000; + break; + case alt_core_clk: + clk_freq = 125000000; + break; + case pa_clk: + clk_freq = 122880000; + break; + case tetris_clk: + clk_freq = 125000000; + break; + case ddr3a_clk: + clk_freq = 100000000; + break; + case ddr3b_clk: + clk_freq = 100000000; + break; + default: + clk_freq = 0; + break; + } + + return clk_freq; +} + static struct pll_init_data core_pll_config[NUM_SPDS] = { [SPD800] = CORE_PLL_799, [SPD1000] = CORE_PLL_999, diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index 2a2e0057e2..f3eea4200c 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -14,13 +14,33 @@ DECLARE_GLOBAL_DATA_PTR; -unsigned int external_clk[ext_clk_count] = { - [sys_clk] = 122880000, - [alt_core_clk] = 100000000, - [pa_clk] = 122880000, - [tetris_clk] = 122880000, - [ddr3a_clk] = 100000000, -}; +unsigned int get_external_clk(u32 clk) +{ + unsigned int clk_freq; + + switch (clk) { + case sys_clk: + clk_freq = 122880000; + break; + case alt_core_clk: + clk_freq = 100000000; + break; + case pa_clk: + clk_freq = 122880000; + break; + case tetris_clk: + clk_freq = 122880000; + break; + case ddr3a_clk: + clk_freq = 100000000; + break; + default: + clk_freq = 0; + break; + } + + return clk_freq; +} static struct pll_init_data core_pll_config[NUM_SPDS] = { [SPD800] = CORE_PLL_799, diff --git a/board/ti/sdp4430/Kconfig b/board/ti/sdp4430/Kconfig index 5826d8fd0b..36f1852821 100644 --- a/board/ti/sdp4430/Kconfig +++ b/board/ti/sdp4430/Kconfig @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "omap4_sdp4430" +config CMD_BAT + bool "Enable board-specific battery command" + endif diff --git a/board/warp7/MAINTAINERS b/board/warp7/MAINTAINERS index 1d3ee29222..0fc9746606 100644 --- a/board/warp7/MAINTAINERS +++ b/board/warp7/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/warp7/ F: include/configs/warp7.h F: configs/warp7_defconfig +F: configs/warp7_secure_defconfig |