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-rw-r--r--board/engicam/geam6ul/MAINTAINERS1
-rw-r--r--board/freescale/mx6qsabreauto/mx6qsabreauto.c28
-rw-r--r--board/udoo/neo/neo.c7
-rw-r--r--board/warp7/warp7.c14
4 files changed, 46 insertions, 4 deletions
diff --git a/board/engicam/geam6ul/MAINTAINERS b/board/engicam/geam6ul/MAINTAINERS
index 66914509a1..079370ccb9 100644
--- a/board/engicam/geam6ul/MAINTAINERS
+++ b/board/engicam/geam6ul/MAINTAINERS
@@ -4,3 +4,4 @@ S: Maintained
F: board/engicam/geam6ul
F: include/configs/imx6ul_geam.h
F: configs/imx6ul_geam_mmc_defconfig
+F: configs/imx6ul_geam_nand_defconfig
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 5fca4d11e0..51bbbc4cdf 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -231,6 +231,33 @@ static void eimnor_cs_setup(void)
set_chipselect_size(CS0_128);
}
+static void eim_clk_setup(void)
+{
+ struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int cscmr1, ccgr6;
+
+
+ /* Turn off EIM clock */
+ ccgr6 = readl(&imx_ccm->CCGR6);
+ ccgr6 &= ~(0x3 << 10);
+ writel(ccgr6, &imx_ccm->CCGR6);
+
+ /*
+ * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
+ * and aclk_eim_slow_podf = 01 --> divide by 2
+ * so that we can have EIM at the maximum clock of 132MHz
+ */
+ cscmr1 = readl(&imx_ccm->cscmr1);
+ cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
+ MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
+ cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
+ writel(cscmr1, &imx_ccm->cscmr1);
+
+ /* Turn on EIM clock */
+ ccgr6 |= (0x3 << 10);
+ writel(ccgr6, &imx_ccm->CCGR6);
+}
+
static void setup_iomux_eimnor(void)
{
imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
@@ -519,6 +546,7 @@ int board_early_init_f(void)
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
+ eim_clk_setup();
return 0;
}
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index 688b522ce3..530c45f600 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -349,9 +349,9 @@ int board_init(void)
/* Active high for ncp692 */
gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
- #ifdef CONFIG_SYS_I2C_MXC
+#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- #endif
+#endif
return 0;
}
@@ -389,9 +389,8 @@ int board_early_init_f(void)
return 0;
}
-static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC2_BASE_ADDR, 0, 4},
- {USDHC3_BASE_ADDR, 0, 4},
};
#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c
index da9afb4ccd..df8e9da6f9 100644
--- a/board/warp7/warp7.c
+++ b/board/warp7/warp7.c
@@ -19,6 +19,7 @@
#include <mmc.h>
#include <asm/arch/crm_regs.h>
#include <usb.h>
+#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../freescale/common/pfuze.h"
@@ -138,6 +139,19 @@ int power_init_board(void)
}
#endif
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#ifdef CONFIG_USB_ETHER
+ ret = usb_eth_initialize(bis);
+ if (ret < 0)
+ printf("Error %d registering USB ether.\n", ret);
+#endif
+
+ return ret;
+}
+
int board_init(void)
{
/* address of boot parameters */