diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/ads5121/ads5121.c | 13 | ||||
| -rw-r--r-- | board/amcc/kilauea/kilauea.c | 14 | ||||
| -rw-r--r-- | board/freescale/mpc8544ds/Makefile | 2 |
3 files changed, 19 insertions, 10 deletions
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 8531657bde..1582c22067 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -33,7 +33,8 @@ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ CLOCK_SCCR1_PSCFIFO_EN | \ CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN) + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_TPR_EN) #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ CLOCK_SCCR2_SPDIF_EN | \ @@ -139,7 +140,7 @@ long int fixed_sdram (void) im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU; im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU; im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU; - im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AU; + im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL; im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL; im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL; im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL; @@ -180,9 +181,17 @@ int checkboard (void) { ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00); uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02); + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile unsigned long *reg; + int i; printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", brd_rev, cpld_rev); + + /* change the slew rate on all pata pins to max */ + reg = (unsigned long *) &(im->io_ctrl.regs[PATA_CE1_IDX]); + for (i = 0; i < 9; i++) + reg[i] |= 0x00000003; return 0; } diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 2ee896abd9..37ef06ef2a 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -192,13 +192,6 @@ int board_early_init_f (void) */ mtsdr(SDR0_SRST, 0); - /* - * Configure FPGA register with PCIe reset - */ - out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */ - mdelay(50); - out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */ - /* Configure 405EX for NAND usage */ val = SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | @@ -214,6 +207,13 @@ int board_early_init_f (void) val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; mtsdr(SDR0_PFC1, val); + /* + * Configure FPGA register with PCIe reset + */ + out_be32((void *)CFG_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ + mdelay(50); + out_be32((void *)CFG_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */ + return 0; } diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile index 006fdc95e7..c6f159ac81 100644 --- a/board/freescale/mpc8544ds/Makefile +++ b/board/freescale/mpc8544ds/Makefile @@ -35,7 +35,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) clean: rm -f $(OBJS) $(SOBJS) |