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-rw-r--r--board/BuR/tseries/board.c2
-rw-r--r--board/BuR/tseries/mux.c9
-rw-r--r--board/compulab/cm_t35/cm_t35.c12
-rw-r--r--board/ti/am43xx/Makefile2
-rw-r--r--board/ti/am43xx/board.c55
5 files changed, 62 insertions, 18 deletions
diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c
index f0510e599e..c0178e75cf 100644
--- a/board/BuR/tseries/board.c
+++ b/board/BuR/tseries/board.c
@@ -117,7 +117,9 @@ void sdram_init(void)
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#ifdef CONFIG_NAND
gpmc_init();
+#endif
return 0;
}
diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c
index 3c76e96926..210ac71738 100644
--- a/board/BuR/tseries/mux.c
+++ b/board/BuR/tseries/mux.c
@@ -27,6 +27,11 @@ static struct module_pin_mux uart0_pin_mux[] = {
};
#ifdef CONFIG_MMC
static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
+
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
@@ -125,7 +130,7 @@ static struct module_pin_mux gpIOs[] = {
{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
/* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
{OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
- /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
+ /* GPIO2_27 (MMC0_DAT1) - MII_nNAND */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
/* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
@@ -148,7 +153,7 @@ static struct module_pin_mux gpIOs[] = {
* DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
*/
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
- /* GPIO0_19 (DMA_INTR0) - ISPLAY_MODE (CPLD) */
+ /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO0_20 (DMA_INTR1) - REP-Switch */
{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index 00bcf41bb3..0944903ec8 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -54,12 +54,12 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
};
static u32 gpmc_nand_config[GPMC_MAX_REG] = {
- SMNAND_GPMC_CONFIG1,
- SMNAND_GPMC_CONFIG2,
- SMNAND_GPMC_CONFIG3,
- SMNAND_GPMC_CONFIG4,
- SMNAND_GPMC_CONFIG5,
- SMNAND_GPMC_CONFIG6,
+ M_NAND_GPMC_CONFIG1,
+ M_NAND_GPMC_CONFIG2,
+ M_NAND_GPMC_CONFIG3,
+ M_NAND_GPMC_CONFIG4,
+ M_NAND_GPMC_CONFIG5,
+ M_NAND_GPMC_CONFIG6,
0,
};
diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile
index cb5fe88901..36ecb302c1 100644
--- a/board/ti/am43xx/Makefile
+++ b/board/ti/am43xx/Makefile
@@ -6,7 +6,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index d7449770a3..71af1ae7c8 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -19,6 +19,7 @@
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include "board.h"
+#include <power/tps65218.h>
#include <miiphy.h>
#include <cpsw.h>
@@ -70,7 +71,7 @@ static int read_eeprom(struct am43xx_board_id *header)
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define NUM_OPPS 6
@@ -254,13 +255,6 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
const struct dpll_params *get_dpll_ddr_params(void)
{
- struct am43xx_board_id header;
-
- enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
- if (read_eeprom(&header) < 0)
- puts("Could not get board ID.\n");
-
if (board_is_eposevm())
return &epos_evm_dpll_ddr;
else if (board_is_gpevm())
@@ -302,7 +296,10 @@ static u32 get_sys_clk_index(void)
static int get_opp_offset(int max_off, int min_off)
{
struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
- int opp = readl(&ctrl->dev_attr), offset, i;
+ int opp, offset, i;
+
+ /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
+ opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
for (i = max_off; i >= min_off; i--) {
offset = opp & (1 << i);
@@ -335,6 +332,46 @@ const struct dpll_params *get_dpll_per_params(void)
return &dpll_per[ind];
}
+void scale_vcores(void)
+{
+ const struct dpll_params *mpu_params;
+ int mpu_vdd;
+ struct am43xx_board_id header;
+
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ /* Get the frequency */
+ mpu_params = get_dpll_mpu_params();
+
+ if (i2c_probe(TPS65218_CHIP_PM))
+ return;
+
+ if (mpu_params->m == 1000) {
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
+ } else if (mpu_params->m == 600) {
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
+ } else {
+ puts("Unknown MPU clock, not scaling\n");
+ return;
+ }
+
+ /* Set DCDC1 (CORE) voltage to 1.1V */
+ if (tps65218_voltage_update(TPS65218_DCDC1,
+ TPS65218_DCDC_VOLT_SEL_1100MV)) {
+ puts("tps65218_voltage_update failure\n");
+ return;
+ }
+
+ /* Set DCDC2 (MPU) voltage */
+ if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
+ puts("tps65218_voltage_update failure\n");
+ return;
+ }
+}
+
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();