diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/MAI/bios_emulator/scitech/src/v86bios/command.c | 3 | ||||
| -rw-r--r-- | board/mpc8266ads/mpc8266ads.c | 40 | ||||
| -rw-r--r-- | board/sc520_cdp/config.mk | 2 | ||||
| -rw-r--r-- | board/sc520_cdp/flash.c | 917 | ||||
| -rw-r--r-- | board/sc520_cdp/flash_old.c | 458 | ||||
| -rw-r--r-- | board/sc520_cdp/sc520_cdp.c | 453 | ||||
| -rw-r--r-- | board/sc520_cdp/sc520_cdp_asm16.S | 22 | ||||
| -rw-r--r-- | board/sc520_cdp/u-boot.lds | 2 | ||||
| -rw-r--r-- | board/sc520_spunk/Makefile | 47 | ||||
| -rw-r--r-- | board/sc520_spunk/config.mk | 25 | ||||
| -rw-r--r-- | board/sc520_spunk/flash.c | 813 | ||||
| -rw-r--r-- | board/sc520_spunk/sc520_spunk.c | 686 | ||||
| -rw-r--r-- | board/sc520_spunk/sc520_spunk_asm.S | 82 | ||||
| -rw-r--r-- | board/sc520_spunk/sc520_spunk_asm16.S | 84 | ||||
| -rw-r--r-- | board/sc520_spunk/u-boot.lds | 85 | ||||
| -rw-r--r-- | board/sixnet/fpgadata.c | 3260 | ||||
| -rw-r--r-- | board/sixnet/sixnet.c | 16 | ||||
| -rw-r--r-- | board/utx8245/flash.c | 781 | ||||
| -rw-r--r-- | board/utx8245/utx8245.c | 37 |
19 files changed, 5349 insertions, 2464 deletions
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/command.c b/board/MAI/bios_emulator/scitech/src/v86bios/command.c index 3a468da313..5494ff83ae 100644 --- a/board/MAI/bios_emulator/scitech/src/v86bios/command.c +++ b/board/MAI/bios_emulator/scitech/src/v86bios/command.c @@ -36,6 +36,3 @@ getline(char *buf,int *num,int max_num) line_pointer = line_pointer + *num; len = len - *num; } - - - diff --git a/board/mpc8266ads/mpc8266ads.c b/board/mpc8266ads/mpc8266ads.c index 3e34828b7d..501e610d59 100644 --- a/board/mpc8266ads/mpc8266ads.c +++ b/board/mpc8266ads/mpc8266ads.c @@ -489,10 +489,13 @@ long int initdram(int board_type) * The appropriate BRx/ORx registers have already been set when we * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. */ -#if 1 + memctl->memc_mptpr = CFG_MPTPR; memctl->memc_psrt = psrt; + memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = or; + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; *ramaddr = c; @@ -530,41 +533,7 @@ long int initdram(int board_type) memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; *ramaddr = c; } -#endif - /* - printf("memctl->memc_mptpr = 0x%08x\n", CFG_MPTPR); - printf("memctl->memc_psrt = 0x%08x\n", psrt); - - printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_PREA); - printf("ramaddr = 0x%08x\n", ramaddr); - - printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_CBRR); - - printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_MRW); - - printf("memctl->memc_psdmr = 0x%08x\n", psdmr | PSDMR_OP_NORM | PSDMR_RFEN); - - immap->im_siu_conf.sc_ppc_acr = 0x00000002; - immap->im_siu_conf.sc_ppc_alrh = 0x01267893; - immap->im_siu_conf.sc_tescr1 = 0x00004000; - */ -#if 0 - /* init sdram dimm */ - ramaddr = (uchar *)CFG_SDRAM_BASE; - memctl->memc_psrt = 0x00000010; - immap->im_memctl.memc_or2 = 0xFF000CA0; - immap->im_memctl.memc_br2 = 0x00000041; - memctl->memc_psdmr = 0x296EB452; - *ramaddr = c; - memctl->memc_psdmr = 0x096EB452; - for (i = 0; i < 8; i++) - *ramaddr = c; - memctl->memc_psdmr = 0x196EB452; - *ramaddr = c; - memctl->memc_psdmr = 0x416EB452; - *ramaddr = c; -#endif /* print info */ printf("SDRAM configuration read from SPD\n"); printf("\tSize per side = %dMB\n", sdram_size >> 20); @@ -576,6 +545,7 @@ long int initdram(int board_type) /*return (16 * 1024 * 1024);*/ } + #ifdef CONFIG_PCI struct pci_controller hose; diff --git a/board/sc520_cdp/config.mk b/board/sc520_cdp/config.mk index d4cd9986d6..2253815647 100644 --- a/board/sc520_cdp/config.mk +++ b/board/sc520_cdp/config.mk @@ -22,4 +22,4 @@ # -TEXT_BASE = 0x387e0000 +TEXT_BASE = 0x387c0000 diff --git a/board/sc520_cdp/flash.c b/board/sc520_cdp/flash.c index 973cde8b99..1ebb32e2e9 100644 --- a/board/sc520_cdp/flash.c +++ b/board/sc520_cdp/flash.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2002, 2003 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Alex Zuepke <azu@sysgo.de> @@ -23,31 +26,23 @@ */ #include <common.h> +#include <asm/io.h> +#include <pci.h> +#include <asm/ic/sc520.h> -ulong myflush(void); +#define PROBE_BUFFER_SIZE 1024 +static unsigned char buffer[PROBE_BUFFER_SIZE]; +#define SC520_MAX_FLASH_BANKS 3 +#define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */ +#define SC520_FLASH_BANK1_BASE 0x30000000 /* ROMCS0 */ +#define SC520_FLASH_BANK2_BASE 0x28000000 /* ROMCS1 */ +#define SC520_FLASH_BANKSIZE 0x8000000 -#define FLASH_BANK_SIZE 0x400000 /* 4 MB */ -#define MAIN_SECT_SIZE 0x20000 /* 128 KB */ +#define AMD29LV016B_SIZE 0x200000 +#define AMD29LV016B_SECTORS 32 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x00F000F0 -#define CMD_UNLOCK1 0x00AA00AA -#define CMD_UNLOCK2 0x00550055 -#define CMD_ERASE_SETUP 0x00800080 -#define CMD_ERASE_CONFIRM 0x00300030 -#define CMD_PROGRAM 0x00A000A0 -#define CMD_UNLOCK_BYPASS 0x00200020 - -#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2))) -#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2))) - -#define BIT_ERASE_DONE 0x00800080 -#define BIT_RDY_MASK 0x00800080 -#define BIT_PROGRAM_ERROR 0x00200020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ +flash_info_t flash_info[SC520_MAX_FLASH_BANKS]; #define READY 1 #define ERR 2 @@ -56,394 +51,592 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- */ -ulong flash_init(void) + +static u32 _probe_flash(u32 addr, u32 bw, int il) { - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) - { - ulong flashbase = 0; - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV160B & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic("configured to many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) - { - - if (j <= 3) - { - /* 1st one is 32 KB */ - if (j == 0) - { - flash_info[i].start[j] = flashbase + 0; + u32 result=0; + + /* First do an unlock cycle for the benefit of + * devices that need it */ + + switch (bw) { + + case 1: + *(volatile u8*)(addr+0x5555) = 0xaa; + *(volatile u8*)(addr+0x2aaa) = 0x55; + *(volatile u8*)(addr+0x5555) = 0x90; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+2); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0x5555), 0xf0; + break; + + case 2: + *(volatile u16*)(addr+0xaaaa) = 0xaaaa; + *(volatile u16*)(addr+0x5554) = 0x5555; + + /* Issue identification command */ + if (il == 2) { + *(volatile u16*)(addr+0xaaaa) = 0x9090; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+2); + + /* Return device to data mode */ + *(volatile u16*)addr = 0xffff; + *(volatile u16*)(addr+0xaaaa), 0xf0f0; + + } else { + *(volatile u8*)(addr+0xaaaa) = 0x90; + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+2); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0xaaaa), 0xf0; } - - /* 2nd and 3rd are both 16 KB */ - if ((j == 1) || (j == 2)) - { - flash_info[i].start[j] = flashbase + 0x8000 + (j-1)*0x4000; + + break; + + case 4: + *(volatile u32*)(addr+0x5554) = 0xaaaaaaaa; + *(volatile u32*)(addr+0xaaa8) = 0x55555555; + + switch (il) { + case 1: + /* Issue identification command */ + *(volatile u8*)(addr+0x5554) = 0x90; + + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+4); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0x5554), 0xf0; + break; + + case 2: + /* Issue identification command */ + *(volatile u32*)(addr + 0x5554) = 0x00900090; + + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+4); + + /* Return device to data mode */ + *(volatile u32*)addr = 0x00ff00ff; + *(volatile u32*)(addr+0x5554), 0x00f000f0; + break; + + case 4: + /* Issue identification command */ + *(volatile u32*)(addr+0x5554) = 0x90909090; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+4); + + /* Return device to data mode */ + *(volatile u32*)addr = 0xffffffff; + *(volatile u32*)(addr+0x5554), 0xf0f0f0f0; + break; } + break; + } + + + + return result; +} + +extern int _probe_flash_end; +asm ("_probe_flash_end:\n" + ".long 0\n"); - /* 4th 64 KB */ - if (j == 3) - { - flash_info[i].start[j] = flashbase + 0x10000; +static int identify_flash(unsigned address, int width) +{ + int is; + int device; + int vendor; + int size; + unsigned res; + + u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il); + + size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; + + if (size > PROBE_BUFFER_SIZE) { + printf("_probe_flash() routine too large (%d) %p - %p\n", + size, &_probe_flash_end, _probe_flash); + return 0; + } + + memcpy(buffer, _probe_flash, size); + _probe_flash_ptr = (void*)buffer; + + is = disable_interrupts(); + res = _probe_flash_ptr(address, width, 1); + if (is) { + enable_interrupts(); + } + + + vendor = res >> 16; + device = res & 0xffff; + + + return res; +} + +ulong flash_init(void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) { + unsigned id; + ulong flashbase = 0; + int sectsize = 0; + + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + switch (i) { + case 0: + flashbase = SC520_FLASH_BANK0_BASE; + break; + case 1: + flashbase = SC520_FLASH_BANK1_BASE; + break; + case 2: + flashbase = SC520_FLASH_BANK2_BASE; + break; + default: + panic("configured to many flash banks!\n"); + } + + id = identify_flash(flashbase, 4); + switch (id & 0x00ff00ff) { + case 0x000100c8: + /* 29LV016B/29LV017B */ + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV016B & FLASH_TYPEMASK); + + flash_info[i].size = AMD29LV016B_SIZE*4; + flash_info[i].sector_count = AMD29LV016B_SECTORS; + sectsize = (AMD29LV016B_SIZE*4)/AMD29LV016B_SECTORS; + printf("Bank %d: 4 x AMD 29LV017B\n", i); + break; + + + default: + printf("Bank %d have unknown flash %08x\n", i, id); + flash_info[i].flash_id = FLASH_UNKNOWN; + continue; + } + + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase + j * sectsize; } - } - else - { - flash_info[i].start[j] = flashbase + (j - 3)*MAIN_SECT_SIZE; - } + size += flash_info[i].size; + + flash_protect(FLAG_PROTECT_CLEAR, + flash_info[i].start[0], + flash_info[i].start[0] + flash_info[i].size - 1, + &flash_info[i]); } - size += flash_info[i].size; - } - - /* - * Protect monitor and environment sectors - */ - flash_protect(FLAG_PROTECT_SET, - i386boot_start-CFG_FLASH_BASE, - i386boot_end-CFG_FLASH_BASE, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - &flash_info[0]); - return size; + + /* + * Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + i386boot_start, + i386boot_end, + &flash_info[0]); +#ifdef CFG_ENV_ADDR + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + return size; } /*----------------------------------------------------------------------- */ -void flash_print_info (flash_info_t *info) +void flash_print_info(flash_info_t *info) { - int i; - - switch (info->flash_id & FLASH_VENDMASK) - { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf("AMD: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) - { - case (AMD_ID_LV160B & FLASH_TYPEMASK): - printf("2x Amd29F160BB (16Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - goto Done; - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) - { - if ((i % 5) == 0) - { - printf ("\n "); + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + + case (AMD_MANUFACT & FLASH_VENDMASK): + printf("AMD: "); + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV016B & FLASH_TYPEMASK): + printf("4x AMD29LV017B (4x16Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + goto done; + break; + } + + break; + default: + printf("Unknown Vendor "); + break; } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: + + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + done: } /*----------------------------------------------------------------------- */ -int flash_erase (flash_info_t *info, int s_first, int s_last) +/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */ +#define __udelay(delay) \ +{ \ + unsigned micro; \ + unsigned milli=0; \ + \ + micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ + \ + for (;;) { \ + \ + milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ + micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \ + \ + if ((delay) <= (micro + (milli * 1000))) { \ + break; \ + } \ + } \ +} while (0) + +static u32 _amd_erase_flash(u32 addr, u32 sector) { - ulong result; - int iflag, prot, sect; - int rc = ERR_OK; - int chip1, chip2; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } + unsigned elapsed; + + /* Issue erase */ + *(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA; + *(volatile u32*)(addr + 0xaaa8) = 0x55555555; + *(volatile u32*)(addr + 0x5554) = 0x80808080; + /* And one unlock */ + *(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA; + *(volatile u32*)(addr + 0xaaa8) = 0x55555555; + /* Sector erase command comes last */ + *(volatile u32*)(addr + sector) = 0x30303030; + + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = 0; + __udelay(50); + while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) { + + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { + *(volatile u32*)(addr) = 0xf0f0f0f0; + return 1; + } + } + + *(volatile u32*)(addr) = 0xf0f0f0f0; + + return 0; +} - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } +extern int _amd_erase_flash_end; +asm ("_amd_erase_flash_end:\n" + ".long 0\n"); - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + u32 (*_erase_flash_ptr)(u32 a, u32 so); + int prot; + int sect; + unsigned size; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - iflag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) - { - printf("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer(); - - if (info->protect[sect] == 0) - { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = chip2 = 0; - - do - { - result = *addr; - - /* check timeout */ - if (get_timer(0) > CFG_FLASH_ERASE_TOUT) - { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; + + if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash; + + if (size > PROBE_BUFFER_SIZE) { + printf("_amd_erase_flash() routine too large (%d) %p - %p\n", + size, &_amd_erase_flash_end, _amd_erase_flash); + return 0; } - - if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip1 = ERR; - - if (!chip2 && (result >> 16) & BIT_ERASE_DONE) - chip2 = READY; - - if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) - chip2 = ERR; - - } while (!chip1 || !chip2); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR || chip2 == ERR) - { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) - { - rc = ERR_TIMOUT; - goto outahere; - } - - printf("ok.\n"); + + memcpy(buffer, _amd_erase_flash, size); + _erase_flash_ptr = (void*)buffer; + + } else { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; } - else /* it was protected */ - { - printf("protected!\n"); + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + + if (info->protect[sect] == 0) { /* not protected */ + int res; + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + + if (res) { + printf("Erase timed out, sector %d\n", sect); + return res; + } + + putc('.'); + } } - } - - if (ctrlc()) - printf("User Interrupt!\n"); - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay(10000); - - if (iflag) - enable_interrupts(); - - return rc; + + return 0; } /*----------------------------------------------------------------------- - * Copy memory to flash + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased */ - -volatile static int write_word (flash_info_t *info, ulong dest, ulong data) +static int _amd_write_word(unsigned start, unsigned dest, unsigned data) { - vu_long *addr = (vu_long *)dest; - ulong result; - int rc = ERR_OK; - int iflag; - int chip1, chip2; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - iflag = disable_interrupts(); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; - *addr = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer(); - - /* wait until flash is ready */ - chip1 = chip2 = 0; - do - { - result = *addr; - - /* check timeout */ - if (get_timer(0) > CFG_FLASH_ERASE_TOUT) - { - chip1 = ERR | TMO; - break; + volatile u32 *addr2 = (u32*)start; + volatile u32 *dest2 = (u32*)dest; + volatile u32 *data2 = (u32*)&data; + unsigned elapsed; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile u32*)dest) & (u32)data) != (u32)data) { + return 2; } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) - { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip1 = READY; - else - chip1 = ERR; - } - - if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) - chip2 = READY; - - if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) - { - result = *addr; - - if ((result & (0x80 << 16)) == (data & (0x80 << 16))) - chip2 = READY; - else - chip2 = ERR; + + addr2[0x5554] = 0xAAAAAAAA; + addr2[0xaaa8] = 0x55555555; + addr2[0x5554] = 0xA0A0A0A0; + + dest2[0] = data; + + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = 0; + + /* data polling for D7 */ + while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) { + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { + addr2[0] = 0xf0f0f0f0; + return 1; + } } - } while (!chip1 || !chip2); - - *addr = CMD_READ_ARRAY; + + addr2[0] = 0xf0f0f0f0; + + return 0; +} - if (chip1 == ERR || chip2 == ERR || *addr != data) - rc = ERR_PROG_ERROR; +extern int _amd_write_word_end; +asm ("_amd_write_word_end:\n" + ".long 0\n"); - if (iflag) - enable_interrupts(); - return rc; -} /*----------------------------------------------------------------------- - * Copy memory to flash. + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 3 - Unsupported flash type */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) { - ulong cp, wp, data; - int l; - int i, rc; + ulong cp, wp, data; + int i, l, rc; + int flag; + u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data); + unsigned size; + + if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word; + + if (size > PROBE_BUFFER_SIZE) { + printf("_amd_write_word() routine too large (%d) %p - %p\n", + size, &_amd_write_word_end, _amd_write_word); + return 0; + } + + memcpy(buffer, _amd_write_word, size); + _write_word_ptr = (void*)buffer; + + } else { + printf ("Can't program unknown flash type - aborted\n"); + return 3; + } - wp = (addr & ~3); /* get lower word aligned address */ - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); + wp = (addr & ~3); /* get lower word aligned address */ + + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); + } + for (; i<4 && cnt>0; ++i) { + data |= *src++ << (8*i); + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + if (rc != 0) { + return rc; + } + wp += 4; } - for (; i<4 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + + for (i=0; i<4; ++i) { + data |= *src++ << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + if (rc != 0) { + return rc; + } + wp += 4; + cnt -= 4; } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); + + if (cnt == 0) { + return 0; } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data |= *src++ << (8*i); + --cnt; } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((vu_long*)src); - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); + + for (; i<4; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - return write_word(info, wp, data); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + return rc; + } + + diff --git a/board/sc520_cdp/flash_old.c b/board/sc520_cdp/flash_old.c new file mode 100644 index 0000000000..d4204a8ced --- /dev/null +++ b/board/sc520_cdp/flash_old.c @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +ulong myflush(void); + + +#define SC520_MAX_FLASH_BANKS 3 +#define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */ +#define SC520_FLASH_BANK1_BASE 0x30000000 /* ROMCS0 */ +#define SC520_FLASH_BANK2_BASE 0x28000000 /* ROMCS1 */ +#define SC520_FLASH_BANKSIZE 0x8000000 + +#define AMD29LV016_SIZE 0x200000 +#define AMD29LV016_SECTORS 32 + +flash_info_t flash_info[SC520_MAX_FLASH_BANKS]; + +#define CMD_READ_ARRAY 0x00F000F0 +#define CMD_UNLOCK1 0x00AA00AA +#define CMD_UNLOCK2 0x00550055 +#define CMD_ERASE_SETUP 0x00800080 +#define CMD_ERASE_CONFIRM 0x00300030 +#define CMD_PROGRAM 0x00A000A0 +#define CMD_UNLOCK_BYPASS 0x00200020 + + +#define BIT_ERASE_DONE 0x00800080 +#define BIT_RDY_MASK 0x00800080 +#define BIT_PROGRAM_ERROR 0x00200020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + +ulong flash_init(void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + int sectsize = 0; + if (i==0 || i==2) { + /* FixMe: this assumes that bank 0 and 2 + * are mapped to the two 8Mb banks */ + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV016B & FLASH_TYPEMASK); + + flash_info[i].size = AMD29LV016_SIZE*4; + flash_info[i].sector_count = AMD29LV016_SECTORS; + sectsize = (AMD29LV016_SIZE*4)/AMD29LV016_SECTORS; + } else { + /* FixMe: this assumes that bank1 is unmapped + * (or mapped to the same flash bank as BOOTCS) */ + flash_info[i].flash_id = 0; + flash_info[i].size = 0; + flash_info[i].sector_count = 0; + sectsize=0; + } + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + switch (i) { + case 0: + flashbase = SC520_FLASH_BANK0_BASE; + break; + case 1: + flashbase = SC520_FLASH_BANK1_BASE; + break; + case 2: + flashbase = SC520_FLASH_BANK0_BASE; + break; + default: + panic("configured to many flash banks!\n"); + } + + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = sectsize; + flash_info[i].start[j] = flashbase + j * sectsize; + } + size += flash_info[i].size; + } + + /* + * Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + i386boot_start-SC520_FLASH_BANK0_BASE, + i386boot_end-SC520_FLASH_BANK0_BASE, + &flash_info[0]); + +#ifdef CFG_ENV_ADDR + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf("AMD: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV016B & FLASH_TYPEMASK): + printf("4x Amd29LV016B (16Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + goto done; + break; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + done: +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + ulong result; + int iflag, prot, sect; + int rc = ERR_OK; + int chip1, chip2; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) { + return ERR_UNKNOWN_FLASH_TYPE; + } + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + return ERR_PROTECTED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + iflag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { + printf("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer(); + + if (info->protect[sect] == 0) { + /* not protected */ + ulong addr = info->start[sect]; + + writel(CMD_UNLOCK1, addr + 1); + writel(CMD_UNLOCK2, addr + 2); + writel(CMD_ERASE_SETUP, addr + 1); + + writel(CMD_UNLOCK1, addr + 1); + writel(CMD_UNLOCK2, addr + 2); + writel(CMD_ERASE_CONFIRM, addr); + + + /* wait until flash is ready */ + chip1 = chip2 = 0; + + do { + result = readl(addr); + + /* check timeout */ + if (get_timer(0) > CFG_FLASH_ERASE_TOUT) { + writel(CMD_READ_ARRAY, addr + 1); + chip1 = TMO; + break; + } + + if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) { + chip1 = READY; + } + + if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) { + chip1 = ERR; + } + + if (!chip2 && (result >> 16) & BIT_ERASE_DONE) { + chip2 = READY; + } + + if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) { + chip2 = ERR; + } + + } while (!chip1 || !chip2); + + writel(CMD_READ_ARRAY, addr + 1); + + if (chip1 == ERR || chip2 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf("ok.\n"); + } else { /* it was protected */ + + printf("protected!\n"); + } + } + + if (ctrlc()) { + printf("User Interrupt!\n"); + } + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay(10000); + + if (iflag) { + enable_interrupts(); + } + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_word(flash_info_t *info, ulong dest, ulong data) +{ + ulong addr = dest; + ulong result; + int rc = ERR_OK; + int iflag; + int chip1, chip2; + + /* + * Check if Flash is (sufficiently) erased + */ + result = readl(addr); + if ((result & data) != data) { + return ERR_NOT_ERASED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + iflag = disable_interrupts(); + + writel(CMD_UNLOCK1, addr + 1); + writel(CMD_UNLOCK2, addr + 2); + writel(CMD_UNLOCK_BYPASS, addr + 1); + writel(addr, CMD_PROGRAM); + writel(addr, data); + + /* arm simple, non interrupt dependent timer */ + reset_timer(); + + /* wait until flash is ready */ + chip1 = chip2 = 0; + do { + result = readl(addr); + + /* check timeout */ + if (get_timer(0) > CFG_FLASH_ERASE_TOUT) { + chip1 = ERR | TMO; + break; + } + + if (!chip1 && ((result & 0x80) == (data & 0x80))) { + chip1 = READY; + } + + if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { + result = readl(addr); + + if ((result & 0x80) == (data & 0x80)) { + chip1 = READY; + } else { + chip1 = ERR; + } + } + + if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) { + chip2 = READY; + } + + if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) { + result = readl(addr); + + if ((result & (0x80 << 16)) == (data & (0x80 << 16))) { + chip2 = READY; + } else { + chip2 = ERR; + } + } + + } while (!chip1 || !chip2); + + writel(CMD_READ_ARRAY, addr); + + if (chip1 == ERR || chip2 == ERR || readl(addr) != data) { + rc = ERR_PROG_ERROR; + } + + if (iflag) { + enable_interrupts(); + } + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int l; + int i, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + for (; i<4 && cnt>0; ++i) { + data = (data >> 8) | (*src++ << 24); + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return rc; + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = *((vu_long*)src); + if ((rc = write_word(info, wp, data)) != 0) { + return rc; + } + src += 4; + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return ERR_OK; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 24); + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + return write_word(info, wp, data); +} diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c index 2809ff72af..50a49e601a 100644 --- a/board/sc520_cdp/sc520_cdp.c +++ b/board/sc520_cdp/sc520_cdp.c @@ -1,4 +1,5 @@ /* + * * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. * @@ -24,109 +25,162 @@ #include <common.h> #include <pci.h> #include <asm/io.h> +#include <asm/pci.h> #include <asm/ic/sc520.h> #include <asm/ic/ali512x.h> +#include <ssi.h> + +#undef SC520_CDP_DEBUG + +#ifdef SC520_CDP_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif /* ------------------------------------------------------------------------- */ + +/* + * Theory: + * We first set up all IRQs to be non-pci, edge triggered, + * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets + * called we reallocate irqs to the pci bus with sc520_pci_set_irq() + * as needed. Whe choose the irqs to gram from a configurable list + * inside pci_sc520_fixup_irq() (If this list contains stupid irq's + * such as 0 thngas will not work) + */ + static void irq_init(void) { - /* disable global interrupt mode */ write_mmcr_byte(SC520_PICICR, 0x40); - /* set irq0-7 to edge */ + /* set all irqs to edge */ write_mmcr_byte(SC520_MPICMODE, 0x00); - - /* set irq9-12 to level, all the other (8, 13-15) are edge */ - write_mmcr_byte(SC520_SL1PICMODE, 0x1e); - - /* set irq16-24 (unused slave pic2) to level */ - write_mmcr_byte(SC520_SL2PICMODE, 0xff); + write_mmcr_byte(SC520_SL1PICMODE, 0x00); + write_mmcr_byte(SC520_SL2PICMODE, 0x00); /* active low polarity on PIC interrupt pins, - active high polarity on all other irq pins */ - write_mmcr_word(SC520_INTPINPOL, 0); + * active high polarity on all other irq pins */ + write_mmcr_word(SC520_INTPINPOL, 0x0000); /* set irq number mapping */ - write_mmcr_byte(SC520_GPTMR0MAP,0); /* disable GP timer 0 INT */ - write_mmcr_byte(SC520_GPTMR1MAP,0); /* disable GP timer 1 INT */ - write_mmcr_byte(SC520_GPTMR2MAP,0); /* disable GP timer 2 INT */ - write_mmcr_byte(SC520_PIT0MAP,0x1); /* Set PIT timer 0 INT to IRQ0 */ - write_mmcr_byte(SC520_PIT1MAP,0); /* diable PIT timer 1 INT */ - write_mmcr_byte(SC520_PIT2MAP,0); /* diable PIT timer 2 INT */ - write_mmcr_byte(SC520_PCIINTAMAP,0x4); /* Set PCI INT A to IRQ9 */ - write_mmcr_byte(SC520_PCIINTBMAP,0x5); /* Set PCI INT B to IRQ10 */ - write_mmcr_byte(SC520_PCIINTCMAP,0x6); /* Set PCI INT C to IRQ11 */ - write_mmcr_byte(SC520_PCIINTDMAP,0x7); /* Set PCI INT D to IRQ12 */ - write_mmcr_byte(SC520_DMABCINTMAP,0); /* disable DMA INT */ - write_mmcr_byte(SC520_SSIMAP,0); /* disable Synchronius serial INT */ - write_mmcr_byte(SC520_WDTMAP,0); /* disable Watchdor INT */ - write_mmcr_byte(SC520_RTCMAP,0x3); /* Set RTC int to 8 */ - write_mmcr_byte(SC520_WPVMAP,0); /* disable write protect INT */ - write_mmcr_byte(SC520_ICEMAP,0x2); /* Set ICE Debug Serielport INT to IRQ1 */ - write_mmcr_byte(SC520_FERRMAP,0x8); /* Set FP error INT to IRQ13 */ - write_mmcr_byte(SC520_GP0IMAP,6); /* Set GPIRQ0 (ISA IRQ2) to IRQ9 */ - write_mmcr_byte(SC520_GP1IMAP,2); /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */ - write_mmcr_byte(SC520_GP2IMAP,7); /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */ + write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */ + write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */ + write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */ + write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */ + write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */ + write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */ + write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */ + write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */ + write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */ + write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */ + write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ + write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED); /* disable Synchronius serial INT */ + write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */ + write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */ + write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */ + write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */ + write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */ if (CFG_USE_SIO_UART) { - write_mmcr_byte(SC520_UART1MAP,0); /* disable internal UART1 INT */ - write_mmcr_byte(SC520_UART2MAP,0); /* disable internal UART2 INT */ - write_mmcr_byte(SC520_GP3IMAP,11); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ - write_mmcr_byte(SC520_GP4IMAP,12); /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */ + write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */ + write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */ + write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ + write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4); /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */ } else { - write_mmcr_byte(SC520_UART1MAP,12); /* Set internal UART2 INT to IRQ4 */ - write_mmcr_byte(SC520_UART2MAP,11); /* Set internal UART2 INT to IRQ3 */ - write_mmcr_byte(SC520_GP3IMAP,0); /* disable GPIRQ3 (ISA IRQ3) */ - write_mmcr_byte(SC520_GP4IMAP,0); /* disable GPIRQ4 (ISA IRQ4) */ + write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */ + write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */ + write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ3 (ISA IRQ3) */ + write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ4 (ISA IRQ4) */ } - write_mmcr_byte(SC520_GP5IMAP,13); /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */ - write_mmcr_byte(SC520_GP6IMAP,21); /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */ - write_mmcr_byte(SC520_GP7IMAP,22); /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */ - write_mmcr_byte(SC520_GP8IMAP,3); /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */ - write_mmcr_byte(SC520_GP9IMAP,4); /* Set GPIRQ9 (ISA IRQ9) to IRQ9 */ - write_mmcr_byte(SC520_GP10IMAP,9); /* Set GPIRQ10 (ISA IRQ10) to IRQ10 */ - write_mmcr_word(SC520_PCIHOSTMAP,0x11f); /* Map PCI hostbridge INT to NMI */ - write_mmcr_word(SC520_ECCMAP,0x100); /* Map SDRAM ECC failure INT to NMI */ + write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1); /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */ + write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5); /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */ + write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6); /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */ + write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7); /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */ + write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8); /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */ + write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9); /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */ + write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11); /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */ + write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12); /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */ + write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14); /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */ + + write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */ + write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */ } + /* PCI stuff */ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { - char pin; - int irq; + /* a configurable lists of irqs to steal + * when we need one (a board with more pci interrupt pins + * would use a larger table */ + static int irq_list[] = { + CFG_FIRST_PCI_IRQ, + CFG_SECOND_PCI_IRQ, + CFG_THIRD_PCI_IRQ, + CFG_FORTH_PCI_IRQ + }; + static int next_irq_index=0; + char tmp_pin; + int pin; - pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); - irq = pin-1; + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); + pin = tmp_pin; + pin-=1; /* pci config space use 1-based numbering */ + if (-1 == pin) { + return; /* device use no irq */ + } + + + + /* map device number + pin to a pin on the sc520 */ switch (PCI_DEV(dev)) { case 20: + pin+=SC520_PCI_INTA; break; + case 19: - irq+=1; + pin+=SC520_PCI_INTB; break; + case 18: - irq+=2; + pin+=SC520_PCI_INTC; break; + case 17: - irq+=3; + pin+=SC520_PCI_INTD; break; + default: return; } - irq&=3; /* wrap around */ - irq+=9; /* lowest IRQ is 9 */ + pin&=3; /* wrap around */ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, irq); -#if 0 - printf("fixup_irq: device %d pin %c irq %d\n", - PCI_DEV(dev), 'A' + pin -1, irq); -#endif + if (sc520_pci_ints[pin] == -1) { + /* re-route one interrupt for us */ + if (next_irq_index > 3) { + return; + } + if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { + return; + } + next_irq_index++; + } + + + if (-1 != sc520_pci_ints[pin]) { + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + sc520_pci_ints[pin]); + } + PRINTF("fixup_irq: device %d pin %c irq %d\n", + PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); } static struct pci_controller sc520_cdp_hose = { @@ -162,8 +216,8 @@ void setup_ali_sio(int uart_primary) /* SSI chip select pins */ ali512x_cio_function(14, 0, 0, 0); /* SSI_CS */ - ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */ - ali512x_cio_function(16, 0, 1, 0); /* SSI_SPI# (inverted) */ + ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */ + ali512x_cio_function(16, 0, 0, 0); /* SSI_SPI# */ /* Board REV pins */ ali512x_cio_function(20, 0, 0, 1); @@ -202,6 +256,7 @@ static void bus_init(void) * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ + /* SRAM = GPCS3 128k @ d0000-effff*/ write_mmcr_long(SC520_PAR2, 0x4e00400d); @@ -219,13 +274,15 @@ static void bus_init(void) /* 680 LEDS */ write_mmcr_long(SC520_PAR15, 0x30000640); + write_mmcr_byte(SC520_ADDDECCTL, 0); + asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ if (CFG_USE_SIO_UART) { write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS); setup_ali_sio(1); } else { - write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS)); + write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS)); setup_ali_sio(0); silence_uart(0x3e8); silence_uart(0x2e8); @@ -233,7 +290,192 @@ static void bus_init(void) } +/* GPCS usage + * GPCS0 PIO27 (NMI) + * GPCS1 ROMCS1 + * GPCS2 ROMCS2 + * GPCS3 SRAMCS PAR2 + * GPCS4 unused PAR3 + * GPCS5 unused PAR4 + * GPCS6 IDE + * GPCS7 IDE + */ + + +/* par usage: + * PAR0 legacy_video + * PAR1 PCI ROM mapping + * PAR2 SRAM + * PAR3 IDE + * PAR4 IDE + * PAR5 legacy_video + * PAR6 legacy_video + * PAR7 legacy_video + * PAR8 legacy_video + * PAR9 legacy_video + * PAR10 legacy_video + * PAR11 ISAROM + * PAR12 BOOTCS + * PAR13 ROMCS1 + * PAR14 ROMCS2 + * PAR15 Port 0x680 LED display + */ + +/* + * This function should map a chunk of size bytes + * of the system address space to the ISA bus + * + * The function will return the memory address + * as seen by the host (which may very will be the + * same as the bus address) + */ +u32 isa_map_rom(u32 bus_addr, int size) +{ + u32 par; + + PRINTF("isa_map_rom asked to map %d bytes at %x\n", + size, bus_addr); + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 12; + par--; + par&=0x7f; + par <<= 18; + par |= (bus_addr>>12); + par |= 0x50000000; + + PRINTF ("setting PAR11 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + write_mmcr_long(SC520_PAR11, par); + + return bus_addr; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void isa_unmap_rom(u32 addr) +{ + PRINTF("isa_unmap_rom asked to unmap %x", addr); + if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) { + write_mmcr_long(SC520_PAR11, 0); + PRINTF(" done\n"); + return; + } + PRINTF(" not ours\n"); +} + +#ifdef CONFIG_PCI +#define PCI_ROM_TEMP_SPACE 0x10000 +/* + * This function should map a chunk of size bytes + * of the system address space to the PCI bus, + * suitable to map PCI ROMS (bus address < 16M) + * the function will return the host memory address + * which should be converted into a bus address + * before used to configure the PCI rom address + * decoder + */ +u32 pci_get_rom_window(struct pci_controller *hose, int size) +{ + u32 par; + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 16; + par--; + par&=0x7ff; + par <<= 14; + par |= (PCI_ROM_TEMP_SPACE>>16); + par |= 0x72000000; + + PRINTF ("setting PAR1 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + write_mmcr_long(SC520_PAR1, par); + + return PCI_ROM_TEMP_SPACE; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void pci_remove_rom_window(struct pci_controller *hose, u32 addr) +{ + PRINTF("pci_remove_rom_window: %x", addr); + if (addr == PCI_ROM_TEMP_SPACE) { + write_mmcr_long(SC520_PAR1, 0); + PRINTF(" done\n"); + return; + } + PRINTF(" not ours\n"); + +} + +/* + * This function is called in order to provide acces to the + * legacy video I/O ports on the PCI bus. + * After this function accesses to I/O ports 0x3b0-0x3bb and + * 0x3c0-0x3df shuld result in transactions on the PCI bus. + * + */ +int pci_enable_legacy_video_ports(struct pci_controller *hose) +{ + /* Map video memory to 0xa0000*/ + write_mmcr_long(SC520_PAR0, 0x7200400a); + + /* forward all I/O accesses to PCI */ + write_mmcr_byte(SC520_ADDDECCTL, + read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI); + + + /* so we map away all io ports to pci (only way to access pci io + * below 0x400. But then we have to map back the portions that we dont + * use so that the generate cycles on the GPIO bus where the sio and + * ISA slots are connected, this requre the use of several PAR registers + */ + + /* bring 0x100 - 0x1ef back to ISA using PAR5 */ + write_mmcr_long(SC520_PAR5, 0x30ef0100); + + /* IDE use 1f0-1f7 */ + + /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */ + write_mmcr_long(SC520_PAR6, 0x30ff01f8); + + /* com2 use 2f8-2ff */ + + /* bring 0x300 - 0x3af back to ISA using PAR7 */ + write_mmcr_long(SC520_PAR7, 0x30af0300); + + /* vga use 3b0-3bb */ + + /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ + write_mmcr_long(SC520_PAR8, 0x300303bc); + + /* vga use 3c0-3df */ + + /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */ + write_mmcr_long(SC520_PAR9, 0x301503e0); + + /* ide use 3f6 */ + + /* bring 0x3f7 back to ISA using PAR10 */ + write_mmcr_long(SC520_PAR10, 0x300003f7); + + /* com1 use 3f8-3ff */ + return 0; +} +#endif /* * Miscelaneous platform dependent initialisations @@ -252,7 +494,6 @@ int board_init(void) /* enter debug mode after next reset (only if jumper is also set) */ write_mmcr_byte(SC520_RESCFG, 0x08); - /* configure the software timer to 33.333MHz */ write_mmcr_byte(SC520_SWTMRCFG, 0); gd->bus_clk = 33333000; @@ -288,3 +529,87 @@ int last_stage_init(void) return 0; } + + + +void ssi_chip_select(int dev) +{ + + /* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */ + switch (dev) { + case 1: /* SPI EEPROM */ + ali512x_cio_out(16, 0); + break; + + case 2: /* MW EEPROM */ + ali512x_cio_out(15, 1); + break; + + case 3: /* AUX */ + ali512x_cio_out(14, 1); + break; + + case 0: + ali512x_cio_out(16, 1); + ali512x_cio_out(15, 0); + ali512x_cio_out(14, 0); + break; + + default: + printf("Illegal SSI device requested: %d\n", dev); + } +} + + +void spi_init_f(void) +{ +#ifdef CONFIG_SC520_CDP_USE_SPI + spi_eeprom_probe(1); +#endif +#ifdef CONFIG_SC520_CDP_USE_MW + mw_eeprom_probe(2); +#endif +} + +ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) +{ + int offset; + int i; + ssize_t res; + + offset = 0; + for (i=0;i<alen;i++) { + offset <<= 8; + offset |= addr[i]; + } + +#ifdef CONFIG_SC520_CDP_USE_SPI + res = spi_eeprom_read(1, offset, buffer, len); +#endif +#ifdef CONFIG_SC520_CDP_USE_MW + res = mw_eeprom_read(2, offset, buffer, len); +#endif + return res; +} + +ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) +{ + int offset; + int i; + ssize_t res; + + offset = 0; + for (i=0;i<alen;i++) { + offset <<= 8; + offset |= addr[i]; + } + +#ifdef CONFIG_SC520_CDP_USE_SPI + res = spi_eeprom_write(1, offset, buffer, len); +#endif +#ifdef CONFIG_SC520_CDP_USE_MW + res = mw_eeprom_write(2, offset, buffer, len); +#endif + return res; +} + diff --git a/board/sc520_cdp/sc520_cdp_asm16.S b/board/sc520_cdp/sc520_cdp_asm16.S index a3cadcfa54..0e0b0c028a 100644 --- a/board/sc520_cdp/sc520_cdp_asm16.S +++ b/board/sc520_cdp/sc520_cdp_asm16.S @@ -60,3 +60,25 @@ board_init16: /* the return address is tored in bp */ jmp *%bp + +.section .bios, "ax" +.code16 +.globl realmode_reset +realmode_reset: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* issue software reset thorugh MMCR */ + movl $0xd72, %edi + movb $0x01, %al + movb %al, (%di) + +1: hlt + jmp 1 + diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds index ac8d3dbecd..fbab9b85f2 100644 --- a/board/sc520_cdp/u-boot.lds +++ b/board/sc520_cdp/u-boot.lds @@ -27,7 +27,7 @@ ENTRY(_start) SECTIONS { - . = 0x387e0000; /* Where bootcode in the flash is mapped */ + . = 0x387c0000; /* Where bootcode in the flash is mapped */ .text : { *(.text); } . = ALIGN(4); diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile new file mode 100644 index 0000000000..53217c380e --- /dev/null +++ b/board/sc520_spunk/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := sc520_spunk.o flash.o +SOBJS := sc520_spunk_asm.o sc520_spunk_asm16.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/sc520_spunk/config.mk b/board/sc520_spunk/config.mk new file mode 100644 index 0000000000..2253815647 --- /dev/null +++ b/board/sc520_spunk/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +TEXT_BASE = 0x387c0000 diff --git a/board/sc520_spunk/flash.c b/board/sc520_spunk/flash.c new file mode 100644 index 0000000000..66ef720660 --- /dev/null +++ b/board/sc520_spunk/flash.c @@ -0,0 +1,813 @@ +/* + * (C) Copyright 2002, 2003 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <pci.h> +#include <asm/ic/sc520.h> + +#define PROBE_BUFFER_SIZE 1024 +static unsigned char buffer[PROBE_BUFFER_SIZE]; + + +#define SC520_MAX_FLASH_BANKS 1 +#define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */ +#define SC520_FLASH_BANKSIZE 0x8000000 + +#define A29LV641DH_SIZE 0x800000 +#define A29LV641DH_SECTORS 128 + +#define A29LV641MH_SIZE 0x800000 +#define A29LV641MH_SECTORS 128 + +#define I28F320J3A_SIZE 0x400000 +#define I28F320J3A_SECTORS 32 + +#define I28F640J3A_SIZE 0x800000 +#define I28F640J3A_SECTORS 64 + +#define I28F128J3A_SIZE 0x1000000 +#define I28F128J3A_SECTORS 128 + +flash_info_t flash_info[SC520_MAX_FLASH_BANKS]; + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + + +static u32 _probe_flash(u32 addr, u32 bw, int il) +{ + u32 result=0; + + /* First do an unlock cycle for the benefit of + * devices that need it */ + + switch (bw) { + + case 1: + *(volatile u8*)(addr+0x5555) = 0xaa; + *(volatile u8*)(addr+0x2aaa) = 0x55; + *(volatile u8*)(addr+0x5555) = 0x90; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+2); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0x5555), 0xf0; + break; + + case 2: + *(volatile u16*)(addr+0xaaaa) = 0xaaaa; + *(volatile u16*)(addr+0x5554) = 0x5555; + + /* Issue identification command */ + if (il == 2) { + *(volatile u16*)(addr+0xaaaa) = 0x9090; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+2); + + /* Return device to data mode */ + *(volatile u16*)addr = 0xffff; + *(volatile u16*)(addr+0xaaaa), 0xf0f0; + + } else { + *(volatile u8*)(addr+0xaaaa) = 0x90; + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+2); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0xaaaa), 0xf0; + } + + break; + + case 4: + *(volatile u32*)(addr+0x5554) = 0xaaaaaaaa; + *(volatile u32*)(addr+0xaaa8) = 0x55555555; + + switch (il) { + case 1: + /* Issue identification command */ + *(volatile u8*)(addr+0x5554) = 0x90; + + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+4); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0x5554), 0xf0; + break; + + case 2: + /* Issue identification command */ + *(volatile u32*)(addr + 0x5554) = 0x00900090; + + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+4); + + /* Return device to data mode */ + *(volatile u32*)addr = 0x00ff00ff; + *(volatile u32*)(addr+0x5554), 0x00f000f0; + break; + + case 4: + /* Issue identification command */ + *(volatile u32*)(addr+0x5554) = 0x90909090; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+4); + + /* Return device to data mode */ + *(volatile u32*)addr = 0xffffffff; + *(volatile u32*)(addr+0x5554), 0xf0f0f0f0; + break; + } + break; + } + + + + return result; +} + +extern int _probe_flash_end; +asm ("_probe_flash_end:\n" + ".long 0\n"); + +static int identify_flash(unsigned address, int width) +{ + int is; + int device; + int vendor; + int size; + unsigned res; + + u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il); + + size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; + + if (size > PROBE_BUFFER_SIZE) { + printf("_probe_flash() routine too large (%d) %p - %p\n", + size, &_probe_flash_end, _probe_flash); + return 0; + } + + memcpy(buffer, _probe_flash, size); + _probe_flash_ptr = (void*)buffer; + + is = disable_interrupts(); + res = _probe_flash_ptr(address, width, 1); + if (is) { + enable_interrupts(); + } + + + vendor = res >> 16; + device = res & 0xffff; + + + return res; +} + +ulong flash_init(void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) { + unsigned id; + ulong flashbase = 0; + int sectsize = 0; + + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + switch (i) { + case 0: + flashbase = SC520_FLASH_BANK0_BASE; + break; + default: + panic("configured to many flash banks!\n"); + } + + id = identify_flash(flashbase, 2); + switch (id) { + case 0x000122d7: + /* 29LV641DH */ + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV640U & FLASH_TYPEMASK); + + flash_info[i].size = A29LV641DH_SIZE; + flash_info[i].sector_count = A29LV641DH_SECTORS; + sectsize = A29LV641DH_SIZE/A29LV641DH_SECTORS; + printf("Bank %d: AMD 29LV641DH\n", i); + break; + + case 0x0001227E: + /* 29LV641MH */ + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_DL640 & FLASH_TYPEMASK); + + flash_info[i].size = A29LV641MH_SIZE; + flash_info[i].sector_count = A29LV641MH_SECTORS; + sectsize = A29LV641MH_SIZE/A29LV641MH_SECTORS; + printf("Bank %d: AMD 29LV641MH\n", i); + break; + + case 0x00890016: + /* 28F320J3A */ + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F320J3A & FLASH_TYPEMASK); + + flash_info[i].size = I28F320J3A_SIZE; + flash_info[i].sector_count = I28F320J3A_SECTORS; + sectsize = I28F320J3A_SIZE/I28F320J3A_SECTORS; + printf("Bank %d: Intel 28F320J3A\n", i); + break; + + case 0x00890017: + /* 28F640J3A */ + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F640J3A & FLASH_TYPEMASK); + + flash_info[i].size = I28F640J3A_SIZE; + flash_info[i].sector_count = I28F640J3A_SECTORS; + sectsize = I28F640J3A_SIZE/I28F640J3A_SECTORS; + printf("Bank %d: Intel 28F640J3A\n", i); + break; + + case 0x00890018: + /* 28F128J3A */ + flash_info[i].flash_id = + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F128J3A & FLASH_TYPEMASK); + + flash_info[i].size = I28F128J3A_SIZE; + flash_info[i].sector_count = I28F128J3A_SECTORS; + sectsize = I28F128J3A_SIZE/I28F128J3A_SECTORS; + printf("Bank %d: Intel 28F128J3A\n", i); + break; + + default: + printf("Bank %d have unknown flash %08x\n", i, id); + flash_info[i].flash_id = FLASH_UNKNOWN; + continue; + } + + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase + j * sectsize; + } + size += flash_info[i].size; + + flash_protect(FLAG_PROTECT_CLEAR, + flash_info[i].start[0], + flash_info[i].start[0] + flash_info[i].size - 1, + &flash_info[i]); + } + + /* + * Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + i386boot_start, + i386boot_end, + &flash_info[0]); +#ifdef CFG_ENV_ADDR + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf("INTEL: "); + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F320J3A & FLASH_TYPEMASK): + printf("1x I28F320J3A (32Mbit)\n"); + break; + case (INTEL_ID_28F640J3A & FLASH_TYPEMASK): + printf("1x I28F640J3A (64Mbit)\n"); + break; + case (INTEL_ID_28F128J3A & FLASH_TYPEMASK): + printf("1x I28F128J3A (128Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + goto done; + break; + } + + break; + + case (AMD_MANUFACT & FLASH_VENDMASK): + printf("AMD: "); + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV640U & FLASH_TYPEMASK): + printf("1x AMD29LV641DH (64Mbit)\n"); + break; + case (AMD_ID_DL640 & FLASH_TYPEMASK): + printf("1x AMD29LV641MH (64Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + goto done; + break; + } + + break; + default: + printf("Unknown Vendor "); + break; + } + + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + done: +} + +/*----------------------------------------------------------------------- + */ + + +static u32 _amd_erase_flash(u32 addr, u32 sector) +{ + unsigned elapsed; + + /* Issue erase */ + *(volatile u16*)(addr + 0xaaaa) = 0x00AA; + *(volatile u16*)(addr + 0x5554) = 0x0055; + *(volatile u16*)(addr + 0xaaaa) = 0x0080; + /* And one unlock */ + *(volatile u16*)(addr + 0xaaaa) = 0x00AA; + *(volatile u16*)(addr + 0x5554) = 0x0055; + /* Sector erase command comes last */ + *(volatile u16*)(addr + sector) = 0x0030; + + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = 0; + while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) { + + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { + *(volatile u16*)(addr) = 0x00f0; + return 1; + } + } + + *(volatile u16*)(addr) = 0x00f0; + + return 0; +} + +extern int _amd_erase_flash_end; +asm ("_amd_erase_flash_end:\n" + ".long 0\n"); + +/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */ +#define __udelay(delay) \ +{ \ + unsigned micro; \ + unsigned milli=0; \ + \ + micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ + \ + for (;;) { \ + \ + milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ + micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \ + \ + if ((delay) <= (micro + (milli * 1000))) { \ + break; \ + } \ + } \ +} while (0) + +static u32 _intel_erase_flash(u32 addr, u32 sector) +{ + unsigned elapsed; + + *(volatile u16*)(addr + sector) = 0x0050; /* clear status register */ + *(volatile u16*)(addr + sector) = 0x0020; /* erase setup */ + *(volatile u16*)(addr + sector) = 0x00D0; /* erase confirm */ + + + /* Wait at least 80us - let's wait 1 ms */ + __udelay(1000); + + elapsed = 0; + while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) { + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { + *(volatile u16*)(addr + sector) = 0x00B0; /* suspend erase */ + *(volatile u16*)(addr + sector) = 0x00FF; /* reset to read mode */ + return 1; + } + } + + *(volatile u16*)(addr + sector) = 0x00FF; /* reset to read mode */ + + return 0; +} + + +extern int _intel_erase_flash_end; +asm ("_intel_erase_flash_end:\n" + ".long 0\n"); + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + u32 (*_erase_flash_ptr)(u32 a, u32 so); + int prot; + int sect; + unsigned size; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash; + + if (size > PROBE_BUFFER_SIZE) { + printf("_amd_erase_flash() routine too large (%d) %p - %p\n", + size, &_amd_erase_flash_end, _amd_erase_flash); + return 0; + } + + memcpy(buffer, _amd_erase_flash, size); + _erase_flash_ptr = (void*)buffer; + + } else if ((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_intel_erase_flash_end - (unsigned)_intel_erase_flash; + + if (size > PROBE_BUFFER_SIZE) { + printf("_intel_erase_flash() routine too large (%d) %p - %p\n", + size, &_intel_erase_flash_end, _intel_erase_flash); + return 0; + } + + memcpy(buffer, _intel_erase_flash, size); + _erase_flash_ptr = (void*)buffer; + } else { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + + if (info->protect[sect] == 0) { /* not protected */ + int res; + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + + if (res) { + printf("Erase timed out, sector %d\n", sect); + return res; + } + + putc('.'); + } + } + + + return 0; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int _amd_write_word(unsigned start, unsigned dest, unsigned data) +{ + volatile u16 *addr2 = (u16*)start; + volatile u16 *dest2 = (u16*)dest; + volatile u16 *data2 = (u16*)&data; + int i; + unsigned elapsed; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile u16*)dest) & (u16)data) != (u16)data) { + return 2; + } + + for (i = 0; i < 2; i++) { + + + addr2[0x5555] = 0x00AA; + addr2[0x2aaa] = 0x0055; + addr2[0x5555] = 0x00A0; + + dest2[i] = (data >> (i*16)) & 0xffff; + + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = 0; + + /* data polling for D7 */ + while ((dest2[i] & 0x0080) != (data2[i] & 0x0080)) { + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { + addr2[i] = 0x00f0; + return 1; + } + } + } + + addr2[i] = 0x00f0; + + return 0; +} + +extern int _amd_write_word_end; +asm ("_amd_write_word_end:\n" + ".long 0\n"); + + + +static int _intel_write_word(unsigned start, unsigned dest, unsigned data) +{ + int i; + unsigned elapsed; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile u16*)dest) & (u16)data) != (u16)data) { + return 2; + } + + for (i = 0; i < 2; i++) { + + *(volatile u16*)(dest+2*i) = 0x0040; /* write setup */ + *(volatile u16*)(dest+2*i) = (data >> (i*16)) & 0xffff; + + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = 0; + + /* data polling for D7 */ + while ((*(volatile u16*)dest & 0x0080) != 0x0080) { + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { + *(volatile u16*)dest = 0x00ff; + return 1; + } + } + } + + *(volatile u16*)dest = 0x00ff; + + + return 0; + +} + +extern int _intel_write_word_end; +asm ("_intel_write_word_end:\n" + ".long 0\n"); + + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 3 - Unsupported flash type + */ + +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + int flag; + u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data); + unsigned size; + + if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word; + + if (size > PROBE_BUFFER_SIZE) { + printf("_amd_write_word() routine too large (%d) %p - %p\n", + size, &_amd_write_word_end, _amd_write_word); + return 0; + } + + memcpy(buffer, _amd_write_word, size); + _write_word_ptr = (void*)buffer; + + } else if ((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_intel_write_word_end - (unsigned)_intel_write_word; + + if (size > PROBE_BUFFER_SIZE) { + printf("_intel_write_word() routine too large (%d) %p - %p\n", + size, &_intel_write_word_end, _intel_write_word); + return 0; + } + + memcpy(buffer, _intel_write_word, size); + _write_word_ptr = (void*)buffer; + } else { + printf ("Can't program unknown flash type - aborted\n"); + return 3; + } + + + wp = (addr & ~3); /* get lower word aligned address */ + + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); + } + for (; i<4 && cnt>0; ++i) { + data |= *src++ << (8*i); + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + if (rc != 0) { + return rc; + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + + for (i=0; i<4; ++i) { + data |= *src++ << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + if (rc != 0) { + return rc; + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return 0; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data |= *src++ << (8*i); + --cnt; + } + + for (; i<4; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + return rc; + +} + + diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c new file mode 100644 index 0000000000..962e04e441 --- /dev/null +++ b/board/sc520_spunk/sc520_spunk.c @@ -0,0 +1,686 @@ +/* + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <ssi.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/ic/sc520.h> + + +/* ------------------------------------------------------------------------- */ + + +/* + * Theory: + * We first set up all IRQs to be non-pci, edge triggered, + * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets + * called we reallocate irqs to the pci bus with sc520_pci_set_irq() + * as needed. Whe choose the irqs to gram from a configurable list + * inside pci_sc520_fixup_irq() (If this list contains stupid irq's + * such as 0 thngas will not work) + */ + +static void irq_init(void) +{ + /* disable global interrupt mode */ + write_mmcr_byte(SC520_PICICR, 0x40); + + /* set all irqs to edge */ + write_mmcr_byte(SC520_MPICMODE, 0x00); + write_mmcr_byte(SC520_SL1PICMODE, 0x00); + write_mmcr_byte(SC520_SL2PICMODE, 0x00); + + /* active low polarity on PIC interrupt pins, + * active high polarity on all other irq pins */ + write_mmcr_word(SC520_INTPINPOL, 0x0000); + + /* set irq number mapping */ + write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */ + write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */ + write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */ + write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */ + write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */ + write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */ + write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */ + write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */ + write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */ + write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */ + write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ + write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6); /* Set Synchronius serial INT to IRQ6*/ + write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */ + write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */ + write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */ + write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */ + write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */ + + write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */ + write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */ + + write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7); /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */ + write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14); /* Set GPIRQ1 (CF IRQ) to IRQ14 */ + write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5); /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */ + write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disbale GIRQ4 ( IRR IRQ ) */ + write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ5 */ + write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ6 */ + write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ7 */ + write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ8 */ + write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ9 */ + write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ2 */ + write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED); /* disable GPIRQ10 */ + + write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */ + write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */ + +} + + +/* PCI stuff */ +static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + int version = read_mmcr_byte(SC520_SYSINFO); + + /* a configurable lists of irqs to steal + * when we need one (a board with more pci interrupt pins + * would use a larger table */ + static int irq_list[] = { + CFG_FIRST_PCI_IRQ, + CFG_SECOND_PCI_IRQ, + CFG_THIRD_PCI_IRQ, + CFG_FORTH_PCI_IRQ + }; + static int next_irq_index=0; + + char tmp_pin; + int pin; + + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); + pin = tmp_pin; + + pin-=1; /* pci config space use 1-based numbering */ + if (-1 == pin) { + return; /* device use no irq */ + } + + + + /* map device number + pin to a pin on the sc520 */ + switch (PCI_DEV(dev)) { + case 6: /* ETH0 */ + pin+=SC520_PCI_INTA; + break; + + case 7: /* ETH1 */ + pin+=SC520_PCI_INTB; + break; + + case 8: /* Crypto */ + pin+=SC520_PCI_INTC; + break; + + case 9: /* PMC slot */ + pin+=SC520_PCI_INTD; + break; + + case 10: /* PC-Card */ + + if (version < 10) { + pin+=SC520_PCI_INTD; + } else { + pin+=SC520_PCI_INTC; + } + break; + + default: + return; + } + + pin&=3; /* wrap around */ + + if (sc520_pci_ints[pin] == -1) { + /* re-route one interrupt for us */ + if (next_irq_index > 3) { + return; + } + if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { + return; + } + next_irq_index++; + } + + + if (-1 != sc520_pci_ints[pin]) { + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + sc520_pci_ints[pin]); + } +#if 0 + printf("fixup_irq: device %d pin %c irq %d\n", + PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); +#endif +} + + +static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *te) +{ + u32 io_base; + u32 temp; + + pciauto_config_device(hose, dev); + + pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07); /* enable device */ + pci_hose_write_config_byte(hose, dev, 0x0c, 0x10); /* cacheline size */ + pci_hose_write_config_byte(hose, dev, 0x0d, 0x40); /* latency timer */ + pci_hose_write_config_byte(hose, dev, 0x1b, 0x40); /* cardbus latency timer */ + pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040); /* reset cardbus */ + pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080); /* route interrupts though ExCA */ + pci_hose_write_config_word(hose, dev, 0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */ + + pci_hose_read_config_dword(hose, dev, 0x80, &temp); /* System control */ + pci_hose_write_config_dword(hose, dev, 0x80, temp | 0x60); /* System control: disable clockrun */ + /* route MF0 to ~INT and MF3 to IRQ7 + * reserve all others */ + pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002); + pci_hose_write_config_byte(hose, dev, 0x91, 0x00); /* card control */ + pci_hose_write_config_byte(hose, dev, 0x92, 0x62); /* device control */ + + if (te->device != 0xac56) { + pci_hose_write_config_byte(hose, dev, 0x93, 0x21); /* async interrupt enable */ + pci_hose_write_config_word(hose, dev, 0xa8, 0x0000); /* reset GPIO */ + pci_hose_write_config_word(hose, dev, 0xac, 0x0000); /* reset GPIO */ + pci_hose_write_config_word(hose, dev, 0xaa, 0x0000); /* reset GPIO */ + pci_hose_write_config_word(hose, dev, 0xae, 0x0000); /* reset GPIO */ + } else { + pci_hose_write_config_byte(hose, dev, 0x93, 0x20); /* */ + } + pci_hose_write_config_word(hose, dev, 0xa4, 0x8000); /* reset power management */ + + + pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base); + io_base &= ~0xfL; + + writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */ + writel(0, io_base+0x10); /* CLKRUN default */ + writel(0, io_base+0x20); /* CLKRUN default */ + +} + + + +static struct pci_config_table pci_sc520_spunk_config_table[] = { + { 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, + { 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, + { 0, 0, 0, 0, 0, 0, NULL, {0,0,0}} +}; + +static struct pci_controller sc520_spunk_hose = { + fixup_irq: pci_sc520_spunk_fixup_irq, + config_table: pci_sc520_spunk_config_table, + first_busno: 0x00, + last_busno: 0xff, +}; + +void pci_init_board(void) +{ + pci_sc520_init(&sc520_spunk_hose); +} + + +/* set up the ISA bus timing and system address mappings */ +static void bus_init(void) +{ + /* versions + * 0 Hyglo versions 0.95 and 0.96 (large baords) + * ?? Hyglo version 0.97 (small board) + * 10 Spunk board + */ + int version = read_mmcr_byte(SC520_SYSINFO); + + if (version) { + /* set up the GP IO pins (for the Spunk board) */ + write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); /* set the GPIO pin function 31-16 reg */ + write_mmcr_word(SC520_PIOPFS15_0, 0x000f); /* set the GPIO pin function 15-0 reg */ + write_mmcr_word(SC520_PIODIR31_16, 0x000f); /* set the GPIO direction 31-16 reg */ + write_mmcr_word(SC520_PIODIR15_0, 0x1ff0); /* set the GPIO direction 15-0 reg */ + write_mmcr_byte(SC520_CSPFS, 0xc0); /* set the CS pin function reg */ + write_mmcr_byte(SC520_CLKSEL, 0x70); + + write_mmcr_word(SC520_PIOCLR31_16, 0x0003); /* reset SSI chip-selects */ + write_mmcr_word(SC520_PIOSET31_16, 0x000c); + + } else { + /* set up the GP IO pins (for the Hyglo board) */ + write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); /* set the GPIO pin function 31-16 reg */ + write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f); /* set the GPIO pin function 15-0 reg */ + write_mmcr_word(SC520_PIODIR31_16, 0x003f); /* set the GPIO direction 31-16 reg */ + write_mmcr_word(SC520_PIODIR15_0, 0xe180); /* set the GPIO direction 15-0 reg */ + write_mmcr_byte(SC520_CSPFS, 0x00); /* set the CS pin function reg */ + write_mmcr_byte(SC520_CLKSEL, 0x70); + + write_mmcr_word(SC520_PIOCLR15_0, 0x0180); /* reset SSI chip-selects */ + } + + write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */ + write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */ + write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */ + write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */ + write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */ + write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */ + write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */ + + write_mmcr_word(SC520_BOOTCSCTL, 0x0407); /* set up timing of BOOTCS */ + + /* adjust the memory map: + * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM + * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio + * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ + + + + /* bootcs */ + write_mmcr_long(SC520_PAR12, 0x8bffe800); + + /* IDE0 = GPCS6 1f0-1f7 */ + write_mmcr_long(SC520_PAR3, 0x380801f0); + + /* IDE1 = GPCS7 3f6 */ + write_mmcr_long(SC520_PAR4, 0x3c0003f6); + + asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ + + write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS)); + +} + + + +/* par usage: + * PAR0 (legacy_video) + * PAR1 (PCI ROM mapping) + * PAR2 + * PAR3 IDE + * PAR4 IDE + * PAR5 (legacy_video) + * PAR6 + * PAR7 (legacy_video) + * PAR8 (legacy_video) + * PAR9 (legacy_video) + * PAR10 + * PAR11 (ISAROM) + * PAR12 BOOTCS + * PAR13 + * PAR14 + * PAR15 + */ + +/* + * This function should map a chunk of size bytes + * of the system address space to the ISA bus + * + * The function will return the memory address + * as seen by the host (which may very will be the + * same as the bus address) + */ +u32 isa_map_rom(u32 bus_addr, int size) +{ + u32 par; + + printf("isa_map_rom asked to map %d bytes at %x\n", + size, bus_addr); + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 12; + par--; + par&=0x7f; + par <<= 18; + par |= (bus_addr>>12); + par |= 0x50000000; + + printf ("setting PAR11 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + write_mmcr_long(SC520_PAR11, par); + + return bus_addr; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void isa_unmap_rom(u32 addr) +{ + printf("isa_unmap_rom asked to unmap %x", addr); + if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) { + write_mmcr_long(SC520_PAR11, 0); + printf(" done\n"); + return; + } + printf(" not ours\n"); +} + +#ifdef CONFIG_PCI +#define PCI_ROM_TEMP_SPACE 0x10000 +/* + * This function should map a chunk of size bytes + * of the system address space to the PCI bus, + * suitable to map PCI ROMS (bus address < 16M) + * the function will return the host memory address + * which should be converted into a bus address + * before used to configure the PCI rom address + * decoder + */ +u32 pci_get_rom_window(struct pci_controller *hose, int size) +{ + u32 par; + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 16; + par--; + par&=0x7ff; + par <<= 14; + par |= (PCI_ROM_TEMP_SPACE>>16); + par |= 0x72000000; + + printf ("setting PAR1 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + write_mmcr_long(SC520_PAR1, par); + + return PCI_ROM_TEMP_SPACE; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void pci_remove_rom_window(struct pci_controller *hose, u32 addr) +{ + printf("pci_remove_rom_window: %x", addr); + if (addr == PCI_ROM_TEMP_SPACE) { + write_mmcr_long(SC520_PAR1, 0); + printf(" done\n"); + return; + } + printf(" not ours\n"); + +} + +/* + * This function is called in order to provide acces to the + * legacy video I/O ports on the PCI bus. + * After this function accesses to I/O ports 0x3b0-0x3bb and + * 0x3c0-0x3df shuld result in transactions on the PCI bus. + * + */ +int pci_enable_legacy_video_ports(struct pci_controller *hose) +{ + /* Map video memory to 0xa0000*/ + write_mmcr_long(SC520_PAR0, 0x7200400a); + + /* forward all I/O accesses to PCI */ + write_mmcr_byte(SC520_ADDDECCTL, + read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI); + + + /* so we map away all io ports to pci (only way to access pci io + * below 0x400. But then we have to map back the portions that we dont + * use so that the generate cycles on the GPIO bus where the sio and + * ISA slots are connected, this requre the use of several PAR registers + */ + + /* bring 0x100 - 0x2f7 back to ISA using PAR5 */ + write_mmcr_long(SC520_PAR5, 0x31f70100); + + /* com2 use 2f8-2ff */ + + /* bring 0x300 - 0x3af back to ISA using PAR7 */ + write_mmcr_long(SC520_PAR7, 0x30af0300); + + /* vga use 3b0-3bb */ + + /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ + write_mmcr_long(SC520_PAR8, 0x300303bc); + + /* vga use 3c0-3df */ + + /* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */ + write_mmcr_long(SC520_PAR9, 0x301703e0); + + /* com1 use 3f8-3ff */ + + return 0; +} +#endif + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + init_sc520(); + bus_init(); + irq_init(); + + /* max drive current on SDRAM */ + write_mmcr_word(SC520_DSCTL, 0x0100); + + /* enter debug mode after next reset (only if jumper is also set) */ + write_mmcr_byte(SC520_RESCFG, 0x08); + /* configure the software timer to 33.000MHz */ + write_mmcr_byte(SC520_SWTMRCFG, 1); + gd->bus_clk = 33000000; + + return 0; +} + +int dram_init(void) +{ + init_sc520_dram(); + return 0; +} + +void show_boot_progress(int val) +{ + int version = read_mmcr_byte(SC520_SYSINFO); + + if (version == 0) { + /* PIO31-PIO16 Data */ + write_mmcr_word(SC520_PIODATA31_16, + (read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */ + + /* PIO0-PIO15 Data */ + write_mmcr_word(SC520_PIODATA15_0, + (read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13)); + } else { + /* newer boards use PIO4-PIO12 */ + /* PIO0-PIO15 Data */ +#if 0 + val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3); +#else + val = (val & 0x007) | ((val & 0x07e) << 2); +#endif + write_mmcr_word(SC520_PIODATA15_0, + (read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4)); + } +} + + +int last_stage_init(void) +{ + + int version = read_mmcr_byte(SC520_SYSINFO); + + printf("Omicron Ceti SC520 Spunk revision %x\n", version); + +#if 0 + if (version) { + int x, y; + + printf("eeprom probe %d\n", spi_eeprom_probe(1)); + + spi_eeprom_read(1, 0, (u8*)&x, 2); + spi_eeprom_read(1, 1, (u8*)&y, 2); + printf("eeprom bytes %04x%04x\n", x, y); + x ^= 0xffff; + y ^= 0xffff; + spi_eeprom_write(1, 0, (u8*)&x, 2); + spi_eeprom_write(1, 1, (u8*)&y, 2); + + spi_eeprom_read(1, 0, (u8*)&x, 2); + spi_eeprom_read(1, 1, (u8*)&y, 2); + printf("eeprom bytes %04x%04x\n", x, y); + + } else { + int x, y; + + printf("eeprom probe %d\n", mw_eeprom_probe(1)); + + mw_eeprom_read(1, 0, (u8*)&x, 2); + mw_eeprom_read(1, 1, (u8*)&y, 2); + printf("eeprom bytes %04x%04x\n", x, y); + + x ^= 0xffff; + y ^= 0xffff; + mw_eeprom_write(1, 0, (u8*)&x, 2); + mw_eeprom_write(1, 1, (u8*)&y, 2); + + mw_eeprom_read(1, 0, (u8*)&x, 2); + mw_eeprom_read(1, 1, (u8*)&y, 2); + printf("eeprom bytes %04x%04x\n", x, y); + + + } +#endif + + ds1722_probe(2); + + return 0; +} + +void ssi_chip_select(int dev) +{ + int version = read_mmcr_byte(SC520_SYSINFO); + + if (version) { + /* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */ + switch (dev) { + case 1: /* EEPROM */ + write_mmcr_word(SC520_PIOCLR31_16, 0x0004); + break; + + case 2: /* Temp Probe */ + write_mmcr_word(SC520_PIOSET31_16, 0x0002); + break; + + case 3: /* CAN */ + write_mmcr_word(SC520_PIOCLR31_16, 0x0008); + break; + + case 4: /* AUX */ + write_mmcr_word(SC520_PIOSET31_16, 0x0001); + break; + + case 0: + write_mmcr_word(SC520_PIOCLR31_16, 0x0003); + write_mmcr_word(SC520_PIOSET31_16, 0x000c); + break; + + default: + printf("Illegal SSI device requested: %d\n", dev); + } + } else { + + /* Globox board: Both EEPROM and TEMP are active-high */ + + switch (dev) { + case 1: /* EEPROM */ + write_mmcr_word(SC520_PIOSET15_0, 0x0100); + break; + + case 2: /* Temp Probe */ + write_mmcr_word(SC520_PIOSET15_0, 0x0080); + break; + + case 0: + write_mmcr_word(SC520_PIOCLR15_0, 0x0180); + break; + + default: + printf("Illegal SSI device requested: %d\n", dev); + } + } +} + + +void spi_init_f(void) +{ + read_mmcr_byte(SC520_SYSINFO) ? + spi_eeprom_probe(1) : + mw_eeprom_probe(1); + +} + +ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) +{ + int offset; + int i; + + offset = 0; + for (i=0;i<alen;i++) { + offset <<= 8; + offset |= addr[i]; + } + + return read_mmcr_byte(SC520_SYSINFO) ? + spi_eeprom_read(1, offset, buffer, len) : + mw_eeprom_read(1, offset, buffer, len); +} + +ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) +{ + int offset; + int i; + + offset = 0; + for (i=0;i<alen;i++) { + offset <<= 8; + offset |= addr[i]; + } + + return read_mmcr_byte(SC520_SYSINFO) ? + spi_eeprom_write(1, offset, buffer, len) : + mw_eeprom_write(1, offset, buffer, len); +} + diff --git a/board/sc520_spunk/sc520_spunk_asm.S b/board/sc520_spunk/sc520_spunk_asm.S new file mode 100644 index 0000000000..e198125b8c --- /dev/null +++ b/board/sc520_spunk/sc520_spunk_asm.S @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* now setup the General purpose bus to give us access to the LEDs. + * We can then use the leds to display status information. + */ + +sc520_cdp_registers: +/* size offset value */ +.word 1 ; .word 0x040 ; .long 0x00 /* SDRAM buffer control */ +.word 2 ; .word 0xc08 ; .long 0x0001 /* GP CS offset */ +.word 2 ; .word 0xc09 ; .long 0x0003 /* GP CS width */ +.word 2 ; .word 0xc0a ; .long 0x0001 /* GP CS width */ +.word 2 ; .word 0xc0b ; .long 0x0003 /* GP RD pulse width */ +.word 2 ; .word 0xc0c ; .long 0x0001 /* GP RD offse */ +.word 2 ; .word 0xc0d ; .long 0x0003 /* GP WR pulse width */ +.word 2 ; .word 0xc0e ; .long 0x0001 /* GP WR offset */ +.word 2 ; .word 0xc2c ; .long 0x003f /* GPIO directionreg 31-16 */ +.word 2 ; .word 0xc2a ; .long 0xe000 /* GPIO directionreg 15-0 */ +.word 2 ; .word 0xc22 ; .long 0xffc0 /* GPIO pin function 31-16 reg */ +.word 2 ; .word 0xc20 ; .long 0x1fff /* GPIO pin function 15-0 reg */ +.word 0 ; .word 0x000 ; .long 0x00 + +/* board early intialization */ +.globl early_board_init +early_board_init: + movl $sc520_cdp_registers,%esi +init_loop: + movl $0xfffef000,%edi /* MMCR base to edi */ + movw (%esi), %bx /* load size to bx */ + cmpw $0, %bx /* if size is 0 we're done */ + je done + xorl %edx,%edx + movw 2(%esi), %dx /* load MMCR offset to dx */ + addl %edx, %edi /* add offset to base in edi */ + movl 4(%esi), %eax /* load value in eax */ + cmpw $1, %bx + je byte /* byte op? */ + cmpw $2, %bx + je word /* word op? */ + movl %eax, (%edi) /* must be long, then */ + jmp next +byte: movb %al,(%edi) + jmp next +word: movw %ax,(%edi) +next: addl $8, %esi /* advance esi */ + jmp init_loop + + /* light all leds */ +done: movl $0xfffefc32,%edx + movw $0000,(%edx) + + jmp *%ebp /* return to caller */ + + +.globl __show_boot_progress +__show_boot_progress: + movl $0xfffefc32,%edx + xorw $0xffff, %ax + movw %ax,(%edx) + jmp *%ebp + diff --git a/board/sc520_spunk/sc520_spunk_asm16.S b/board/sc520_spunk/sc520_spunk_asm16.S new file mode 100644 index 0000000000..cdcbbbef6a --- /dev/null +++ b/board/sc520_spunk/sc520_spunk_asm16.S @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * 16bit initialization code. + * This code have to map the area of the boot flash + * that is used by U-boot to its final destination. + */ + +.text +.section .start16, "ax" +.code16 +.globl board_init16 +board_init16: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* Map the entire flash at 0x38000000 + * (with BOOTCS and PAR14, use 0xabfff800 for ROMCS1) */ + movl $0xc0, %edi + movl $0x8bfff800, %eax + movl %eax, (%di) + + /* Disable SDRAM write buffer */ + movw $0x40,%di + xorw %ax,%ax + movb %al, (%di) + + /* Disabe MMCR alias */ + movw $0xfffc, %dx + movl $0x000000cb, %eax + outl %eax, %dx + + /* the return address is stored in bp */ + jmp *%bp + + +.section .bios, "ax" +.code16 +.globl realmode_reset +realmode_reset: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* issue software reset thorugh MMCR */ + movl $0xd72, %edi + movb $0x01, %al + movb %al, (%di) + +1: hlt + jmp 1 + diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds new file mode 100644 index 0000000000..fbab9b85f2 --- /dev/null +++ b/board/sc520_spunk/u-boot.lds @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) + +SECTIONS +{ + . = 0x387c0000; /* Where bootcode in the flash is mapped */ + .text : { *(.text); } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = 0x400000; /* Ram data segment to use */ + _i386boot_romdata_dest = ABSOLUTE(.); + .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } + _i386boot_romdata_start = LOADADDR(.data); + + . = ALIGN(4); + .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) } + _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got); + + + . = ALIGN(4); + _i386boot_bss_start = ABSOLUTE(.); + .bss : { *(.bss) } + _i386boot_bss_size = SIZEOF(.bss); + + + /* 16bit realmode trampoline code */ + .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) } + + _i386boot_realmode = LOADADDR(.realmode); + _i386boot_realmode_size = SIZEOF(.realmode); + + /* 16bit BIOS emulation code (just enough to boot Linux) */ + .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } + + _i386boot_bios = LOADADDR(.bios); + _i386boot_bios_size = SIZEOF(.bios); + + + /* The load addresses below assumes that the flash + * will be mapped so that 0x387f0000 == 0xffff0000 + * at reset time + * + * The fe00 and ff00 offsets of the start32 and start16 + * segments are arbitrary, the just have to be mapped + * at reset and the code have to fit. + * The fff0 offset of reset is important, however. + */ + + + . = 0xfffffe00; + .start32 : AT (0x387ffe00) { *(.start32); } + + . = 0xff00; + .start16 : AT (0x387fff00) { *(.start16); } + + . = 0xfff0; + .reset : AT (0x387ffff0) { *(.reset); } + _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); +} diff --git a/board/sixnet/fpgadata.c b/board/sixnet/fpgadata.c index d6252fb365..b756a65039 100644 --- a/board/sixnet/fpgadata.c +++ b/board/sixnet/fpgadata.c @@ -1,1719 +1,1719 @@ - 0xff, 0x87, 0xdf, 0xa8, 0x7f, 0xff, 0xfc, 0xff, - 0xff, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0x8f, 0x71, + 0xff, 0x87, 0xff, 0x88, 0x7f, 0xff, 0xf9, 0xff, + 0xff, 0xf5, 0xff, 0x8f, 0xff, 0xf0, 0x8f, 0xf9, + 0xff, 0xef, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xf0, + 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xcf, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xaf, 0xff, 0xf0, 0xff, 0xdf, 0xff, - 0xf7, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xff, - 0xdf, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xaf, 0x7f, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xdf, 0xdf, 0x83, 0x73, 0xf0, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, - 0xf1, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xf8, 0xdf, 0xdf, 0xf3, 0xf0, 0xff, 0xff, - 0x7f, 0x8f, 0x7f, 0xf0, 0xff, 0x8f, 0x7f, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, + 0x7f, 0x7b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x77, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x86, 0xf6, 0xf0, 0xff, + 0xf0, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x0f, 0x7f, + 0xc1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0xff, 0xff, 0xf6, 0xf0, 0xff, 0xff, + 0x7f, 0x8f, 0x7f, 0xf0, 0xff, 0x0f, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, - 0xff, 0xfa, 0xff, 0x97, 0xcb, 0xf5, 0xf0, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71, - 0xf1, 0xff, 0xff, 0xdf, 0x7f, - 0xff, 0x7f, 0xd7, 0xff, 0xf3, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xf8, 0xf7, 0x8f, 0xcf, 0xf0, 0xf6, 0xff, + 0xff, 0xef, 0xff, 0xfb, 0x7f, 0x2f, 0x1f, 0x71, + 0xf5, 0xff, 0xff, 0xef, 0x7f, + 0xff, 0x7f, 0xff, 0xf7, 0xf6, 0xfe, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xd7, 0x7f, 0x73, 0xff, 0xff, 0xff, - 0x0f, 0xff, 0xf0, 0xff, 0x7f, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xf7, 0x7f, 0x77, 0xf7, 0xff, 0xfb, + 0x0f, 0xff, 0xf0, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xfe, 0xff, 0x8f, 0x7f, 0xf1, - 0xbf, 0xef, 0xf8, 0xdf, 0xff, 0xf5, 0xff, 0xff, - 0x8f, 0xff, 0xa0, 0xff, 0xfb, 0x8f, 0x7f, 0xf1, - 0xff, 0xdf, 0x8f, 0x75, 0x81, - 0xff, 0xff, 0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xaf, 0xff, 0xfb, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfa, 0xce, 0xff, 0xfd, 0xff, 0xff, + 0x9f, 0xff, 0x8e, 0xff, 0xf0, 0xbf, 0x7f, 0xf5, + 0xff, 0xef, 0x9f, 0xfd, 0x81, + 0xff, 0xf9, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, + 0xff, 0xef, 0x9f, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, - 0xbf, 0x2f, 0xf0, 0xba, 0xfb, 0xf8, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0xff, 0x77, 0xfa, 0xb6, 0xff, 0x78, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xbf, 0xfd, 0x0f, 0x7f, 0xf1, 0xff, 0xff, 0xff, 0xff, 0x8f, - 0xff, 0xaa, 0xf7, 0xfa, 0xfb, 0xbf, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xfe, 0xff, 0xff, 0xdf, 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0x0f, 0xff, 0x78, 0x8f, 0x8f, + 0x70, 0x70, 0x7f, 0xfe, 0xff, 0x8f, 0xff, 0x70, + 0xff, 0xfe, 0xff, 0xff, 0xbe, + 0xff, 0xf8, 0xf7, 0x0b, 0xf7, 0x88, 0xf7, 0xf0, + 0x8f, 0x8f, 0x70, 0xf0, 0x7e, 0x73, 0xff, 0x8f, + 0x7e, 0xf0, 0xff, 0x8f, 0x7f, + 0xff, 0x78, 0x77, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, + 0xff, 0x8f, 0x77, 0x70, 0x77, 0x7f, 0xff, 0x7f, + 0xff, 0xff, 0xfe, 0x8f, 0x7f, + 0xff, 0xff, 0x77, 0x8f, 0xff, 0xf0, 0xff, 0xff, + 0x77, 0x7f, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xef, 0x7f, 0xff, 0xbf, + 0xbf, 0xff, 0x74, 0xff, 0xff, 0x8f, 0xff, 0xfc, + 0x0f, 0xf3, 0x8c, 0xff, 0xfd, 0xff, 0xff, 0x8f, + 0x7f, 0xf1, 0x8f, 0x7d, 0x83, + 0xff, 0x7f, 0x77, 0xff, 0xff, 0xff, 0xff, 0xfb, + 0xf7, 0x7f, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xf8, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x78, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x8f, 0x70, 0x70, 0xf7, 0xff, 0xff, 0xff, - 0xff, 0xcf, 0x8f, 0x1f, 0x71, - 0xff, 0xf8, 0xff, 0x7f, 0xff, 0x8f, 0x8f, 0x80, - 0x80, 0x80, 0x70, 0x70, 0x7f, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x8f, 0x1f, 0x71, - 0xbf, 0x7f, 0x70, 0xff, 0xff, 0xff, 0xff, 0xff, - 0x7f, 0xff, 0x8f, 0xff, 0x70, 0xff, 0xff, 0xff, - 0xef, 0xff, 0xff, 0xef, 0x8f, - 0xff, 0x07, 0x7f, 0x78, 0xfe, 0xff, 0xae, 0xff, - 0xfb, 0x7f, 0xff, 0x0f, 0xff, 0xf0, 0xdf, 0xff, - 0xff, 0xfe, 0xff, 0xfe, 0xff, - 0x7f, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x8f, - 0xff, 0x70, 0xff, 0x7f, 0xff, 0xff, 0xcf, 0xff, + 0xff, 0xff, 0x8e, 0x0f, 0x71, + 0xff, 0xf8, 0xf7, 0x7f, 0xff, 0x8f, 0x8f, 0x80, + 0x80, 0x81, 0x70, 0x70, 0x7f, 0xff, 0xff, 0xff, + 0xff, 0x6f, 0x8f, 0x0f, 0x71, + 0xbf, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x7b, 0xff, 0x9f, 0xff, 0x70, 0xff, 0xff, 0xff, + 0xff, 0x7f, 0xff, 0xfe, 0x8f, + 0xff, 0x87, 0x7f, 0x78, 0xfe, 0xff, 0x9e, 0xff, + 0xf2, 0x7f, 0xff, 0x0f, 0xff, 0xf0, 0xff, 0xef, + 0xff, 0x7f, 0xff, 0xff, 0xff, + 0x7f, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0xfe, 0x8f, + 0xff, 0x70, 0xff, 0x7f, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, - 0xff, 0xff, 0x7f, 0xf7, 0xff, 0xff, 0xfe, 0xff, - 0x7f, 0x7f, 0xf7, 0xff, 0xdf, 0xff, 0xcf, 0xff, + 0xff, 0xff, 0x7f, 0xf7, 0xff, 0xfe, 0xff, 0xff, + 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0x77, 0x8f, 0x8f, 0xf0, 0xf0, - 0xdf, 0xff, 0xf6, 0xff, 0xef, 0xef, 0x8f, 0x0f, - 0x71, 0xb1, 0x3e, 0xf9, 0xf8, - 0xff, 0xff, 0x7f, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, - 0xdf, 0xff, 0xf6, 0xff, 0xff, 0xef, 0xbf, 0x0f, - 0x7d, 0xf1, 0x9e, 0xfe, 0xe9, - 0xff, 0xdf, 0x7b, 0x72, 0x8f, 0xff, 0xf0, 0xbf, - 0xff, 0xfa, 0xff, 0xef, 0xff, 0xfa, 0x8f, 0x7f, - 0xf1, 0xbf, 0x7f, 0xf9, 0xff, - 0xff, 0xfc, 0xfb, 0xff, 0xbf, 0xcf, 0xff, 0xe1, - 0xaf, 0xdf, 0xfa, 0xf6, 0xff, 0xff, 0xff, 0xbf, - 0x7f, 0xfd, 0xbe, 0xb7, 0xf5, - 0xff, 0xf8, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xfe, - 0xff, 0x8f, 0xff, 0xf8, 0xff, 0xff, 0x8f, 0x7f, - 0xf1, 0x7f, 0xfb, 0x9f, 0xff, - 0xff, 0xf8, 0x8b, 0x8f, 0xf0, 0xf0, 0xff, 0xcf, - 0x7f, 0x8f, 0xff, 0xf8, 0x8f, 0x0f, 0x71, 0xf1, - 0xff, 0x4f, 0x7b, 0x95, 0x7f, - 0xff, 0xff, 0x8e, 0x7f, 0xf0, 0xff, 0xff, 0xff, - 0xbf, 0xff, 0xfa, 0xff, 0x8f, 0x7f, 0xf1, 0xff, - 0xfe, 0xff, 0xbf, 0xff, 0xbd, + 0xff, 0xff, 0x7f, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xaf, 0x0f, + 0x70, 0xd1, 0xff, 0xf8, 0xfe, + 0xff, 0xff, 0xff, 0xf7, 0xaf, 0x8f, 0xfa, 0xf0, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x9f, 0x8f, 0x0f, + 0x79, 0xe1, 0xff, 0xfe, 0xff, + 0xbf, 0xff, 0xff, 0x7a, 0x8f, 0xff, 0xf0, 0xef, + 0xff, 0xfb, 0xff, 0xaf, 0xff, 0xfb, 0x8f, 0x7f, + 0xf1, 0xdf, 0xff, 0xf9, 0xff, + 0xbf, 0xff, 0xff, 0xf7, 0xff, 0xaf, 0xff, 0xba, + 0xaf, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xef, 0xdf, + 0xff, 0xfd, 0xbe, 0xf7, 0xf5, + 0xff, 0xf8, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, + 0xff, 0x8f, 0xf7, 0xf0, 0xff, 0xff, 0x8f, 0x3f, + 0x11, 0xeb, 0xdb, 0xcf, 0x7f, + 0xbf, 0xf0, 0x8f, 0x87, 0xf0, 0xf0, 0xff, 0xbf, + 0xff, 0x8f, 0xff, 0xf1, 0x8f, 0x0f, 0x31, 0xf1, + 0x9f, 0xdf, 0xf9, 0x85, 0x7f, + 0xbf, 0xff, 0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff, + 0xee, 0xff, 0xfb, 0xf7, 0x8f, 0x7f, 0xb1, 0xff, + 0xff, 0xff, 0xff, 0xdf, 0xfd, 0xff, 0xff, 0xff, 0x8f, 0x8f, 0xf0, 0x80, 0xff, - 0xf0, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71, - 0x81, 0x7f, 0xf1, 0xff, 0xff, - 0xff, 0xff, 0xff, 0x87, 0xff, 0xf0, 0xff, 0xef, - 0xbf, 0xbf, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xf1, - 0xbf, 0x7f, 0x99, 0xd7, 0xfd, - 0xff, 0xff, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xfe, - 0xff, 0xff, 0xef, 0x77, 0xbf, - 0xff, 0xce, 0xff, 0x88, 0xff, 0xf0, 0xef, 0xef, - 0xfa, 0xdf, 0xff, 0xff, 0xff, 0x86, 0x7f, 0xd1, - 0xff, 0xff, 0xf7, 0xb7, 0xff, + 0xf0, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x2f, 0x71, + 0xc1, 0x7f, 0xf1, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xbf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xd1, + 0x9f, 0xff, 0x7b, 0xb7, 0xff, + 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xfe, 0x8f, 0xff, 0xf1, 0xff, 0xff, + 0xff, 0xff, 0xbf, 0xb7, 0xff, + 0xff, 0xa4, 0xf7, 0x88, 0xff, 0xf0, 0xaf, 0xbf, + 0xfb, 0xef, 0xff, 0xf7, 0xff, 0x8f, 0x7f, 0xf1, + 0xff, 0xdd, 0xf7, 0x97, 0x7f, 0xff, 0xff, 0xf7, 0xff, 0x8f, 0xff, 0xf0, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0x8f, 0x7e, - 0xf1, 0xff, 0xff, 0xff, 0xef, - 0xff, 0xf7, 0xff, 0xf7, 0xcf, 0x8f, 0xa8, 0xf0, - 0xfa, 0xff, 0xff, 0xb7, 0xf7, 0xf7, 0x8f, 0x8f, - 0x71, 0xf1, 0xf7, 0x77, 0xef, - 0xff, 0xf0, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0x8f, 0xff, 0xf0, 0xf7, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0x8f, 0x6f, - 0xbf, 0xff, 0xf0, 0xef, 0xff, 0xcf, 0xff, 0xf8, - 0xff, 0xff, 0x8f, 0xff, 0xf0, 0x9f, 0xff, 0x8f, - 0xff, 0xf1, 0xff, 0xff, 0x8f, - 0xff, 0xff, 0xe7, 0xaf, 0xff, 0xf0, 0xff, 0xff, - 0xff, 0xff, 0x7f, 0xbf, 0x9f, 0x9f, 0x7f, 0xf9, - 0xff, 0xfe, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0x7f, - 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xef, 0xff, 0x7f, - 0xbf, 0xff, 0xf7, 0xcf, 0xff, 0xf8, 0xff, 0x7f, - 0x9f, 0xff, 0xf1, 0xff, 0xff, 0x8f, 0xff, 0xf1, - 0xff, 0xff, 0xdf, 0xff, 0xe1, - 0xff, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xfe, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x9f, - 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, - 0xff, 0xff, 0xff, 0xef, 0xff, - 0xff, 0xf8, 0xff, 0xf7, 0xbf, 0xff, 0xf7, 0xff, - 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0x7f, - 0xff, 0xff, 0xff, 0x9f, 0xff, - 0xff, 0xf8, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0x8f, 0xef, 0xf0, 0xff, 0xff, 0xff, 0xff, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, + 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xf7, 0xaf, 0x0f, 0xa0, 0xf0, + 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x0f, + 0x71, 0xb1, 0x37, 0xf7, 0xff, + 0xff, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xf0, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, - 0xff, 0xff, 0xf7, 0xff, 0x0f, 0xfe, 0xf0, 0xff, - 0xff, 0xef, 0xff, 0xef, 0xff, 0xcf, 0x8f, 0x7f, + 0xbf, 0xff, 0xf8, 0xf7, 0xff, 0xa7, 0xff, 0xf0, + 0xff, 0xff, 0x8f, 0xfe, 0xf0, 0xff, 0xff, 0x8f, + 0x7f, 0xf1, 0xff, 0xff, 0xcf, + 0xff, 0xff, 0xf7, 0x9f, 0xf7, 0xf3, 0xff, 0xff, + 0xff, 0xff, 0x7f, 0xff, 0xff, 0xbf, 0x7f, 0xf9, + 0xff, 0xfe, 0xff, 0xff, 0xdf, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f, + 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xbf, 0xbf, + 0xff, 0xff, 0xff, 0xaf, 0xff, 0xf0, 0xff, 0xff, + 0x9f, 0xfe, 0xf1, 0xff, 0xff, 0xcf, 0x7f, 0xf1, + 0xff, 0xff, 0xdf, 0xff, 0xf1, + 0xbf, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xbf, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0x6f, + 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0x7f, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xbf, + 0xff, 0xf8, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xcf, 0xff, + 0xff, 0xd8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x8f, 0xef, 0xe0, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x8f, 0x3f, + 0xff, 0xdf, 0xf7, 0xff, 0x0f, 0xfe, 0xf0, 0xff, + 0xff, 0xff, 0xff, 0xef, 0xff, 0xdf, 0x8e, 0x7f, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xef, 0x7f, 0xff, 0xff, + 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xbf, 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xef, 0xff, 0xbf, 0x7f, 0xf1, 0xff, - 0xbf, 0xff, 0xff, 0xff, 0xbf, + 0xff, 0xff, 0xef, 0xff, 0xbf, 0x7f, 0xe1, 0xff, + 0xdf, 0xff, 0x7f, 0xff, 0xbf, 0xff, 0xa7, 0xff, 0x88, 0xff, 0xf1, 0xfe, 0xff, - 0xff, 0xff, 0xff, 0x1f, 0xff, 0xf0, 0xcf, 0xf1, - 0xff, 0xff, 0xff, 0xbf, 0xff, + 0xff, 0xff, 0xff, 0x1f, 0xff, 0xf0, 0xcf, 0xb1, + 0xff, 0xef, 0xff, 0x7f, 0xff, diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c index 1570c46823..ec1cb8b00f 100644 --- a/board/sixnet/sixnet.c +++ b/board/sixnet/sixnet.c @@ -32,6 +32,11 @@ # include <status_led.h> #endif +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include <linux/mtd/nand.h> +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +#endif + #define ORMASK(size) ((-size) & OR_AM_MSK) static long ram_size(ulong *, long); @@ -321,6 +326,17 @@ int misc_init_r (void) return (0); } +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +void nand_init(void) +{ + nand_probe(CFG_DFLASH_BASE); /* see if any NAND flash present */ + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + puts("NAND: "); + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif + /* ------------------------------------------------------------------------- */ /* diff --git a/board/utx8245/flash.c b/board/utx8245/flash.c index 73bb04d98e..3271827081 100644 --- a/board/utx8245/flash.c +++ b/board/utx8245/flash.c @@ -45,25 +45,19 @@ # endif #endif -#define FLASH_BANK_SIZE 0x200000 +#define FLASH_BANK_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ #define MAIN_SECT_SIZE 0x10000 #define SECT_SIZE_32KB 0x8000 #define SECT_SIZE_8KB 0x2000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; -static int write_word (flash_info_t *info, ulong dest, ulong data); - -static __inline__ unsigned long get_msr(void) -{ unsigned long msr; - __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void set_msr(unsigned long msr) -{ - __asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); -} +static int write_word (flash_info_t * info, ulong dest, ulong data); +#if 0 +static void write_via_fpu (vu_long * addr, ulong * data); +#endif +static __inline__ unsigned long get_msr (void); +static __inline__ void set_msr (unsigned long msr); /*flash command address offsets*/ #define ADDR0 (0x555) @@ -77,285 +71,336 @@ static __inline__ void set_msr(unsigned long msr) /*---------------------------------------------------------------------*/ -unsigned long flash_init(void) +unsigned long flash_init (void) { - int i, j; - ulong size = 0; + int i; /* flash bank counter */ + int j; /* flash device sector counter */ + int k; /* flash size calculation loop counter */ + int N; /* pow(2,N) is flash size, but we don't have <math.h> */ + ulong total_size = 0, device_size = 1; unsigned char manuf_id, device_id; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) - { - vu_char *addr = (vu_char *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE); + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + vu_char *addr = (vu_char *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE); + + addr[0x555] = 0xAA; /* get manuf/device info command */ + addr[0x2AA] = 0x55; /* 3-cycle command */ + addr[0x555] = 0x90; + + manuf_id = addr[0]; /* read back manuf/device info */ + device_id = addr[1]; - addr[0x555] = 0xAA; /* 3 cycles to read device info. See */ - addr[0x2AA] = 0x55; /* AM29LV116D datasheet for list of */ - addr[0x555] = 0x90; /* available commands. */ + addr[0x55] = 0x98; /* CFI command */ + N = addr[0x27]; /* read back device_size = pow(2,N) */ - manuf_id = addr[0]; - device_id = addr[1]; + for (k = 0; k < N; k++) /* calculate device_size = pow(2,N) */ + device_size *= 2; + + flash_info[i].size = device_size; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; #if defined DEBUG_FLASH - printf("manuf_id = %x, device_id = %x\n", manuf_id, device_id); + printf ("manuf_id = %x, device_id = %x\n", manuf_id, device_id); #endif + /* find out what kind of flash we are using */ + if ((manuf_id == (uchar) (AMD_MANUFACT)) + && (device_id == AMD_ID_LV033C)) { + flash_info[i].flash_id = + ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | + (FLASH_AM033C & FLASH_TYPEMASK); + + /* set individual sector start addresses */ + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = + (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + j * MAIN_SECT_SIZE); + } + } - if ( (manuf_id == (uchar)(AMD_MANUFACT)) && - ( device_id == AMD_ID_LV116DT)) - { - flash_info[i].flash_id = ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | - (AMD_ID_LV116DT & FLASH_TYPEMASK); - } else { - flash_info[i].flash_id = FLASH_UNKNOWN; - addr[0] = (long)0xFFFFFFFF; - goto Done; + else if ((manuf_id == (uchar) (AMD_MANUFACT)) && + (device_id == AMD_ID_LV116DT)) { + flash_info[i].flash_id = + ((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) | + (FLASH_AM160T & FLASH_TYPEMASK); + + /* set individual sector start addresses */ + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = + (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + j * MAIN_SECT_SIZE); + + if (j < (CFG_MAX_FLASH_SECT - 3)) { + flash_info[i].start[j] = + (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + j * MAIN_SECT_SIZE); + } else if (j == (CFG_MAX_FLASH_SECT - 3)) { + flash_info[i].start[j] = + (flash_info[i].start[j - 1] + SECT_SIZE_32KB); + + } else { + flash_info[i].start[j] = + (flash_info[i].start[j - 1] + SECT_SIZE_8KB); + } + } + } + + else { + flash_info[i].flash_id = FLASH_UNKNOWN; + addr[0] = 0xFF; + goto Done; } #if defined DEBUG_FLASH printf ("flash_id = 0x%08lX\n", flash_info[i].flash_id); #endif - addr[0] = (long)0xFFFFFFFF; - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - - for (j = 0; j < flash_info[i].sector_count; j++) - { + addr[0] = 0xFF; - if (j < (CFG_MAX_FLASH_SECT - 3) ) + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - flash_info[i].start[j] = CFG_FLASH_BASE + i * FLASH_BANK_SIZE + - j * MAIN_SECT_SIZE; + total_size += flash_info[i].size; + } - else if (j == (CFG_MAX_FLASH_SECT - 3) ) - - flash_info[i].start[j] = flash_info[i].start[j-1] + SECT_SIZE_32KB; - - - else - - flash_info[i].start[j] = flash_info[i].start[j-1] + SECT_SIZE_8KB; - - } - - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ + /* Protect monitor and environment sectors + */ #if CFG_MONITOR_BASE >= CFG_FLASH_BASE - flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); #endif #if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) - flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); #endif -Done: - return size; + Done: + return total_size; } /*----------------------------------------------------------------------- */ -void flash_print_info(flash_info_t *info) +void flash_print_info (flash_info_t * info) { - static const char unk[] = "Unknown"; - const char *mfct = unk, *type = unk; - unsigned int i; - - if(info->flash_id != FLASH_UNKNOWN) - { - switch(info->flash_id & FLASH_VENDMASK) - { - case FLASH_MAN_AMD: mfct = "AMD"; break; - case FLASH_MAN_FUJ: mfct = "FUJITSU"; break; - case FLASH_MAN_STM: mfct = "STM"; break; - case FLASH_MAN_SST: mfct = "SST"; break; - case FLASH_MAN_BM: mfct = "Bright Microelectonics"; break; - case FLASH_MAN_INTEL: mfct = "Intel"; break; - } - - switch(info->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: type = "AM29F040B (512K * 8, uniform sector size)"; break; - case FLASH_AM400B: type = "AM29LV400B (4 Mbit, bottom boot sect)"; break; - case FLASH_AM400T: type = "AM29LV400T (4 Mbit, top boot sector)"; break; - case FLASH_AM800B: type = "AM29LV800B (8 Mbit, bottom boot sect)"; break; - case FLASH_AM800T: type = "AM29LV800T (8 Mbit, top boot sector)"; break; - case FLASH_AM160T: type = "AM29LV160T (16 Mbit, top boot sector)"; break; - case FLASH_AM320B: type = "AM29LV320B (32 Mbit, bottom boot sect)"; break; - case FLASH_AM320T: type = "AM29LV320T (32 Mbit, top boot sector)"; break; - case FLASH_STM800AB: type = "M29W800AB (8 Mbit, bottom boot sect)"; break; - case FLASH_SST800A: type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; break; - case FLASH_SST160A: type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; break; - } - } - - printf( - "\n Brand: %s Type: %s\n" - " Size: %lu KB in %d Sectors\n", - mfct, - type, - info->size >> 10, - info->sector_count - ); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; i++) - { - unsigned long size; - unsigned int erased; - unsigned long * flash = (unsigned long *) info->start[i]; - - /* - * Check if whole sector is erased - */ - size = - (i != (info->sector_count - 1)) ? - (info->start[i + 1] - info->start[i]) >> 2 : - (info->start[0] + info->size - info->start[i]) >> 2; - - for( - flash = (unsigned long *) info->start[i], erased = 1; - (flash != (unsigned long *) info->start[i] + size) && erased; - flash++ - ) - erased = *flash == ~0x0UL; - - printf( - "%s %08lX %s %s", - (i % 5) ? "" : "\n ", - info->start[i], - erased ? "E" : " ", - info->protect[i] ? "RO" : " " - ); - } - - puts("\n"); - return; + static const char unk[] = "Unknown"; + const char *mfct = unk, *type = unk; + unsigned int i; + + if (info->flash_id != FLASH_UNKNOWN) { + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + mfct = "AMD"; + break; + case FLASH_MAN_FUJ: + mfct = "FUJITSU"; + break; + case FLASH_MAN_STM: + mfct = "STM"; + break; + case FLASH_MAN_SST: + mfct = "SST"; + break; + case FLASH_MAN_BM: + mfct = "Bright Microelectonics"; + break; + case FLASH_MAN_INTEL: + mfct = "Intel"; + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM033C: + type = "AM29LV033C (32 Mbit, uniform sector size)"; + break; + case FLASH_AM160T: + type = "AM29LV160T (16 Mbit, top boot sector)"; + break; + case FLASH_AM040: + type = "AM29F040B (512K * 8, uniform sector size)"; + break; + case FLASH_AM400B: + type = "AM29LV400B (4 Mbit, bottom boot sect)"; + break; + case FLASH_AM400T: + type = "AM29LV400T (4 Mbit, top boot sector)"; + break; + case FLASH_AM800B: + type = "AM29LV800B (8 Mbit, bottom boot sect)"; + break; + case FLASH_AM800T: + type = "AM29LV800T (8 Mbit, top boot sector)"; + break; + case FLASH_AM320B: + type = "AM29LV320B (32 Mbit, bottom boot sect)"; + break; + case FLASH_AM320T: + type = "AM29LV320T (32 Mbit, top boot sector)"; + break; + case FLASH_STM800AB: + type = "M29W800AB (8 Mbit, bottom boot sect)"; + break; + case FLASH_SST800A: + type = "SST39LF/VF800 (8 Mbit, uniform sector size)"; + break; + case FLASH_SST160A: + type = "SST39LF/VF160 (16 Mbit, uniform sector size)"; + break; + } + } + + printf ("\n Brand: %s Type: %s\n" + " Size: %lu KB in %d Sectors\n", + mfct, type, info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i = 0; i < info->sector_count; i++) { + unsigned long size; + unsigned int erased; + unsigned long *flash = (unsigned long *) info->start[i]; + + /* + * Check if whole sector is erased + */ + size = (i != (info->sector_count - 1)) ? + (info->start[i + 1] - info->start[i]) >> 2 : + (info->start[0] + info->size - info->start[i]) >> 2; + + for (flash = (unsigned long *) info->start[i], erased = 1; + (flash != (unsigned long *) info->start[i] + size) && erased; + flash++) + erased = *flash == ~0x0UL; + + printf ("%s %08lX %s %s", + (i % 5) ? "" : "\n ", + info->start[i], + erased ? "E" : " ", info->protect[i] ? "RO" : " "); + } + + puts ("\n"); + return; } /*----------------------------------------------------------------------- */ -int flash_erase (flash_info_t *info, int s_first, int s_last) +int flash_erase (flash_info_t * info, int s_first, int s_last) { - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - unsigned char sh8b; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + unsigned char sh8b; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Check the ROM CS */ + if ((info->start[0] >= ROM_CS1_START) + && (info->start[0] < ROM_CS0_START)) + sh8b = 3; + else + sh8b = 0; /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) - { - if (info->protect[sect] == 0) - { /* not protected */ - addr = (FLASH_WORD_SIZE *)(info->start[0] + ( - (info->start[sect] - info->start[0]) << sh8b)); - - if (info->flash_id & FLASH_MAN_SST) - { - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - udelay(30000); /* wait 30 ms */ + flag = disable_interrupts (); + + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info-> + start[sect] - + info-> + start[0]) << + sh8b)); + + if (info->flash_id & FLASH_MAN_SST) { + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080; + addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ + udelay (30000); /* wait 30 ms */ + } else { + addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ } - else - addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (FLASH_WORD_SIZE *)(info->start[0] + ( - (info->start[l_sect] - info->start[0]) << sh8b)); - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] - + info-> + start[0]) << sh8b)); + while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != + (FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; } @@ -366,68 +411,68 @@ DONE: * 2 - Flash not erased */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) { - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word (info, wp, data)); } @@ -437,55 +482,79 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word (flash_info_t * info, ulong dest, ulong data) { - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0]; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0]; volatile FLASH_WORD_SIZE *dest2; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; ulong start; int flag; int i; unsigned char sh8b; - /* Check the ROM CS */ - if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)) - sh8b = 3; - else - sh8b = 0; - - dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) + - info->start[0]); - - /* Check if Flash is (sufficiently) erased */ - if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0; - - dest2[i << sh8b] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); + /* Check the ROM CS */ + if ((info->start[0] >= ROM_CS1_START) + && (info->start[0] < ROM_CS0_START)) + sh8b = 3; + else + sh8b = 0; + + dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) + + info->start[0]); + + /* Check if Flash is (sufficiently) erased */ + if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i << sh8b] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + */ +#if 0 +static void write_via_fpu (vu_long * addr, ulong * data) +{ + __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data)); + __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr)); } +#endif + /*----------------------------------------------------------------------- */ +static __inline__ unsigned long get_msr (void) +{ + unsigned long msr; + + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + return msr; +} + +static __inline__ void set_msr (unsigned long msr) +{ + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); +} diff --git a/board/utx8245/utx8245.c b/board/utx8245/utx8245.c index 63b4e3ee85..a8c82e47c5 100644 --- a/board/utx8245/utx8245.c +++ b/board/utx8245/utx8245.c @@ -30,6 +30,7 @@ #include <mpc824x.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/mmu.h> #include <pci.h> #define SAVE_SZ 32 @@ -53,11 +54,18 @@ long int initdram(int board_type) volatile ulong *addr; ulong save[SAVE_SZ]; ulong val, ret = 0; +/* + write_bat(IBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP), + ( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE)); + + write_bat(DBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP), + ( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE)); +*/ + for (i=0; i<SAVE_SZ; i++) { + save[i] = 0; /* clear table */ + } - for (i=0; i<SAVE_SZ; i++) {save[i] = 0;} /* clear table */ - - for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) - { + for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { addr = (volatile ulong *)base + cnt; save[i++] = *addr; *addr = ~cnt; @@ -67,19 +75,16 @@ long int initdram(int board_type) save[i] = *addr; *addr = 0; - if (*addr != 0) - { + if (*addr != 0) { *addr = save[i]; goto Done; } - for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) - { + for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) { addr = (volatile ulong *)base + cnt; val = *addr; *addr = save[--i]; - if (val != ~cnt) - { + if (val != ~cnt) { ulong new_bank0_end = cnt * sizeof(long) - 1; ulong mear1 = mpc824x_mpc107_getreg(MEAR1); ulong emear1 = mpc824x_mpc107_getreg(EMEAR1); @@ -111,11 +116,11 @@ Done: static struct pci_config_table pci_utx8245_config_table[] = { #ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID, pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, PCI_ENET0_MEMADDR, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID, pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR, PCI_FIREWIRE_MEMADDR, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, @@ -133,6 +138,14 @@ static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev) else if (PCI_DEV(dev) == 12) /* assign serial interrupt line 8 (int24) to Ethernet */ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24); + + else if (PCI_DEV(dev) == 14) + /* assign serial interrupt line 0 (int16) to PMC slot 0 */ + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16); + + else if (PCI_DEV(dev) == 15) + /* assign serial interrupt line 1 (int17) to PMC slot 1 */ + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17); } static struct pci_controller utx8245_hose = { |