diff options
Diffstat (limited to 'board')
307 files changed, 1966 insertions, 16313 deletions
diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c index a462941448..79608f4efe 100644 --- a/board/AndesTech/adp-ag101p/adp-ag101p.c +++ b/board/AndesTech/adp-ag101p/adp-ag101p.c @@ -11,6 +11,8 @@ #include <netdev.h> #endif #include <linux/io.h> +#include <asm/io.h> +#include <asm/mach-types.h> #include <faraday/ftsdc010.h> #include <faraday/ftsmc020.h> diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c index fd1965d9f5..3a584021ac 100644 --- a/board/Barix/ipam390/ipam390.c +++ b/board/Barix/ipam390/ipam390.c @@ -29,6 +29,7 @@ #include <asm/gpio.h> #include <hwconfig.h> #include <bootstage.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index b1ae079df4..e8c64018eb 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -687,7 +687,12 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_MMC) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(1, 0, 0, -1, -1); + int rc = 0; + + rc |= omap_mmc_init(0, 0, 0, -1, -1); + rc |= omap_mmc_init(1, 0, 0, -1, -1); + + return rc; } #endif int overwrite_console(void) diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index edf6281797..736d65caa1 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -14,6 +14,7 @@ #include "../common/common.h" #include <spl.h> #include <ns16550.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 263bb5426c..2e6e9ef916 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -12,6 +12,7 @@ #include <common.h> #include <command.h> #include <i2c.h> +#include <asm/mach-types.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <asm/arch/mpp.h> diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 17e629622f..16d694716f 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -11,6 +11,7 @@ #include <common.h> #include <command.h> +#include <asm/mach-types.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <asm/arch/mpp.h> diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c index 24ee6791a6..0ef63b7b7c 100644 --- a/board/Marvell/aspenite/aspenite.c +++ b/board/Marvell/aspenite/aspenite.c @@ -9,6 +9,7 @@ #include <common.h> #include <mvmfp.h> +#include <asm/mach-types.h> #include <asm/arch/cpu.h> #include <asm/arch/mfp.h> #include <asm/arch/armada100.h> diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c index 16040e19d7..05ce98bb61 100644 --- a/board/Marvell/gplugd/gplugd.c +++ b/board/Marvell/gplugd/gplugd.c @@ -19,6 +19,7 @@ #include <asm/arch/armada100.h> #include <asm/gpio.h> #include <miiphy.h> +#include <asm/mach-types.h> #ifdef CONFIG_ARMADA100_FEC #include <net.h> diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index b0d5f1e10f..af0c491632 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -8,6 +8,7 @@ #include <common.h> #include <miiphy.h> +#include <asm/mach-types.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <asm/arch/mpp.h> diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index 17a65600e4..f6cffc8cbb 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -13,6 +13,7 @@ #include <common.h> #include <miiphy.h> +#include <asm/mach-types.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <asm/arch/mpp.h> diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 8907fb58ff..c7dfaa276c 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -8,6 +8,7 @@ #include <common.h> #include <miiphy.h> +#include <asm/mach-types.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <asm/arch/mpp.h> diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index 83ab1bc32d..f444c1628d 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -15,6 +15,7 @@ #include <asm/arch/mpp.h> #include <asm/arch/cpu.h> #include <asm/io.h> +#include <asm/mach-types.h> #include "dockstar.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index 1f4fb92494..5d0a4242a8 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -14,6 +14,7 @@ #include <common.h> #include <miiphy.h> +#include <asm/mach-types.h> #include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/cpu.h> diff --git a/board/Seagate/nas220/nas220.c b/board/Seagate/nas220/nas220.c index c5349b900e..18c2895993 100644 --- a/board/Seagate/nas220/nas220.c +++ b/board/Seagate/nas220/nas220.c @@ -11,6 +11,7 @@ #include <common.h> #include <miiphy.h> +#include <asm/mach-types.h> #include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/arch/cpu.h> diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c index b46c09d648..0c2f5258e9 100644 --- a/board/Synology/ds109/ds109.c +++ b/board/Synology/ds109/ds109.c @@ -8,6 +8,7 @@ #include <common.h> #include <miiphy.h> +#include <asm/setup.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <asm/arch/mpp.h> diff --git a/board/a3m071/Kconfig b/board/a3m071/Kconfig deleted file mode 100644 index 444c450d8a..0000000000 --- a/board/a3m071/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_A3M071 - -config SYS_BOARD - default "a3m071" - -config SYS_CONFIG_NAME - default "a3m071" - -endif diff --git a/board/a3m071/MAINTAINERS b/board/a3m071/MAINTAINERS deleted file mode 100644 index 975107d2c0..0000000000 --- a/board/a3m071/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -A3M071 BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/a3m071/ -F: include/configs/a3m071.h -F: configs/a3m071_defconfig -F: configs/a4m2k_defconfig diff --git a/board/a3m071/README b/board/a3m071/README deleted file mode 100644 index 112c47b60d..0000000000 --- a/board/a3m071/README +++ /dev/null @@ -1,80 +0,0 @@ ------------------------------------------------------------------------- -A3M071 board support ------------------------------------------------------------------------- - - -SPL NOR flash support: ----------------------- -To boot fast into the OS (Linux), this board port integrates the SPL -framework. This means, that a special, stripped-down version of -U-Boot runs in the beginning. In the case of the A3M071 board, this -SPL U-Boot version is less than 16 KiB big. This SPL U-Boot can either -boot the OS (Linux) or a "real", full-blown U-Boot. This detection -on whether to boot Linux or U-Boot is done by using the "boot_os" -environment variable. If "boot_os" is set to "yes", Linux will be -loaded and booted from the SPL U-Boot version. Otherwise, the -full-blown U-Boot version will be loaded and run. - -Enabling Linux booting: ------------------------ -From U-Boot: -=> setenv boot_os yes -=> saveenv - -From Linux: -$ fw_setenv boot_os yes - -Enabling U-Boot booting: ------------------------- -From U-Boot: -=> setenv boot_os no -=> saveenv - -From Linux: -$ fw_setenv boot_os no - - -Preparing Linux image(s) for booting from SPL U-Boot: ------------------------------------------------------ -To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get -prepard/patched first. U-Boot usually inserts some dynamic values into -the DT binary (blob), e.g. autodetected memory size, MAC addresses, -clocks speeds etc. To generate this patched DT blob, you can use -the following command: - -1. Load fdt blob to SDRAM: -=> tftp 1800000 a3m071/a3m071.dtb - -2. Set bootargs as desired for Linux booting (e.g. flash_mtd): -=> run mtdargs addip2 addtty - -3. Use "fdt" commands to patch the DT blob: -=> fdt addr 1800000 -=> fdt boardsetup -=> fdt chosen - -4. Display patched DT blob (optional): -=> fdt print - -5. Save fdt to NOR flash: -=> erase fc180000 fc07ffff -=> cp.b 1800000 fc180000 10000 - -All this can be integrated into an environment command: -=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip addtty; \ - fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc180000 fc07ffff; \ - cp.b 1800000 fc180000 10000' -=> saveenv - -After this, only "run upd_fdt" needs to get called to load, patch -and save the DT blob into NOR flash. - -Additionally, the Linux kernel image has to be saved uncompressed in -its uImage file (and not gzip compressed). This can be done with this -command: - -$ mkimage -A ppc -O linux -T kernel -C none -a 0 -e 0 \ - -n "Linux Kernel Image" -d vmlinux.bin uImage.uncompressed - ------------------------------------------------------------------------- -Stefan Roese, 2012-08-23 diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c deleted file mode 100644 index 7e16aaf4b2..0000000000 --- a/board/a3m071/a3m071.c +++ /dev/null @@ -1,479 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2006 - * MicroSys GmbH - * - * Copyright 2012-2013 Stefan Roese <sr@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <miiphy.h> -#include <linux/compiler.h> -#include <asm/processor.h> -#include <asm/io.h> - -#ifdef CONFIG_A4M2K -#include "is46r16320d.h" -#else -#include "mt46v16m16-75.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_SYS_RAMBOOT) && \ - (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - long control = SDRAM_CONTROL | hi_addr_bit; - - /* unlock mode register */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000); - - /* precharge all banks */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); - -#ifdef SDRAM_DDR - /* set mode register: extended mode */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); - - /* set mode register: reset DLL */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); -#endif - - /* precharge all banks */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); - - /* auto refresh */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004); - - /* set mode register */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - - /* normal operation */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control); - - /* - * Wait a short while for the DLL to lock before accessing - * the SDRAM - */ - udelay(100); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if - * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. - */ -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; -#if !defined(CONFIG_SYS_RAMBOOT) && \ - (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) - ulong test1, test2; - - /* setup SDRAM chip selects */ - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */ - out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ - - /* setup config registers */ - out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - -#ifdef SDRAM_DDR - /* set tap delay */ - out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, - 0x13 + __builtin_ffs(dramsize >> 20) - 1); - } else { - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ - } -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF; - if (dramsize2 >= 0x13) - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - else - dramsize2 = 0; - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) - out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04); - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -static void get_revisions(int *failsavelevel, int *digiboardversion, - int *fpgaversion) -{ - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - u8 val; - - /* read digitalboard-version from TMR[2..4] */ - val = 0; - val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0; - val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0; - val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0; - *digiboardversion = val; - - /* - * A4M2K only supports digiboardversion. No failsavelevel and - * fpgaversion here. - */ -#if !defined(CONFIG_A4M2K) - /* - * Figure out failsavelevel - * see ticket dsvk#59 - */ - *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */ - - if (*digiboardversion == 0) { - *failsavelevel = 1; /* digiboard-version ok */ - - /* read fpga-version from TMR[5..7] */ - val = 0; - val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0; - val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0; - val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0; - *fpgaversion = val; - - if (*fpgaversion == 1) - *failsavelevel = 2; /* fpga-version ok */ - } -#endif -} - -/* - * This function is called from the SPL U-Boot version for - * early init stuff, that needs to be done for OS (e.g. Linux) - * booting. Doing it later in the real U-Boot would not work - * in case that the SPL U-Boot boots Linux directly. - */ -void spl_board_init(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; - -#if defined(CONFIG_A4M2K) - /* enable CS3 and CS5 (FPGA) */ - setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21)); -#else - int digiboardversion; - int failsavelevel; - int fpgaversion; - u32 val; - - get_revisions(&failsavelevel, &digiboardversion, &fpgaversion); - - val = in_be32(&mm->ipbi_ws_ctrl); - - /* first clear bits 19..21 (CS3...5) */ - val &= ~((1 << 19) | (1 << 20) | (1 << 21)); - if (failsavelevel == 2) { - /* FPGA ok */ - val |= (1 << 19) | (1 << 21); - } - - if (failsavelevel >= 1) { - /* at least digiboard-version ok */ - val |= (1 << 20); - } - - /* And write new value back to register */ - out_be32(&mm->ipbi_ws_ctrl, val); - - - /* Setup pin multiplexing */ - if (failsavelevel == 2) { - /* fpga-version ok */ -#if defined(CONFIG_SYS_GPS_PORT_CONFIG_2) - out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_2); -#endif - } else if (failsavelevel == 1) { - /* digiboard-version ok - fpga not */ -#if defined(CONFIG_SYS_GPS_PORT_CONFIG_1) - out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_1); -#endif - } else { - /* full failsave-mode */ -#if defined(CONFIG_SYS_GPS_PORT_CONFIG) - out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG); -#endif - } -#endif - - /* - * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see - * ticket #60 - * - * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT) - * set bit 0(msb) to 1 - */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN); - -#if defined(CONFIG_A4M2K) - /* Setup USB[x] as MPCDiag[0..3] GPIO outputs */ - - /* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */ - gpio->simple_ddr |= 1 << (31 - 15); - gpio->simple_ddr |= 1 << (31 - 14); - gpio->simple_ddr |= 1 << (31 - 13); - gpio->simple_ddr |= 1 << (31 - 12); - - /* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */ - gpio->simple_gpioe |= 1 << (31 - 15); - gpio->simple_gpioe |= 1 << (31 - 14); - gpio->simple_gpioe |= 1 << (31 - 13); - gpio->simple_gpioe |= 1 << (31 - 12); - - /* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */ - - /* set PSC2[0..2] (STSLED[0..2]) direction to output */ - gpio->simple_ddr |= 1 << (31 - 27); - gpio->simple_ddr |= 1 << (31 - 26); - gpio->simple_ddr |= 1 << (31 - 25); - - /* enable PSC2[0..2] (STSLED[0..2]) as GPIO */ - gpio->simple_gpioe |= 1 << (31 - 27); - gpio->simple_gpioe |= 1 << (31 - 26); - gpio->simple_gpioe |= 1 << (31 - 25); - - /* Setup PSC6[2] as MRST2 self reset GPIO output */ - - /* set PSC6[2]/IRDA_TX (MRST2) direction to output */ - gpio->simple_ddr |= 1 << (31 - 3); - - /* set PSC6[2]/IRDA_TX (MRST2) output as open drain */ - gpio->simple_ode |= 1 << (31 - 3); - - /* set PSC6[2]/IRDA_TX (MRST2) output as default high */ - gpio->simple_dvo |= 1 << (31 - 3); - - /* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */ - gpio->simple_gpioe |= 1 << (31 - 3); - - /* Setup PSC6[3] as HARNSSCD harness code GPIO input */ - - /* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */ - gpio->simple_ddr |= 0 << (31 - 2); - - /* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */ - gpio->simple_gpioe |= 1 << (31 - 2); -#else - /* setup GPIOs for status-leds if needed - see ticket #57 */ - if (failsavelevel > 0) { - /* digiboard-version is OK */ - /* LED is LOW ACTIVE - so deactivate by set output to 1 */ - gpio->simple_dvo |= 1 << (31 - 12); - gpio->simple_dvo |= 1 << (31 - 13); - /* set GPIO direction to output */ - gpio->simple_ddr |= 1 << (31 - 12); - gpio->simple_ddr |= 1 << (31 - 13); - /* open drain config is set to "normal output" at reset */ - /* gpio->simple_ode &=~ ( 1 << (31-12) ); */ - /* gpio->simple_ode &=~ ( 1 << (31-13) ); */ - /* enable as GPIO */ - gpio->simple_gpioe |= 1 << (31 - 12); - gpio->simple_gpioe |= 1 << (31 - 13); - } - - /* setup fpga irq - see ticket #65 */ - if (failsavelevel > 1) { - /* - * The main irq initialisation is done in interrupts.c - * mpc5xxx_init_irq - */ - struct mpc5xxx_intr *intr = - (struct mpc5xxx_intr *)(MPC5XXX_ICTL); - - setbits_be32(&intr->ctrl, 0x08C01801); - - /* - * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the - * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above - */ - } -#endif -} - -int checkboard(void) -{ - int digiboardversion; - int failsavelevel; - int fpgaversion; - - get_revisions(&failsavelevel, &digiboardversion, &fpgaversion); - -#ifdef CONFIG_A4M2K - puts("Board: A4M2K\n"); - printf(" digiboard IO version %u\n", digiboardversion); -#else - puts("Board: A3M071\n"); - printf("Rev: failsave level %u\n", failsavelevel); - printf(" digiboard IO version %u\n", digiboardversion); - if (failsavelevel > 0) /* only if fpga-version red */ - printf(" fpga IO version %u\n", fpgaversion); -#endif - - return 0; -} - -/* miscellaneous platform dependent initialisations */ -int misc_init_r(void) -{ - /* adjust flash start and offset to detected values */ - gd->bd->bi_flashstart = flash_info[0].start[0]; - gd->bd->bi_flashoffset = 0; - - /* adjust mapping */ - out_be32((void *)MPC5XXX_BOOTCS_START, - START_REG(gd->bd->bi_flashstart)); - out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart)); - out_be32((void *)MPC5XXX_BOOTCS_STOP, - STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize)); - out_be32((void *)MPC5XXX_CS0_STOP, - STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize)); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -#ifdef CONFIG_SPL_OS_BOOT -/* - * A3M071 specific implementation of spl_start_uboot() - * - * RETURN - * 0 if booting into OS is selected (default) - * 1 if booting into U-Boot is selected - */ -int spl_start_uboot(void) -{ - char s[8]; - - env_init(); - getenv_f("boot_os", s, sizeof(s)); - if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' || - *s == 't' || *s == 'T')) - return 0; - - return 1; -} -#endif - -#if defined(CONFIG_HW_WATCHDOG) -static int watchdog_toggle; - -void hw_watchdog_reset(void) -{ - int val; - - /* - * Check if watchdog is enabled via user command - */ - if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) { - /* Set direction to output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN); - - /* - * Toggle watchdog output - */ - val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) & - CONFIG_WDOG_GPIO_PIN); - if (val) { - clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, - CONFIG_WDOG_GPIO_PIN); - } else { - setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, - CONFIG_WDOG_GPIO_PIN); - } - } -} - -int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc != 2) - goto usage; - - if (strncmp(argv[1], "on", 2) == 0) - watchdog_toggle = 1; - else if (strncmp(argv[1], "off", 3) == 0) - watchdog_toggle = 0; - else - goto usage; - - return 0; -usage: - printf("Usage: wdogtoggle %s\n", cmdtp->usage); - return 1; -} - -U_BOOT_CMD( - wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle, - "toggle GPIO pin to service watchdog", - "[on/off] - Switch watchdog toggling via GPIO pin on/off" -); -#endif diff --git a/board/a3m071/is46r16320d.h b/board/a3m071/is46r16320d.h deleted file mode 100644 index 981359f22b..0000000000 --- a/board/a3m071/is46r16320d.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR /* is DDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */ - -/* SDRAM Config Standard timing */ -#define SDRAM_MODE 0x008d0000 -#define SDRAM_EMODE 0x40010000 -#define SDRAM_CONTROL 0x70430f00 -#define SDRAM_CONFIG1 0x33622930 -#define SDRAM_CONFIG2 0x46670000 -#define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/a3m071/mt46v16m16-75.h b/board/a3m071/mt46v16m16-75.h deleted file mode 100644 index 8f428306fe..0000000000 --- a/board/a3m071/mt46v16m16-75.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR /* is DDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x704f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/a4m072/Kconfig b/board/a4m072/Kconfig deleted file mode 100644 index ba5447fb9a..0000000000 --- a/board/a4m072/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_A4M072 - -config SYS_BOARD - default "a4m072" - -config SYS_CONFIG_NAME - default "a4m072" - -endif diff --git a/board/a4m072/MAINTAINERS b/board/a4m072/MAINTAINERS deleted file mode 100644 index 83dc59e87f..0000000000 --- a/board/a4m072/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -A4M072 BOARD -M: Sergei Poselenov <sposelenov@emcraft.com> -S: Maintained -F: board/a4m072/ -F: include/configs/a4m072.h -F: configs/a4m072_defconfig diff --git a/board/a4m072/Makefile b/board/a4m072/Makefile deleted file mode 100644 index 2a40e5799e..0000000000 --- a/board/a4m072/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := a4m072.o diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c deleted file mode 100644 index 6f0d4489a2..0000000000 --- a/board/a4m072/a4m072.c +++ /dev/null @@ -1,479 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2010 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <libfdt.h> -#include <netdev.h> -#include <led-display.h> -#include <linux/err.h> - -#include "mt46v32m16.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - long control = SDRAM_CONTROL | hi_addr_bit; - - /* unlock mode register */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000); - __asm__ volatile ("sync"); - - /* precharge all banks */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); - __asm__ volatile ("sync"); - - /* auto refresh */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004); - __asm__ volatile ("sync"); - - /* set mode register */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - __asm__ volatile ("sync"); - - /* normal operation */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control); - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - ulong dramsize = 0; - uint svr, pvr; - -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */ - out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY); - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, - 0x13 + __builtin_ffs(dramsize >> 20) - 1); - } else { - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04); - __asm__ volatile ("sync"); - } - - gd->ram_size = dramsize; - - return 0; -} - -int checkboard (void) -{ - puts ("Board: A4M072\n"); - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -int board_eth_init(bd_t *bis) -{ - int rv, num_if = 0; - - /* Initialize TSECs first */ - if ((rv = cpu_eth_init(bis)) >= 0) - num_if += rv; - else - printf("ERROR: failed to initialize FEC.\n"); - - if ((rv = pci_eth_init(bis)) >= 0) - num_if += rv; - else - printf("ERROR: failed to initialize PCI Ethernet.\n"); - - return num_if; -} -/* - * Miscellaneous late-boot configurations - * - * Initialize EEPROM write-protect GPIO pin. - */ -int misc_init_r(void) -{ -#if defined(CONFIG_SYS_EEPROM_WREN) - /* Enable GPIO pin */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP); - /* Set direction, output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP); - /* De-assert write enable */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); -#endif - return 0; -} -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: <dev_addr> I2C address of EEPROM device to enable. - * <state> -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if <state> was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) -{ - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access */ - clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) & - CONFIG_SYS_EEPROM_WP)); - break; - } - } - return state; -} -#endif - -#ifdef CONFIG_CMD_DISPLAY -#define DISPLAY_BUF_SIZE 2 -static u8 display_buf[DISPLAY_BUF_SIZE]; -static u8 display_putc_pos; -static u8 display_out_pos; - -void display_set(int cmd) { - - if (cmd & DISPLAY_CLEAR) { - display_buf[0] = display_buf[1] = 0; - } - - if (cmd & DISPLAY_HOME) { - display_putc_pos = 0; - } -} - -#define SEG_A (1<<0) -#define SEG_B (1<<1) -#define SEG_C (1<<2) -#define SEG_D (1<<3) -#define SEG_E (1<<4) -#define SEG_F (1<<5) -#define SEG_G (1<<6) -#define SEG_P (1<<7) -#define SEG__ 0 - -/* - * +- A -+ - * | | - * F B - * | | - * +- G -+ - * | | - * E C - * | | - * +- D -+ P - * - * 0..9 index 0..9 - * A..Z index 10..35 - * - index 36 - * _ index 37 - * . index 38 - */ - -#define SYMBOL_DASH (36) -#define SYMBOL_UNDERLINE (37) -#define SYMBOL_DOT (38) - -static u8 display_char2seg7_tbl[]= -{ - SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* 0 */ - SEG_B | SEG_C, /* 1 */ - SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* 2 */ - SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, /* 3 */ - SEG_B | SEG_C | SEG_F | SEG_G, /* 4 */ - SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* 5 */ - SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 6 */ - SEG_A | SEG_B | SEG_C, /* 7 */ - SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 8 */ - SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* 9 */ - SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* A */ - SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* b */ - SEG_A | SEG_D | SEG_E | SEG_F, /* C */ - SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */ - SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */ - SEG_A | SEG_E | SEG_F | SEG_G, /* F */ - 0, /* g - not displayed */ - SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */ - SEG_B | SEG_C, /* I */ - 0, /* J - not displayed */ - 0, /* K - not displayed */ - SEG_D | SEG_E | SEG_F, /* L */ - 0, /* m - not displayed */ - 0, /* n - not displayed */ - SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* O */ - SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */ - 0, /* q - not displayed */ - 0, /* r - not displayed */ - SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */ - SEG_D | SEG_E | SEG_F | SEG_G, /* t */ - SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */ - 0, /* V - not displayed */ - 0, /* w - not displayed */ - 0, /* X - not displayed */ - SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */ - 0, /* Z - not displayed */ - SEG_G, /* - */ - SEG_D, /* _ */ - SEG_P /* . */ -}; - -/* Convert char to the LED segments representation */ -static u8 display_char2seg7(char c) -{ - u8 val = 0; - - if (c >= '0' && c <= '9') - c -= '0'; - else if (c >= 'a' && c <= 'z') - c -= 'a' - 10; - else if (c >= 'A' && c <= 'Z') - c -= 'A' - 10; - else if (c == '-') - c = SYMBOL_DASH; - else if (c == '_') - c = SYMBOL_UNDERLINE; - else if (c == '.') - c = SYMBOL_DOT; - else - c = ' '; /* display unsupported symbols as space */ - - if (c != ' ') - val = display_char2seg7_tbl[(int)c]; - - return val; -} - -int display_putc(char c) -{ - if (display_putc_pos >= DISPLAY_BUF_SIZE) - return -1; - - display_buf[display_putc_pos++] = display_char2seg7(c); - /* one-symbol message should be steady */ - if (display_putc_pos == 1) - display_buf[display_putc_pos] = display_char2seg7(c); - - return c; -} - -/* - * Flush current symbol to the LED display hardware - */ -static inline void display_flush(void) -{ - u32 val = display_buf[display_out_pos]; - - val |= (val << 8) | (val << 16) | (val << 24); - out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val); -} - -/* - * Output contents of the software display buffer to the LED display every 0.5s - */ -void board_show_activity(ulong timestamp) -{ - static ulong last; - static u8 once; - - if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) { - display_flush(); - display_out_pos ^= 1; - last = timestamp; - once = 1; - } -} - -/* - * Empty fake function - */ -void show_activity(int arg) -{ -} -#endif -#if defined (CONFIG_SHOW_BOOT_PROGRESS) -static int a4m072_status2code(int status, char *buf) -{ - char c = 0; - - if (((status > 0) && (status <= 8)) || - ((status >= 100) && (status <= 108)) || - ((status < 0) && (status >= -9)) || - (status == -100) || (status == -101) || - ((status <= -103) && (status >= -113))) { - c = '5'; - } else if (((status >= 9) && (status <= 14)) || - ((status >= 120) && (status <= 123)) || - ((status >= 125) && (status <= 129)) || - ((status >= -13) && (status <= -10)) || - (status == -120) || (status == -122) || - ((status <= -124) && (status >= -127)) || - (status == -129)) { - c = '8'; - } else if (status == 15) { - c = '9'; - } else if ((status <= -30) && (status >= -32)) { - c = 'A'; - } else if (((status <= -35) && (status >= -40)) || - ((status <= -42) && (status >= -51)) || - ((status <= -53) && (status >= -58)) || - (status == -64) || - ((status <= -80) && (status >= -83)) || - (status == -130) || (status == -140) || - (status == -150)) { - c = 'B'; - } - - if (c == 0) - return -EINVAL; - - buf[0] = (status < 0) ? '-' : c; - buf[1] = c; - - return 0; -} - -void show_boot_progress(int status) -{ - char buf[2]; - - if (a4m072_status2code(status, buf) < 0) - return; - - display_putc(buf[0]); - display_putc(buf[1]); - display_set(DISPLAY_HOME); - display_out_pos = 0; /* reset output position */ - - /* we want to flush status 15 now */ - if (status == BOOTSTAGE_ID_RUN_OS) - display_flush(); -} -#endif diff --git a/board/a4m072/mt46v32m16.h b/board/a4m072/mt46v32m16.h deleted file mode 100644 index c0a08a8452..0000000000 --- a/board/a4m072/mt46v32m16.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40010000 -#define SDRAM_CONTROL 0x704f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/amazon/kc1/kc1.c b/board/amazon/kc1/kc1.c index b3fa7896c5..13a9c6a0fe 100644 --- a/board/amazon/kc1/kc1.c +++ b/board/amazon/kc1/kc1.c @@ -17,6 +17,7 @@ #include <asm/emif.h> #include <twl6030.h> #include "kc1.h" +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 6a50b393f4..9f642071cc 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -1880,7 +1880,7 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED) { mfsdr(SDR0_MFR, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;; + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN; mtsdr(SDR0_MFR, sdr0_mfr); } diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 774671db43..f98231a8da 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -161,7 +161,7 @@ static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ - while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */ + while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ; /* poll L2_SR for completion */ mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c index b61daaa4a7..9306b56a6a 100644 --- a/board/amlogic/odroid-c2/odroid-c2.c +++ b/board/amlogic/odroid-c2/odroid-c2.c @@ -5,10 +5,10 @@ */ #include <common.h> +#include <dm.h> #include <asm/io.h> #include <asm/arch/gxbb.h> #include <asm/arch/sm.h> -#include <dm/platdata.h> #include <phy.h> #define EFUSE_SN_OFFSET 20 diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index cbe706170d..c3bafd453e 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -18,12 +18,13 @@ */ #include <common.h> +#include <dm.h> #include <netdev.h> #include <asm/io.h> -#include <dm/platdata.h> #include <dm/platform_data/serial_pl01x.h> #include "arm-ebi.h" #include "integrator-sc.h" +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 458f1d8148..89ab8f7a59 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -21,6 +21,7 @@ #include <errno.h> #include <netdev.h> #include <asm/io.h> +#include <asm/mach-types.h> #include <asm/arch/systimer.h> #include <asm/arch/sysctrl.h> #include <asm/arch/wdt.h> diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 0a224178df..26e22c4c25 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -6,12 +6,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <dm.h> #include <malloc.h> #include <errno.h> #include <netdev.h> #include <asm/io.h> #include <linux/compiler.h> -#include <dm/platdata.h> #include <dm/platform_data/serial_pl01x.h> #include "pcie.h" #include <asm/armv8/mmu.h> diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c index 98d76a6fa7..36f147b44d 100644 --- a/board/atmel/at91rm9200ek/at91rm9200ek.c +++ b/board/atmel/at91rm9200ek/at91rm9200ek.c @@ -12,6 +12,7 @@ #include <common.h> #include <netdev.h> +#include <asm/mach-types.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pio.h> #include <asm/arch/at91_common.h> diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 6398bcbc9e..b4acb742b3 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -21,6 +21,7 @@ #include <net.h> #include <netdev.h> #endif +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 3de978311d..b37e9d3c7a 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -20,6 +20,7 @@ #include <asm/arch/hardware.h> #include <lcd.h> #include <atmel_lcdc.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index d3bc5c69d4..8e377593ef 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -18,6 +18,7 @@ #include <lcd.h> #include <linux/mtd/nand.h> #include <atmel_lcdc.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 0b603ed13a..7966269ff3 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -9,6 +9,7 @@ #include <common.h> #include <debug_uart.h> #include <asm/io.h> +#include <asm/mach-types.h> #include <asm/arch/at91sam9rl.h> #include <asm/arch/at91sam9rl_matrix.h> #include <asm/arch/at91sam9_smc.h> diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 81c2aad1a5..1e4a4a2acf 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -19,6 +19,7 @@ #include <nand.h> #include <version.h> #endif +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c index c5d55dc68f..e903bc1807 100644 --- a/board/beckhoff/mx53cx9020/mx53cx9020.c +++ b/board/beckhoff/mx53cx9020/mx53cx9020.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <dm.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> @@ -26,7 +27,6 @@ #include <linux/fb.h> #include <ipu_pixfmt.h> #include <fs.h> -#include <dm/platdata.h> #include <dm/platform_data/serial_mxc.h> enum LED_GPIOS { diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c index 08e79bd7ac..2215c29c9c 100644 --- a/board/bluegiga/apx4devkit/apx4devkit.c +++ b/board/bluegiga/apx4devkit/apx4devkit.c @@ -17,6 +17,7 @@ #include <common.h> #include <asm/gpio.h> #include <asm/io.h> +#include <asm/setup.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux-mx28.h> #include <asm/arch/clock.h> diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c index 08b1401372..e82c691841 100644 --- a/board/bluewater/gurnard/gurnard.c +++ b/board/bluewater/gurnard/gurnard.c @@ -21,6 +21,7 @@ #include <spi.h> #include <asm/gpio.h> #include <asm/io.h> +#include <asm/mach-types.h> #include <asm/arch/at91sam9g45_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c index 2d1a89e102..7e9da4e7b7 100644 --- a/board/bluewater/snapper9260/snapper9260.c +++ b/board/bluewater/snapper9260/snapper9260.c @@ -12,6 +12,7 @@ #include <dm.h> #include <asm/io.h> #include <asm/gpio.h> +#include <asm/mach-types.h> #include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c index 39b9b12567..0265e9bb36 100644 --- a/board/cadence/xtfpga/xtfpga.c +++ b/board/cadence/xtfpga/xtfpga.c @@ -7,7 +7,7 @@ #include <common.h> #include <command.h> -#include <dm/platdata.h> +#include <dm.h> #include <dm/platform_data/net_ethoc.h> #include <linux/ctype.h> #include <linux/string.h> diff --git a/board/canmb/Kconfig b/board/canmb/Kconfig deleted file mode 100644 index b5cf2057f4..0000000000 --- a/board/canmb/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_CANMB - -config SYS_BOARD - default "canmb" - -config SYS_CONFIG_NAME - default "canmb" - -endif diff --git a/board/canmb/MAINTAINERS b/board/canmb/MAINTAINERS deleted file mode 100644 index 71750ead47..0000000000 --- a/board/canmb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CANMB BOARD -#M: - -S: Maintained -F: board/canmb/ -F: include/configs/canmb.h -F: configs/canmb_defconfig diff --git a/board/canmb/Makefile b/board/canmb/Makefile deleted file mode 100644 index 4286a9123c..0000000000 --- a/board/canmb/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2005-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := canmb.o - diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c deleted file mode 100644 index 54de0e2673..0000000000 --- a/board/canmb/canmb.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> - -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -#include "mt48lc16m32s2-75.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -int checkboard (void) -{ - puts ("Board: CANMB\n"); - return 0; -} - -int board_early_init_r (void) -{ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - *(vu_long *)MPC5XXX_BOOTCS_START = - *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE); - *(vu_long *)MPC5XXX_BOOTCS_STOP = - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE); - return 0; -} diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/canmb/mt48lc16m32s2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index 960ca53b02..02253af5d9 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -5,6 +5,7 @@ **/ #include <common.h> +#include <dm.h> #include <malloc.h> #include <errno.h> #include <linux/compiler.h> @@ -13,7 +14,6 @@ #include <asm/armv8/mmu.h> #if !CONFIG_IS_ENABLED(OF_CONTROL) -#include <dm/platdata.h> #include <dm/platform_data/serial_pl01x.h> static const struct pl01x_serial_platdata serial0 = { diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c index 720b490f2b..02e2896fa7 100644 --- a/board/cirrus/edb93xx/edb93xx.c +++ b/board/cirrus/edb93xx/edb93xx.c @@ -18,6 +18,7 @@ #include <common.h> #include <netdev.h> #include <asm/io.h> +#include <asm/mach-types.h> #include <asm/arch/ep93xx.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/cm5200/Kconfig b/board/cm5200/Kconfig deleted file mode 100644 index ccea5c96e4..0000000000 --- a/board/cm5200/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_CM5200 - -config SYS_BOARD - default "cm5200" - -config SYS_CONFIG_NAME - default "cm5200" - -endif diff --git a/board/cm5200/MAINTAINERS b/board/cm5200/MAINTAINERS deleted file mode 100644 index 1e1df3f6dc..0000000000 --- a/board/cm5200/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CM5200 BOARD -#M: - -S: Maintained -F: board/cm5200/ -F: include/configs/cm5200.h -F: configs/cm5200_defconfig diff --git a/board/cm5200/Makefile b/board/cm5200/Makefile deleted file mode 100644 index 76f8b9fc05..0000000000 --- a/board/cm5200/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := cm5200.o cmd_cm5200.o fwupdate.o diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c deleted file mode 100644 index 0c647bbd3d..0000000000 --- a/board/cm5200/cm5200.c +++ /dev/null @@ -1,355 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * Adapted to U-Boot 1.2 by: - * Bartlomiej Sieka <tur@semihalf.com>: - * - HW ID readout from EEPROM - * - module detection - * Grzegorz Bernacki <gjb@semihalf.com>: - * - run-time SDRAM controller configuration - * - LIBFDT support - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <asm/processor.h> -#include <i2c.h> -#include <linux/ctype.h> - -#ifdef CONFIG_OF_LIBFDT -#include <libfdt.h> -#include <fdt_support.h> -#endif /* CONFIG_OF_LIBFDT */ - - -#include "cm5200.h" -#include "fwupdate.h" - -DECLARE_GLOBAL_DATA_PTR; - -static hw_id_t hw_id; - - -#ifndef CONFIG_SYS_RAMBOOT -/* - * Helper function to initialize SDRAM controller. - */ -static void sdram_start(int hi_addr, mem_conf_t *mem_conf) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 | - hi_addr_bit; - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 | - hi_addr_bit; - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 | - hi_addr_bit; - - /* auto refresh, second time */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 | - hi_addr_bit; - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode; - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit; -} -#endif /* CONFIG_SYS_RAMBOOT */ - - -/* - * Retrieve memory configuration for a given module. board_type is the index - * in hw_id_list[] corresponding to the module we are executing on; we return - * SDRAM controller settings approprate for this module. - */ -static mem_conf_t* get_mem_config(int board_type) -{ - switch(board_type){ - case CM1_QA: - return memory_config[0]; - case CM11_QA: - case CMU1_QA: - return memory_config[1]; - default: - printf("ERROR: Unknown module, using a default SDRAM " - "configuration - things may not work!!!.\n"); - return memory_config[0]; - } -} - - -/* - * Initalize SDRAM - configure SDRAM controller, detect memory size. - */ -int dram_init(void) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - mem_conf_t *mem_conf; - - mem_conf = get_mem_config(gd->board_type); - - /* configure SDRAM start/end for detection */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2; - - sdram_start(0, mem_conf); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1, mem_conf); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0, mem_conf); - dramsize = test1; - } else - dramsize = test2; - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ -#else /* CONFIG_SYS_RAMBOOT */ - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; -#endif /* !CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of - * the MPC5200B User's Manual. - */ - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - - gd->ram_size = dramsize; - - return 0; -} - - -/* - * Read module hardware identification data from the I2C EEPROM. - */ -static void read_hw_id(hw_id_t hw_id) -{ - printf("ERROR: can't read HW ID from EEPROM\n"); -} - - -/* - * Identify module we are running on, set gd->board_type to the index in - * hw_id_list[] corresponding to the module identifed, or to - * CM5200_UNKNOWN_MODULE if we can't identify the module. - */ -static void identify_module(hw_id_t hw_id) -{ - int i, j, element; - char match; - gd->board_type = CM5200_UNKNOWN_MODULE; - for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) { - match = 1; - for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) { - element = hw_id_identify[j]; - if (strncmp(hw_id_list[i][element], - &hw_id[element][0], - hw_id_format[element].length) != 0) { - match = 0; - break; - } - } - if (match) { - gd->board_type = i; - break; - } - } -} - - -/* - * Compose string with module name. - * buf is assumed to have enough space, and be null-terminated. - */ -static void compose_module_name(hw_id_t hw_id, char *buf) -{ - char tmp[MODULE_NAME_MAXLEN]; - strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length); - strncat(buf, ".", 1); - strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length); - strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length); - strncat(buf, " (", 2); - strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0], - hw_id_format[IDENTIFICATION_NUMBER].length); - sprintf(tmp, " / %u.%u)", - hw_id[MAJOR_SW_VERSION][0], - hw_id[MINOR_SW_VERSION][0]); - strcat(buf, tmp); -} - -#if defined(CONFIG_SYS_I2C_SOFT) -/* - * Compose string with hostname. - * buf is assumed to have enough space, and be null-terminated. - */ -static void compose_hostname(hw_id_t hw_id, char *buf) -{ - char *p; - strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length); - strncat(buf, "_", 1); - strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length); - strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length); - for (p = buf; *p; ++p) - *p = tolower(*p); - -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -/* - * Update 'model' and 'memory' properties in the blob according to the module - * that we are running on. - */ -static void ft_blob_update(void *blob, bd_t *bd) -{ - int len, ret, nodeoffset = 0; - char module_name[MODULE_NAME_MAXLEN] = {0}; - - compose_module_name(hw_id, module_name); - len = strlen(module_name) + 1; - - ret = fdt_setprop(blob, nodeoffset, "model", module_name, len); - if (ret < 0) - printf("ft_blob_update(): cannot set /model property err:%s\n", - fdt_strerror(ret)); -} -#endif /* CONFIG_OF_BOARD_SETUP */ - - -/* - * Read HW ID from I2C EEPROM and detect the modue we are running on. Note - * that we need to use local variable for readout, because global data is not - * writable yet (and we'll have to redo the readout later on). - */ -int checkboard(void) -{ - hw_id_t hw_id_tmp; - char module_name_tmp[MODULE_NAME_MAXLEN] = ""; - - read_hw_id(hw_id_tmp); - identify_module(hw_id_tmp); /* this sets gd->board_type */ - compose_module_name(hw_id_tmp, module_name_tmp); - - if (gd->board_type != CM5200_UNKNOWN_MODULE) - printf("Board: %s\n", module_name_tmp); - else - printf("Board: unrecognized cm5200 module (%s)\n", - module_name_tmp); - - return 0; -} - - -int board_early_init_r(void) -{ - /* - * Now, when we are in RAM, enable flash write access for detection - * process. Note that CS_BOOT cannot be cleared when executing in - * flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - - /* Now that we can write to global data, read HW ID again. */ - read_hw_id(hw_id); - return 0; -} - - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ -#if defined(CONFIG_SYS_I2C_SOFT) - uchar buf[6]; - char str[18]; - char hostname[MODULE_NAME_MAXLEN]; - - /* Read ethaddr from EEPROM */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) { - sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", - buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); - /* Check if MAC addr is owned by Schindler */ - if (strstr(str, "00:06:C3") != str) - printf(LOG_PREFIX "Warning - Illegal MAC address (%s)" - " in EEPROM.\n", str); - else { - printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n", - str); - setenv("ethaddr", str); - } - } else { - printf(LOG_PREFIX "Warning - Unable to read MAC from I2C" - " device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM, - CONFIG_MAC_OFFSET); - } - hostname[0] = 0x00; - /* set the hostname appropriate to the module we're running on */ - compose_hostname(hw_id, hostname); - setenv("hostname", hostname); - -#endif /* defined(CONFIG_SYS_I2C_SOFT) */ - if (!getenv("ethaddr")) - printf(LOG_PREFIX "MAC address not set, networking is not " - "operational\n"); - - return 0; -} -#endif /* CONFIG_MISC_INIT_R */ - - -#ifdef CONFIG_LAST_STAGE_INIT -int last_stage_init(void) -{ -#ifdef CONFIG_USB_STORAGE - cm5200_fwupdate(); -#endif /* CONFIG_USB_STORAGE */ - return 0; -} -#endif /* CONFIG_LAST_STAGE_INIT */ - - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - ft_blob_update(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h deleted file mode 100644 index c2573f3bf6..0000000000 --- a/board/cm5200/cm5200.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2007 DENX Software Engineering - * - * Author: Bartlomiej Sieka <tur@semihalf.com> - * Author: Grzegorz Bernacki <gjb@semihalf.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CM5200_H -#define _CM5200_H - - -/* - * Definitions and declarations for the modules of the cm5200 platform. Mostly - * related to reading the hardware identification data (HW ID) from the I2C - * EEPROM, detection of the particular module we are executing on, and - * appropriate SDRAM controller initialization. - */ - - -#define CM5200_UNKNOWN_MODULE 0xffffffff - -enum { - DEVICE_NAME, /* 0 */ - GENERATION, /* 1 */ - PCB_NAME, /* 2 */ - FORM, /* 3 */ - VERSION, /* 4 */ - IDENTIFICATION_NUMBER, /* 5 */ - MAJOR_SW_VERSION, /* 6 */ - MINOR_SW_VERSION, /* 7 */ - /* add new alements above this line */ - HW_ID_ELEM_COUNT /* count */ -}; - -/* - * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition" - */ - -#define DEVICE_NAME_OFFSET 0x02 -#define GENERATION_OFFSET 0x0b -#define PCB_NAME_OFFSET 0x0c -#define FORM_OFFSET 0x15 -#define VERSION_OFFSET 0x16 -#define IDENTIFICATION_NUMBER_OFFSET 0x19 -#define MAJOR_SW_VERSION_OFFSET 0x0480 -#define MINOR_SW_VERSION_OFFSET 0x0481 - - -#define DEVICE_NAME_LEN 0x09 -#define GENERATION_LEN 0x01 -#define PCB_NAME_LEN 0x09 -#define FORM_LEN 0x01 -#define VERSION_LEN 0x03 -#define IDENTIFICATION_NUMBER_LEN 0x09 -#define MAJOR_SW_VERSION_LEN 0x01 -#define MINOR_SW_VERSION_LEN 0x01 - -#define HW_ID_ELEM_MAXLEN 0x09 /* MAX(XXX_LEN) */ - -/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */ -#define MODULE_NAME_MAXLEN 64 - - -/* storage for HW ID read from EEPROM */ -typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN]; - - -/* HW ID layout in EEPROM */ -static struct { - unsigned int offset; - unsigned int length; -} hw_id_format[HW_ID_ELEM_COUNT] = { - {DEVICE_NAME_OFFSET, DEVICE_NAME_LEN}, - {GENERATION_OFFSET, GENERATION_LEN}, - {PCB_NAME_OFFSET, PCB_NAME_LEN}, - {FORM_OFFSET, FORM_LEN}, - {VERSION_OFFSET, VERSION_LEN}, - {IDENTIFICATION_NUMBER_OFFSET, IDENTIFICATION_NUMBER_LEN}, - {MAJOR_SW_VERSION_OFFSET, MAJOR_SW_VERSION_LEN}, - {MINOR_SW_VERSION_OFFSET, MINOR_SW_VERSION_LEN}, -}; - - -/* HW ID data found in EEPROM on supported modules */ -static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = { - "CM", /* DEVICE_NAME */ - "1", /* GENERATION */ - "CM1", /* PCB_NAME */ - "Q", /* FORM */ - "A", /* VERSION */ - "591881", /* IDENTIFICATION_NUMBER */ - "", /* MAJOR_SW_VERSION */ - "", /* MINOR_SW_VERSION */ -}; - -static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = { - "CM", /* DEVICE_NAME */ - "1", /* GENERATION */ - "CM11", /* PCB_NAME */ - "Q", /* FORM */ - "A", /* VERSION */ - "594200", /* IDENTIFICATION_NUMBER */ - "", /* MAJOR_SW_VERSION */ - "", /* MINOR_SW_VERSION */ -}; - -static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = { - "CMU", /* DEVICE_NAME */ - "1", /* GENERATION */ - "CMU1", /* PCB_NAME */ - "Q", /* FORM */ - "A", /* VERSION */ - "594128", /* IDENTIFICATION_NUMBER */ - "", /* MAJOR_SW_VERSION */ - "", /* MINOR_SW_VERSION */ -}; - - -/* list of known modules */ -static char **hw_id_list[] = { - cm1_qa_hw_id, - cm11_qa_hw_id, - cmu1_qa_hw_id, -}; - -/* indices to the above list - keep in sync */ -enum { - CM1_QA, - CM11_QA, - CMU1_QA, -}; - - -/* identify modules based on these hw id elements */ -static int hw_id_identify[] = { - PCB_NAME, - FORM, - VERSION, -}; - - -/* Registers' settings for SDRAM controller intialization */ -typedef struct { - ulong mode; - ulong control; - ulong config1; - ulong config2; -} mem_conf_t; - -static mem_conf_t k4s561632E = { - 0x00CD0000, /* CASL 3, burst length 8 */ - 0x514F0000, - 0xE2333900, - 0x8EE70000 -}; - -static mem_conf_t mt48lc32m16a2 = { - 0x00CD0000, /* CASL 3, burst length 8 */ - 0x514F0000, - 0xD2322800, - 0x8AD70000 -}; - -static mem_conf_t* memory_config[] = { - &k4s561632E, - &mt48lc32m16a2 -}; - -#endif /* _CM5200_H */ diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c deleted file mode 100644 index 60097dc8c7..0000000000 --- a/board/cm5200/cmd_cm5200.c +++ /dev/null @@ -1,402 +0,0 @@ -/* - * (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com> - * - * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <i2c.h> -#include <usb.h> - -#ifdef CONFIG_CMD_BSP - -static int do_usb_test(char * const argv[]) -{ - int i; - static int usb_stor_curr_dev = -1; /* current device */ - - printf("Starting USB Test\n" - "Please insert USB Memmory Stick\n\n" - "Please press any key to start\n\n"); - getc(); - - usb_stop(); - printf("(Re)start USB...\n"); - i = usb_init(); -#ifdef CONFIG_USB_STORAGE - /* try to recognize storage devices immediately */ - if (i >= 0) - usb_stor_curr_dev = usb_stor_scan(1); -#endif /* CONFIG_USB_STORAGE */ - if (usb_stor_curr_dev >= 0) - printf("Found USB Storage Dev continue with Test...\n"); - else { - printf("No USB Storage Device detected.. Stop Test\n"); - return 1; - } - - usb_stor_info(); - - printf("stopping USB..\n"); - usb_stop(); - - return 0; -} - -static int do_led_test(char * const argv[]) -{ - int i = 0; - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - printf("Starting LED Test\n" - "Please set Switch S500 all off\n\n" - "Please press any key to start\n\n"); - getc(); - - /* configure timer 2-3 for simple GPIO output High */ - gpt->gpt2.emsr |= 0x00000034; - gpt->gpt3.emsr |= 0x00000034; - - (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000; - (*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000; - printf("Please press any key to stop\n\n"); - while (!tstc()) { - if (i == 1) { - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; - gpt->gpt2.emsr &= ~0x00000010; - gpt->gpt3.emsr &= ~0x00000010; - } else if (i == 2) { - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; - gpt->gpt2.emsr &= ~0x00000010; - gpt->gpt3.emsr |= 0x00000010; - } else if (i >= 3) { - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; - gpt->gpt3.emsr &= ~0x00000010; - gpt->gpt2.emsr |= 0x00000010; - i = 0; - } - i++; - udelay(200000); - } - getc(); - - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; - gpt->gpt2.emsr |= 0x00000010; - gpt->gpt3.emsr |= 0x00000010; - - return 0; -} - -static int do_rs232_test(char * const argv[]) -{ - int error_status = 0; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; - - /* Configure PSC 2-3-6 as GPIO */ - gpio->port_config &= 0xFF0FF80F; - - switch (simple_strtoul(argv[2], NULL, 10)) { - case 1: - /* check RTS <-> CTS loop */ - /* set rts to 0 */ - printf("Uart 1 test: RX TX tested by using U-Boot\n" - "Please connect RTS with CTS on Uart1 plug\n\n" - "Press any key to start\n\n"); - getc(); - - psc1->op1 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 0) { - error_status = 3; - printf("%s: failure at rs232_1, cts status is %d " - "(should be 0)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - - /* set rts to 1 */ - psc1->op0 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 1) { - error_status = 3; - printf("%s: failure at rs232_1, cts status is %d " - "(should be 1)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - break; - case 2: - /* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */ - printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n" - "\nPress any key to start\n\n"); - getc(); - - gpio->simple_gpioe &= ~(0x000000F0); - gpio->simple_gpioe |= 0x000000F0; - gpio->simple_ddr &= ~(0x000000F0); - gpio->simple_ddr |= 0x00000050; - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 4); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000020) != 0x00000020) { - error_status = 2; - printf("%s: failure at rs232_2, rxd status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000020) >> 5); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 4); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000020) != 0x00000000) { - error_status = 2; - printf("%s: failure at rs232_2, rxd status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000020) >> 5); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 6); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000080) != 0x00000080) { - error_status = 3; - printf("%s: failure at rs232_2, cts status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000080) >> 7); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 6); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000080) != 0x00000000) { - error_status = 3; - printf("%s: failure at rs232_2, cts status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000080) >> 7); - } - break; - case 3: - /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ - printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n" - "\nPress any key to start\n\n"); - getc(); - - gpio->simple_gpioe &= ~(0x00000F00); - gpio->simple_gpioe |= 0x00000F00; - - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000500; - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000200) { - error_status = 2; - printf("%s: failure at rs232_3, rxd status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000000) { - error_status = 2; - printf("%s: failure at rs232_3, rxd status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000800) { - error_status = 3; - printf("%s: failure at rs232_3, cts status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000000) { - error_status = 3; - printf("%s: failure at rs232_3, cts status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - break; - case 4: - /* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */ - printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n" - "\nPress any key to start\n\n"); - getc(); - - gpio->simple_gpioe &= ~(0xF0000000); - gpio->simple_gpioe |= 0x30000000; - - gpio->simple_ddr &= ~(0xf0000000); - gpio->simple_ddr |= 0x30000000; - - (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000; - (*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000); - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 28); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != - 0x10000000) { - error_status = 2; - printf("%s: failure at rs232_4, rxd status is %lu " - "(should be 1)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x10000000) >> 28); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 28); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != - 0x00000000) { - error_status = 2; - printf("%s: failure at rs232_4, rxd status is %lu " - "(should be 0)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x10000000) >> 28); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 29); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != - 0x20000000) { - error_status = 3; - printf("%s: failure at rs232_4, cts status is %lu " - "(should be 1)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x20000000) >> 29); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 29); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != - 0x00000000) { - error_status = 3; - printf("%s: failure at rs232_4, cts status is %lu " - "(should be 0)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x20000000) >> 29); - } - break; - default: - printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); - error_status = 1; - break; - } - gpio->port_config |= (CONFIG_SYS_GPS_PORT_CONFIG & 0xFF0FF80F); - - return error_status; -} - -static int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int rcode = -1; - - switch (argc) { - case 2: - if (strncmp(argv[1], "led", 3) == 0) - rcode = do_led_test(argv); - else if (strncmp(argv[1], "usb", 3) == 0) - rcode = do_usb_test(argv); - break; - case 3: - if (strncmp(argv[1], "rs232", 3) == 0) - rcode = do_rs232_test(argv); - break; - } - - switch (rcode) { - case -1: - printf("Usage:\n" - "fkt { i2c | led | usb }\n" - "fkt rs232 number\n"); - rcode = 1; - break; - case 0: - printf("Test passed\n"); - break; - default: - printf("Test failed with code: %d\n", rcode); - } - - return rcode; -} - -U_BOOT_CMD( - fkt, 4, 1, cmd_fkt, - "Function test routines", - "i2c\n" - " - Test I2C communication\n" - "fkt led\n" - " - Test LEDs\n" - "fkt rs232 number\n" - " - Test RS232 (loopback plug(s) for RS232 required)\n" - "fkt usb\n" - " - Test USB communication" -); -#endif /* CONFIG_CMD_BSP */ diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c deleted file mode 100644 index 4740c8394c..0000000000 --- a/board/cm5200/fwupdate.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (C) Copyright 2007 Schindler Lift Inc. - * (C) Copyright 2007 DENX Software Engineering - * - * Author: Michel Marti <mma@objectxp.com> - * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>: - * - code clean-up - * - bugfix for overwriting bootargs by user - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <fat.h> -#include <malloc.h> -#include <image.h> -#include <usb.h> -#include <fat.h> - -#include "fwupdate.h" - -static int load_rescue_image(ulong); - -void cm5200_fwupdate(void) -{ - cmd_tbl_t *bcmd; - char *rsargs; - char *tmp = NULL; - char ka[16]; - char * const argv[3] = { "bootm", ka, NULL }; - - /* Check if rescue system is disabled... */ - if (getenv("norescue")) { - printf(LOG_PREFIX "Rescue System disabled.\n"); - return; - } - - /* Check if we have a USB storage device and load image */ - if (load_rescue_image(LOAD_ADDR)) - return; - - bcmd = find_cmd("bootm"); - if (!bcmd) - return; - - sprintf(ka, "%lx", (ulong)LOAD_ADDR); - - /* prepare our bootargs */ - rsargs = getenv("rs-args"); - if (!rsargs) - rsargs = RS_BOOTARGS; - else { - tmp = malloc(strlen(rsargs+1)); - if (!tmp) { - printf(LOG_PREFIX "Memory allocation failed\n"); - return; - } - strcpy(tmp, rsargs); - rsargs = tmp; - } - - setenv("bootargs", rsargs); - - if (rsargs == tmp) - free(rsargs); - - printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs); - do_bootm(bcmd, 0, 2, argv); -} - -static int load_rescue_image(ulong addr) -{ - disk_partition_t info; - int devno; - int partno; - int i; - char fwdir[64]; - char nxri[128]; - char *tmp; - char dev[7]; - char addr_str[16]; - char * const argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL }; - struct blk_desc *stor_dev = NULL; - cmd_tbl_t *bcmd; - - /* Get name of firmware directory */ - tmp = getenv("fw-dir"); - - /* Copy it into fwdir */ - strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir)); - fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */ - - printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB" - " storage...\n", fwdir); - usb_stop(); - if (usb_init() != 0) - return 1; - - /* Check for storage device */ - if (usb_stor_scan(1) != 0) { - usb_stop(); - return 1; - } - - /* Detect storage device */ - for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) { - stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno); - if (stor_dev->type != DEV_TYPE_UNKNOWN) - break; - } - if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) { - printf(LOG_PREFIX "No valid storage device found...\n"); - usb_stop(); - return 1; - } - - /* Detect partition */ - for (partno = -1, i = 0; i < 6; i++) { - if (part_get_info(stor_dev, i, &info) == 0) { - if (fat_register_device(stor_dev, i) == 0) { - /* Check if rescue image is present */ - FW_DEBUG("Looking for firmware directory '%s'" - " on partition %d\n", fwdir, i); - if (!fat_exists(fwdir)) { - FW_DEBUG("No NX rescue image on " - "partition %d.\n", i); - partno = -2; - } else { - partno = i; - FW_DEBUG("Partition %d contains " - "firmware directory\n", partno); - break; - } - } - } - } - - if (partno < 0) { - switch (partno) { - case -1: - printf(LOG_PREFIX "Error: No valid (FAT) partition " - "detected\n"); - break; - case -2: - printf(LOG_PREFIX "Error: No NX rescue image on FAT " - "partition\n"); - break; - default: - printf(LOG_PREFIX "Error: Failed with code %d\n", - partno); - } - usb_stop(); - return 1; - } - - /* Load the rescue image */ - bcmd = find_cmd("fatload"); - if (!bcmd) { - printf(LOG_PREFIX "Error - 'fatload' command not present.\n"); - usb_stop(); - return 1; - } - - tmp = getenv("nx-rescue-image"); - sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE); - sprintf(dev, "%d:%d", devno, partno); - sprintf(addr_str, "%lx", addr); - - FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n", - dev, addr_str, nxri); - - if (do_fat_fsload(bcmd, 0, 5, argv) != 0) { - usb_stop(); - return 1; - } - - /* Stop USB */ - usb_stop(); - return 0; -} diff --git a/board/cm5200/fwupdate.h b/board/cm5200/fwupdate.h deleted file mode 100644 index 6ddf0bac35..0000000000 --- a/board/cm5200/fwupdate.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2007 Schindler Lift Inc. - * - * Author: Michel Marti <mma@objectxp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FW_UPDATE_H -#define __FW_UPDATE_H - -/* Default prefix for output messages */ -#define LOG_PREFIX "CM5200:" - -/* Extra debug macro */ -#ifdef CONFIG_FWUPDATE_DEBUG -#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt) -#else -#define FW_DEBUG(fmt...) -#endif - -/* Name of the directory holding firmware images */ -#define FW_DIR "nx-fw" -#define RESCUE_IMAGE "nxrs.img" -#define LOAD_ADDR 0x400000 -#define RS_BOOTARGS "ramdisk_size=8192K" - -/* Main function for fwupdate */ -void cm5200_fwupdate(void); - -#endif /* __FW_UPDATE_H */ diff --git a/board/compulab/cl-som-am57x/spl.c b/board/compulab/cl-som-am57x/spl.c index 855678fd5f..de2dadc517 100644 --- a/board/compulab/cl-som-am57x/spl.c +++ b/board/compulab/cl-som-am57x/spl.c @@ -19,7 +19,12 @@ static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = { void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { + /* Disable SDRAM controller EMIF2 for single core SOC */ *dmm_lisa_regs = &cl_som_am57x_lisa_regs; + if (omap_revision() == DRA722_ES1_0) { + ((struct dmm_lisa_map_regs *) *dmm_lisa_regs)->dmm_lisa_map_3 = + 0x80640100; + } } static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = { diff --git a/board/compulab/common/common.c b/board/compulab/common/common.c index b25d9a20b4..bf2ac7bd7f 100644 --- a/board/compulab/common/common.c +++ b/board/compulab/common/common.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/bootm.h> #include <asm/gpio.h> +#include <asm/setup.h> #include "common.h" #include "eeprom.h" diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index b5f1aa61cb..bb4c9e9740 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -11,6 +11,7 @@ #include <i2c.h> #include <eeprom_layout.h> #include <eeprom_field.h> +#include <asm/setup.h> #include <linux/kernel.h> #include "eeprom.h" diff --git a/board/comtrend/ct5361/Kconfig b/board/comtrend/ct5361/Kconfig new file mode 100644 index 0000000000..d77d814db7 --- /dev/null +++ b/board/comtrend/ct5361/Kconfig @@ -0,0 +1,12 @@ +if BOARD_COMTREND_CT5361 + +config SYS_BOARD + default "ct5361" + +config SYS_VENDOR + default "comtrend" + +config SYS_CONFIG_NAME + default "comtrend_ct5361" + +endif diff --git a/board/comtrend/ct5361/MAINTAINERS b/board/comtrend/ct5361/MAINTAINERS new file mode 100644 index 0000000000..aea737a0bb --- /dev/null +++ b/board/comtrend/ct5361/MAINTAINERS @@ -0,0 +1,6 @@ +COMTREND CT-5361 BOARD +M: Álvaro Fernández Rojas <noltari@gmail.com> +S: Maintained +F: board/comtrend/ct-5361/ +F: include/configs/comtrend_ct5361.h +F: configs/comtrend_ct5361_ram_defconfig diff --git a/board/a3m071/Makefile b/board/comtrend/ct5361/Makefile index 4e31e33936..872e80a0c1 100644 --- a/board/a3m071/Makefile +++ b/board/comtrend/ct5361/Makefile @@ -2,4 +2,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := a3m071.o +obj-y += ct-5361.o diff --git a/board/comtrend/ct5361/ct-5361.c b/board/comtrend/ct5361/ct-5361.c new file mode 100644 index 0000000000..d181ca68a0 --- /dev/null +++ b/board/comtrend/ct5361/ct-5361.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> diff --git a/board/davedenx/aria/Kconfig b/board/davedenx/aria/Kconfig deleted file mode 100644 index 54a86b9e13..0000000000 --- a/board/davedenx/aria/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ARIA - -config SYS_BOARD - default "aria" - -config SYS_VENDOR - default "davedenx" - -config SYS_CONFIG_NAME - default "aria" - -endif diff --git a/board/davedenx/aria/MAINTAINERS b/board/davedenx/aria/MAINTAINERS deleted file mode 100644 index a6152c985a..0000000000 --- a/board/davedenx/aria/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ARIA BOARD -M: Wolfgang Denk <wd@denx.de> -S: Maintained -F: board/davedenx/aria/ -F: include/configs/aria.h -F: configs/aria_defconfig diff --git a/board/davedenx/aria/Makefile b/board/davedenx/aria/Makefile deleted file mode 100644 index dd38b7f389..0000000000 --- a/board/davedenx/aria/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2009 Wolfgang Denk <wd@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := aria.o diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c deleted file mode 100644 index e389819e9d..0000000000 --- a/board/davedenx/aria/aria.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> - * (C) Copyright 2009 Dave Srl www.dave.eu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/bitops.h> -#include <command.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/mpc512x.h> -#include <fdt_support.h> -#ifdef CONFIG_MISC_INIT_R -#include <i2c.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - gd->ram_size = fixed_sdram(NULL, NULL, 0); - - return 0; -} - -int misc_init_r(void) -{ - u32 tmp; - - tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE); - printf("FPGA: %u-%u.%u.%u\n", - (tmp & 0xFF000000) >> 24, - (tmp & 0x00FF0000) >> 16, - (tmp & 0x0000FF00) >> 8, - tmp & 0x000000FF - ); - - return 0; -} - -static iopin_t ioregs_init[] = { - /* - * FEC - */ - - /* FEC on PSCx_x*/ - { - offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - { - offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - { - offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - - /* - * DIU - */ - /* FUNC2=DIU CLK */ - { - offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=DIU_HSYNC */ - { - offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */ - { - offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* - * On board SRAM - */ - /* FUNC2=/LPC CS6 */ - { - offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, -}; - -int checkboard (void) -{ - puts("Board: ARIA\n"); - - /* initialize function mux & slew rate IO inter alia on IO Pins */ - - iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 9e17eb865d..11ea52f240 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -23,6 +23,7 @@ #include <asm/arch/davinci_misc.h> #include <linux/errno.h> #include <hwconfig.h> +#include <asm/mach-types.h> #ifdef CONFIG_MMC_DAVINCI #include <mmc.h> diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index d941285977..52bb7363a7 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -19,6 +19,7 @@ #include <asm/ti-common/davinci_nand.h> #include <asm/io.h> #include <linux/errno.h> +#include <asm/mach-types.h> #include <asm/arch/davinci_misc.h> #ifdef CONFIG_MMC_DAVINCI #include <mmc.h> diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 6edfa17a91..2a187f1900 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -18,6 +18,7 @@ #include <i2c.h> #include <net.h> #include <netdev.h> +#include <asm/mach-types.h> #include <asm/arch/hardware.h> #include <asm/ti-common/davinci_nand.h> #include <asm/arch/emac_defs.h> diff --git a/board/esd/mecp5123/Kconfig b/board/esd/mecp5123/Kconfig deleted file mode 100644 index 3f2a411196..0000000000 --- a/board/esd/mecp5123/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MECP5123 - -config SYS_BOARD - default "mecp5123" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "mecp5123" - -endif diff --git a/board/esd/mecp5123/MAINTAINERS b/board/esd/mecp5123/MAINTAINERS deleted file mode 100644 index ae5fcead90..0000000000 --- a/board/esd/mecp5123/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MECP5123 BOARD -M: Reinhard Arlt <reinhard.arlt@esd-electronics.com> -S: Maintained -F: board/esd/mecp5123/ -F: include/configs/mecp5123.h -F: configs/mecp5123_defconfig diff --git a/board/esd/mecp5123/Makefile b/board/esd/mecp5123/Makefile deleted file mode 100644 index f5ebb0144f..0000000000 --- a/board/esd/mecp5123/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2009 Wolfgang Denk <wd@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mecp5123.o diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c deleted file mode 100644 index 78a6b66110..0000000000 --- a/board/esd/mecp5123/mecp5123.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> - * (C) Copyright 2009 Dave Srl www.dave.eu - * (C) Copyright 2009 Stefan Roese <sr@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/bitops.h> -#include <command.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/mpc512x.h> -#include <fdt_support.h> - -DECLARE_GLOBAL_DATA_PTR; - -int eeprom_write_enable(unsigned dev_addr, int state) -{ - return -ENOSYS; -} - -int board_early_init_f(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - int i; - - /* - * Initialize Local Window for boot access - */ - out_be32(&im->sysconf.lpbaw, - CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000)); - sync_law(&im->sysconf.lpbaw); - - /* - * Configure MSCAN clocks - */ - for (i=0; i<4; ++i) { - out_be32(&im->clk.msccr[i], 0x00300000); - out_be32(&im->clk.msccr[i], 0x00310000); - } - - /* - * Configure GPIO's - */ - clrbits_be32(&im->gpio.gpodr, 0x000000e0); - clrbits_be32(&im->gpio.gpdir, 0x00ef0000); - setbits_be32(&im->gpio.gpdir, 0x001000e0); - setbits_be32(&im->gpio.gpdat, 0x00100000); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0)); - - return 0; -} - -int misc_init_r(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 val; - - /* - * Optimize access to profibus chip (VPC3) on the local bus - */ - - /* - * Select 1:1 for LPC_DIV - */ - val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK; - out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT)); - - /* - * Configure LPC Chips Select Deadcycle Control Register - * CS0 - device can drive data 2 clock cycle(s) after CS deassertion - * CS1 - device can drive data 1 clock cycle(s) after CS deassertion - */ - clrbits_be32(&im->lpc.cs_dccr, 0x000000ff); - setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0)); - - /* - * Configure LPC Chips Select Holdcycle Control Register - * CS0 - data is valid 2 clock cycle(s) after CS deassertion - * CS1 - data is valid 1 clock cycle(s) after CS deassertion - */ - clrbits_be32(&im->lpc.cs_hccr, 0x000000ff); - setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0)); - - return 0; -} - -static iopin_t ioregs_init[] = { - /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ - { - offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=FEC_COL Sets Next 15 to FEC pads */ - { - offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=SELECT LPC_CS1 */ - { - offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC5_2 */ - { - offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC5_3 */ - { - offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC7_3 */ - { - offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC9_0 */ - { - offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC10_0 */ - { - offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC10_3 */ - { - offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=SELECT PSC11_0 */ - { - offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC0=SELECT IRQ0 */ - { - offsetof(struct ioctrl512x, io_control_irq0), 4, 0, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - } -}; - -static iopin_t rev2_silicon_pci_ioregs_init[] = { - /* FUNC0=PCI Sets next 54 to PCI pads */ - { - offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0) - } -}; - -int checkboard(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 spridr; - - puts("Board: MECP_5123\n"); - - /* - * Initialize function mux & slew rate IO inter alia on IO - * Pins - */ - iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); - - spridr = in_be32(&im->sysconf.spridr); - if (SVR_MJREV(spridr) >= 2) - iopin_initialize(rev2_silicon_pci_ioregs_init, 1); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 19b673e6d2..e4bda7909a 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -13,6 +13,8 @@ #include <common.h> #include <asm/io.h> #include <asm/gpio.h> +#include <asm/mach-types.h> +#include <asm/setup.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> diff --git a/board/freescale/b4860qds/MAINTAINERS b/board/freescale/b4860qds/MAINTAINERS index 97304c5325..34ac099e44 100644 --- a/board/freescale/b4860qds/MAINTAINERS +++ b/board/freescale/b4860qds/MAINTAINERS @@ -1,5 +1,5 @@ B4860QDS BOARD -#M: - +M: Ashish Kumar <ashish.kumar@nxp.com> S: Maintained F: board/freescale/b4860qds/ F: include/configs/B4860QDS.h diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index aad1b93d14..2cd4fba13f 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <dm.h> #include <fsl_validate.h> #include <fsl_secboot_err.h> #include <fsl_sfp.h> diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index ed48c5c8bd..ef93407646 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -5,13 +5,13 @@ */ #include <common.h> +#include <dm.h> #include <fsl_validate.h> #include <fsl_secboot_err.h> #include <fsl_sfp.h> #include <fsl_sec.h> #include <command.h> #include <malloc.h> -#include <dm/uclass.h> #include <u-boot/rsa-mod-exp.h> #include <hash.h> #include <fsl_secboot_err.h> diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index 81c921122e..1c2287d22a 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -39,7 +39,10 @@ static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) void enable_layerscape_ns_access(void) { - enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#ifdef CONFIG_ARM64 + if (current_el() == 3) +#endif + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); } void set_pcie_ns_access(int pcie, u16 val) diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index d16a69fc98..2ee8749f36 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -8,6 +8,7 @@ #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <asm/io.h> +#include <asm/arch/clock.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index b22d3784dc..f219a77e98 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -10,6 +10,7 @@ #ifdef CONFIG_FSL_DEEP_SLEEP #include <fsl_sleep.h> #endif +#include <asm/arch/clock.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 36d27ecfae..354b864eb9 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -11,6 +11,7 @@ #ifdef CONFIG_FSL_DEEP_SLEEP #include <fsl_sleep.h> #endif +#include <asm/arch/clock.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index 5fcfa0f701..e1858d6060 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -10,6 +10,7 @@ #ifdef CONFIG_FSL_DEEP_SLEEP #include <fsl_sleep.h> #endif +#include <asm/arch/clock.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index ae5046cab6..fb4f6abe0b 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -11,6 +11,7 @@ #ifdef CONFIG_FSL_DEEP_SLEEP #include <fsl_sleep.h> #endif +#include <asm/arch/clock.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c index 9d176d3851..025e5aa8d0 100644 --- a/board/freescale/ls2080a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -8,6 +8,7 @@ #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <asm/arch/soc.h> +#include <asm/arch/clock.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index 9e7701d81f..41417e9dc6 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -64,13 +64,13 @@ int board_eth_init(bd_t *bis) error = smc91111_initialize(0, CONFIG_SMC91111_BASE); #endif -#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) error = cpu_eth_init(bis); #endif return error; } -#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) void fdt_fixup_board_enet(void *fdt) { int offset; @@ -128,10 +128,16 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, base, size, 2); -#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) fdt_fixup_board_enet(blob); #endif return 0; } #endif + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ +} +#endif diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index 79877d7774..62c8fac09c 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -7,6 +7,7 @@ F: include/configs/ls2080aqds.h F: configs/ls2080aqds_defconfig F: configs/ls2080aqds_nand_defconfig F: configs/ls2080aqds_qspi_defconfig +F: configs/ls2080aqds_sdcard_defconfig LS2080A_SECURE_BOOT BOARD M: Saksham Jain <saksham.jain@nxp.freescale.com> diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index cad860eac2..8e31e9e41e 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -102,6 +102,19 @@ DPAA2 DPL 0x00D00000 DPAA2 DPC 0x00E00000 Kernel.itb 0x01000000 +Memory map for SD boot +------------------------- +Image Flash Offset SD Card + Start Block No. +RCW+PBI 0x00000000 0x00008 +Boot firmware (U-Boot) 0x00100000 0x00800 +Boot firmware Environment 0x00300000 0x01800 +PPA firmware 0x00400000 0x02000 +DPAA2 MC 0x00A00000 0x05000 +DPAA2 DPL 0x00D00000 0x06800 +DPAA2 DPC 0x00E00000 0x07000 +Kernel.itb 0x01000000 0x08000 + Environment Variables --------------------- - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index 22a2676a95..20b8c1fef7 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -8,6 +8,7 @@ #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <asm/arch/soc.h> +#include <asm/arch/clock.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 59361e9111..defcac5263 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -14,6 +14,7 @@ #include <fm_eth.h> #include <i2c.h> #include <miiphy.h> +#include <fsl-mc/fsl_mc.h> #include <fsl-mc/ldpaa_wriop.h> #include "../common/qixis.h" @@ -22,7 +23,7 @@ #define MC_BOOT_ENV_VAR "mcinitcmd" -#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks. * Bank 1 -> Lanes A, B, C, D, E, F, G, H * Bank 2 -> Lanes A,B, C, D, E, F, G, H @@ -834,8 +835,7 @@ void ls2080a_handle_phy_interface_xsgmii(int i) int board_eth_init(bd_t *bis) { int error; - char *mc_boot_env_var; -#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) @@ -902,9 +902,6 @@ int board_eth_init(bd_t *bis) } } - mc_boot_env_var = getenv(MC_BOOT_ENV_VAR); - if (mc_boot_env_var) - run_command_list(mc_boot_env_var, -1, 0); error = cpu_eth_init(bis); if (hwconfig_f("xqsgmii", env_hwconfig)) { @@ -919,6 +916,9 @@ int board_eth_init(bd_t *bis) return error; } -#ifdef CONFIG_FSL_MC_ENET - -#endif +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ + mc_env_boot(); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 6da9c6cfe8..f36fb9810b 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -280,7 +280,7 @@ int arch_misc_init(void) } #endif -#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) void fdt_fixup_board_enet(void *fdt) { int offset; @@ -336,7 +336,7 @@ int ft_board_setup(void *blob, bd_t *bd) fsl_fdt_fixup_dr_usb(blob, bd); -#ifdef CONFIG_FSL_MC_ENET +#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) fdt_fixup_board_enet(blob); #endif diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index 7002dfb236..01f7d82fb6 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -8,6 +8,7 @@ #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <asm/arch/soc.h> +#include <asm/arch/clock.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index ba584c8a76..32677f7ae1 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -16,15 +16,14 @@ #include <asm/io.h> #include <exports.h> #include <asm/arch/fsl_serdes.h> +#include <fsl-mc/fsl_mc.h> #include <fsl-mc/ldpaa_wriop.h> DECLARE_GLOBAL_DATA_PTR; -#define MC_BOOT_ENV_VAR "mcinitcmd" int board_eth_init(bd_t *bis) { #if defined(CONFIG_FSL_MC_ENET) - char *mc_boot_env_var; int i, interface; struct memac_mdio_info mdio_info; struct mii_dev *dev; @@ -98,11 +97,8 @@ int board_eth_init(bd_t *bis) } } - mc_boot_env_var = getenv(MC_BOOT_ENV_VAR); - if (mc_boot_env_var) - run_command_list(mc_boot_env_var, -1, 0); cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ +#endif /* CONFIG_FSL_MC_ENET */ #ifdef CONFIG_PHY_AQUANTIA /* @@ -118,3 +114,10 @@ int board_eth_init(bd_t *bis) #endif return pci_eth_init(bis); } + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ + mc_env_boot(); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/freescale/mpc5121ads/Kconfig b/board/freescale/mpc5121ads/Kconfig deleted file mode 100644 index f125f9e596..0000000000 --- a/board/freescale/mpc5121ads/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC5121ADS - -config SYS_BOARD - default "mpc5121ads" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "mpc5121ads" - -endif diff --git a/board/freescale/mpc5121ads/MAINTAINERS b/board/freescale/mpc5121ads/MAINTAINERS deleted file mode 100644 index d4aab8fb51..0000000000 --- a/board/freescale/mpc5121ads/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MPC5121ADS BOARD -#M: - -S: Maintained -F: board/freescale/mpc5121ads/ -F: include/configs/mpc5121ads.h -F: configs/mpc5121ads_defconfig -F: configs/mpc5121ads_rev2_defconfig diff --git a/board/freescale/mpc5121ads/Makefile b/board/freescale/mpc5121ads/Makefile deleted file mode 100644 index 67cf55546b..0000000000 --- a/board/freescale/mpc5121ads/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mpc5121ads.o diff --git a/board/freescale/mpc5121ads/README b/board/freescale/mpc5121ads/README deleted file mode 100644 index 741bc40382..0000000000 --- a/board/freescale/mpc5121ads/README +++ /dev/null @@ -1,7 +0,0 @@ -To configure for the current (Rev 3.x) ADS5121 - make mpc5121ads_config -This will automatically include PCI, the Real Time CLock, add backup flash -ability and set the correct frequency and memory configuration. - -To configure for the older Rev 2 ADS5121 type (this will not have PCI) - make mpc5121ads_rev2_config diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c deleted file mode 100644 index d729056fd0..0000000000 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * (C) Copyright 2007-2009 DENX Software Engineering - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/bitops.h> -#include <command.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/mpc512x.h> -#include <fdt_support.h> -#ifdef CONFIG_MISC_INIT_R -#include <i2c.h> -#endif -#include <net.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand.h> - -DECLARE_GLOBAL_DATA_PTR; - -void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip); - -/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */ -extern int mpc5121_nfc_chip; - -/* Control chips select signal on MPC5121ADS board */ -void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip) -{ - unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09; - u8 v; - - v = in_8(csreg); - v |= 0x0F; - - if (chip >= 0) { - __mpc5121_nfc_select_chip(mtd, 0); - v &= ~(1 << mpc5121_nfc_chip); - } else { - __mpc5121_nfc_select_chip(mtd, -1); - } - - out_8(csreg, v); -} - -int board_early_init_f(void) -{ - /* - * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control - * - * Without this the flash identification routine fails, as it needs to issue - * write commands in order to establish the device ID. - */ - -#ifdef CONFIG_MPC5121ADS_REV2 - out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1); -#else - if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) { - out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1); - } else { - /* running from Backup flash */ - out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32); - } -#endif - return 0; -} - -int is_micron(void){ - - ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00); - uchar macaddr[6]; - u32 brddate, macchk, ismicron; - - /* - * MAC address has serial number with date of manufacture - * Boards made before Nov-08 #1180 use Micron memory; - * 001e59 is the STx vendor # - * Default is Elpida since it works for both but is slightly slower - */ - ismicron = 0; - if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) { - brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5]; - macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2]; - debug("brddate = %d\n\t", brddate); - - if (macchk == 0x001e59 && brddate <= 8111180) - ismicron = 1; - } else if (brd_rev < 0x400) { - ismicron = 1; - } - debug("Using %s Memory settings\n\t", - ismicron ? "Micron" : "Elpida"); - return(ismicron); -} - -int dram_init(void) -{ - u32 msize = 0; - /* - * Elpida MDDRC and initialization settings are an alternative - * to the Default Micron ones for all but the earliest Rev 4 boards - */ - ddr512x_config_t elpida_mddrc_config = { - .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, - .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0, - .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, - .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA, - }; - - u32 elpida_init_sequence[] = { - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_EM2, - CONFIG_SYS_DDRCMD_EM3, - CONFIG_SYS_DDRCMD_EN_DLL, - CONFIG_SYS_ELPIDA_RES_DLL, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_ELPIDA_INIT_DEV_OP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_OCD_DEFAULT, - CONFIG_SYS_ELPIDA_OCD_EXIT, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP - }; - - if (is_micron()) { - msize = fixed_sdram(NULL, NULL, 0); - } else { - msize = fixed_sdram(&elpida_mddrc_config, - elpida_init_sequence, - sizeof(elpida_init_sequence)/sizeof(u32)); - } - - gd->ram_size = msize; - - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -static iopin_t ioregs_init[] = { - /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ - { - offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* Set highest Slew on 9 PATA pins */ - { - offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=FEC_COL Sets Next 15 to FEC pads */ - { - offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=SPDIF_TXCLK */ - { - offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */ - { - offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=DIU CLK */ - { - offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=DIU_HSYNC */ - { - offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */ - { - offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - } -}; - -static iopin_t rev2_silicon_pci_ioregs_init[] = { - /* FUNC0=PCI Sets next 54 to PCI pads */ - { - offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0) - } -}; - -int checkboard (void) -{ - ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); - uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02); - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 spridr = in_be32(&im->sysconf.spridr); - - printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n", - brd_rev, cpld_rev); - - /* initialize function mux & slew rate IO inter alia on IO Pins */ - iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); - - if (SVR_MJREV (spridr) >= 2) - iopin_initialize(rev2_silicon_pci_ioregs_init, 1); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc8536ds/MAINTAINERS b/board/freescale/mpc8536ds/MAINTAINERS index 953072cdd0..af221f9cad 100644 --- a/board/freescale/mpc8536ds/MAINTAINERS +++ b/board/freescale/mpc8536ds/MAINTAINERS @@ -1,5 +1,5 @@ MPC8536DS BOARD -#M: - +M: York Sun <york.sun@nxp.com> S: Maintained F: board/freescale/mpc8536ds/ F: include/configs/MPC8536DS.h diff --git a/board/freescale/mpc8540ads/Kconfig b/board/freescale/mpc8540ads/Kconfig deleted file mode 100644 index 35a8545547..0000000000 --- a/board/freescale/mpc8540ads/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8540ADS - -config SYS_BOARD - default "mpc8540ads" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8540ADS" - -endif diff --git a/board/freescale/mpc8540ads/MAINTAINERS b/board/freescale/mpc8540ads/MAINTAINERS deleted file mode 100644 index acc48218d4..0000000000 --- a/board/freescale/mpc8540ads/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8540ADS BOARD -#M: Kumar Gala <kumar.gala@freescale.com> -S: Orphan (since 2014-06) -F: board/freescale/mpc8540ads/ -F: include/configs/MPC8540ADS.h -F: configs/MPC8540ADS_defconfig diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile deleted file mode 100644 index 6f82c7f7ac..0000000000 --- a/board/freescale/mpc8540ads/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mpc8540ads.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c deleted file mode 100644 index 10fb2b3d60..0000000000 --- a/board/freescale/mpc8540ads/ddr.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c deleted file mode 100644 index 41f2e02bfd..0000000000 --- a/board/freescale/mpc8540ads/law.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c deleted file mode 100644 index 1069e2c8c8..0000000000 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <fsl_ddr_sdram.h> -#include <libfdt.h> -#include <fdt_support.h> - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -void local_bus_init(void); - -int checkboard (void) -{ - puts("Board: ADS\n"); - -#ifdef CONFIG_PCI - printf("PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf("PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init(); - - return 0; -} - -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66MHz, DLL bypass mode must be used. - * If localbus freq is > 133MHz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr(); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void lbc_sdram_init(void) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - - puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n "); - - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("sync"); - - /* - * Configure the SDRAM controller. - */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -phys_size_t fixed_sdram(void) -{ - #ifndef CONFIG_SYS_RAMBOOT - struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - - -static struct pci_controller hose; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} - - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - int node, tmp[2]; - const char *path; - - ft_cpu_setup(blob, bd); - - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { -#ifdef CONFIG_PCI - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = hose.last_busno - hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } - - return 0; -} -#endif diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c deleted file mode 100644 index d5ee791da6..0000000000 --- a/board/freescale/mpc8540ads/tlb.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xf8000000 16K BCSR registers - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8541cds/MAINTAINERS b/board/freescale/mpc8541cds/MAINTAINERS index d421b1281b..1d969f1107 100644 --- a/board/freescale/mpc8541cds/MAINTAINERS +++ b/board/freescale/mpc8541cds/MAINTAINERS @@ -1,6 +1,6 @@ MPC8541CDS BOARD -#M: Kumar Gala <kumar.gala@freescale.com> -S: Orphan (since 2014-06) +M: York Sun <york.sun@nxp.com> +S: Maintained F: board/freescale/mpc8541cds/ F: include/configs/MPC8541CDS.h F: configs/MPC8541CDS_defconfig diff --git a/board/freescale/mpc8544ds/MAINTAINERS b/board/freescale/mpc8544ds/MAINTAINERS index 328be7fecc..3c6f80e6e3 100644 --- a/board/freescale/mpc8544ds/MAINTAINERS +++ b/board/freescale/mpc8544ds/MAINTAINERS @@ -1,5 +1,5 @@ MPC8544DS BOARD -#M: - +M: York Sun <york.sun@nxp.com> S: Maintained F: board/freescale/mpc8544ds/ F: include/configs/MPC8544DS.h diff --git a/board/freescale/mpc8548cds/MAINTAINERS b/board/freescale/mpc8548cds/MAINTAINERS index 6f229227c0..a99f84bc87 100644 --- a/board/freescale/mpc8548cds/MAINTAINERS +++ b/board/freescale/mpc8548cds/MAINTAINERS @@ -1,5 +1,5 @@ MPC8548CDS BOARD -#M: - +M: York Sun <york.sun@nxp.com> S: Maintained F: board/freescale/mpc8548cds/ F: include/configs/MPC8548CDS.h diff --git a/board/freescale/mpc8555cds/MAINTAINERS b/board/freescale/mpc8555cds/MAINTAINERS index 1ef669000f..3be1598c40 100644 --- a/board/freescale/mpc8555cds/MAINTAINERS +++ b/board/freescale/mpc8555cds/MAINTAINERS @@ -1,6 +1,6 @@ MPC8555CDS BOARD -#M: Kumar Gala <kumar.gala@freescale.com> -S: Orphan (since 2014-06) +M: York Sun <york.sun@nxp.com> +S: Maintained F: board/freescale/mpc8555cds/ F: include/configs/MPC8555CDS.h F: configs/MPC8555CDS_defconfig diff --git a/board/freescale/mpc8560ads/Kconfig b/board/freescale/mpc8560ads/Kconfig deleted file mode 100644 index 828c068e9e..0000000000 --- a/board/freescale/mpc8560ads/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8560ADS - -config SYS_BOARD - default "mpc8560ads" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8560ADS" - -endif diff --git a/board/freescale/mpc8560ads/MAINTAINERS b/board/freescale/mpc8560ads/MAINTAINERS deleted file mode 100644 index 96e6da2aad..0000000000 --- a/board/freescale/mpc8560ads/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPC8560ADS BOARD -#M: Kumar Gala <kumar.gala@freescale.com> -S: Orphan (since 2014-06) -F: board/freescale/mpc8560ads/ -F: include/configs/MPC8560ADS.h -F: configs/MPC8560ADS_defconfig diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile deleted file mode 100644 index 685168e08d..0000000000 --- a/board/freescale/mpc8560ads/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += mpc8560ads.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c deleted file mode 100644 index 10fb2b3d60..0000000000 --- a/board/freescale/mpc8560ads/ddr.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twot_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c deleted file mode 100644 index 41f2e02bfd..0000000000 --- a/board/freescale/mpc8560ads/law.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c deleted file mode 100644 index f99d639b2f..0000000000 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ /dev/null @@ -1,462 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <fsl_ddr_sdram.h> -#include <ioports.h> -#include <spd_sdram.h> -#include <miiphy.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_lbc.h> - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - - -void local_bus_init(void); - - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - - -/* - * MPC8560ADS Board Status & Control Registers - */ -typedef struct bcsr_ { - volatile unsigned char bcsr0; - volatile unsigned char bcsr1; - volatile unsigned char bcsr2; - volatile unsigned char bcsr3; - volatile unsigned char bcsr4; - volatile unsigned char bcsr5; -} bcsr_t; - -void reset_phy (void) -{ -#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ - volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR; -#endif - /* reset Giga bit Ethernet port if needed here */ - - /* reset the CPM FEC port */ -#if (CONFIG_ETHER_INDEX == 2) - bcsr->bcsr2 &= ~FETH2_RST; - udelay(2); - bcsr->bcsr2 |= FETH2_RST; - udelay(1000); -#elif (CONFIG_ETHER_INDEX == 3) - bcsr->bcsr3 &= ~FETH3_RST; - udelay(2); - bcsr->bcsr3 |= FETH3_RST; - udelay(1000); -#endif -#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) - /* reset PHY */ - miiphy_reset("FCC1", 0x0); - - /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - - bb_miiphy_write(NULL, 0x02, MII_BMCR, - BMCR_ANENABLE | BMCR_ANRESTART); -#endif /* CONFIG_MII */ -} - - -int checkboard (void) -{ - puts("Board: ADS\n"); - -#ifdef CONFIG_PCI - printf("PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf("PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init(); - - return 0; -} - -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66MHz, DLL bypass mode must be used. - * If localbus freq is > 133MHz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr(); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - - -/* - * Initialize SDRAM memory on the Local Bus. - */ -void lbc_sdram_init(void) -{ - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - - puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, - "\n "); - - /* - * Setup SDRAM Base and Option Registers - */ - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - asm("msync"); - - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("sync"); - - /* - * Configure the SDRAM controller. - */ - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); - - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; - asm("sync"); - *sdram_addr = 0xff; - ppcDcbf((unsigned long) sdram_addr); - udelay(100); -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -phys_size_t fixed_sdram(void) -{ - #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxads_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} - - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - int node, tmp[2]; - const char *path; - - ft_cpu_setup(blob, bd); - - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { -#ifdef CONFIG_PCI - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = hose.last_busno - hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } - - return 0; -} -#endif diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c deleted file mode 100644 index d5ee791da6..0000000000 --- a/board/freescale/mpc8560ads/tlb.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xf8000000 16K BCSR registers - */ - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8568mds/MAINTAINERS b/board/freescale/mpc8568mds/MAINTAINERS index 379d8cc1d5..56c5373c07 100644 --- a/board/freescale/mpc8568mds/MAINTAINERS +++ b/board/freescale/mpc8568mds/MAINTAINERS @@ -1,5 +1,5 @@ MPC8568MDS BOARD -#M: - +M: York Sun <york.sun@nxp.com> S: Maintained F: board/freescale/mpc8568mds/ F: include/configs/MPC8568MDS.h diff --git a/board/freescale/mpc8569mds/MAINTAINERS b/board/freescale/mpc8569mds/MAINTAINERS index c181407f25..49a9361575 100644 --- a/board/freescale/mpc8569mds/MAINTAINERS +++ b/board/freescale/mpc8569mds/MAINTAINERS @@ -1,5 +1,5 @@ MPC8569MDS BOARD -#M: - +M: York Sun <york.sun@nxp.com> S: Maintained F: board/freescale/mpc8569mds/ F: include/configs/MPC8569MDS.h diff --git a/board/freescale/mpc8610hpcd/MAINTAINERS b/board/freescale/mpc8610hpcd/MAINTAINERS index de6ab89299..8986c1140d 100644 --- a/board/freescale/mpc8610hpcd/MAINTAINERS +++ b/board/freescale/mpc8610hpcd/MAINTAINERS @@ -1,5 +1,5 @@ MPC8610HPCD BOARD -#M: - +M: York Sun <york.sun@nxp.com> S: Maintained F: board/freescale/mpc8610hpcd/ F: include/configs/MPC8610HPCD.h diff --git a/board/freescale/mpc8641hpcn/MAINTAINERS b/board/freescale/mpc8641hpcn/MAINTAINERS index 97902475ba..86dcf6b1ff 100644 --- a/board/freescale/mpc8641hpcn/MAINTAINERS +++ b/board/freescale/mpc8641hpcn/MAINTAINERS @@ -1,6 +1,6 @@ MPC8641HPCN BOARD -#M: Kumar Gala <kumar.gala@freescale.com> -S: Orphan (since 2014-06) +M: York Sun <york.sun@nxp.com> +S: Maintained F: board/freescale/mpc8641hpcn/ F: include/configs/MPC8641HPCN.h F: configs/MPC8641HPCN_defconfig diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index 123fb11f42..ea0bd8f30a 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -24,6 +24,7 @@ #include <asm/gpio.h> #include <asm/arch/sys_proto.h> #include <netdev.h> +#include <asm/mach-types.h> #ifndef CONFIG_BOARD_LATE_INIT #error "CONFIG_BOARD_LATE_INIT must be set for this board" diff --git a/board/freescale/p1010rdb/MAINTAINERS b/board/freescale/p1010rdb/MAINTAINERS index db001437b1..c9f7fa3e2a 100644 --- a/board/freescale/p1010rdb/MAINTAINERS +++ b/board/freescale/p1010rdb/MAINTAINERS @@ -1,5 +1,5 @@ P1010RDB BOARD -#M: - +M: Qiang Zhao <qiang.zhao@nxp.com> S: Maintained F: board/freescale/p1010rdb/ F: include/configs/P1010RDB.h diff --git a/board/freescale/p1_twr/MAINTAINERS b/board/freescale/p1_twr/MAINTAINERS index c19d43616b..0f9f98f459 100644 --- a/board/freescale/p1_twr/MAINTAINERS +++ b/board/freescale/p1_twr/MAINTAINERS @@ -1,5 +1,5 @@ P1_TWR BOARD -#M: - +M: Xiaobo Xie <xiaobo.xie@nxp.com> S: Maintained F: board/freescale/p1_twr/ F: include/configs/p1_twr.h diff --git a/board/freescale/s32v234evb/clock.c b/board/freescale/s32v234evb/clock.c index d218c21419..e8996e094f 100644 --- a/board/freescale/s32v234evb/clock.c +++ b/board/freescale/s32v234evb/clock.c @@ -45,7 +45,7 @@ static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq) pll_idx = 1; break; case DDR_PLL: - pll_idx = 2;; + pll_idx = 2; break; default: pll_idx = pll; diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS index 05789890f6..8e3267917f 100644 --- a/board/freescale/t104xrdb/MAINTAINERS +++ b/board/freescale/t104xrdb/MAINTAINERS @@ -1,5 +1,5 @@ T104XRDB BOARD -M: Priyanka Jain <Priyanka.Jain@freescale.com> +M: Priyanka Jain <priyanka.jain@nxp.com> S: Maintained F: board/freescale/t104xrdb/ F: include/configs/T104xRDB.h @@ -18,7 +18,7 @@ F: configs/T1042RDB_PI_NAND_defconfig F: configs/T1042RDB_PI_SPIFLASH_defconfig T1040RDB_SDCARD BOARD -#M: - +M: Priyanka Jain <priyanka.jain@nxp.com> S: Maintained F: configs/T1040RDB_SDCARD_defconfig F: configs/T1040D4RDB_SDCARD_defconfig diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index a68ec69f18..6b950eeb21 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -19,6 +19,7 @@ #include <asm/imx-common/spi.h> #include <asm/imx-common/video.h> #include <asm/io.h> +#include <asm/setup.h> #include <dm.h> #include <dm/platform_data/serial_mxc.h> #include <hwconfig.h> diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c index db8a917563..95f11fb69f 100644 --- a/board/gdsys/p1022/controlcenterd-id.c +++ b/board/gdsys/p1022/controlcenterd-id.c @@ -142,20 +142,6 @@ static int hre_err = HRE_E_OK; #define IS_VAR_HREG(spec) (((spec) & 0x38) == 0x10) #define HREG_IDX(spec) ((spec) & (IS_PCR_HREG(spec) ? 0x1f : 0x7)) - -static const uint8_t prg_stage1_prepare[] = { - 0x00, 0x20, 0x00, 0x00, /* opcode: SYNC f0 */ - 0x00, 0x24, 0x00, 0x00, /* opcode: SYNC f1 */ - 0x01, 0x80, 0x00, 0x00, /* opcode: CHECK0 PCR0 */ - 0x81, 0x22, 0x00, 0x00, /* opcode: LOAD PCR0, f0 */ - 0x01, 0x84, 0x00, 0x00, /* opcode: CHECK0 PCR1 */ - 0x81, 0x26, 0x10, 0x00, /* opcode: LOAD PCR1, f1 */ - 0x01, 0x88, 0x00, 0x00, /* opcode: CHECK0 PCR2 */ - 0x81, 0x2a, 0x20, 0x00, /* opcode: LOAD PCR2, f2 */ - 0x01, 0x8c, 0x00, 0x00, /* opcode: CHECK0 PCR3 */ - 0x81, 0x2e, 0x30, 0x00, /* opcode: LOAD PCR3, f3 */ -}; - static const uint8_t vendor[] = "Guntermann & Drunck"; /** @@ -931,6 +917,19 @@ end: #endif #if defined(CCDM_FIRST_STAGE) || (defined CCDM_AUTO_FIRST_STAGE) +static const uint8_t prg_stage1_prepare[] = { + 0x00, 0x20, 0x00, 0x00, /* opcode: SYNC f0 */ + 0x00, 0x24, 0x00, 0x00, /* opcode: SYNC f1 */ + 0x01, 0x80, 0x00, 0x00, /* opcode: CHECK0 PCR0 */ + 0x81, 0x22, 0x00, 0x00, /* opcode: LOAD PCR0, f0 */ + 0x01, 0x84, 0x00, 0x00, /* opcode: CHECK0 PCR1 */ + 0x81, 0x26, 0x10, 0x00, /* opcode: LOAD PCR1, f1 */ + 0x01, 0x88, 0x00, 0x00, /* opcode: CHECK0 PCR2 */ + 0x81, 0x2a, 0x20, 0x00, /* opcode: LOAD PCR2, f2 */ + 0x01, 0x8c, 0x00, 0x00, /* opcode: CHECK0 PCR3 */ + 0x81, 0x2e, 0x30, 0x00, /* opcode: LOAD PCR3, f3 */ +}; + static int first_stage_actions(void) { int result = 0; diff --git a/board/geekbuying/geekbox/Kconfig b/board/geekbuying/geekbox/Kconfig new file mode 100644 index 0000000000..41aa8fbe03 --- /dev/null +++ b/board/geekbuying/geekbox/Kconfig @@ -0,0 +1,15 @@ +if TARGET_GEEKBOX + +config SYS_BOARD + default "geekbox" + +config SYS_VENDOR + default "geekbuying" + +config SYS_CONFIG_NAME + default "geekbox" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/geekbuying/geekbox/MAINTAINERS b/board/geekbuying/geekbox/MAINTAINERS new file mode 100644 index 0000000000..7a4989f943 --- /dev/null +++ b/board/geekbuying/geekbox/MAINTAINERS @@ -0,0 +1,6 @@ +GEEKBOX +M: Andreas Färber <afaerber@suse.de> +S: Maintained +F: board/geekbuying/geekbox +F: include/configs/geekbox.h +F: configs/geekbox_defconfig diff --git a/board/geekbuying/geekbox/Makefile b/board/geekbuying/geekbox/Makefile new file mode 100644 index 0000000000..5c1d66cc98 --- /dev/null +++ b/board/geekbuying/geekbox/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2016 Andreas Färber +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += geekbox.o diff --git a/board/geekbuying/geekbox/README b/board/geekbuying/geekbox/README new file mode 100644 index 0000000000..de980f2f23 --- /dev/null +++ b/board/geekbuying/geekbox/README @@ -0,0 +1 @@ +see board/rockchip/sheep_rk3368/README diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c new file mode 100644 index 0000000000..75d121d736 --- /dev/null +++ b/board/geekbuying/geekbox/geekbox.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x80000000; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = 0x80000000; + + return 0; +} diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c index fefcde87ae..849224efda 100644 --- a/board/gumstix/duovero/duovero.c +++ b/board/gumstix/duovero/duovero.c @@ -14,6 +14,7 @@ #include <asm/arch/clock.h> #include <asm/arch/gpio.h> #include <asm/gpio.h> +#include <asm/mach-types.h> #include "duovero_mux_data.h" diff --git a/board/h2200/h2200.c b/board/h2200/h2200.c index 01f8e67be1..2a2b7979f1 100644 --- a/board/h2200/h2200.c +++ b/board/h2200/h2200.c @@ -11,6 +11,7 @@ #include <asm/arch/pxa-regs.h> #include <asm/io.h> #include <usb.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/hisilicon/hikey/README b/board/hisilicon/hikey/README index 0f6aab717c..4c2021f509 100644 --- a/board/hisilicon/hikey/README +++ b/board/hisilicon/hikey/README @@ -56,7 +56,7 @@ Compile U-Boot Compile ARM Trusted Firmware (ATF) ================================== - > cd ~/hikey/src/atf + > cd ~/hikey/src/arm-trusted-firmware > make CROSS_COMPILE=aarch64-linux-gnu- all fip \ BL30=~/hikey/bin/mcuimage.bin \ BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey @@ -67,10 +67,10 @@ Copy resulting binaries Compile l-loader =============== - > cd ~/hikey/l-loader + > cd ~/hikey/src/l-loader > make BL1=~/hikey/bin/bl1.bin all > cp *.img ~/hikey/bin - > cp l-loader.bin ~/hikey.bin + > cp l-loader.bin ~/hikey/bin These instructions are adapted from https://github.com/96boards/documentation/wiki/HiKeyUEFI @@ -82,7 +82,7 @@ FLASHING the hisi-idt.py utility. The command below assumes HiKey enumerated as the first USB serial port - > sudo ~/hikey/burn_boot/hisi-idt.py -d /dev/ttyUSB0 --img1=~/hikey/bin/l-loader.bin + > sudo ~/hikey/src/burn-boot/hisi-idt.py -d /dev/ttyUSB0 --img1=~/hikey/bin/l-loader.bin 2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device by plugging a USB A to mini B cable from your PC to the USB OTG port of HiKey (on some boards I've found this to be unreliable). diff --git a/board/ifm/ac14xx/Kconfig b/board/ifm/ac14xx/Kconfig deleted file mode 100644 index 97e80d5ddd..0000000000 --- a/board/ifm/ac14xx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_AC14XX - -config SYS_BOARD - default "ac14xx" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "ac14xx" - -endif diff --git a/board/ifm/ac14xx/MAINTAINERS b/board/ifm/ac14xx/MAINTAINERS deleted file mode 100644 index 8fd74e516e..0000000000 --- a/board/ifm/ac14xx/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -AC14XX BOARD -M: Anatolij Gustschin <agust@denx.de> -S: Maintained -F: board/ifm/ac14xx/ -F: include/configs/ac14xx.h -F: configs/ac14xx_defconfig diff --git a/board/ifm/ac14xx/Makefile b/board/ifm/ac14xx/Makefile deleted file mode 100644 index 55def60417..0000000000 --- a/board/ifm/ac14xx/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2009 Wolfgang Denk <wd@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ac14xx.o diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c deleted file mode 100644 index cd79e804a0..0000000000 --- a/board/ifm/ac14xx/ac14xx.c +++ /dev/null @@ -1,569 +0,0 @@ -/* - * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> - * (C) Copyright 2009 Dave Srl www.dave.eu - * (C) Copyright 2010 ifm ecomatic GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/bitops.h> -#include <command.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/mpc512x.h> -#include <fdt_support.h> -#ifdef CONFIG_MISC_INIT_R -#include <i2c.h> -#endif - -static int mac_diag; -static int gpio_diag; - -DECLARE_GLOBAL_DATA_PTR; - -static void gpio_configure(void) -{ - immap_t *im; - gpio512x_t *gpioregs; - - im = (immap_t *) CONFIG_SYS_IMMR; - gpioregs = &im->gpio; - out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */ - out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */ - - /* - * out_be32(&gpioregs->gpdir, 0xC2293020); - * workaround for a hardware effect: configure direction in pieces, - * setting all outputs at once drops the reset line too low and - * makes us lose the MII connection (breaks ethernet for us) - */ - out_be32(&gpioregs->gpdir, 0x02003060); /* direction */ - setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */ - udelay(10); - setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */ - udelay(10); - setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */ - udelay(10); - setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */ - - /* to turn from red to yellow when U-Boot runs */ - setbits_be32(&gpioregs->gpdat, 0x00002020); - out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */ - out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */ - out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */ - out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */ -} - -/* the physical location of the pins */ -#define GPIOKEY_ROW_BITMASK 0x40000000 -#define GPIOKEY_ROW_UPPER 0 -#define GPIOKEY_ROW_LOWER 1 - -#define GPIOKEY_COL0_BITMASK 0x20000000 -#define GPIOKEY_COL1_BITMASK 0x10000000 -#define GPIOKEY_COL2_BITMASK 0x08000000 - -/* the logical presentation of pressed keys */ -#define GPIOKEY_BIT_FNLEFT (1 << 5) -#define GPIOKEY_BIT_FNRIGHT (1 << 4) -#define GPIOKEY_BIT_DIRUP (1 << 3) -#define GPIOKEY_BIT_DIRLEFT (1 << 2) -#define GPIOKEY_BIT_DIRRIGHT (1 << 1) -#define GPIOKEY_BIT_DIRDOWN (1 << 0) - -/* the hotkey combination which starts recovery */ -#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \ - GPIOKEY_BIT_DIRDOWN) - -static void gpio_selectrow(gpio512x_t *gpioregs, u32 row) -{ - - if (row) - setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK); - else - clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK); - udelay(10); -} - -static u32 gpio_querykbd(void) -{ - immap_t *im; - gpio512x_t *gpioregs; - u32 keybits; - u32 input; - - im = (immap_t *)CONFIG_SYS_IMMR; - gpioregs = &im->gpio; - keybits = 0; - - /* query upper row */ - gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER); - input = in_be32(&gpioregs->gpdat); - if ((input & GPIOKEY_COL0_BITMASK) == 0) - keybits |= GPIOKEY_BIT_FNLEFT; - if ((input & GPIOKEY_COL1_BITMASK) == 0) - keybits |= GPIOKEY_BIT_DIRUP; - if ((input & GPIOKEY_COL2_BITMASK) == 0) - keybits |= GPIOKEY_BIT_FNRIGHT; - - /* query lower row */ - gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER); - input = in_be32(&gpioregs->gpdat); - if ((input & GPIOKEY_COL0_BITMASK) == 0) - keybits |= GPIOKEY_BIT_DIRLEFT; - if ((input & GPIOKEY_COL1_BITMASK) == 0) - keybits |= GPIOKEY_BIT_DIRRIGHT; - if ((input & GPIOKEY_COL2_BITMASK) == 0) - keybits |= GPIOKEY_BIT_DIRDOWN; - - /* return bit pattern for keys */ - return keybits; -} - -/* excerpt from the recovery's hw_info.h */ - -struct __attribute__ ((__packed__)) eeprom_layout { - char magic[3]; /** 'ifm' */ - u8 len[2]; /** content length without magic/len fields */ - u8 version[3]; /** structure version */ - u8 type; /** type of PCB */ - u8 reserved[0x37]; /** padding up to offset 0x40 */ - u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */ -}; - -#define HW_COMP_MAINCPU 2 - -static struct eeprom_layout eeprom_content; -static int eeprom_is_valid; -static int eeprom_version; - -#define get_eeprom_field_int(name) ({ \ - int value; \ - int idx; \ - value = 0; \ - for (idx = 0; idx < sizeof(name); idx++) { \ - value <<= 8; \ - value |= name[idx]; \ - } \ - value; \ -}) - -static int read_eeprom(void) -{ - return -ENOSYS; -} - -int mac_read_from_eeprom(void) -{ - const u8 *mac; - const char *mac_txt; - - if (read_eeprom()) { - printf("I2C EEPROM read failed.\n"); - return -1; - } - - if (!eeprom_is_valid) { - printf("I2C EEPROM content not valid\n"); - return -1; - } - - mac = NULL; - switch (eeprom_version) { - case 1: - case 2: - mac = (const u8 *)&eeprom_content.macaddress; - break; - } - - if (mac && is_valid_ethaddr(mac)) { - eth_setenv_enetaddr("ethaddr", mac); - if (mac_diag) { - mac_txt = getenv("ethaddr"); - if (mac_txt) - printf("DIAG: MAC value [%s]\n", mac_txt); - else - printf("DIAG: failed to setup MAC env\n"); - } - } - - return 0; -} - -/* - * BEWARE! - * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2 - * which the ADS, Aria or PDM360NG boards are using - * (the steps outlined here refer to the Micron datasheet) - */ -u32 sdram_init_seq[] = { - /* item 6, at least one NOP after CKE went high */ - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - /* item 7, precharge all; item 8, tRP (20ns) */ - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_NOP, - /* item 9, extended mode register; item 10, tMRD 10ns) */ - CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM, - CONFIG_SYS_DDRCMD_NOP, - /* - * item 11, (base) mode register _with_ reset DLL; - * item 12, tMRD (10ns) - */ - CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL | - CONFIG_SYS_MICRON_BMODE_PARAM, - CONFIG_SYS_DDRCMD_NOP, - /* item 13, precharge all; item 14, tRP (20ns) */ - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_NOP, - /* - * item 15, auto refresh (i.e. refresh with CKE held high); - * item 16, tRFC (70ns) - */ - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - /* - * item 17, auto refresh (i.e. refresh with CKE held high); - * item 18, tRFC (70ns) - */ - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */ - CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM, - CONFIG_SYS_DDRCMD_NOP, - /* - * item 21, "actually done", but make sure 200 DRAM clock cycles - * have passed after DLL reset before READ requests are issued - * (200 cycles at 160MHz -> 1.25 usec) - */ - /* EMPTY, optional, we don't do it */ -}; - -int dram_init(void) -{ - gd->ram_size = fixed_sdram(NULL, sdram_init_seq, - ARRAY_SIZE(sdram_init_seq)); - - return 0; -} - -int misc_init_r(void) -{ - u32 keys; - char *s; - int want_recovery; - - /* setup GPIO directions and initial values */ - gpio_configure(); - - /* - * enforce the start of the recovery system when - * - the appropriate keys were pressed - * - "some" external software told us to - * - a previous installation was aborted or has failed - */ - want_recovery = 0; - keys = gpio_querykbd(); - if (gpio_diag) - printf("GPIO keyboard status [0x%02X]\n", keys); - if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) { - printf("detected recovery request (keyboard)\n"); - want_recovery = 1; - } - s = getenv("want_recovery"); - if ((s != NULL) && (*s != '\0')) { - printf("detected recovery request (environment)\n"); - want_recovery = 1; - } - s = getenv("install_in_progress"); - if ((s != NULL) && (*s != '\0')) { - printf("previous installation has not completed\n"); - want_recovery = 1; - } - s = getenv("install_failed"); - if ((s != NULL) && (*s != '\0')) { - printf("previous installation has failed\n"); - want_recovery = 1; - } - if (want_recovery) { - printf("enforced start of the recovery system\n"); - setenv("bootcmd", "run recovery"); - } - - /* - * boot the recovery system without waiting; boot the - * production system without waiting by default, only - * insert a pause (to provide a chance to get a prompt) - * when GPIO keys were pressed during power on - */ - if (want_recovery) - setenv("bootdelay", "0"); - else if (!keys) - setenv("bootdelay", "0"); - else - setenv("bootdelay", "2"); - - /* get the ethernet MAC from I2C EEPROM */ - mac_read_from_eeprom(); - - return 0; -} - -/* setup specific IO pad configuration */ -static iopin_t ioregs_init[] = { - { /* LPC CS3 */ - offsetof(struct ioctrl512x, io_control_nfc_ce0), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - { /* LPC CS1 */ - offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { /* LPC CS2 */ - offsetof(struct ioctrl512x, io_control_lpc_cs2), 1, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { /* LPC CS4, CS5 */ - offsetof(struct ioctrl512x, io_control_pata_ce1), 2, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - { /* SDHC CLK, CMD, D0, D1, D2, D3 */ - offsetof(struct ioctrl512x, io_control_pata_ior), 6, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - { /* GPIO keyboard */ - offsetof(struct ioctrl512x, io_control_pci_ad30), 4, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO DN1 PF, LCD power, DN2 PF */ - offsetof(struct ioctrl512x, io_control_pci_ad26), 3, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO reset AS-i */ - offsetof(struct ioctrl512x, io_control_pci_ad21), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO reset safety */ - offsetof(struct ioctrl512x, io_control_pci_ad19), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO reset netX */ - offsetof(struct ioctrl512x, io_control_pci_ad16), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO ma2 en */ - offsetof(struct ioctrl512x, io_control_pci_ad15), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO SD CD, SD WP */ - offsetof(struct ioctrl512x, io_control_pci_ad08), 2, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* FEC RX DV */ - offsetof(struct ioctrl512x, io_control_pci_ad06), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(2), - }, - { /* GPIO AS-i prog, AS-i done, LCD backlight */ - offsetof(struct ioctrl512x, io_control_pci_ad05), 3, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO AS-i wdg */ - offsetof(struct ioctrl512x, io_control_pci_req2), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO safety wdg */ - offsetof(struct ioctrl512x, io_control_pci_req1), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO netX wdg */ - offsetof(struct ioctrl512x, io_control_pci_req0), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO IRQ powerfail */ - offsetof(struct ioctrl512x, io_control_pci_inta), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO AS-i PWRD */ - offsetof(struct ioctrl512x, io_control_pci_frame), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO LED0, LED1 */ - offsetof(struct ioctrl512x, io_control_pci_idsel), 2, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */ - offsetof(struct ioctrl512x, io_control_pci_irdy), 3, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* DIU clk */ - offsetof(struct ioctrl512x, io_control_spdif_txclk), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(2), - }, - { /* FEC TX ER, CRS */ - offsetof(struct ioctrl512x, io_control_spdif_tx), 2, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */ - offsetof(struct ioctrl512x, io_control_irq0), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - { /* - * FEC col, tx en, tx clk, txd 0-3, mdc, rx er, - * rdx 3-0, mdio, rx clk - */ - offsetof(struct ioctrl512x, io_control_psc0_0), 15, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - /* optional: make sure PSC3 remains the serial console */ - { /* LPC CS6 */ - offsetof(struct ioctrl512x, io_control_psc3_4), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - /* make sure PSC4 remains available for SPI, - *BUT* PSC4_1 is a GPIO kind of SS! */ - { /* enforce drive strength on the SPI pin */ - offsetof(struct ioctrl512x, io_control_psc4_0), 5, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { - offsetof(struct ioctrl512x, io_control_psc4_1), 1, - IO_PIN_OVER_FMUX, - IO_PIN_FMUX(3), - }, - /* optional: make sure PSC5 remains available for SPI */ - { /* enforce drive strength on the SPI pin */ - offsetof(struct ioctrl512x, io_control_psc5_0), 5, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(1), - }, - { /* LPC TSIZ1 */ - offsetof(struct ioctrl512x, io_control_psc6_0), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(1) | IO_PIN_DS(2), - }, - { /* DIU hsync */ - offsetof(struct ioctrl512x, io_control_psc6_1), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(1), - }, - { /* DIU vsync */ - offsetof(struct ioctrl512x, io_control_psc6_4), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(1), - }, - { /* PSC7, part of DIU RGB */ - offsetof(struct ioctrl512x, io_control_psc7_0), 2, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(1), - }, - { /* PSC7, safety UART */ - offsetof(struct ioctrl512x, io_control_psc7_2), 2, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(0) | IO_PIN_DS(1), - }, - { /* DIU (part of) RGB[] */ - offsetof(struct ioctrl512x, io_control_psc8_3), 16, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(1), - }, - { /* DIU data enable */ - offsetof(struct ioctrl512x, io_control_psc11_4), 1, - IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, - IO_PIN_FMUX(2) | IO_PIN_DS(1), - }, - /* reduce LPB drive strength for improved EMI */ - { /* LPC OE, LPC RW */ - offsetof(struct ioctrl512x, io_control_lpc_oe), 2, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { /* LPC AX03 through LPC AD00 */ - offsetof(struct ioctrl512x, io_control_lpc_ax03), 36, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { /* LPC CS5 */ - offsetof(struct ioctrl512x, io_control_pata_ce2), 1, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { /* SDHC CLK */ - offsetof(struct ioctrl512x, io_control_nfc_wp), 1, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, - { /* SDHC DATA */ - offsetof(struct ioctrl512x, io_control_nfc_ale), 4, - IO_PIN_OVER_DRVSTR, - IO_PIN_DS(2), - }, -}; - -int checkboard(void) -{ - puts("Board: ifm AC14xx\n"); - - /* initialize function mux & slew rate IO inter alia on IO Pins */ - iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init)); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/ifm/o2dnt2/Kconfig b/board/ifm/o2dnt2/Kconfig deleted file mode 100644 index e9d32ddc54..0000000000 --- a/board/ifm/o2dnt2/Kconfig +++ /dev/null @@ -1,77 +0,0 @@ -if TARGET_O2D - -config SYS_BOARD - default "o2dnt2" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "o2d" - -endif - -if TARGET_O2D300 - -config SYS_BOARD - default "o2dnt2" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "o2d300" - -endif - -if TARGET_O2DNT2 - -config SYS_BOARD - default "o2dnt2" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "o2dnt2" - -endif - -if TARGET_O2I - -config SYS_BOARD - default "o2dnt2" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "o2i" - -endif - -if TARGET_O2MNT - -config SYS_BOARD - default "o2dnt2" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "o2mnt" - -endif - -if TARGET_O3DNT - -config SYS_BOARD - default "o2dnt2" - -config SYS_VENDOR - default "ifm" - -config SYS_CONFIG_NAME - default "o3dnt" - -endif diff --git a/board/ifm/o2dnt2/MAINTAINERS b/board/ifm/o2dnt2/MAINTAINERS deleted file mode 100644 index 002f89e729..0000000000 --- a/board/ifm/o2dnt2/MAINTAINERS +++ /dev/null @@ -1,20 +0,0 @@ -O2DNT2 BOARD -M: Anatolij Gustschin <agust@denx.de> -S: Maintained -F: board/ifm/o2dnt2/ -F: include/configs/o2d.h -F: configs/O2D_defconfig -F: include/configs/o2d300.h -F: configs/O2D300_defconfig -F: include/configs/o2dnt2.h -F: configs/O2DNT2_defconfig -F: configs/O2DNT2_RAMBOOT_defconfig -F: include/configs/o2i.h -F: configs/O2I_defconfig -F: include/configs/o2mnt.h -F: configs/O2MNT_defconfig -F: configs/O2MNT_O2M110_defconfig -F: configs/O2MNT_O2M112_defconfig -F: configs/O2MNT_O2M113_defconfig -F: include/configs/o3dnt.h -F: configs/O3DNT_defconfig diff --git a/board/ifm/o2dnt2/Makefile b/board/ifm/o2dnt2/Makefile deleted file mode 100644 index 64d6ba8c55..0000000000 --- a/board/ifm/o2dnt2/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2005-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := o2dnt2.o diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c deleted file mode 100644 index 7770806bd2..0000000000 --- a/board/ifm/o2dnt2/o2dnt2.c +++ /dev/null @@ -1,388 +0,0 @@ -/* - * Partially derived from board code for digsyMTC, - * (C) Copyright 2009 - * Grzegorz Bernacki, Semihalf, gjb@semihalf.com - * - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin <agust@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <i2c.h> -#include <miiphy.h> -#include <net.h> -#include <pci.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 - -enum ifm_sensor_type { - O2DNT = 0x00, /* !< O2DNT 32MB */ - O2DNT2 = 0x01, /* !< O2DNT2 64MB */ - O3DNT = 0x02, /* !< O3DNT 32MB */ - O3DNT_MIN = 0x40, /* !< O3DNT Minerva 32MB */ - UNKNOWN = 0xff, /* !< Unknow sensor */ -}; - -static enum ifm_sensor_type gt_ifm_sensor_type; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start(int hi_addr) -{ - struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - long control = SDRAM_CONTROL | hi_addr_bit; - - /* unlock mode register */ - out_be32(&sdram->ctrl, control | 0x80000000); - - /* precharge all banks */ - out_be32(&sdram->ctrl, control | 0x80000002); - - /* auto refresh */ - out_be32(&sdram->ctrl, control | 0x80000004); - - /* set mode register */ - out_be32(&sdram->mode, SDRAM_MODE); - - /* normal operation */ - out_be32(&sdram->ctrl, control); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if - * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. - */ -int dram_init(void) -{ - struct mpc5xxx_mmap_ctl *mmap_ctl = - (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; - struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; - - if (gt_ifm_sensor_type == O2DNT2) { - /* activate SDRAM CS1 */ - setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000); - } - -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */ - out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */ - - /* setup config registers */ - out_be32(&sdram->config1, SDRAM_CONFIG1); - out_be32(&sdram->config2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32(&mmap_ctl->sdram0, - (0x13 + __builtin_ffs(dramsize >> 20) - 1)); - } else { - out_be32(&mmap_ctl->sdram0, 0); /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), - 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), - 0x80000000); - } - - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) - dramsize2 = 0; - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - out_be32(&mmap_ctl->sdram1, (dramsize | - (0x13 + __builtin_ffs(dramsize2 >> 20) - 1))); - } else { - out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF; - if (dramsize2 >= 0x13) - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - else - dramsize2 = 0; - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) - out_be32(&sdram->sdelay, 0x04); - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - - -#define GPT_GPIO_IN 0x4 - -int checkboard(void) -{ - struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT; - unsigned char board_config = 0; - int i; - - /* switch gpt0 - gpt7 to input */ - for (i = 0; i < 7; i++) - out_be32(&gpt[i].emsr, GPT_GPIO_IN); - - /* get configuration byte on timer-port */ - for (i = 0; i < 7; i++) - board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i); - - puts("Board: "); - - switch (board_config) { - case 0: - puts("O2DNT\n"); - gt_ifm_sensor_type = O2DNT; - break; - case 1: - puts("O3DNT\n"); - gt_ifm_sensor_type = O3DNT; - break; - case 2: - puts("O2DNT2\n"); - gt_ifm_sensor_type = O2DNT2; - break; - case 64: - puts("O3DNT Minerva\n"); - gt_ifm_sensor_type = O3DNT_MIN; - break; - default: - puts("Unknown\n"); - gt_ifm_sensor_type = UNKNOWN; - break; - } - - return 0; -} - -int board_early_init_r(void) -{ - struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB; - - /* - * Now, when we are in RAM, enable flash write access for detection - * process. Note that CS_BOOT cannot be cleared when executing in flash. - */ - clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */ - /* disable CS_BOOT */ - clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25)); - /* enable CS0 */ - setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16)); - - return 0; -} - -#define MIIM_LXT971_LED_CFG_REG 0x14 -#define LXT971_LED_CFG_LINK_STATUS 0x4000 -#define LXT971_LED_CFG_RX_TX_ACTIVITY 0x0700 -#define LXT971_LED_CFG_LINK_ACTIVITY 0x00D0 -#define LXT971_LED_CFG_PULSE_STRETCH 0x0002 -/* - * Additional PHY intialization after reset in mpc5xxx_fec_init_phy() - */ -void reset_phy(void) -{ - /* - * Set LED configuration bits. - * It can't be done in misc_init_r() since FEC is not - * initialized at this time. Therefore we do it here. - */ - miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG, - LXT971_LED_CFG_LINK_STATUS | - LXT971_LED_CFG_RX_TX_ACTIVITY | - LXT971_LED_CFG_LINK_ACTIVITY | - LXT971_LED_CFG_PULSE_STRETCH); -} - -#if defined(CONFIG_POST) -/* - * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 - * is left open, no keypress is detected. - */ -int post_hotkeys_pressed(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO; - - /* - * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in - * CODEC or UART mode. Consumer IrDA should still be possible. - */ - clrbits_be32(&gpio->port_config, 0x07000000); - setbits_be32(&gpio->port_config, 0x03000000); - - /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ - setbits_be32(&gpio->simple_gpioe, 0x20000000); - - /* Configure GPIO_IRDA_1 as input */ - clrbits_be32(&gpio->simple_ddr, 0x20000000); - - return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1; -} -#endif - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) -static void ft_adapt_flash_base(void *blob) -{ - flash_info_t *dev = &flash_info[0]; - int off; - struct fdt_property *prop; - int len; - u32 *reg, *reg2; - - off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb"); - if (off < 0) { - printf("Could not find fsl,mpc5200b-lpb node.\n"); - return; - } - - /* found compatible property */ - prop = fdt_get_property_w(blob, off, "ranges", &len); - if (prop) { - reg = reg2 = (u32 *)&prop->data[0]; - - reg[2] = dev->start[0]; - reg[3] = dev->size; - fdt_setprop(blob, off, "ranges", reg2, len); - } else - printf("Could not find ranges\n"); -} - -extern ulong flash_get_size(phys_addr_t base, int banknum); - -/* Update the flash baseaddr settings */ -int update_flash_size(int flash_size) -{ - struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; - flash_info_t *dev; - int i; - int size = 0; - unsigned long base = 0x0; - u32 *cs_reg = (u32 *)&mm->cs0_start; - - for (i = 0; i < 2; i++) { - dev = &flash_info[i]; - - if (dev->size) { - /* calculate new base addr for this chipselect */ - base -= dev->size; - out_be32(cs_reg, START_REG(base)); - cs_reg++; - out_be32(cs_reg, STOP_REG(base, dev->size)); - cs_reg++; - /* recalculate the sectoraddr in the cfi driver */ - size += flash_get_size(base, i); - } - } - flash_protect_default(); - gd->bd->bi_flashstart = base; - return 0; -} -#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */ - -int ft_board_setup(void *blob, bd_t *bd) -{ - int phy_addr = CONFIG_PHY_ADDR; - char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0"; - - ft_cpu_setup(blob, bd); - -#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) -#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE - /* Update reg property in all nor flash nodes too */ - fdt_fixup_nor_flash_size(blob); -#endif - ft_adapt_flash_base(blob); -#endif - /* fix up the phy address */ - do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index 3f45e4e4b8..653246615f 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -11,6 +11,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/mach-types.h> #include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/inka4x0/Kconfig b/board/inka4x0/Kconfig deleted file mode 100644 index 94a41f01a5..0000000000 --- a/board/inka4x0/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_INKA4X0 - -config SYS_BOARD - default "inka4x0" - -config SYS_CONFIG_NAME - default "inka4x0" - -endif diff --git a/board/inka4x0/MAINTAINERS b/board/inka4x0/MAINTAINERS deleted file mode 100644 index e8cec73a1a..0000000000 --- a/board/inka4x0/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -INKA4X0 BOARD -M: Anatolij Gustschin <agust@denx.de> -S: Maintained -F: board/inka4x0/ -F: include/configs/inka4x0.h -F: configs/inka4x0_defconfig diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile deleted file mode 100644 index c9a3540799..0000000000 --- a/board/inka4x0/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2009 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := inka4x0.o inkadiag.o diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c deleted file mode 100644 index 88cae59e8f..0000000000 --- a/board/inka4x0/inka4x0.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Andreas Pfefferle, DENX Software Engineering, ap@denx.de. - * - * (C) Copyright 2009 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/io.h> -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> - -#if defined(CONFIG_DDR_MT46V16M16) -#include "mt46v16m16-75.h" -#elif defined(CONFIG_SDR_MT48LC16M16A2) -#include "mt48lc16m16a2-75.h" -#elif defined(CONFIG_DDR_MT46V32M16) -#include "mt46v32m16.h" -#elif defined(CONFIG_DDR_HYB25D512160BF) -#include "hyb25d512160bf.h" -#elif defined(CONFIG_DDR_K4H511638C) -#include "k4h511638c.h" -#else -#error "INKA4x0 SDRAM: invalid chip type specified!" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit); - - /* precharge all banks */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit); - -#if SDRAM_DDR - /* set mode register: extended mode */ - out_be32(&sdram->mode, SDRAM_EMODE); - - /* set mode register: reset DLL */ - out_be32(&sdram->mode, SDRAM_MODE | 0x04000000); -#endif - - /* precharge all banks */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit); - - /* auto refresh */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit); - - /* set mode register */ - out_be32(&sdram->mode, SDRAM_MODE); - - /* normal operation */ - out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - volatile struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *) MPC5XXX_CDM; - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *) MPC5XXX_SDRAM; - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - long test1, test2; - - /* setup SDRAM chip selects */ - out_be32(&mm->sdram0, 0x0000001c); /* 512MB at 0x0 */ - out_be32(&mm->sdram1, 0x40000000); /* disabled */ - - /* setup config registers */ - out_be32(&sdram->config1, SDRAM_CONFIG1); - out_be32(&sdram->config2, SDRAM_CONFIG2); - -#if SDRAM_DDR - /* set tap delay */ - out_be32(&cdm->porcfg, SDRAM_TAPDELAY); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32(&mm->sdram0, 0x13 + - __builtin_ffs(dramsize >> 20) - 1); - } else { - out_be32(&mm->sdram0, 0); /* disabled */ - } - - out_be32(&mm->sdram1, dramsize); /* disabled */ -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32(&mm->sdram0) & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } -#endif /* CONFIG_SYS_RAMBOOT */ - - gd->ram_size = dramsize; - - return 0; -} - -int checkboard (void) -{ - puts ("Board: INKA 4X0\n"); - return 0; -} - -void flash_preinit(void) -{ - volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB; - - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT (CS0) cannot be cleared when - * executing in flash. - */ - clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */ -} - -int misc_init_f (void) -{ - volatile struct mpc5xxx_gpio *gpio = - (struct mpc5xxx_gpio *) MPC5XXX_GPIO; - volatile struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - volatile struct mpc5xxx_gpt *gpt; - char tmp[10]; - int i, br; - - i = getenv_f("brightness", tmp, sizeof(tmp)); - br = (i > 0) - ? (int) simple_strtoul (tmp, NULL, 10) - : CONFIG_SYS_BRIGHTNESS; - if (br > 255) - br = 255; - - /* Initialize GPIO output pins. - */ - /* Configure GPT as GPIO output (and set them as they control low-active LEDs */ - for (i = 0; i <= 5; i++) { - gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10)); - out_be32(&gpt->emsr, 0x34); - } - - /* Configure GPT7 as PWM timer, 1kHz, no ints. */ - gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10)); - out_be32(&gpt->emsr, 0); /* Disable */ - out_be32(&gpt->cir, 0x020000fe); - out_be32(&gpt->pwmcr, (br << 16)); - out_be32(&gpt->emsr, 0x3); /* Enable PWM mode and start */ - - /* Configure PSC3_6,7 as GPIO output */ - setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 | - MPC5XXX_GPIO_SIMPLE_PSC3_7); - setbits_be32(&gpio->simple_ddr, MPC5XXX_GPIO_SIMPLE_PSC3_6 | - MPC5XXX_GPIO_SIMPLE_PSC3_7); - - /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */ - setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_6 | - MPC5XXX_GPIO_WKUP_7 | - MPC5XXX_GPIO_WKUP_PSC3_9); - setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_6 | - MPC5XXX_GPIO_WKUP_7 | - MPC5XXX_GPIO_WKUP_PSC3_9); - - /* Set LR mirror bit because it is low-active */ - setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_7); - - /* Reset Coral-P graphics controller */ - setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC3_9); - - /* Enable display backlight */ - clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8); - setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8); - setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_8); - setbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_8); - - /* - * Configure three wire serial interface to RTC (PSC1_4, - * PSC2_4, PSC3_4, PSC3_5) - */ - setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4 | - MPC5XXX_GPIO_WKUP_PSC2_4); - setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4 | - MPC5XXX_GPIO_WKUP_PSC2_4); - clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4); - clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 | - MPC5XXX_GPIO_SINT_PSC3_5); - setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 | - MPC5XXX_GPIO_SINT_PSC3_5); - setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_5); - clrbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_5); - - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c deleted file mode 100644 index 4c43205129..0000000000 --- a/board/inka4x0/inkadiag.c +++ /dev/null @@ -1,465 +0,0 @@ -/* - * (C) Copyright 2008, 2009 Andreas Pfefferle, - * DENX Software Engineering, ap@denx.de. - * (C) Copyright 2009 Detlev Zundel, - * DENX Software Engineering, dzu@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/io.h> -#include <common.h> -#include <config.h> -#include <console.h> -#include <mpc5xxx.h> -#include <pci.h> - -#include <command.h> - -/* This is needed for the includes in ns16550.h */ -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#include <ns16550.h> - -#define GPIO_BASE ((u_char *)CONFIG_SYS_CS3_START) - -#define DIGIN_TOUCHSCR_MASK 0x00003000 /* Inputs 12-13 */ -#define DIGIN_KEYB_MASK 0x00010000 /* Input 16 */ - -#define DIGIN_DRAWER_SW1 0x00400000 /* Input 22 */ -#define DIGIN_DRAWER_SW2 0x00800000 /* Input 23 */ - -#define DIGIO_LED0 0x00000001 /* Output 0 */ -#define DIGIO_LED1 0x00000002 /* Output 1 */ -#define DIGIO_LED2 0x00000004 /* Output 2 */ -#define DIGIO_LED3 0x00000008 /* Output 3 */ -#define DIGIO_LED4 0x00000010 /* Output 4 */ -#define DIGIO_LED5 0x00000020 /* Output 5 */ - -#define DIGIO_DRAWER1 0x00000100 /* Output 8 */ -#define DIGIO_DRAWER2 0x00000200 /* Output 9 */ - -#define SERIAL_PORT_BASE ((u_char *)CONFIG_SYS_CS2_START) - -#define PSC_OP1_RTS 0x01 -#define PSC_OP0_RTS 0x01 - -/* - * Table with supported baudrates (defined in inka4x0.h) - */ -static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; -#define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0])) - -static unsigned int inka_digin_get_input(void) -{ - return in_8(GPIO_BASE + 0) << 0 | in_8(GPIO_BASE + 1) << 8 | - in_8(GPIO_BASE + 2) << 16 | in_8(GPIO_BASE + 3) << 24; -} - -#define LED_HIGH(NUM) \ - do { \ - setbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \ - } while (0) - -#define LED_LOW(NUM) \ - do { \ - clrbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \ - } while (0) - -#define CHECK_LED(NUM) \ - do { \ - if (state & (1 << NUM)) { \ - LED_HIGH(NUM); \ - } else { \ - LED_LOW(NUM); \ - } \ - } while (0) - -static void inka_digio_set_output(unsigned int state, int which) -{ - volatile struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (which == 0) { - /* other */ - CHECK_LED(0); - CHECK_LED(1); - CHECK_LED(2); - CHECK_LED(3); - CHECK_LED(4); - CHECK_LED(5); - } else { - if (which == 1) { - /* drawer1 */ - if (state) { - clrbits_be32(&gpio->simple_dvo, 0x1000); - udelay(1); - setbits_be32(&gpio->simple_dvo, 0x1000); - } else { - setbits_be32(&gpio->simple_dvo, 0x1000); - udelay(1); - clrbits_be32(&gpio->simple_dvo, 0x1000); - } - } - if (which == 2) { - /* drawer 2 */ - if (state) { - clrbits_be32(&gpio->simple_dvo, 0x2000); - udelay(1); - setbits_be32(&gpio->simple_dvo, 0x2000); - } else { - setbits_be32(&gpio->simple_dvo, 0x2000); - udelay(1); - clrbits_be32(&gpio->simple_dvo, 0x2000); - } - } - } - udelay(1); -} - -static int do_inkadiag_io(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) { - unsigned int state, val; - - switch (argc) { - case 3: - /* Write a value */ - val = simple_strtol(argv[2], NULL, 16); - - if (strcmp(argv[1], "drawer1") == 0) { - inka_digio_set_output(val, 1); - } else if (strcmp(argv[1], "drawer2") == 0) { - inka_digio_set_output(val, 2); - } else if (strcmp(argv[1], "other") == 0) - inka_digio_set_output(val, 0); - else { - printf("Invalid argument: %s\n", argv[1]); - return -1; - } - /* fall through */ - case 2: - /* Read a value */ - state = inka_digin_get_input(); - - if (strcmp(argv[1], "drawer1") == 0) { - val = (state & DIGIN_DRAWER_SW1) >> (ffs(DIGIN_DRAWER_SW1) - 1); - } else if (strcmp(argv[1], "drawer2") == 0) { - val = (state & DIGIN_DRAWER_SW2) >> (ffs(DIGIN_DRAWER_SW2) - 1); - } else if (strcmp(argv[1], "other") == 0) { - val = ((state & DIGIN_KEYB_MASK) >> (ffs(DIGIN_KEYB_MASK) - 1)) - | (state & DIGIN_TOUCHSCR_MASK) >> (ffs(DIGIN_TOUCHSCR_MASK) - 2); - } else { - printf("Invalid argument: %s\n", argv[1]); - return -1; - } - printf("exit code: 0x%X\n", val); - return 0; - default: - return cmd_usage(cmdtp); - } - - return -1; -} - -DECLARE_GLOBAL_DATA_PTR; - -static int ser_init(volatile struct mpc5xxx_psc *psc, int baudrate) -{ - unsigned long baseclk; - int div; - - /* reset PSC */ - out_8(&psc->command, PSC_SEL_MODE_REG_1); - - /* select clock sources */ - - out_be16(&psc->psc_clock_select, 0); - baseclk = (gd->arch.ipb_clk + 16) / 32; - - /* switch to UART mode */ - out_be32(&psc->sicr, 0); - - /* configure parity, bit length and so on */ - - out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE); - out_8(&psc->mode, PSC_MODE_ONE_STOP); - - /* set up UART divisor */ - div = (baseclk + (baudrate / 2)) / baudrate; - out_8(&psc->ctur, (div >> 8) & 0xff); - out_8(&psc->ctlr, div & 0xff); - - /* disable all interrupts */ - out_be16(&psc->psc_imr, 0); - - /* reset and enable Rx/Tx */ - out_8(&psc->command, PSC_RST_RX); - out_8(&psc->command, PSC_RST_TX); - out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE); - - return 0; -} - -static void ser_putc(volatile struct mpc5xxx_psc *psc, const char c) -{ - /* Wait 1 second for last character to go. */ - int i = 0; - - while (!(psc->psc_status & PSC_SR_TXEMP) && (i++ < 1000000/10)) - udelay(10); - psc->psc_buffer_8 = c; - -} - -static int ser_getc(volatile struct mpc5xxx_psc *psc) -{ - /* Wait for a character to arrive. */ - int i = 0; - - while (!(in_be16(&psc->psc_status) & PSC_SR_RXRDY) && (i++ < 1000000/10)) - udelay(10); - - return in_8(&psc->psc_buffer_8); -} - -static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) { - volatile struct NS16550 *uart; - volatile struct mpc5xxx_psc *psc; - unsigned int num, mode; - int combrd, baudrate, i, j, len; - int address; - - if (argc < 5) - return cmd_usage(cmdtp); - - argc--; - argv++; - - num = simple_strtol(argv[0], NULL, 0); - if (num < 0 || num > 11) { - printf("invalid argument for num: %d\n", num); - return -1; - } - - mode = simple_strtol(argv[1], NULL, 0); - - combrd = 0; - baudrate = simple_strtoul(argv[2], NULL, 10); - for (i=0; i<N_BAUDRATES; ++i) { - if (baudrate == baudrate_table[i]) - break; - } - if (i == N_BAUDRATES) { - printf("## Baudrate %d bps not supported\n", - baudrate); - return 1; - } - combrd = 115200 / baudrate; - - uart = (struct NS16550 *)(SERIAL_PORT_BASE + (num << 3)); - - printf("Testing uart %d.\n\n", num); - - if ((num >= 0) && (num <= 7)) { - if (mode & 1) { - /* turn on 'loopback' mode */ - out_8(&uart->mcr, UART_MCR_LOOP); - } else { - /* - * establish the UART's operational parameters - * set DLAB=1, so rbr accesses DLL - */ - out_8(&uart->lcr, UART_LCR_DLAB); - /* set baudrate */ - out_8(&uart->rbr, combrd); - /* set data-format: 8-N-1 */ - out_8(&uart->lcr, UART_LCR_WLS_8); - } - - if (mode & 2) { - /* set request to send */ - out_8(&uart->mcr, UART_MCR_RTS); - udelay(10); - /* check clear to send */ - if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00) - return -1; - } - if (mode & 4) { - /* set data terminal ready */ - out_8(&uart->mcr, UART_MCR_DTR); - udelay(10); - /* check data set ready and carrier detect */ - if ((in_8(&uart->msr) & (UART_MSR_DSR | UART_MSR_DCD)) - != (UART_MSR_DSR | UART_MSR_DCD)) - return -1; - } - - /* write each message-character, read it back, and display it */ - for (i = 0, len = strlen(argv[3]); i < len; ++i) { - j = 0; - while ((in_8(&uart->lsr) & UART_LSR_THRE) == 0x00) { - if (j++ > CONFIG_SYS_HZ) - break; - udelay(10); - } - out_8(&uart->rbr, argv[3][i]); - j = 0; - while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) { - if (j++ > CONFIG_SYS_HZ) - break; - udelay(10); - } - printf("%c", in_8(&uart->rbr)); - } - printf("\n\n"); - out_8(&uart->mcr, 0x00); - } else { - address = 0; - - switch (num) { - case 8: - address = MPC5XXX_PSC6; - break; - case 9: - address = MPC5XXX_PSC3; - break; - case 10: - address = MPC5XXX_PSC2; - break; - case 11: - address = MPC5XXX_PSC1; - break; - } - psc = (struct mpc5xxx_psc *)address; - ser_init(psc, simple_strtol(argv[2], NULL, 0)); - if (mode & 2) { - /* set request to send */ - out_8(&psc->op0, PSC_OP0_RTS); - udelay(10); - /* check clear to send */ - if ((in_8(&psc->ip) & PSC_IPCR_CTS) == 0) - return -1; - } - len = strlen(argv[3]); - for (i = 0; i < len; ++i) { - ser_putc(psc, argv[3][i]); - printf("%c", ser_getc(psc)); - } - printf("\n\n"); - } - return 0; -} - -#define BUZZER_GPT (MPC5XXX_GPT + 0x60) /* GPT6 */ -static void buzzer_turn_on(unsigned int freq) -{ - volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT); - - const u32 prescale = gd->arch.ipb_clk / freq / 128; - const u32 count = 128; - const u32 width = 64; - - gpt->cir = (prescale << 16) | count; - gpt->pwmcr = width << 16; - gpt->emsr = 3; /* Timer enabled for PWM */ -} - -static void buzzer_turn_off(void) -{ - volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT); - - gpt->emsr = 0; -} - -static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) { - - unsigned int period, freq; - int prev, i; - - if (argc != 3) - return cmd_usage(cmdtp); - - argc--; - argv++; - - period = simple_strtol(argv[0], NULL, 0); - if (!period) - printf("Zero period is senseless\n"); - argc--; - argv++; - - freq = simple_strtol(argv[0], NULL, 0); - /* avoid zero prescale in buzzer_turn_on() */ - if (freq > gd->arch.ipb_clk / 128) { - printf("%dHz exceeds maximum (%ldHz)\n", freq, - gd->arch.ipb_clk / 128); - } else if (!freq) - printf("Zero frequency is senseless\n"); - else - buzzer_turn_on(freq); - - clear_ctrlc(); - prev = disable_ctrlc(0); - - printf("Buzzing for %d ms. Type ^C to abort!\n\n", period); - - i = 0; - while (!ctrlc() && (i++ < CONFIG_SYS_HZ)) - udelay(period); - - clear_ctrlc(); - disable_ctrlc(prev); - - buzzer_turn_off(); - - return 0; -} - -static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - -cmd_tbl_t cmd_inkadiag_sub[] = { - U_BOOT_CMD_MKENT(io, 1, 1, do_inkadiag_io, "read digital input", - "<drawer1|drawer2|other> [value] - get or set specified signal"), - U_BOOT_CMD_MKENT(serial, 4, 1, do_inkadiag_serial, "test serial port", - "<num> <mode> <baudrate> <msg> - test uart num [0..11] in mode\n" - "and baudrate with msg"), - U_BOOT_CMD_MKENT(buzzer, 2, 1, do_inkadiag_buzzer, "activate buzzer", - "<period> <freq> - turn buzzer on for period ms with freq hz"), - U_BOOT_CMD_MKENT(help, 4, 1, do_inkadiag_help, "get help", - "[command] - get help for command"), -}; - -static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) { - extern int _do_help (cmd_tbl_t *cmd_start, int cmd_items, - cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]); - /* do_help prints command name - we prepend inkadiag to our subcommands! */ -#ifdef CONFIG_SYS_LONGHELP - puts ("inkadiag "); -#endif - return _do_help(&cmd_inkadiag_sub[0], - ARRAY_SIZE(cmd_inkadiag_sub), cmdtp, flag, argc, argv); -} - -static int do_inkadiag(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) { - cmd_tbl_t *c; - - c = find_cmd_tbl(argv[1], &cmd_inkadiag_sub[0], ARRAY_SIZE(cmd_inkadiag_sub)); - - if (c) { - argc--; - argv++; - return c->cmd(c, flag, argc, argv); - } else { - /* Unrecognized command */ - return cmd_usage(cmdtp); - } -} - -U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag, - "inkadiag - inka diagnosis\n", - "[inkadiag what ...]\n" - " - perform a diagnosis on inka hardware\n" - "'inkadiag' performs hardware tests."); diff --git a/board/inka4x0/k4h511638c.h b/board/inka4x0/k4h511638c.h deleted file mode 100644 index 054ddafd59..0000000000 --- a/board/inka4x0/k4h511638c.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2007 Semihalf - * Written by Marian Balakowicz <m8@semihalf.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x46770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h deleted file mode 100644 index 23fc6f06be..0000000000 --- a/board/inka4x0/mt46v16m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h deleted file mode 100644 index f16f450d01..0000000000 --- a/board/inka4x0/mt46v32m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2007 Semihalf - * Written by Marian Balakowicz <m8@semihalf.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 -#define SDRAM_CONFIG1 0x73711930 -#define SDRAM_CONFIG2 0x46770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/inka4x0/mt48lc16m16a2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c index 94b22edd57..99aed53100 100644 --- a/board/intel/minnowmax/minnowmax.c +++ b/board/intel/minnowmax/minnowmax.c @@ -5,9 +5,62 @@ */ #include <common.h> +#include <dm.h> #include <asm/gpio.h> +#include <dm/device-internal.h> +#include <dm/uclass-internal.h> + +#define GPIO_BANKE_NAME "gpioe" int arch_early_init_r(void) { return 0; } + +int misc_init_r(void) +{ + struct udevice *dev; + struct gpio_desc desc; + int ret; + + /* + * Turn on USB VBUS for the two USB ports on the board. + * Each port's VBUS is controlled by a GPIO pin. + */ + + ret = uclass_find_device_by_name(UCLASS_GPIO, GPIO_BANKE_NAME, &dev); + if (ret) { + debug("%s: GPIO %s device cannot be not found (ret=%d)\n", + __func__, GPIO_BANKE_NAME, ret); + return ret; + } + + ret = device_probe(dev); + if (ret) { + debug("%s: GPIO %s device probe failed (ret=%d)\n", + __func__, GPIO_BANKE_NAME, ret); + return ret; + } + + desc.dev = dev; + desc.flags = GPIOD_IS_OUT; + + /* GPIO E8 controls the bottom port */ + desc.offset = 8; + + ret = dm_gpio_request(&desc, "usb_host_en0"); + if (ret) + return ret; + dm_gpio_set_value(&desc, 1); + + /* GPIO E9 controls the upper port */ + desc.offset = 9; + + ret = dm_gpio_request(&desc, "usb_host_en1"); + if (ret) + return ret; + + dm_gpio_set_value(&desc, 1); + + return 0; +} diff --git a/board/intercontrol/digsy_mtc/Kconfig b/board/intercontrol/digsy_mtc/Kconfig deleted file mode 100644 index 1cf2275d81..0000000000 --- a/board/intercontrol/digsy_mtc/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DIGSY_MTC - -config SYS_BOARD - default "digsy_mtc" - -config SYS_VENDOR - default "intercontrol" - -config SYS_CONFIG_NAME - default "digsy_mtc" - -endif diff --git a/board/intercontrol/digsy_mtc/MAINTAINERS b/board/intercontrol/digsy_mtc/MAINTAINERS deleted file mode 100644 index c83ebcdab9..0000000000 --- a/board/intercontrol/digsy_mtc/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -DIGSY_MTC BOARD -M: Werner Pfister <Pfister_Werner@intercontrol.de> -S: Maintained -F: board/intercontrol/digsy_mtc/ -F: include/configs/digsy_mtc.h -F: configs/digsy_mtc_defconfig -F: configs/digsy_mtc_RAMBOOT_defconfig -F: configs/digsy_mtc_rev5_defconfig -F: configs/digsy_mtc_rev5_RAMBOOT_defconfig diff --git a/board/intercontrol/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile deleted file mode 100644 index 4d13eadf5b..0000000000 --- a/board/intercontrol/digsy_mtc/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := digsy_mtc.o -obj-$(CONFIG_VIDEO) += cmd_disp.o diff --git a/board/intercontrol/digsy_mtc/cmd_disp.c b/board/intercontrol/digsy_mtc/cmd_disp.c deleted file mode 100644 index 2ffa8bfe40..0000000000 --- a/board/intercontrol/digsy_mtc/cmd_disp.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2011 DENX Software Engineering, - * Anatolij Gustschin <agust@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <mpc5xxx.h> -#include <asm/io.h> - -#define GPIO_USB1_0 0x00010000 - -static int cmd_disp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - - if (argc < 2) { - printf("%s\n", - in_be32(&gpio->simple_dvo) & GPIO_USB1_0 ? "on" : "off"); - return 0; - } - - if (!strncmp(argv[1], "on", 2)) { - setbits_be32(&gpio->simple_dvo, GPIO_USB1_0); - } else if (!strncmp(argv[1], "off", 3)) { - clrbits_be32(&gpio->simple_dvo, GPIO_USB1_0); - } else { - cmd_usage(cmdtp); - return 1; - } - return 0; -} - -U_BOOT_CMD(disp, 2, 1, cmd_disp, - "disp [on/off] - switch display on/off", - "\n - print display on/off status\n" - "on\n - turn on\n" - "off\n - turn off\n" -); diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c deleted file mode 100644 index 6c33eeb022..0000000000 --- a/board/intercontrol/digsy_mtc/digsy_mtc.c +++ /dev/null @@ -1,477 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2005-2009 - * Modified for InterControl digsyMTC MPC5200 board by - * Frank Bodammer, GCD Hard- & Software GmbH, - * frank.bodammer@gcd-solutions.de - * - * (C) Copyright 2009 - * Grzegorz Bernacki, Semihalf, gjb@semihalf.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <net.h> -#include <pci.h> -#include <asm/processor.h> -#include <asm/io.h> -#include "eeprom.h" -#if defined(CONFIG_DIGSY_REV5) -#include "is45s16800a2.h" -#include <mtd/cfi_flash.h> -#include <flash.h> -#else -#include "is42s16800a-7t.h" -#endif -#include <libfdt.h> -#include <fdt_support.h> -#include <i2c.h> -#include <mb862xx.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern int usb_cpu_init(void); - -#if defined(CONFIG_DIGSY_REV5) -/* - * The M29W128GH needs a special reset command function, - * details see the doc/README.cfi file - */ -void flash_cmd_reset(flash_info_t *info) -{ - flash_write_cmd(info, 0, 0, AMD_CMD_RESET); -} -#endif - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - long control = SDRAM_CONTROL | hi_addr_bit; - - /* unlock mode register */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000); - - /* precharge all banks */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); - - /* auto refresh */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004); - - /* set mode register */ - out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); - - /* normal operation */ - out_be32((void *)MPC5XXX_SDRAM_CTRL, control); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if - * CONFIG_SYS_SDRAM_BASE is something other than 0x00000000. - */ - -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */ - out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ - - /* setup config registers */ - out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); - out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, - (0x13 + __builtin_ffs(dramsize >> 20) - 1)); - } else { - out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C); - - /* find RAM size using SDRAM CS1 only */ - test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), - 0x08000000); - dramsize2 = test1; - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) - dramsize2 = 0; - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize | - (0x13 + __builtin_ffs(dramsize2 >> 20) - 1))); - } else { - out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF; - if (dramsize2 >= 0x13) - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - else - dramsize2 = 0; - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) - out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04); - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: InterControl digsyMTC"); -#if defined(CONFIG_DIGSY_REV5) - puts (" rev5"); -#endif - if (i > 0) { - puts(", "); - puts(buf); - } - putc('\n'); - - return 0; -} - -#if defined(CONFIG_VIDEO) - -#define GPIO_USB1_0 0x00010000 /* Power-On pin */ -#define GPIO_USB1_9 0x08 /* PX_~EN pin */ - -#define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */ -#define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */ -#define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */ -#define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */ - -#define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */ - -static void exbo_hw_init(void) -{ - struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - - /* configure IrDA pins (PSC6 port) as gpios */ - gpio->port_config &= 0xFF8FFFFF; - - /* Init for USB1_0, EE_CLK and EE_DI - Low */ - setbits_be32(&gpio->simple_ddr, - GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); - clrbits_be32(&gpio->simple_ode, - GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); - clrbits_be32(&gpio->simple_dvo, - GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); - setbits_be32(&gpio->simple_gpioe, - GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI); - - /* Init for EE_DO, EE_CTS - Input */ - clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS); - setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS); - - /* Init for PX_~EN (USB1_9) - High */ - clrbits_8(&gpio->sint_ode, GPIO_USB1_9); - setbits_8(&gpio->sint_ddr, GPIO_USB1_9); - clrbits_8(&gpio->sint_inten, GPIO_USB1_9); - setbits_8(&gpio->sint_dvo, GPIO_USB1_9); - setbits_8(&gpio->sint_gpioe, GPIO_USB1_9); - - /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */ - out_be32(&gpt[0].emsr, GPT_GPIO_ON); - /* Init for S Switch (GPIO4) - Timer_1 GPIO High */ - out_be32(&gpt[1].emsr, GPT_GPIO_ON); - - /* Power-On camera supply */ - setbits_be32(&gpio->simple_dvo, GPIO_USB1_0); -} -#else -static inline void exbo_hw_init(void) {} -#endif /* CONFIG_VIDEO */ - -int board_early_init_r(void) -{ - /* - * Now, when we are in RAM, enable flash write access for detection - * process. Note that CS_BOOT cannot be cleared when executing in - * flash. - */ - /* disable CS_BOOT */ - clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25)); - /* enable CS1 */ - setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17)); - /* enable CS0 */ - setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16)); - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) - /* Low level USB init, required for proper kernel operation */ - usb_cpu_init(); -#endif - - return (0); -} - -void board_get_enetaddr (uchar * enet) -{ - ushort read = 0; - ushort addr_of_eth_addr = 0; - ushort len_sys = 0; - ushort len_sys_cfg = 0; - - /* check identification word */ - eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2); - if (read != EEPROM_IDENT) - return; - - /* calculate offset of config area */ - eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2); - eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG, - (uchar *)&len_sys_cfg, 2); - addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1; - if (addr_of_eth_addr >= EEPROM_LEN) - return; - - eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6); -} - -int misc_init_r(void) -{ - pci_dev_t devbusfn; - uchar enetaddr[6]; - - /* check if graphic extension board is present */ - devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU, - PCI_DEVICE_ID_CORAL_PA, 0); - if (devbusfn != -1) - exbo_hw_init(); - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#ifdef CONFIG_IDE - -#ifdef CONFIG_IDE_RESET - -void init_ide_reset(void) -{ - debug ("init_ide_reset\n"); - - /* set gpio output value to 1 */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); - /* open drain output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); - /* direction output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); - /* enable gpio */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); - -} - -void ide_set_reset(int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - - /* set gpio output value to 0 */ - clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); - /* open drain output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); - /* direction output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); - /* enable gpio */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); - - udelay(10000); - - /* set gpio output value to 1 */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); - /* open drain output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); - /* direction output */ - setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); - /* enable gpio */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); -} -#endif /* CONFIG_IDE_RESET */ -#endif /* CONFIG_IDE */ - -#ifdef CONFIG_OF_BOARD_SETUP -static void ft_delete_node(void *fdt, const char *compat) -{ - int off = -1; - int ret; - - off = fdt_node_offset_by_compatible(fdt, -1, compat); - if (off < 0) { - printf("Could not find %s node.\n", compat); - return; - } - - ret = fdt_del_node(fdt, off); - if (ret < 0) - printf("Could not delete %s node.\n", compat); -} -#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) -static void ft_adapt_flash_base(void *blob) -{ - flash_info_t *dev = &flash_info[0]; - int off; - struct fdt_property *prop; - int len; - u32 *reg, *reg2; - - off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb"); - if (off < 0) { - printf("Could not find fsl,mpc5200b-lpb node.\n"); - return; - } - - /* found compatible property */ - prop = fdt_get_property_w(blob, off, "ranges", &len); - if (prop) { - reg = reg2 = (u32 *)&prop->data[0]; - - reg[2] = dev->start[0]; - reg[3] = dev->size; - fdt_setprop(blob, off, "ranges", reg2, len); - } else - printf("Could not find ranges\n"); -} - -extern ulong flash_get_size (phys_addr_t base, int banknum); - -/* Update the Flash Baseaddr settings */ -int update_flash_size (int flash_size) -{ - volatile struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; - flash_info_t *dev; - int i; - int size = 0; - unsigned long base = 0x0; - u32 *cs_reg = (u32 *)&mm->cs0_start; - - for (i = 0; i < 2; i++) { - dev = &flash_info[i]; - - if (dev->size) { - /* calculate new base addr for this chipselect */ - base -= dev->size; - out_be32(cs_reg, START_REG(base)); - cs_reg++; - out_be32(cs_reg, STOP_REG(base, dev->size)); - cs_reg++; - /* recalculate the sectoraddr in the cfi driver */ - size += flash_get_size(base, i); - } - } - flash_protect_default(); - gd->bd->bi_flashstart = base; - return 0; -} -#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */ - -int ft_board_setup(void *blob, bd_t *bd) -{ - int phy_addr = CONFIG_PHY_ADDR; - char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0"; - - ft_cpu_setup(blob, bd); - /* - * There are 2 RTC nodes in the DTS, so remove - * the unneeded node here. - */ -#if defined(CONFIG_DIGSY_REV5) - ft_delete_node(blob, "dallas,ds1339"); -#else - ft_delete_node(blob, "mc,rv3029c2"); -#endif -#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) -#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE - /* Update reg property in all nor flash nodes too */ - fdt_fixup_nor_flash_size(blob); -#endif - ft_adapt_flash_base(blob); -#endif - /* fix up the phy address */ - do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/intercontrol/digsy_mtc/eeprom.h b/board/intercontrol/digsy_mtc/eeprom.h deleted file mode 100644 index 17bd034072..0000000000 --- a/board/intercontrol/digsy_mtc/eeprom.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * (C) Copyright 2009 Semihalf. - * Written by: Grzegorz Bernacki <gjb@semihalf.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef CMD_EEPROM_H -#define CMD_EEPROM_H - -#define EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR -#define EEPROM_LEN 1024 /* eeprom length */ -#define EEPROM_IDENT 2408 /* identification word */ -#define EEPROM_ADDR_IDENT 0 /* identification word offset */ -#define EEPROM_ADDR_LEN_SYS 2 /* system area lenght offset */ -#define EEPROM_ADDR_LEN_SYSCFG 4 /* system config area length offset */ -#define EEPROM_ADDR_ETHADDR 23 /* ethernet address offset */ - -#endif diff --git a/board/intercontrol/digsy_mtc/is42s16800a-7t.h b/board/intercontrol/digsy_mtc/is42s16800a-7t.h deleted file mode 100644 index c555d2d623..0000000000 --- a/board/intercontrol/digsy_mtc/is42s16800a-7t.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x505F0000 -#define SDRAM_CONFIG1 0xD2322900 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/intercontrol/digsy_mtc/is45s16800a2.h b/board/intercontrol/digsy_mtc/is45s16800a2.h deleted file mode 100644 index c42ba38e34..0000000000 --- a/board/intercontrol/digsy_mtc/is45s16800a2.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * based on: - * (C) Copyright 2004-2009 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x50470000 -#define SDRAM_CONFIG1 0xD2322900 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/ipek01/Kconfig b/board/ipek01/Kconfig deleted file mode 100644 index 34e094d79d..0000000000 --- a/board/ipek01/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_IPEK01 - -config SYS_BOARD - default "ipek01" - -config SYS_CONFIG_NAME - default "ipek01" - -endif diff --git a/board/ipek01/MAINTAINERS b/board/ipek01/MAINTAINERS deleted file mode 100644 index 906d39ef80..0000000000 --- a/board/ipek01/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -IPEK01 BOARD -M: Anatolij Gustschin <agust@denx.de> -S: Maintained -F: board/ipek01/ -F: include/configs/ipek01.h -F: configs/ipek01_defconfig diff --git a/board/ipek01/Makefile b/board/ipek01/Makefile deleted file mode 100644 index a786ab2118..0000000000 --- a/board/ipek01/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ipek01.o diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c deleted file mode 100644 index 133db8c6bd..0000000000 --- a/board/ipek01/ipek01.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2006 - * MicroSys GmbH - * - * (C) Copyright 2009 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <netdev.h> -#include <miiphy.h> -#include <libfdt.h> -#include <mb862xx.h> -#include <video_fb.h> -#include <asm/processor.h> -#include <asm/io.h> - -#ifdef CONFIG_OF_LIBFDT -#include <fdt_support.h> -#endif /* CONFIG_OF_LIBFDT */ - -/* mt46v16m16-75 */ -#ifdef CONFIG_MPC5200_DDR -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 -#else -#error SDRAM is not supported on this board -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static void sdram_start (int hi_addr) -{ - struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit); - - /* precharge all banks */ - out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit); - - /* set mode register: extended mode */ - out_be32 (&sdram->mode, SDRAM_EMODE); - - /* set mode register: reset DLL */ - out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000); - - /* precharge all banks */ - out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit); - - /* auto refresh */ - out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit); - - /* set mode register */ - out_be32 (&sdram->mode, SDRAM_MODE); - - /* normal operation */ - out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit); -} - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if - * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. - */ - -int dram_init(void) -{ - struct mpc5xxx_mmap_ctl *mmap_ctl = - (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; - struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM; - ulong dramsize = 0; - ulong dramsize2 = 0; - ulong test1, test2; - - /* setup SDRAM chip selects */ - out_be32 (&mmap_ctl->sdram0, 0x0000001e); /* 2G at 0x0 */ - out_be32 (&mmap_ctl->sdram1, 0x00000000); /* disabled */ - - /* setup config registers */ - out_be32 (&sdram->config1, SDRAM_CONFIG1); - out_be32 (&sdram->config2, SDRAM_CONFIG2); - - /* set tap delay */ - out_be32 (&cdm->porcfg, SDRAM_TAPDELAY); - - /* find RAM size using SDRAM CS0 only */ - sdram_start (0); - test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start (1); - test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start (0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) - out_be32 (&mmap_ctl->sdram0, - 0x13 + __builtin_ffs (dramsize >> 20) - 1); - else - out_be32 (&mmap_ctl->sdram1, 0); /* disabled */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - out_be32 (&sdram->sdelay, 0x04); - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -int checkboard (void) -{ - puts ("Board: IPEK01 \n"); - return 0; -} - -void flash_preinit (void) -{ - struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB; - - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - clrbits_be32 (&lpb->cs0_cfg, 0x1); /* clear RO */ -} - -void flash_afterinit (ulong start, ulong size) -{ - struct mpc5xxx_mmap_ctl *mmap_ctl = - (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; - -#if defined(CONFIG_BOOT_ROM) - /* adjust mapping */ - out_be32 (&mmap_ctl->cs1_start, START_REG (start)); - out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size)); -#else - /* adjust mapping */ - out_be32 (&mmap_ctl->boot_start, START_REG (start)); - out_be32 (&mmap_ctl->cs0_start, START_REG (start)); - out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size)); - out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size)); -#endif -} - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -int misc_init_r (void) -{ - /* adjust flash start */ - gd->bd->bi_flashstart = flash_info[0].start[0]; - return (0); -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init (struct pci_controller *); - -void pci_init_board (void) -{ - pci_mpc5xxx_init (&hose); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup (blob, bd); - fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} - -#ifdef CONFIG_VIDEO -extern GraphicDevice mb862xx; - -static const gdc_regs init_regs[] = { - {0x0100, 0x00000900}, - {0x0020, 0x80190257}, - {0x0024, 0x00000000}, - {0x0028, 0x00000000}, - {0x002c, 0x00000000}, - {0x0110, 0x00000000}, - {0x0114, 0x00000000}, - {0x0118, 0x02570320}, - {0x0004, 0x041f0000}, - {0x0008, 0x031f031f}, - {0x000c, 0x067f0347}, - {0x0010, 0x02780000}, - {0x0014, 0x0257025c}, - {0x0018, 0x00000000}, - {0x001c, 0x02570320}, - {0x0100, 0x80010900}, - {0x0, 0x0} -}; - -const gdc_regs *board_get_regs (void) -{ - return init_regs; -} - -/* Returns Lime base address */ -unsigned int board_video_init (void) -{ - if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME) - return 0; - - mb862xx.winSizeX = 800; - mb862xx.winSizeY = 600; - mb862xx.gdfIndex = GDF_15BIT_555RGB; - mb862xx.gdfBytesPP = 2; - - return CONFIG_SYS_LIME_BASE; -} - -#if defined(CONFIG_CONSOLE_EXTRA_INFO) -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) - strcpy (info, " Board: IPEK01"); - else - info[0] = '\0'; -} -#endif -#endif /* CONFIG_VIDEO */ diff --git a/board/jupiter/Kconfig b/board/jupiter/Kconfig deleted file mode 100644 index d71acbbc4d..0000000000 --- a/board/jupiter/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_JUPITER - -config SYS_BOARD - default "jupiter" - -config SYS_CONFIG_NAME - default "jupiter" - -endif diff --git a/board/jupiter/MAINTAINERS b/board/jupiter/MAINTAINERS deleted file mode 100644 index 5a79a616cc..0000000000 --- a/board/jupiter/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -JUPITER BOARD -M: Heiko Schocher <hs@denx.de> -S: Maintained -F: board/jupiter/ -F: include/configs/jupiter.h -F: configs/jupiter_defconfig diff --git a/board/jupiter/Makefile b/board/jupiter/Makefile deleted file mode 100644 index 4d3ef9ed7a..0000000000 --- a/board/jupiter/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := jupiter.o diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c deleted file mode 100644 index 52d2766e9a..0000000000 --- a/board/jupiter/jupiter.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <asm/processor.h> -#include <libfdt.h> - -#define SDRAM_DDR 0 -#if 1 -/* Settings Icecube */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 -#else -/*Settings Jupiter UB 1.0.0 */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0xD04F0000 -#define SDRAM_CONFIG1 0xf7277f00 -#define SDRAM_CONFIG2 0x88b70004 -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; - -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -int checkboard (void) -{ - puts ("Board: Sauter (Jupiter)\n"); - return 0; -} - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - -int board_early_init_r (void) -{ - flash_preinit (); - return 0; -} - -void flash_afterinit(ulong size) -{ - if (size == 0x1000000) { /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(CONFIG_SYS_BOOTCS_START | size); - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); - } - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -} - -int update_flash_size (int flash_size) -{ - flash_afterinit (flash_size); - return 0; -} - -int board_early_init_f (void) -{ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; - /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; - /* Make a delay. MPC5200 spec says 25 usec min */ - udelay(500000); - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; - } -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/keymile/km82xx/Kconfig b/board/keymile/km82xx/Kconfig deleted file mode 100644 index c9a093ce02..0000000000 --- a/board/keymile/km82xx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KM82XX - -config SYS_BOARD - default "km82xx" - -config SYS_VENDOR - default "keymile" - -config SYS_CONFIG_NAME - default "km82xx" - -endif diff --git a/board/keymile/km82xx/MAINTAINERS b/board/keymile/km82xx/MAINTAINERS deleted file mode 100644 index 50e06b261c..0000000000 --- a/board/keymile/km82xx/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -KM82XX BOARD -M: Holger Brunck <holger.brunck@keymile.com> -S: Maintained -F: board/keymile/km82xx/ -F: include/configs/km82xx.h -F: configs/mgcoge_defconfig -F: configs/mgcoge3ne_defconfig diff --git a/board/keymile/km82xx/Makefile b/board/keymile/km82xx/Makefile deleted file mode 100644 index 20f193ab1d..0000000000 --- a/board/keymile/km82xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := km82xx.o ../common/common.o ../common/ivm.o diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c deleted file mode 100644 index f5a98b33e7..0000000000 --- a/board/keymile/km82xx/km82xx.c +++ /dev/null @@ -1,463 +0,0 @@ -/* - * (C) Copyright 2007 - 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8260.h> -#include <ioports.h> -#include <malloc.h> -#include <asm/io.h> - -#include <libfdt.h> -#include <i2c.h> -#include "../common/common.h" - -DECLARE_GLOBAL_DATA_PTR; - -static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PA31 */ - { 0, 0, 0, 0, 0, 0 }, /* PA30 */ - { 0, 0, 0, 0, 0, 0 }, /* PA29 */ - { 0, 0, 0, 0, 0, 0 }, /* PA28 */ - { 0, 0, 0, 0, 0, 0 }, /* PA27 */ - { 0, 0, 0, 0, 0, 0 }, /* PA26 */ - { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - { 0, 0, 0, 0, 0, 0 }, /* PA21 */ - { 0, 0, 0, 0, 0, 0 }, /* PA20 */ - { 0, 0, 0, 0, 0, 0 }, /* PA19 */ - { 0, 0, 0, 0, 0, 0 }, /* PA18 */ - { 0, 0, 0, 0, 0, 0 }, /* PA17 */ - { 0, 0, 0, 0, 0, 0 }, /* PA16 */ - { 0, 0, 0, 0, 0, 0 }, /* PA15 */ - { 0, 0, 0, 0, 0, 0 }, /* PA14 */ - { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - { 1, 1, 0, 1, 0, 0 }, /* PA9 SMC2 TxD */ - { 1, 1, 0, 0, 0, 0 }, /* PA8 SMC2 RxD */ - { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PB31 */ - { 0, 0, 0, 0, 0, 0 }, /* PB30 */ - { 0, 0, 0, 0, 0, 0 }, /* PB29 */ - { 0, 0, 0, 0, 0, 0 }, /* PB28 */ - { 0, 0, 0, 0, 0, 0 }, /* PB27 */ - { 0, 0, 0, 0, 0, 0 }, /* PB26 */ - { 0, 0, 0, 0, 0, 0 }, /* PB25 */ - { 0, 0, 0, 0, 0, 0 }, /* PB24 */ - { 0, 0, 0, 0, 0, 0 }, /* PB23 */ - { 0, 0, 0, 0, 0, 0 }, /* PB22 */ - { 0, 0, 0, 0, 0, 0 }, /* PB21 */ - { 0, 0, 0, 0, 0, 0 }, /* PB20 */ - { 0, 0, 0, 0, 0, 0 }, /* PB19 */ - { 0, 0, 0, 0, 0, 0 }, /* PB18 */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - { 1, 1, 0, 0, 0, 0 }, /* PC25 RxClk */ - { 1, 1, 0, 0, 0, 0 }, /* PC24 TxClk */ - { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - { 0, 0, 0, 0, 0, 0 }, /* PC21 */ - { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - { 0, 0, 0, 0, 0, 0 }, /* PC18 */ - { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - { 1, 1, 0, 0, 0, 0 }, /* PC9 SCC4: CTS */ - { 1, 1, 0, 0, 0, 0 }, /* PC8 SCC4: CD */ - { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - { 0, 0, 0, 0, 0, 0 }, /* PD31 */ - { 0, 0, 0, 0, 0, 0 }, /* PD30 */ - { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - { 1, 1, 0, 0, 0, 0 }, /* PD22 SCC4: RXD */ - { 1, 1, 0, 1, 0, 0 }, /* PD21 SCC4: TXD */ - { 1, 1, 0, 1, 0, 0 }, /* PD20 SCC4: RTS */ - { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - { 0, 0, 0, 0, 0, 0 }, /* PD16 */ - { 1, 0, 0, 0, 1, 1 }, /* PD15 */ - { 1, 0, 0, 1, 1, 1 }, /* PD14 */ - { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -/* - * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init(memctl8260_t *memctl, ulong sdmr, - ulong orx, uchar *base) -{ - uchar c = 0xff; - ulong maxsize, size; - int i; - - /* - * We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff))/* / 2*/; - - out_be32(&memctl->memc_or1, orx); - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address - * CONFIG_SYS_SDRAM_BASE. - */ - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA); - out_8(base, c); - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR); - for (i = 0; i < 8; i++) - out_8(base, c); - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW); - /* setting MR on address lines */ - out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c); - - out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN); - out_8(base, c); - - size = get_ram_size((long *)base, maxsize); - out_be32(&memctl->memc_or1, orx | ~(size - 1)); - - return size; -} - -#ifdef CONFIG_SYS_SDRAM_LIST - -/* - * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM - * configurations therein (should be from high to lower) to find the - * one actually matching the current configuration. - * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are - * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST - * (defined as the initialization value for the array of struct sdram_conf_s) - * will then be ORed with such base values. - */ - -struct sdram_conf_s { - ulong size; - int or1; - int psdmr; -}; - -static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST; - -static long probe_sdram(memctl8260_t *memctl) -{ - int n = 0; - long psize = 0; - - for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) { - psize = try_init(memctl, - CONFIG_SYS_PSDMR | sdram_conf[n].psdmr, - CONFIG_SYS_OR1 | sdram_conf[n].or1, - (uchar *) CONFIG_SYS_SDRAM_BASE); - debug("Probing %ld bytes returned %ld\n", - sdram_conf[n].size, psize); - if (psize == sdram_conf[n].size) - break; - } - return psize; -} - -#else /* CONFIG_SYS_SDRAM_LIST */ - -static long probe_sdram(memctl8260_t *memctl) -{ - return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1, - (uchar *) CONFIG_SYS_SDRAM_BASE); -} -#endif /* CONFIG_SYS_SDRAM_LIST */ - - -int dram_init(void) -{ - immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - memctl8260_t *memctl = &immap->im_memctl; - - long psize; - - out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT); - out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); - - /* 60x SDRAM setup: - */ - psize = probe_sdram(memctl); - - icache_enable(); - - gd->ram_size = psize; - - return 0; -} - -int checkboard(void) -{ -#if defined(CONFIG_MGCOGE) - puts("Board: Keymile mgcoge"); -#else - puts("Board: Keymile mgcoge3ne"); -#endif - if (ethernet_present()) - puts(" with PIGGY."); - puts("\n"); - return 0; -} - -int last_stage_init(void) -{ - struct bfticu_iomap *base = - (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE; - u8 dip_switch; - - dip_switch = in_8(&base->mswitch); - dip_switch &= BFTICU_DIPSWITCH_MASK; - /* dip switch 'full reset' or 'db erase' or 'Local mgmt IP' or any */ - if (dip_switch != 0) { - /* start bootloader */ - puts("DIP: Enabled\n"); - setenv("actual_bank", "0"); - } - set_km_env(); - return 0; -} - -#ifdef CONFIG_MGCOGE3NE -static void set_pin(int state, unsigned long mask, int port); - -/* - * For mgcoge3ne boards, the mgcoge3un control is controlled from - * a GPIO line on the PPC CPU. If bobcatreset is set the line - * will toggle once what forces the mgocge3un part to restart - * immediately. - */ -static void handle_mgcoge3un_reset(void) -{ - char *bobcatreset = getenv("bobcatreset"); - if (bobcatreset) { - if (strcmp(bobcatreset, "true") == 0) { - puts("Forcing bobcat reset\n"); - set_pin(0, 0x00000004, 3); /* clear PD29 (reset arm) */ - udelay(1000); - set_pin(1, 0x00000004, 3); - } else - set_pin(1, 0x00000004, 3); /* don't reset arm */ - } -} -#endif - -int ethernet_present(void) -{ - struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; - - return in_8(&base->bprth) & PIGGY_PRESENT; -} - -/* - * Early board initalization. - */ -int board_early_init_r(void) -{ - struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; - - /* setup the UPIOx */ - /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */ - out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED)); - /* SCC4 enable, halfduplex, FCC1 powerdown */ - out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA | - H_OPORTS_FCC1_PW_DWN)); - -#ifdef CONFIG_MGCOGE3NE - handle_mgcoge3un_reset(); -#endif - return 0; -} - -int misc_init_r(void) -{ - ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); - return 0; -} - -int hush_init_var(void) -{ - ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); - return 0; -} - -#define SDA_MASK 0x00010000 -#define SCL_MASK 0x00020000 - -static void set_pin(int state, unsigned long mask, int port) -{ - ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port); - - if (state) - setbits_be32(&iop->pdat, mask); - else - clrbits_be32(&iop->pdat, mask); - - setbits_be32(&iop->pdir, mask); -} - -static int get_pin(unsigned long mask, int port) -{ - ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port); - - clrbits_be32(&iop->pdir, mask); - return 0 != (in_be32(&iop->pdat) & mask); -} - -void set_sda(int state) -{ - set_pin(state, SDA_MASK, 3); -} - -void set_scl(int state) -{ - set_pin(state, SCL_MASK, 3); -} - -int get_sda(void) -{ - return get_pin(SDA_MASK, 3); -} - -int get_scl(void) -{ - return get_pin(SCL_MASK, 3); -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} - -#if defined(CONFIG_MGCOGE3NE) -int get_testpin(void) -{ - /* Testpin is Port C pin 29 - enable = low */ - int testpin = !get_pin(0x00000004, 2); - return testpin; -} -#endif diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c index 0ad33eaeae..26534394ab 100644 --- a/board/lego/ev3/legoev3.c +++ b/board/lego/ev3/legoev3.c @@ -25,6 +25,8 @@ #include <asm/arch/davinci_misc.h> #include <linux/errno.h> #include <hwconfig.h> +#include <asm/mach-types.h> +#include <asm/setup.h> #ifdef CONFIG_MMC_DAVINCI #include <mmc.h> diff --git a/board/mini-box/picosam9g45/picosam9g45.c b/board/mini-box/picosam9g45/picosam9g45.c index 5eb2ad77ca..09ec247663 100644 --- a/board/mini-box/picosam9g45/picosam9g45.c +++ b/board/mini-box/picosam9g45/picosam9g45.c @@ -27,6 +27,7 @@ #include <net.h> #endif #include <netdev.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/motionpro/Kconfig b/board/motionpro/Kconfig deleted file mode 100644 index f624f6c95f..0000000000 --- a/board/motionpro/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MOTIONPRO - -config SYS_BOARD - default "motionpro" - -config SYS_CONFIG_NAME - default "motionpro" - -endif diff --git a/board/motionpro/MAINTAINERS b/board/motionpro/MAINTAINERS deleted file mode 100644 index 2f8b5cb580..0000000000 --- a/board/motionpro/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MOTIONPRO BOARD -#M: - -S: Maintained -F: board/motionpro/ -F: include/configs/motionpro.h -F: configs/motionpro_defconfig diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile deleted file mode 100644 index 898a384c39..0000000000 --- a/board/motionpro/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := motionpro.o diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c deleted file mode 100644 index 7883a179e8..0000000000 --- a/board/motionpro/motionpro.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * modified for Promess PRO - by Andy Joseph, andy@promessdev.com - * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com - * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3 - * Also changed the refresh for 100MHz operation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <miiphy.h> -#include <libfdt.h> - -#if defined(CONFIG_LED_STATUS) -#include <status_led.h> -#endif /* CONFIG_LED_STATUS */ - -DECLARE_GLOBAL_DATA_PTR; - -/* Kollmorgen DPR initialization data */ -struct init_elem { - unsigned long addr; - unsigned len; - char *data; - } init_seq[] = { - {0x500003F2, 2, "\x86\x00"}, /* HW parameter */ - {0x500003F0, 2, "\x00\x00"}, - {0x500003EC, 4, "\x00\x80\xc1\x52"}, /* Magic word */ - }; - -/* - * Initialize Kollmorgen DPR - */ -static void kollmorgen_init(void) -{ - unsigned i, j; - vu_char *p; - - for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) { - p = (vu_char *)init_seq[i].addr; - for (j = 0; j < init_seq[i].len; ++j) - *(p + j) = *(init_seq[i].data + j); - } - - printf("DPR: Kollmorgen DPR initialized\n"); -} - - -/* - * Early board initalization. - */ -int board_early_init_r(void) -{ - /* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); - - /* Initialize Kollmorgen DPR */ - kollmorgen_init(); - - return 0; -} - - -/* - * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(), - * PHY goes into FX mode. To take it out of the FX mode and switch into - * desired TX operation, one needs to clear the FX_SEL bit of Mode Control - * Register. - */ -void reset_phy(void) -{ - unsigned short mode_control; - - miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control); - miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15, - mode_control & 0xfffe); - return; -} - -#ifndef CONFIG_SYS_RAMBOOT -/* - * Helper function to initialize SDRAM controller. - */ -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | - hi_addr_bit; - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - - /* auto refresh, second time */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; -} -#endif /* !CONFIG_SYS_RAMBOOT */ - - -/* - * Initalize SDRAM - configure SDRAM controller, detect memory size. - */ -int dram_init(void) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* According to AN3221 (MPC5200B SDRAM Initialization and - * Configuration), the SDelay register must be written a value of - * 0x00000004 as the first step of the SDRAM contorller configuration. - */ - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - - /* configure SDRAM start/end for detection */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 and disable it */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; - -#else /* !CONFIG_SYS_RAMBOOT */ - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; -#endif /* CONFIG_SYS_RAMBOOT */ - - /* return total ram size */ - gd->ram_size = dramsize; - - return 0; -} - - -int checkboard(void) -{ - uchar rev = *(vu_char *)CPLD_REV_REGISTER; - printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev); - return 0; -} - - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - - -#if defined(CONFIG_LED_STATUS) -vu_long *regcode_to_regaddr(led_id_t regcode) -{ - /* GPT Enable and Mode Select Register address */ - vu_long *reg_translate[] = { - (vu_long *)MPC5XXX_GPT6_ENABLE, - (vu_long *)MPC5XXX_GPT7_ENABLE, - }; - - if (ARRAY_SIZE(reg_translate) <= regcode) - return NULL; - return reg_translate[regcode]; -} - -void __led_init(led_id_t regcode, int state) -{ - vu_long *regaddr = regcode_to_regaddr(regcode); - - *regaddr |= ENABLE_GPIO_OUT; - - if (state == CONFIG_LED_STATUS_ON) - *((vu_long *) regaddr) |= LED_ON; - else - *((vu_long *) regaddr) &= ~LED_ON; -} - -void __led_set(led_id_t regcode, int state) -{ - vu_long *regaddr = regcode_to_regaddr(regcode); - - if (state == CONFIG_LED_STATUS_ON) - *regaddr |= LED_ON; - else - *regaddr &= ~LED_ON; -} - -void __led_toggle(led_id_t regcode) -{ - vu_long *regaddr = regcode_to_regaddr(regcode); - - *regaddr ^= LED_ON; -} -#endif /* CONFIG_LED_STATUS */ diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 5ea5a5187b..31636b30ee 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -28,10 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_PATI) -#define FIRM_START 0xFFF00000 -#endif - extern int mem_test(ulong start, ulong ramsize, int quiet); #define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */ @@ -189,11 +185,8 @@ mpl_prg(uchar *src, ulong size) ulong start; flash_info_t *info = &flash_info[0]; int i, rc; -#if defined(CONFIG_PATI) - int start_sect; -#endif -#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \ - || defined(CONFIG_TARGET_MIP405T) || defined(CONFIG_PATI) +#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) || \ + defined(CONFIG_TARGET_MIP405T) char *copystr = (char *)src; ulong *magic = (ulong *)src; @@ -219,7 +212,6 @@ mpl_prg(uchar *src, ulong size) printf("Wrong Firmware Image: %s\n", ©str[i]); return -1; } -#if !defined(CONFIG_PATI) start = 0 - size; /* unprotect sectors used by u-boot */ @@ -241,38 +233,6 @@ mpl_prg(uchar *src, ulong size) flash_perror(rc); return (1); } - -#else /* #if !defined(CONFIG_PATI) */ - start = FIRM_START; - start_sect = -1; - - /* search start sector */ - for (i = info->sector_count-1; i > 0; i--) - if (start >= info->start[i]) - break; - - start_sect = i; - - for (i = info->sector_count-1; i > 0; i--) - if ((start + size) >= info->start[i]) - break; - - /* unprotect sectors used by u-boot */ - flash_protect(FLAG_PROTECT_CLEAR, - start, - start + size, - info); - - /* now erase flash */ - printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n", - start, start + size, start_sect, i, - info->start[start_sect], info->start[i]); - if ((rc = flash_erase (info, start_sect, i)) != 0) { - puts ("ERROR "); - flash_perror (rc); - return (1); - } -#endif /* defined(CONFIG_PATI) */ #endif printf("flash erased, programming from 0x%lx 0x%lx Bytes\n", (ulong)src, size); @@ -380,7 +340,6 @@ mpl_prg_image(uchar *ld_addr) return(rc); } -#if !defined(CONFIG_PATI) void get_backup_values(backup_t *buf) { i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t)); @@ -541,17 +500,13 @@ void check_env(void) } } -#endif /* #if !defined(CONFIG_PATI) */ - int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong ld_addr; int result; -#if !defined(CONFIG_PATI) ulong size = IMAGE_SIZE; ulong src = MULTI_PURPOSE_SOCKET_ADDR; backup_t back; -#endif if (strcmp(argv[1], "flash") == 0) { @@ -587,15 +542,12 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) result=mpl_prg_image((uchar *)ld_addr); return result; } -#if !defined(CONFIG_PATI) if (strcmp(argv[2], "mps") == 0) { puts("\nupdating bootloader image from MPS\n"); result=mpl_prg((uchar *)src,size); return result; } -#endif /* #if !defined(CONFIG_PATI) */ } -#if !defined(CONFIG_PATI) if (strcmp(argv[1], "clearenvvalues") == 0) { if (strcmp(argv[2], "yes") == 0) @@ -618,7 +570,6 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) set_backup_values(1); return 0; } -#endif return cmd_usage(cmdtp); } diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c index cd969cb518..ad97ffae4f 100644 --- a/board/mpl/common/pci.c +++ b/board/mpl/common/pci.c @@ -20,26 +20,35 @@ DECLARE_GLOBAL_DATA_PTR; #include "piix4_pci.h" #include "pci_parts.h" +void pci_405gp_init(struct pci_controller *hose); + void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *entry) + struct pci_config_table *entry) { struct pci_pip405_config_entry *table; int i; - table = (struct pci_pip405_config_entry*) entry->priv[0]; + table = (struct pci_pip405_config_entry *)entry->priv[0]; - for (i=0; table[i].width; i++) - { + for (i = 0; table[i].width; i++) { #ifdef DEBUG printf("Reg 0x%02X Value 0x%08lX Width %02d written\n", table[i].index, table[i].val, table[i].width); #endif - switch(table[i].width) - { - case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break; - case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break; - case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break; + switch (table[i].width) { + case 1: + pci_hose_write_config_byte(hose, dev, + table[i].index, table[i].val); + break; + case 2: + pci_hose_write_config_word(hose, dev, + table[i].index, table[i].val); + break; + case 4: + pci_hose_write_config_dword(hose, dev, + table[i].index, table[i].val); + break; } } } @@ -52,26 +61,24 @@ static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev) /* * Write pci interrupt line register */ - if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */ + if (PCI_DEV(dev) == 0) /* Device0 = PPC405 -> skip */ return; pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); if ((pin == 0) || (pin > 4)) - return; + return; int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28; pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); #ifdef DEBUG printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", - PCI_DEV(dev),dev,int_line,int_line); + PCI_DEV(dev), dev, int_line, int_line); #endif } -extern void pci_405gp_init(struct pci_controller *hose); - static struct pci_controller hose = { - config_table: pci_pip405_config_table, - fixup_irq: pci_pip405_fixup_irq, +config_table: pci_pip405_config_table, +fixup_irq : pci_pip405_fixup_irq, }; @@ -81,7 +88,8 @@ void pci_init_board(void) hose.fixup_irq = pci_pip405_fixup_irq; hose.config_table = pci_pip405_config_table; #ifdef DEBUG - printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose); + printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n", + pci_pip405_fixup_irq, pci_pip405_config_table, hose); #endif pci_405gp_init(&hose); } diff --git a/board/mpl/pati/Kconfig b/board/mpl/pati/Kconfig deleted file mode 100644 index 0eeaf7096b..0000000000 --- a/board/mpl/pati/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_PATI - -config SYS_BOARD - default "pati" - -config SYS_VENDOR - default "mpl" - -config SYS_CONFIG_NAME - default "PATI" - -config ISO_STRING - string - default "MEV-10084-001" -endif diff --git a/board/mpl/pati/MAINTAINERS b/board/mpl/pati/MAINTAINERS deleted file mode 100644 index 19ad05d274..0000000000 --- a/board/mpl/pati/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PATI BOARD -#M: - -S: Maintained -F: board/mpl/pati/ -F: include/configs/PATI.h -F: configs/PATI_defconfig diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile deleted file mode 100644 index 9822082612..0000000000 --- a/board/mpl/pati/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := pati.o cmd_pati.o \ - ../common/common_util.o diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c deleted file mode 100644 index fcae5e0de6..0000000000 --- a/board/mpl/pati/cmd_pati.c +++ /dev/null @@ -1,433 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Adapted for PATI - */ - -#include <common.h> -#include <command.h> -#define PLX9056_LOC -#include "plx9056.h" -#include "pati.h" -#include "pci_eeprom.h" - -extern void show_pld_regs(void); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - -extern void user_led0(int led_on); -extern void user_led1(int led_on); - -/* ------------------------------------------------------------------------- */ -#if defined(CONFIG_SYS_PCI_CON_DEVICE) -extern void pci_con_disc(void); -extern void pci_con_connect(void); -#endif - -/****************************************************************************** - * Eeprom Support - ******************************************************************************/ -unsigned long get32(unsigned long addr) -{ - unsigned long *p=(unsigned long *)addr; - return *p; -} - -void set32(unsigned long addr,unsigned long data) -{ - unsigned long *p=(unsigned long *)addr; - *p=data; -} - -#define PCICFG_GET_REG(x) (get32((x) + PCI_CONFIG_BASE)) -#define PCICFG_SET_REG(x,y) (set32((x) + PCI_CONFIG_BASE,(y))) - - -/****************************************************************************** - * reload_pci_eeprom - ******************************************************************************/ - -static void reload_pci_eeprom(void) -{ - unsigned long reg; - /* Set Bit 29 and clear it again */ - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - udelay(1); - /* set it*/ - reg|=(1<<29); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - /* EECLK @ 33MHz = 125kHz - * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec - * use 20msec - */ - udelay(20000); /* wait 20ms */ - reg &= ~(1<<29); /* set it low */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ -} - -/****************************************************************************** - * clock_pci_eeprom - ******************************************************************************/ - -static void clock_pci_eeprom(void) -{ - unsigned long reg; - /* clock is low, data is valid */ - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - udelay(1); - /* set clck high */ - reg|=(1<<24); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ - reg &= ~(1<<24); /* set clock low */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ -} - -/****************************************************************************** - * send_pci_eeprom_cmd - ******************************************************************************/ -static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len) -{ - unsigned long reg; - int i; - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Clear all EEPROM bits */ - reg &= ~(0xF << 24); - /* Toggle EEPROM's Chip select to get it out of Shift Register Mode */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - udelay(1); /* wait some time */ - /* Enable EEPROM Chip Select */ - reg |= (1 << 25); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - /* Send EEPROM command - one bit at a time */ - for (i = (int)(len-1); i >= 0; i--) { - /* Check if current bit is 0 or 1 */ - if (cmd & (1 << i)) - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26))); - else - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg); - clock_pci_eeprom(); - } -} - -/****************************************************************************** - * write_pci_eeprom_offs - ******************************************************************************/ -static void write_pci_eeprom_offs(unsigned short offset, unsigned short value) -{ - unsigned long reg; - int bitpos, cmdshft, cmdlen, timeout; - /* we're using the Eeprom 93CS66 */ - cmdshft = 2; - cmdlen = EE66_CMD_LEN; - /* Send Write_Enable command to EEPROM */ - send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen); - /* Send EEPROM Write command and offset to EEPROM */ - send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen); - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Clear all EEPROM bits */ - reg &= ~(0xF << 24); - /* Make sure EEDO Input is disabled for some PLX chips */ - reg &= ~(1 << 31); - /* Enable EEPROM Chip Select */ - reg |= (1 << 25); - /* Write 16-bit value to EEPROM - one bit at a time */ - for (bitpos = 15; bitpos >= 0; bitpos--) { - /* Get bit value and shift into result */ - if (value & (1 << bitpos)) - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26))); - else - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg ); - clock_pci_eeprom(); - } /* for */ - /* Deselect Chip */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25)); - /* Re-select Chip */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25)); - /* A small delay is needed to let EEPROM complete */ - timeout = 0; - do { - udelay(10); - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - timeout++; - } while (((reg & (1 << 27)) == 0) && timeout < 20000); - /* Send Write_Disable command to EEPROM */ - send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen); - /* Clear Chip Select and all other EEPROM bits */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); -} - - -/****************************************************************************** - * read_pci_eeprom_offs - ******************************************************************************/ -static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue) -{ - unsigned long reg; - int bitpos, cmdshft, cmdlen; - /* we're using the Eeprom 93CS66 */ - cmdshft = 2; - cmdlen = EE66_CMD_LEN; - /* Send EEPROM read command and offset to EEPROM */ - send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen); - /* Set EEPROM write output bit */ - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Set EEDO Input enable */ - reg |= (1 << 31); - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26)); - /* Get 16-bit value from EEPROM - one bit at a time */ - for (bitpos = 0; bitpos < 16; bitpos++) { - clock_pci_eeprom(); - udelay(10); - reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT); - /* Get bit value and shift into result */ - if (reg & (1 << 27)) - *pvalue = (unsigned short)((*pvalue << 1) | 1); - else - *pvalue = (unsigned short)(*pvalue << 1); - } - /* Clear EEDO Input enable */ - reg &= ~(1 << 31); - /* Clear Chip Select and all other EEPROM bits */ - PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24)); -} - - -/****************************************************************************** - * EEPROM read/writes -******************************************************************************/ - -#undef EEPROM_DBG -static int pati_pci_eeprom_erase(void) -{ - int i; - printf("Erasing EEPROM "); - for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) { - write_pci_eeprom_offs(i,0xffff); - if((i%0x10)) - printf("."); - } - printf("\nDone\n"); - return 0; -} - -static int pati_pci_eeprom_prg(void) -{ - int i; - i=0; - printf("Programming EEPROM "); - while(pati_eeprom[i].offset<0xffff) { - write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value); - #ifdef EEPROM_DBG - printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value); - #else - if((i%0x10)) - printf("."); - #endif - i++; - } - printf("\nDone\n"); - return 0; -} - -static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size) -{ - int i; - unsigned short value; - unsigned short *buffer =(unsigned short *)addr; - if((offset + size) > PATI_EEPROM_LAST_OFFSET) { - size = PATI_EEPROM_LAST_OFFSET - offset; - } - printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2); - for( i = offset; i< (offset + size); i+=2) { - value = *buffer++; - write_pci_eeprom_offs(i,value); - #ifdef EEPROM_DBG - printf("0x%04X: 0x%04X\n",i, value); - #else - if((i%0x10)) - printf("."); - #endif - } - printf("\nDone\n"); - return 0; -} - -static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size) -{ - int i; - unsigned short value = 0; - unsigned short *buffer =(unsigned short *)addr; - if((offset + size) > PATI_EEPROM_LAST_OFFSET) { - size = PATI_EEPROM_LAST_OFFSET - offset; - } - printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2); - for( i = offset; i< (offset + size); i+=2) { - read_pci_eeprom_offs(i,&value); - *buffer++=value; - #ifdef EEPROM_DBG - printf("0x%04X: 0x%04X\n",i, value); - #else - if((i%0x10)) - printf("."); - #endif - } - printf("\nDone\n"); - return 0; -} - -/****************************************************************************** - * PCI Bridge Registers Dump -*******************************************************************************/ -static void display_pci_regs(void) -{ - printf(" PCI9056_SPACE0_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE)); - printf(" PCI9056_SPACE0_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP)); - printf(" PCI9056_LOCAL_DMA_ARBIT %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT)); - printf(" PCI9056_ENDIAN_DESC %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC)); - printf(" PCI9056_EXP_ROM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE)); - printf(" PCI9056_EXP_ROM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP)); - printf(" PCI9056_SPACE0_ROM_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC)); - printf(" PCI9056_DM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE)); - printf(" PCI9056_DM_MEM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE)); - printf(" PCI9056_DM_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE)); - printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP)); - printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG)); - printf(" PCI9056_SPACE1_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE)); - printf(" PCI9056_SPACE1_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP)); - printf(" PCI9056_SPACE1_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC)); - printf(" PCI9056_DM_DAC %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC)); - printf(" PCI9056_MAILBOX0 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0)); - printf(" PCI9056_MAILBOX1 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1)); - printf(" PCI9056_MAILBOX2 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2)); - printf(" PCI9056_MAILBOX3 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3)); - printf(" PCI9056_MAILBOX4 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4)); - printf(" PCI9056_MAILBOX5 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5)); - printf(" PCI9056_MAILBOX6 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6)); - printf(" PCI9056_MAILBOX7 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7)); - printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL)); - printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL)); - printf(" PCI9056_INT_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT)); - printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT)); - printf(" PCI9056_PERM_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID)); - printf(" PCI9056_REVISION_ID %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID)); - printf(" \n"); - printf(" PCI9056_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID)); - printf(" PCI9056_COMMAND %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND)); - printf(" PCI9056_REVISION %08lX\n",PCICFG_GET_REG(PCI9056_REVISION)); - printf(" PCI9056_CACHE_SIZE %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE)); - printf(" PCI9056_RTR_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE)); - printf(" PCI9056_RTR_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE)); - printf(" PCI9056_LOCAL_BASE0 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0)); - printf(" PCI9056_LOCAL_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1)); - printf(" PCI9056_UNUSED_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1)); - printf(" PCI9056_UNUSED_BASE2 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2)); - printf(" PCI9056_CIS_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR)); - printf(" PCI9056_SUB_ID %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID)); - printf(" PCI9056_EXP_ROM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE)); - printf(" PCI9056_CAP_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR)); - printf(" PCI9056_INT_LINE %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE)); - printf(" PCI9056_PM_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID)); - printf(" PCI9056_PM_CSR %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR)); - printf(" PCI9056_HS_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID)); - printf(" PCI9056_VPD_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID)); - printf(" PCI9056_VPD_DATA %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA)); -} - - -int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (strcmp(argv[1], "info") == 0) - { - show_pld_regs(); - return 0; - } - if (strcmp(argv[1], "pci") == 0) - { - display_pci_regs(); - return 0; - } - if (strcmp(argv[1], "led") == 0) - { - int led_nr,led_on; - led_nr = (int)simple_strtoul(argv[2], NULL, 10); - led_on = (int)simple_strtoul(argv[3], NULL, 10); - if(!led_nr) - user_led0(led_on); - else - user_led1(led_on); - return 0; - } -#if defined(CONFIG_SYS_PCI_CON_DEVICE) - if (strcmp(argv[1], "con") == 0) { - pci_con_connect(); - return 0; - } - if (strcmp(argv[1], "disc") == 0) { - pci_con_disc(); - return 0; - } -#endif - if (strcmp(argv[1], "eeprom") == 0) { - unsigned long addr; - int size, offset; - offset = 0; - size = PATI_EEPROM_LAST_OFFSET; - if(argc>2) { - if(argc>3) { - addr = simple_strtoul(argv[3], NULL, 16); - if(argc>4) - offset = (int) simple_strtoul(argv[4], NULL, 16); - if(argc>5) - size = (int) simple_strtoul(argv[5], NULL, 16); - if (strcmp(argv[2], "read") == 0) { - return (pati_pci_eeprom_read(offset, addr, size)); - } - if (strcmp(argv[2], "write") == 0) { - return (pati_pci_eeprom_write(offset, addr, size)); - } - } - if (strcmp(argv[2], "prg") == 0) { - return (pati_pci_eeprom_prg()); - } - if (strcmp(argv[2], "era") == 0) { - return (pati_pci_eeprom_erase()); - } - if (strcmp(argv[2], "reload") == 0) { - reload_pci_eeprom(); - return 0; - } - - - } - } - - return (do_mplcommon(cmdtp, flag, argc, argv)); -} - -U_BOOT_CMD( - pati, 8, 1, do_pati, - "PATI specific Cmds", - "info - displays board information\n" - "pati pci - displays PCI registers\n" - "pati led <nr> <on> \n" - " - switch LED <nr> <on>\n" - "pati flash mem [SrcAddr]\n" - " - updates U-Boot with image in memory\n" - "pati eeprom <cmd> - PCI EEPROM sub-system\n" - " read <addr> <offset> <size>\n" - " - read PCI EEPROM to <addr> from <offset> <size> words\n" - " write <addr> <offset> <size>\n" - " - write PCI EEPROM from <addr> to <offset> <size> words\n" - " prg - programm PCI EEPROM with default values\n" - " era - erase PCI EEPROM (write all word to 0xffff)\n" - " reload- Reload PCI Bridge with EEPROM Values\n" - " NOTE: <addr> must start on word boundary\n" - " <offset> and <size> must be even byte values" -); - -/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c deleted file mode 100644 index 1288f743cc..0000000000 --- a/board/mpl/pati/pati.c +++ /dev/null @@ -1,610 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * Atapted for PATI - * Denis Peter, d.peter@mpl.ch - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*********************************************************************************** - * Bits for the SDRAM controller - * ----------------------------- - * - * CAL: CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on - * the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM - * controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3). - * RCD: RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default) - * tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns. - * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns. - * If set to 1 tWR must be equal or less 50ns. - * RP: Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less - * 25ns. If set to 1 tRP must be equal or less 50ns. - * RC: Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal - * or less 75ns. If set to 1 tRC must be equal or less 100ns. - * LMR: Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM - * is the Load Mode Register Command. - * IIP: Init in progress. Set to 1 for starting the init sequence - * (Precharge All). As long this bit is set, the Precharge All is still in progress. - * After command has completed, wait at least for 8 refresh (200usec) before proceed. - **********************************************************************************/ - -#include <common.h> -#include <console.h> -#include <mpc5xx.h> -#include <stdio_dev.h> -#include <pci_ids.h> -#define PLX9056_LOC -#include "plx9056.h" -#include "pati.h" - -#if defined(__APPLE__) -/* Leading underscore on symbols */ -# define SYM_CHAR "_" -#else /* No leading character on symbols */ -# define SYM_CHAR -#endif - -#undef SDRAM_DEBUG -/* - * Macros to generate global absolutes. - */ -#define GEN_SYMNAME(str) SYM_CHAR #str -#define GEN_VALUE(str) #str -#define GEN_ABS(name, value) \ - asm (".globl " GEN_SYMNAME(name)); \ - asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) - - -DECLARE_GLOBAL_DATA_PTR; - -/************************************************************************ - * Early debug routines - */ -void write_hex (unsigned char i) -{ - char cc; - - cc = i >> 4; - cc &= 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); - cc = i & 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); -} - -#if defined(SDRAM_DEBUG) - -void write_4hex (unsigned long val) -{ - write_hex ((unsigned char) (val >> 24)); - write_hex ((unsigned char) (val >> 16)); - write_hex ((unsigned char) (val >> 8)); - write_hex ((unsigned char) val); -} - -#endif - -unsigned long in32(unsigned long addr) -{ - unsigned long *p=(unsigned long *)addr; - return *p; -} - -void out32(unsigned long addr,unsigned long data) -{ - unsigned long *p=(unsigned long *)addr; - *p=data; -} - -typedef struct { - unsigned short boardtype; /* Board revision and Population Options */ - unsigned char cal; /* cas Latency 0:CAL=2 1:CAL=3 */ - unsigned char rcd; /* ras to cas delay 0:<25ns 1:<50ns*/ - unsigned char wrec; /* write recovery 0:<25ns 1:<50ns */ - unsigned char pr; /* Precharge Command Time 0:<25ns 1:<50ns */ - unsigned char rc; /* Auto Refresh to Active Time 0:<75ns 1:<100ns */ - unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */ -} sdram_t; - -const sdram_t sdram_table[] = { - { 0x0000, /* PATI Rev A, 16MByte -1 Board */ - 1, /* Case Latenty = 3 */ - 0, /* ras to cas delay 0 (20ns) */ - 0, /* write recovery 0:<25ns 1:<50ns*/ - 0, /* Precharge Command Time 0 (20ns) */ - 0, /* Auto Refresh to Active Time 0 (68) */ - 2 /* log binary => Size 2 = 16MByte, 1=8 */ - }, - { 0xffff, /* terminator */ - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff } -}; - - -extern int mem_test (unsigned long start, unsigned long ramsize, int quiet); - -/* - * Get RAM size. - */ -int dram_init(void) -{ - unsigned char board_rev; - unsigned long reg; - unsigned long lmr; - int i,timeout; - -#if defined(SDRAM_DEBUG) - reg=in32(PLD_CONFIG_BASE+PLD_PART_ID); - puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg)); - puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg)); - puts("\nSDRAM part 0x"); write_4hex(SDRAM_PART(reg)); - puts(" Vers 0x"); write_4hex(SDRAM_ID(reg)); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - puts("\nBoard rev. 0x"); write_4hex(SYSCNTR_BREV(reg)); - putc('\n'); -#endif - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - board_rev=(unsigned char)(SYSCNTR_BREV(reg)); - i=0; - while(1) { - if(sdram_table[i].boardtype==0xffff) { - puts("ERROR, found no table for Board 0x"); - write_hex(board_rev); - while(1); - } - if(sdram_table[i].boardtype==(unsigned char)board_rev) - break; - i++; - } - /* Set CAL, RCD, WREQ, PR and RC Bits */ -#if defined(SDRAM_DEBUG) - puts("Set CAL, RCD, WREQ, PR and RC Bits\n"); -#endif - /* mask bits */ - reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) | - SET_REG_BIT(1,SDRAM_PR) | SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR) | - SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0)); - /* set bits */ - reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) | - SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) | - SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) | - SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) | - SET_REG_BIT(sdram_table[i].rc,SDRAM_RC)); - - out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg); - /* step 2 set IIP */ -#if defined(SDRAM_DEBUG) - puts("step 2 set IIP\n"); -#endif - /* step 2 set IIP */ - reg |= SET_REG_BIT(1,SDRAM_IIP); - timeout=0; - while (timeout!=0xffff) { - __asm__ volatile("eieio"); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - if((reg & SET_REG_BIT(1,SDRAM_IIP))==0) - break; - timeout++; - udelay(1); - } - /* wait for at least 8 refresh */ - udelay(1000); - /* set LMR */ - reg |= SET_REG_BIT(1,SDRAM_LMR); - out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg); - __asm__ volatile("eieio"); - lmr=0x00000002; /* sequential burst 4 data */ - if(sdram_table[i].cal==1) - lmr|=0x00000030; /* cal = 3 */ - else - lmr|=0000000020; /* cal = 2 */ - /* rest standard operation programmed write burst length */ - /* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */ - lmr<<=2; - in32(CONFIG_SYS_SDRAM_BASE + lmr); - /* ok, we're done, set SDRAM size to log2 value of 4MByte*/ - gd->ram_size = 0x400000 << sdram_table[i].sz; - - return 0; -} - - -void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp) -{ - unsigned long reg; - reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE); - reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) | - SET_REG_BIT(1,SYSCNTR_FL_VPP) | - SET_REG_BIT(1,SYSCNTR_FL_WP)); - - reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) | - SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) | - SET_REG_BIT(ext_wp,SYSCNTR_FL_WP)); - out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg); - udelay(100); -} - - -void show_pld_regs(void) -{ - unsigned long reg,reg1; - reg=in32(PLD_CONFIG_BASE+PLD_PART_ID); - printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg)); - printf("SDRAM part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg)); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - printf("Board rev. %c\n",(char) (SYSCNTR_BREV(reg)+'A')); - printf("Waitstates %ld\n",GET_SYSCNTR_FLWAIT(reg)); - printf("SDRAM: CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n RC=%ld LMR=%ld IIP=%ld\n", - GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD), - GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR), - GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR), - GET_REG_BIT(reg,SDRAM_IIP)); - reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1); - reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2); - printf("HW Config: FLAG=%ld IP=%ld index=%ld PRPM=%ld\n ICW=%ld ISB=%ld BDIS=%ld PCIM=%ld\n", - GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP), - GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM), - GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg), - GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM)); - printf("Switches: MUX=%ld PCI_DIS=%ld Boot_EN=%ld Config=%ld\n",GET_SDRAM_MUX(reg), - GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN), - GET_SYSCNTR_CFG(reg1)); - printf("Misc: RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n", - GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP), - GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP)); -} - - -/**************************************************************** - * Setting IOs - * ----------- - * GPIO6 is User LED1 - * GPIO7 is Interrupt PLX (Output) - * GPIO5 is User LED0 - * GPIO2 is PLX USERi (Output) - * GPIO1 is PLX Interrupt (Input) - ****************************************************************/ - void init_ios(void) - { - volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR; - volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; - unsigned long reg; - reg=sysconf->sc_sgpiocr; /* Data direction register */ - reg &= ~0x67000000; - reg |= 0x27000000; /* set outpupts */ - sysconf->sc_sgpiocr=reg; /* Data direction register */ - reg=sysconf->sc_sgpiodt2; /* Data register */ - /* set output to 0 */ - reg &= ~0x27000000; - /* set IRQ and USERi to 1 */ - reg |= 0x28000000; - sysconf->sc_sgpiodt2=reg; /* Data register */ -} - -void user_led0(int led_on) -{ - volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR; - volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; - unsigned long reg; - reg=sysconf->sc_sgpiodt2; /* Data register */ - if(led_on) /* set output to 1 */ - reg |= 0x04000000; - else - reg &= ~0x04000000; - sysconf->sc_sgpiodt2=reg; /* Data register */ -} - -void user_led1(int led_on) -{ - volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR; - volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; - unsigned long reg; - reg=sysconf->sc_sgpiodt2; /* Data register */ - if(led_on) /* set output to 1 */ - reg |= 0x02000000; - else - reg &= ~0x02000000; - sysconf->sc_sgpiodt2=reg; /* Data register */ -} - -int board_early_init_f(void) -{ - spi_init_f(); - return 0; -} - -/**************************************************************** - * Last Stage Init - ****************************************************************/ -int last_stage_init (void) -{ - init_ios(); - return 0; -} - -/**************************************************************** - * Check the board - ****************************************************************/ - -#define BOARD_NAME "PATI" - -int checkboard (void) -{ - char s[50]; - ulong reg; - char rev; - int i; - - puts ("\nBoard: "); - reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); - rev=(char)(SYSCNTR_BREV(reg)+'A'); - i = getenv_f("serial#", s, 32); - if ((i == -1)) { - puts ("### No HW ID - assuming " BOARD_NAME); - printf(" Rev. %c\n",rev); - } - else { - s[sizeof(BOARD_NAME)-1] = 0; - printf ("%s-1 Rev %c SN: %s\n", s,rev, - &s[sizeof(BOARD_NAME)]); - } - set_flash_vpp(1,0,0); /* set Flash VPP */ - return 0; -} - - -#ifdef CONFIG_SYS_PCI_CON_DEVICE -/************************************************************************ - * PCI Communication - * - * Alive (Pinging): - * ---------------- - * PCI Host sends message ALIVE, Local acknowledges with ALIVE - * - * PCI_CON console over PCI: - * ------------------------- - * Local side: - * - uses PCI9056_LOC_TO_PCI_DBELL register to signal that - * data is avaible (PCIMSG_CONN) - * - uses PCI9056_MAILBOX1 to send data - * - uses PCI9056_MAILBOX0 to receive data - * PCI side: - * - uses PCI9056_PCI_TO_LOC_DBELL register to signal that - * data is avaible (PCIMSG_CONN) - * - uses PCI9056_MAILBOX0 to send data - * - uses PCI9056_MAILBOX1 to receive data - * - * How it works: - * Send: - * - check if PCICON_TRANSMIT_REG is empty - * - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG - * - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data - * is waiting - * Receive: - * - get an interrupt via the PCICON_ACK_REG register message - * PCIMSG_CONN - * - write the data from the PCICON_RECEIVE_REG into the receive - * buffer and if the receive buffer is not full, clear the - * PCICON_RECEIVE_REG (this allows the counterpart to write more data) - * - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG - * - * The PCICON_RECEIVE_REG must be cleared by the routine which reads - * the receive buffer if the buffer is not full any more - * - */ - -#undef PCI_CON_DEBUG - -#ifdef PCI_CON_DEBUG -#define PCI_CON_PRINTF(fmt,args...) serial_printf (fmt ,##args) -#else -#define PCI_CON_PRINTF(fmt,args...) -#endif - - -/********************************************************* - * we work only with a receive buffer on eiter side. - * Transmit buffer is free, if mailbox is cleared. - * Transmit character is or'ed with 0x80000000 - * PATI receive register MAILBOX0 - * PATI transmit register MAILBOX1 - *********************************************************/ -#define PCICON_RECEIVE_REG PCI9056_MAILBOX0 -#define PCICON_TRANSMIT_REG PCI9056_MAILBOX1 -#define PCICON_DBELL_REG PCI9056_LOC_TO_PCI_DBELL -#define PCICON_ACK_REG PCI9056_PCI_TO_LOC_DBELL - - -#define PCIMSG_ALIVE 0x1 -#define PCIMSG_CONN 0x2 -#define PCIMSG_DISC 0x3 -#define PCIMSG_CON_DATA 0x5 - - -#define PCICON_GET_REG(x) (in32(x + PCI_CONFIG_BASE)) -#define PCICON_SET_REG(x,y) (out32(x + PCI_CONFIG_BASE,y)) -#define PCICON_TX_FLAG 0x80000000 - - -#define REC_BUFFER_SIZE 0x100 -int recbuf[REC_BUFFER_SIZE]; -static int r_ptr = 0; -int w_ptr; -struct stdio_dev pci_con_dev; -int conn=0; -int buff_full=0; - -void pci_con_put_it(const char c) -{ - /* Test for completition */ - unsigned long reg; - do { - reg=PCICON_GET_REG(PCICON_TRANSMIT_REG); - }while(reg); - reg=PCICON_TX_FLAG + c; - PCICON_SET_REG(PCICON_TRANSMIT_REG,reg); - PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA); -} - -void pci_con_putc(struct stdio_dev *dev, const char c) -{ - pci_con_put_it(c); - if(c == '\n') - pci_con_put_it('\r'); -} - - -int pci_con_getc(struct stdio_dev *dev) -{ - int res; - int diff; - while(r_ptr==(volatile int)w_ptr); - res=recbuf[r_ptr++]; - if(r_ptr==REC_BUFFER_SIZE) - r_ptr=0; - if(w_ptr<r_ptr) - diff=r_ptr+REC_BUFFER_SIZE-w_ptr; - else - diff=r_ptr-w_ptr; - if((diff<(REC_BUFFER_SIZE-4)) && buff_full) { - /* clear Mail box */ - buff_full=0; - PCICON_SET_REG(PCICON_RECEIVE_REG,0L); - } - return res; -} - -int pci_con_tstc(struct stdio_dev *dev) -{ - if(r_ptr==(volatile int)w_ptr) - return 0; - return 1; -} - -void pci_con_puts(struct stdio_dev *dev, const char *s) -{ - while (*s) { - pci_con_putc(*s); - ++s; - } -} - -void pci_con_init (void) -{ - w_ptr = 0; - r_ptr = 0; - PCICON_SET_REG(PCICON_RECEIVE_REG,0L); - conn=1; -} - -/******************************************* - * IRQ routine - ******************************************/ -int pci_dorbell_irq(void) -{ - unsigned long reg,data; - int diff; - reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT); - PCI_CON_PRINTF(" PCI9056_INT_CTRL_STAT = %08lX\n",reg); - if(reg & (1<<20) ) { - /* read doorbell */ - reg=PCICON_GET_REG(PCICON_ACK_REG); - switch(reg) { - case PCIMSG_ALIVE: - PCI_CON_PRINTF(" Alive\n"); - PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_ALIVE); - break; - case PCIMSG_CONN: - PCI_CON_PRINTF(" Conn %d",conn); - w_ptr = 0; - r_ptr = 0; - buff_full=0; - PCICON_SET_REG(PCICON_RECEIVE_REG,0L); - conn=1; - PCI_CON_PRINTF(" ... %d\n",conn); - break; - case PCIMSG_CON_DATA: - data=PCICON_GET_REG(PCICON_RECEIVE_REG); - recbuf[w_ptr++]=(int)(data&0xff); - PCI_CON_PRINTF(" Data Console %lX, %X %d %d %X\n",data,((int)(data&0xFF)), - r_ptr,w_ptr,recbuf[w_ptr-1]); - if(w_ptr==REC_BUFFER_SIZE) - w_ptr=0; - if(w_ptr<r_ptr) - diff=r_ptr+REC_BUFFER_SIZE-w_ptr; - else - diff=r_ptr-w_ptr; - if(diff>(REC_BUFFER_SIZE-4)) - buff_full=1; - else - /* clear Mail box */ - PCICON_SET_REG(PCICON_RECEIVE_REG,0L); - break; - default: - serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg); - } - /* clear IRQ */ - PCICON_SET_REG(PCICON_ACK_REG,~0L); - } - return 0; -} - -void pci_con_connect(void) -{ - unsigned long reg; - conn=0; - reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT); - /* default 0x0f010180 */ - reg &= 0xff000000; - reg |= 0x00030000; /* enable local dorbell */ - reg |= 0x00000300; /* enable PCI dorbell */ - PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg); - irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL); - memset (&pci_con_dev, 0, sizeof (pci_con_dev)); - strcpy (pci_con_dev.name, "pci_con"); - pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; - pci_con_dev.putc = pci_con_putc; - pci_con_dev.puts = pci_con_puts; - pci_con_dev.getc = pci_con_getc; - pci_con_dev.tstc = pci_con_tstc; - stdio_register (&pci_con_dev); - printf("PATI ready for PCI connection, type ctrl-c for exit\n"); - do { - udelay(10); - if((volatile int)conn) - break; - if(ctrlc()) { - irq_free_handler(0x2); - return; - } - }while(1); - console_assign(stdin,"pci_con"); - console_assign(stderr,"pci_con"); - console_assign(stdout,"pci_con"); -} - -void pci_con_disc(void) -{ - console_assign(stdin,"serial"); - console_assign(stderr,"serial"); - console_assign(stdout,"serial"); - PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC); - /* reconnection */ - irq_free_handler(0x02); - pci_con_connect(); -} -#endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */ - -/* - * Absolute environment address for linker file. - */ -GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE); diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h deleted file mode 100644 index 93a5918252..0000000000 --- a/board/mpl/pati/pati.h +++ /dev/null @@ -1,423 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter, d.peter@mpl.ch - * SPDX-License-Identifier: GPL-2.0+ - */ -/************************************************************************ - * MACROS and register definitions for PATI Registers - ************************************************************************/ -#ifndef __PATI_H_ -#define __PATI_H_ 1 - -#define PLD_PART_ID 0x0 -#define PLD_BOARD_TIMING 0x4 -#define PLD_CONF_REG1 0x8 -#define PLD_CONF_REG2 0xC -#define PLD_CONF_RES 0x10 - -#define SET_REG_BIT(y,x) (y<<(31-x)) -#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L) - -/* SDRAM Controller PLD_PART_ID */ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_PART3 9 -#define SDRAM_PART2 10 -#define SDRAM_PART1 11 -#define SDRAM_PART0 12 -#define SDRAM_ID3 13 -#define SDRAM_ID2 14 -#define SDRAM_ID1 19 -#define SDRAM_ID0 31 - -#define SDRAM_PART(x) ( \ - (GET_REG_BIT(x,SDRAM_PART3)<<3) |\ - (GET_REG_BIT(x,SDRAM_PART2)<<2) |\ - (GET_REG_BIT(x,SDRAM_PART1)<<1) |\ - (GET_REG_BIT(x,SDRAM_PART0))) - -#define SDRAM_ID(x) ( \ - (GET_REG_BIT(x,SDRAM_ID3)<<3) |\ - (GET_REG_BIT(x,SDRAM_ID2)<<2) |\ - (GET_REG_BIT(x,SDRAM_ID1)<<1) |\ - (GET_REG_BIT(x,SDRAM_ID0))) - -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_PART4 0 -#define SYSCNTR_PART3 1 -#define SYSCNTR_PART2 3 -#define SYSCNTR_PART1 4 -#define SYSCNTR_PART0 5 -#define SYSCNTR_ID4 16 -#define SYSCNTR_ID3 20 -#define SYSCNTR_ID2 28 -#define SYSCNTR_ID1 29 -#define SYSCNTR_ID0 30 - -#define SYSCNTR_PART(x) ( \ - (GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\ - (GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\ - (GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_PART0))) - -#define SYSCNTR_ID(x) ( \ - (GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\ - (GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\ - (GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_ID0))) - -/* SDRAM Controller PLD_BOARD_TIMING */ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_CAL 9 -#define SDRAM_RCD 10 -#define SDRAM_WREQ 11 -#define SDRAM_PR 12 -#define SDRAM_RC 13 -#define SDRAM_LMR 14 -#define SDRAM_IIP 19 -#define SDRAM_RES0 31 -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_BREV0 0 -#define SYSCNTR_BREV1 1 -#define SYSCNTR_BREV2 3 -#define SYSCNTR_BREV3 4 -#define SYSCNTR_RES0 5 -#define SYSCNTR_RES1 16 -#define SYSCNTR_RES2 20 -#define SYSCNTR_FLWAIT2 28 -#define SYSCNTR_FLWAIT1 29 -#define SYSCNTR_FLWAIT0 30 - -#define SYSCNTR_BREV(x) ( \ - (GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\ - (GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_BREV0))) - -#define GET_SYSCNTR_FLWAIT(x) ( \ - (GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_FLWAIT0))) - -#define SET_SYSCNTR_FLWAIT(x) ( \ - (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\ - (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\ - (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0))) - -/* SDRAM Controller REG 2*/ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_MUX0 9 -#define SDRAM_MUX1 10 -#define SDRAM_PDIS 11 -#define SDRAM_RES1 12 -#define SDRAM_RES2 13 -#define SDRAM_RES3 14 -#define SDRAM_RES4 19 -#define SDRAM_RIP 31 - -#define GET_SDRAM_MUX(x) ( \ - (GET_REG_BIT(x,SDRAM_MUX1)<<1)| \ - (GET_REG_BIT(x,SDRAM_MUX0))) - - -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_FLAG 0 -#define SYSCNTR_IP 1 -#define SYSCNTR_BIND2 3 -#define SYSCNTR_BIND1 4 -#define SYSCNTR_BIND0 5 -#define SYSCNTR_PRM 16 -#define SYSCNTR_ICW 20 -#define SYSCNTR_ISB2 28 -#define SYSCNTR_ISB1 29 -#define SYSCNTR_ISB0 30 - -#define GET_SYSCNTR_BOOTIND(x) ( \ - (GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\ - (GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\ - (GET_REG_BIT(x,SYSCNTR_BIND0))) - -#define SET_SYSCNTR_BOOTIND(x) ( \ - (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\ - (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \ - (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0))) - -#define GET_SYSCNTR_ISB(x) ( \ - (GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \ - (GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \ - (GET_REG_BIT(x,SYSCNTR_ISB0))) - -#define SET_SYSCNTR_ISB(x) ( \ - (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \ - (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \ - (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0))) - -/* SDRAM Controller REG 3*/ -/* 9 10 11 12 13 14 19 31 */ -#define SDRAM_RES5 9 -#define SDRAM_CFG1 10 -#define SDRAM_CFG2 11 -#define SDRAM_CFG3 12 -#define SDRAM_RES6 13 -#define SDRAM_CFG5 14 -#define SDRAM_CFG6 19 -#define SDRAM_RES7 31 - -#define GET_SDRAM_CFG(x) ( \ - (GET_REG_BIT(x,SDRAM_CFG6)<<4) |\ - (GET_REG_BIT(x,SDRAM_CFG5)<<3) |\ - (GET_REG_BIT(x,SDRAM_CFG3)<<2) |\ - (GET_REG_BIT(x,SDRAM_CFG2)<<1) |\ - (GET_REG_BIT(x,SDRAM_CFG1))) - -/* System Controller */ -/* 0 1 3 4 5 16 20 28 29 30 */ -#define SYSCNTR_BDIS 0 -#define SYSCNTR_PCIM 1 -#define SYSCNTR_CFG0 3 -#define SYSCNTR_CFG1 4 -#define SYSCNTR_CFG2 5 -#define SYSCNTR_CFG3 16 -#define SYSCNTR_BOOTEN 20 -#define SYSCNTR_CPU_VPP 28 -#define SYSCNTR_FL_VPP 29 -#define SYSCNTR_FL_WP 30 - -#define GET_SYSCNTR_CFG(x) ( \ - (GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \ - (GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \ - (GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \ - (GET_REG_BIT(x,SYSCNTR_CFG0))) - - -/*************************************************************** - * MISC Defines - ***************************************************************/ - -#define PCI_VENDOR_ID_MPL 0x18E6 -#define PCI_DEVICE_ID_PATI 0x00DA - -#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T) -#define PATI_FIRMWARE_START_OFFSET 0x00300000 -#endif - -#define PATI_ENDIAN_MODE 0x3E - -/******************************************* - * PATI Mapping: - * ------------- - * PCI Map: - * ------- - * All addreses are mapped into the memory area - * (IO Area on some areas may also be possible) - * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes - * - pci_space0_addr: configurable - * - pci_space1_addr configurable - * - * Local Map: - * ---------- - * Local addresses (Remap) - * - SDRAM 0x06000000 Size 16MByte mask 0xff000000 - * - EPLD CFG 0x07000000 Size 512Bytes - * - FLASH 0x03000000 Size up to 8MByte - * - CPU 0x01000000 Size 4MByte (only accessable if special configured) - * - * Implemention: - * ------------- - * To prevent using large resources reservation on the host following - * PCI mapping is choosed: - * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes - * - pci_space0_addr: configured to the EPLD Config Area size 256Bytes - * - pci_space1_addr: configured to the SDRAM Area size 1MBytes, this - * space is used to switch between SDRAM, Flash and CPU - * - */ - -/* Attribute definitions */ -#define PATI_BUS_SIZE_8 0 -#define PATI_BUS_SIZE_16 1 -#define PATI_BUS_SIZE_32 3 - -#define PATI_SPACE0_MASK (0xFEFFFE00) /* Mask Attributes */ -#define PATI_SPACE1_MASK (0x00000000) /* Mask Attributes */ - -#define PATI_EXTRA_LONG_EEPROM 1 - -#define SPACE0_TA_ENABLE (1<<6) -#define SPACE1_TA_ENABLE (1<<6) - -/* Config Area */ -#define PATI_LOC_CFG_ADDR 0x07000000 /* Local Address */ -#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */ -/* Attributes */ -#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_CFG_BURST 0 /* No Burst */ -#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */ - -#define PATI_LOC_CFG_SPACE0_ATTR ( \ - PATI_LOC_CFG_BUS_SIZE | \ - (PATI_LOC_CFG_TA_ENABLE << 6) | \ - (PATI_LOC_CFG_NO_PREFETCH << 8) | \ - (PATI_LOC_CFG_BURST << 24) | \ - (PATI_EXTRA_LONG_EEPROM << 25)) - -/* should never be used */ -#define PATI_LOC_CFG_SPACE1_ATTR ( \ - PATI_LOC_CFG_BUS_SIZE | \ - (PATI_LOC_CFG_TA_ENABLE << 6) | \ - (PATI_LOC_CFG_NO_PREFETCH << 9) | \ - (PATI_LOC_CFG_BURST << 8)) - - -/* SDRAM Area */ -#define PATI_LOC_SDRAM_ADDR 0x06000000 /* Local Address */ -#define PATI_LOC_SDRAM_MASK 0xFFF00000 /* 1MByte */ -/* Attributes */ -#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_SDRAM_BURST 0 /* No Burst */ -#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */ -#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */ - -/* should never be used */ -#define PATI_LOC_SDRAM_SPACE0_ATTR ( \ - PATI_LOC_SDRAM_BUS_SIZE | \ - (PATI_LOC_SDRAM_TA_ENABLE << 6) | \ - (PATI_LOC_SDRAM_NO_PREFETCH << 8) | \ - (PATI_LOC_SDRAM_BURST << 24) | \ - (PATI_EXTRA_LONG_EEPROM << 25)) - -#define PATI_LOC_SDRAM_SPACE1_ATTR ( \ - PATI_LOC_SDRAM_BUS_SIZE | \ - (PATI_LOC_SDRAM_TA_ENABLE << 6) | \ - (PATI_LOC_SDRAM_NO_PREFETCH << 9) | \ - (PATI_LOC_SDRAM_BURST << 8)) - - -/* Flash Area */ -#define PATI_LOC_FLASH_ADDR 0x03000000 /* Local Address */ -#define PATI_LOC_FLASH_MASK 0xFFF00000 /* 1MByte */ -/* Attributes */ -#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */ -#define PATI_LOC_FLASH_BURST 0 /* No Burst */ -#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */ - -/* should never be used */ -#define PATI_LOC_FLASH_SPACE0_ATTR ( \ - PATI_LOC_FLASH_BUS_SIZE | \ - (PATI_LOC_FLASH_TA_ENABLE << 6) | \ - (PATI_LOC_FLASH_NO_PREFETCH << 8) | \ - (PATI_LOC_FLASH_BURST << 24) | \ - (PATI_EXTRA_LONG_EEPROM << 25)) - -#define PATI_LOC_FLASH_SPACE1_ATTR ( \ - PATI_LOC_FLASH_BUS_SIZE | \ - (PATI_LOC_FLASH_TA_ENABLE << 6) | \ - (PATI_LOC_FLASH_NO_PREFETCH << 9) | \ - (PATI_LOC_FLASH_BURST << 8)) - - -/* CPU Area */ -#define PATI_LOC_CPU_ADDR 0x01000000 /* Local Address */ -#define PATI_LOC_CPU_MASK 0xFFF00000 /* 1Mbyte */ -/* Attributes */ -#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_CPU_BURST 0 /* No Burst */ -#define PATI_LOC_CPU_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_CPU_TA_ENABLE 1 /* Enable TA */ - -/* should never be used */ -#define PATI_LOC_CPU_SPACE0_ATTR ( \ - PATI_LOC_CPU_BUS_SIZE | \ - (PATI_LOC_CPU_TA_ENABLE << 6) | \ - (PATI_LOC_CPU_NO_PREFETCH << 8) | \ - (PATI_LOC_CPU_BURST << 24) | \ - (PATI_EXTRA_CPU_EEPROM << 25)) - -#define PATI_LOC_CPU_SPACE1_ATTR ( \ - PATI_LOC_CPU_BUS_SIZE | \ - (PATI_LOC_CPU_TA_ENABLE << 6) | \ - (PATI_LOC_CPU_NO_PREFETCH << 9) | \ - (PATI_LOC_CPU_BURST << 8)) - -/*************************************************** - * Hardware Config word definition - ***************************************************/ -#define BOOT_EXT_FLASH 0x00000000 -#define BOOT_INT_FLASH 0x00000004 -#define BOOT_FROM_PCI 0x00000006 -#define BOOT_FROM_SDRAM 0x00000005 - -#define ENABLE_INT_ARB 0x00000008 - -#define INITIAL_IRQ_PREF 0x00000010 - -#define INITIAL_MEM_0M 0x00000000 -#define INITIAL_MEM_4M 0x00000080 -#define INITIAL_MEM_8M 0x00000040 -#define INITIAL_MEM_12M 0x000000C0 -#define INITIAL_MEM_16M 0x00000020 -#define INITIAL_MEM_20M 0x000000A0 -#define INITIAL_MEM_24M 0x00000060 -#define INITIAL_MEM_28M 0x000000E0 -/* CONF */ -#define INTERNAL_HWCONF 0x00000100 -/* PRPM */ -#define LOCAL_CPU_SLAVE 0x00000200 -/* BDIS */ -#define DISABLE_MEM_CNTR 0x00000400 -/* PCIM */ -#define PCI_MASTER_ONLY 0x00000800 - - -#define PATI_HW_START ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF)) -#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) -#define PATI_HW_CPU_ACC ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) -#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE)) - -/*************************************************** - * Direct Master Config - ***************************************************/ -#define PATI_DMASTER_PCI_ADDR 0x01000000 -#define PATI_BUS_MASTER 1 - - -#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */ -#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */ - -#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */ -#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */ -#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */ -#define PATI_DMASTER_PRE_SIZE_CNTRL_0 0x00000000 -#define PATI_DMASTER_PRE_SIZE_CNTRL_4 0x00000008 -#define PATI_DMASTER_PRE_SIZE_CNTRL_8 0x00001000 -#define PATI_DMASTER_PRE_SIZE_CNTRL_16 0x00001008 -#define PATI_DMASTER_REL_PCI 0x00000000 -#define PATI_DMASTER_NOT_REL_PCI 0x00000010 -#define PATI_DMASTER_WR_INVAL 0x00000200 -#define PATI_DMASTER_NOT_WR_INVAL 0x00000000 -#define PATI_DMASTER_PRE_LIMIT 0x00000800 -#define PATI_DMASTER_PRE_CONT 0x00000000 -#define PATI_DMASTER_DELAY_WR_0 0x00000000 -#define PATI_DMASTER_DELAY_WR_4 0x00004000 -#define PATI_DMASTER_DELAY_WR_8 0x00008000 -#define PATI_DMASTER_DELAY_WR_16 0x0000C000 - -#define PATI_DMASTER_PCI_ADDR_MASK 0xFFFF0000 - -#define PATI_DMASTER_ATTR \ - PATI_DMASTER_MEMORY_EN | \ - PATI_DMASTER_READ_AHEAD | \ - PATI_DMASTER_PRE_SIZE_CNTRL_4 | \ - PATI_DMASTER_REL_PCI | \ - PATI_DMASTER_NOT_WR_INVAL | \ - PATI_DMASTER_PRE_LIMIT | \ - PATI_DMASTER_DELAY_WR_0 - - -#endif /* #ifndef __PATI_H_ */ diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h deleted file mode 100644 index 459c14381d..0000000000 --- a/board/mpl/pati/pci_eeprom.h +++ /dev/null @@ -1,90 +0,0 @@ -#ifndef __PCI_EEPROM_H_ -#define __PCI_EEPROM_H_ 1 - -#include "pati.h" -/****************************************************************************** - * Eeprom Support - ******************************************************************************/ -/********************************************** -* Definitions -**********************************************/ -#define EE46_CMD_LEN 9 /* Bits in instructions */ -#define EE56_CMD_LEN 11 /* Bits in instructions */ -#define EE66_CMD_LEN 11 /* Bits in instructions */ -#define EE_READ 0x0180 /* 01 1000 0000 read instruction */ -#define EE_WRITE 0x0140 /* 01 0100 0000 write instruction */ -#define EE_WREN 0x0130 /* 01 0011 0000 write enable instruction */ -#define EE_WRALL 0x0110 /* 01 0001 0000 write all registers */ -#define EE_PRREAD 0x0180 /* 01 1000 0000 read address stored in Protect Register */ -#define EE_PRWRITE 0x0140 /* 01 0100 0000 write the address into PR */ -#define EE_WDS 0x0100 /* 01 0000 0000 write disable instruction */ -#define EE_PREN 0x0130 /* 01 0011 0000 protect enable instruction */ -#define EE_PRCLEAR 0x01FF /* 01 1111 1111 clear protect register instr */ -#define EE_PRDS 0x0100 /* 01 0000 0000 ONE TIME ONLY, permenant */ - -/*************************************************** - * EEPROM - ***************************************************/ -#define LOW_WORD(x) (((x) & 0xFFFF)) -#define HIGH_WORD(x) (((x) >> 16) & 0xFFFF) - -typedef struct pci_eeprom_t { - unsigned short offset; - unsigned short value; -} pci_eeprom; - -static pci_eeprom pati_eeprom[] = { - { 0x00,PCI_DEVICE_ID_PATI }, /* PCI Device ID PCIIDR[31:16] */ - { 0x02,PCI_VENDOR_ID_MPL }, /* PCI Vendor ID PCIIDR[15:0] */ - { 0x04,PCI_CLASS_PROCESSOR_POWERPC }, /* PCI Class Code PCICCR[23:8] */ - { 0x06,0x00BA }, /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */ - { 0x08,0x0007 }, /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */ - { 0x0A,0x0100 }, /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */ - { 0x0C,0x0000 }, /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */ - { 0x0E,0x0000 }, /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */ - { 0x10,0x0000 }, /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */ - { 0x12,0x0000 }, /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */ - { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */ - { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */ - { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */ - { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */ - { 0x1C,0x0000 }, /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */ - { 0x1E,0x0000 }, /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */ - { 0x20,0x0030 }, /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */ - { 0x22,0x0510 }, /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */ - { 0x24,0x0000 }, /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */ - { 0x26,0x0000 }, /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1] */ - { 0x28,0x0000 }, /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */ - { 0x2A,0x0000 }, /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */ - { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */ - { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */ - { 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */ - { 0x32,LOW_WORD(PATI_DMASTER_MASK) }, /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */ - { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */ - { 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */ - { 0x38,0x0000 }, /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */ - { 0x3A,0x0000 }, /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */ - { 0x3C,0x0000 }, /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */ - { 0x3E,0x0000 }, /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */ - { 0x40,0x0000 }, /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/ - { 0x42,0x0000 }, /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */ - { 0x44,0x0000 }, /* PCI Subsystem ID PCISID[15:0] */ - { 0x46,0x0000 }, /* PCI Subsystem Vendor ID PCISVID[15:0] */ - { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */ - { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */ - { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */ - { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */ - { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */ - { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */ - { 0x54,0x0000 }, /* Hot Swap Control/Status (Reserved) Reserved */ - { 0x56,0x0000 }, /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */ - { 0x58,0x0000 }, /* Reserved Reserved */ - { 0x5A,0x0000 }, /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */ - { 0x5C,0x0000 }, /* Power Management Capabilities PMC[15:9, 2:0] */ - { 0x5E,0x0000 }, /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/ - { 0x60,0x0000 }, /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */ - { 0x62,0x0000 }, /* Power Management Control/Status PMCSR[14:8] */ - { 0xFFFF,0xFFFF} /* terminaror */ -}; -#define PATI_EEPROM_LAST_OFFSET 0x64 -#endif /* #ifndef __PCI_EEPROM_H_ */ diff --git a/board/mpl/pati/plx9056.h b/board/mpl/pati/plx9056.h deleted file mode 100644 index 754e72098e..0000000000 --- a/board/mpl/pati/plx9056.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter, d.peter@mpl.ch - * SPDX-License-Identifier: GPL-2.0+ - */ -/* PLX9096 register definitions -*/ -#ifndef __PLX9056_H_ -#define __PLX9056_H_ 1 - -#include <pci.h> - -#ifdef PLX9056_LOC -#define LOCAL_OFFSET 0x080 -/* PCI Config regs */ -#else -#define LOCAL_OFFSET 0x000 -#endif - -#define PCI9056_VENDOR_ID PCI_VENDOR_ID -/*#define PCI9656_DEVICE_ID PCI_DEVICE_ID */ -#define PCI9056_COMMAND PCI_COMMAND -/*#define PCI9656_STATUS PCI_STATUS */ -#define PCI9056_REVISION PCI_REVISION_ID - -#define PCI9056_CACHE_SIZE PCI_CACHE_LINE_SIZE -#define PCI9056_RTR_BASE PCI_BASE_ADDRESS_0 -#define PCI9056_RTR_IO_BASE PCI_BASE_ADDRESS_1 -#define PCI9056_LOCAL_BASE0 PCI_BASE_ADDRESS_2 -#define PCI9056_LOCAL_BASE1 PCI_BASE_ADDRESS_3 -#define PCI9056_UNUSED_BASE1 PCI_BASE_ADDRESS_4 -#define PCI9056_UNUSED_BASE2 PCI_BASE_ADDRESS_5 -#define PCI9056_CIS_PTR PCI_CARDBUS_CIS -#define PCI9056_SUB_ID PCI_SUBSYSTEM_VENDOR_ID -#define PCI9056_EXP_ROM_BASE PCI_ROM_ADDRESS -#define PCI9056_CAP_PTR PCI_CAPABILITY_LIST -#define PCI9056_INT_LINE PCI_INTERRUPT_LINE - -#if defined(PLX9056_LOC) - #define PCI9056_PM_CAP_ID 0x180 - #define PCI9056_PM_CSR 0x184 - #define PCI9056_HS_CAP_ID 0x188 - #define PCI9056_VPD_CAP_ID 0x18C - #define PCI9056_VPD_DATA 0x190 -#endif - - -#define PCI_DEVICE_ID_PLX9056 0x9056 - -/* Local Configuration Registers Accessible via the PCI Base address + Variable */ -#define PCI9056_SPACE0_RANGE (0x000 + LOCAL_OFFSET) -#define PCI9056_SPACE0_REMAP (0x004 + LOCAL_OFFSET) -#define PCI9056_LOCAL_DMA_ARBIT (0x008 + LOCAL_OFFSET) -#define PCI9056_ENDIAN_DESC (0x00c + LOCAL_OFFSET) -#define PCI9056_EXP_ROM_RANGE (0x010 + LOCAL_OFFSET) -#define PCI9056_EXP_ROM_REMAP (0x014 + LOCAL_OFFSET) -#define PCI9056_SPACE0_ROM_DESC (0x018 + LOCAL_OFFSET) -#define PCI9056_DM_RANGE (0x01c + LOCAL_OFFSET) -#define PCI9056_DM_MEM_BASE (0x020 + LOCAL_OFFSET) -#define PCI9056_DM_IO_BASE (0x024 + LOCAL_OFFSET) -#define PCI9056_DM_PCI_MEM_REMAP (0x028 + LOCAL_OFFSET) -#define PCI9056_DM_PCI_IO_CONFIG (0x02c + LOCAL_OFFSET) -#define PCI9056_SPACE1_RANGE (0x0f0 + LOCAL_OFFSET) -#define PCI9056_SPACE1_REMAP (0x0f4 + LOCAL_OFFSET) -#define PCI9056_SPACE1_DESC (0x0f8 + LOCAL_OFFSET) -#define PCI9056_DM_DAC (0x0fc + LOCAL_OFFSET) - -#ifdef PLX9056_LOC -#define PCI9056_ARBITER_CTRL 0x1A0 -#define PCI9056_ABORT_ADDRESS 0x1A4 -#endif - -/* Runtime registers PCI Address + LOCAL_OFFSET */ -#ifdef PLX9056_LOC -#define PCI9056_MAILBOX0 0x0C0 -#define PCI9056_MAILBOX1 0x0C4 -#else -#define PCI9056_MAILBOX0 0x078 -#define PCI9056_MAILBOX1 0x07c -#endif - -#define PCI9056_MAILBOX2 (0x048 + LOCAL_OFFSET) -#define PCI9056_MAILBOX3 (0x04c + LOCAL_OFFSET) -#define PCI9056_MAILBOX4 (0x050 + LOCAL_OFFSET) -#define PCI9056_MAILBOX5 (0x054 + LOCAL_OFFSET) -#define PCI9056_MAILBOX6 (0x058 + LOCAL_OFFSET) -#define PCI9056_MAILBOX7 (0x05c + LOCAL_OFFSET) -#define PCI9056_PCI_TO_LOC_DBELL (0x060 + LOCAL_OFFSET) -#define PCI9056_LOC_TO_PCI_DBELL (0x064 + LOCAL_OFFSET) -#define PCI9056_INT_CTRL_STAT (0x068 + LOCAL_OFFSET) -#define PCI9056_EEPROM_CTRL_STAT (0x06c + LOCAL_OFFSET) -#define PCI9056_PERM_VENDOR_ID (0x070 + LOCAL_OFFSET) -#define PCI9056_REVISION_ID (0x074 + LOCAL_OFFSET) - -#endif /* #ifndef __PLX9056_H_ */ diff --git a/board/munices/Kconfig b/board/munices/Kconfig deleted file mode 100644 index 019aaae3e9..0000000000 --- a/board/munices/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MUNICES - -config SYS_BOARD - default "munices" - -config SYS_CONFIG_NAME - default "munices" - -endif diff --git a/board/munices/MAINTAINERS b/board/munices/MAINTAINERS deleted file mode 100644 index 50d3e7ebda..0000000000 --- a/board/munices/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MUNICES BOARD -#M: - -S: Maintained -F: board/munices/ -F: include/configs/munices.h -F: configs/munices_defconfig diff --git a/board/munices/Makefile b/board/munices/Makefile deleted file mode 100644 index d16e2a1fa2..0000000000 --- a/board/munices/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := munices.o diff --git a/board/munices/mt48lc16m16a2-75.h b/board/munices/mt48lc16m16a2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/munices/mt48lc16m16a2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/munices/munices.c b/board/munices/munices.c deleted file mode 100644 index 468eb3723e..0000000000 --- a/board/munices/munices.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> - -#include "mt48lc16m16a2-75.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR && SDRAM_TAPDELAY - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000); - sdram_start(1); - test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -int checkboard (void) -{ - puts ("Board: MUNICes\n"); - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/netgear/cg3100d/Kconfig b/board/netgear/cg3100d/Kconfig new file mode 100644 index 0000000000..632c22d1f7 --- /dev/null +++ b/board/netgear/cg3100d/Kconfig @@ -0,0 +1,12 @@ +if BOARD_NETGEAR_CG3100D + +config SYS_BOARD + default "cg3100d" + +config SYS_VENDOR + default "netgear" + +config SYS_CONFIG_NAME + default "netgear_cg3100d" + +endif diff --git a/board/netgear/cg3100d/MAINTAINERS b/board/netgear/cg3100d/MAINTAINERS new file mode 100644 index 0000000000..f1dcb1f62f --- /dev/null +++ b/board/netgear/cg3100d/MAINTAINERS @@ -0,0 +1,6 @@ +NETGEAR CG3100D BOARD +M: Álvaro Fernández Rojas <noltari@gmail.com> +S: Maintained +F: board/netgear/cg3100d/ +F: include/configs/netgear_cg3100d.h +F: configs/netgear_cg3100d_ram_defconfig diff --git a/board/netgear/cg3100d/Makefile b/board/netgear/cg3100d/Makefile new file mode 100644 index 0000000000..b82e59ee36 --- /dev/null +++ b/board/netgear/cg3100d/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cg3100d.o diff --git a/board/netgear/cg3100d/cg3100d.c b/board/netgear/cg3100d/cg3100d.c new file mode 100644 index 0000000000..d181ca68a0 --- /dev/null +++ b/board/netgear/cg3100d/cg3100d.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index b56bc529d1..0d5eec9dd8 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/mach-types.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/board.h> #include <asm/arch/clock.h> diff --git a/board/nvidia/whistler/Kconfig b/board/nvidia/whistler/Kconfig deleted file mode 100644 index 5febc07777..0000000000 --- a/board/nvidia/whistler/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_WHISTLER - -config SYS_BOARD - default "whistler" - -config SYS_VENDOR - default "nvidia" - -config SYS_CONFIG_NAME - default "whistler" - -endif diff --git a/board/nvidia/whistler/MAINTAINERS b/board/nvidia/whistler/MAINTAINERS deleted file mode 100644 index 66e2c8d082..0000000000 --- a/board/nvidia/whistler/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -WHISTLER BOARD -M: Tom Warren <twarren@nvidia.com> -M: Stephen Warren <swarren@nvidia.com> -S: Maintained -F: board/nvidia/whistler/ -F: include/configs/whistler.h -F: configs/whistler_defconfig diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile deleted file mode 100644 index b54c5fd338..0000000000 --- a/board/nvidia/whistler/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2010-2012 -# NVIDIA Corporation <www.nvidia.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := whistler.o diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c deleted file mode 100644 index db48978061..0000000000 --- a/board/nvidia/whistler/whistler.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <asm/io.h> -#include <asm/arch/tegra.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> -#include <asm/gpio.h> -#include <i2c.h> - -#ifdef CONFIG_MMC_SDHCI_TEGRA -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -void pin_mux_mmc(void) -{ - struct udevice *dev; - uchar val; - int ret; - - /* Turn on MAX8907B LDO12 to 2.8V for J40 power */ - ret = i2c_get_chip_for_busnum(0, 0x3c, 1, &dev); - if (ret) { - printf("%s: Cannot find MAX8907B I2C chip\n", __func__); - return; - } - val = 0x29; - ret = dm_i2c_write(dev, 0x46, &val, 1); - if (ret) - printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret); - val = 0x00; - ret = dm_i2c_write(dev, 0x45, &val, 1); - if (ret) - printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret); - val = 0x1f; - ret = dm_i2c_write(dev, 0x44, &val, 1); - if (ret) - printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret); - - funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); -} -#endif - -/* this is a weak define that we are overriding */ -void pin_mux_usb(void) -{ - struct udevice *dev; - uchar val; - int ret; - - /* - * This is a hack. This should be represented in DT using the - * vbus-gpio property. However, U-Boot's DT support doesn't - * support any GPIO controller other than the Tegra's yet. - */ - - /* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */ - ret = i2c_get_chip_for_busnum(0, 0x20, 1, &dev); - if (ret) { - printf("%s: Cannot find TAC6416 I2C chip\n", __func__); - return; - } - val = 0x03; - ret = dm_i2c_write(dev, 2, &val, 1); - if (ret) - printf("i2c_write 0 0x20 2 failed: %d\n", ret); - val = 0xfc; - ret = dm_i2c_write(dev, 6, &val, 1); - if (ret) - printf("i2c_write 0 0x20 6 failed: %d\n", ret); -} diff --git a/board/overo/common.c b/board/overo/common.c index f6f6792d09..5656e2d17f 100644 --- a/board/overo/common.c +++ b/board/overo/common.c @@ -18,6 +18,7 @@ #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/pdm360ng/Kconfig b/board/pdm360ng/Kconfig deleted file mode 100644 index 33173a0a2a..0000000000 --- a/board/pdm360ng/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_PDM360NG - -config SYS_BOARD - default "pdm360ng" - -config SYS_CONFIG_NAME - default "pdm360ng" - -endif diff --git a/board/pdm360ng/MAINTAINERS b/board/pdm360ng/MAINTAINERS deleted file mode 100644 index 5c99f59e8f..0000000000 --- a/board/pdm360ng/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PDM360NG BOARD -M: Michael Weiss <michael.weiss@ifm.com> -S: Maintained -F: board/pdm360ng/ -F: include/configs/pdm360ng.h -F: configs/pdm360ng_defconfig diff --git a/board/pdm360ng/Makefile b/board/pdm360ng/Makefile deleted file mode 100644 index 99201a41f6..0000000000 --- a/board/pdm360ng/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := pdm360ng.o diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c deleted file mode 100644 index 371bcd9e6b..0000000000 --- a/board/pdm360ng/pdm360ng.c +++ /dev/null @@ -1,581 +0,0 @@ -/* - * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de> - * - * (C) Copyright 2009-2010 - * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/bitops.h> -#include <command.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/mpc512x.h> -#include <fdt_support.h> -#include <flash.h> -#ifdef CONFIG_MISC_INIT_R -#include <i2c.h> -#endif -#include <serial.h> -#include <jffs2/load_kernel.h> -#include <mtd_node.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; -ulong flash_get_size (phys_addr_t base, int banknum); - -sdram_conf_t mddrc_config[] = { - { - (512 << 20), /* 512 MB RAM configuration */ - { - CONFIG_SYS_MDDRC_SYS_CFG, - CONFIG_SYS_MDDRC_TIME_CFG0, - CONFIG_SYS_MDDRC_TIME_CFG1, - CONFIG_SYS_MDDRC_TIME_CFG2 - } - }, - { - (128 << 20), /* 128 MB RAM configuration */ - { - CONFIG_SYS_MDDRC_SYS_CFG_ALT1, - CONFIG_SYS_MDDRC_TIME_CFG0_ALT1, - CONFIG_SYS_MDDRC_TIME_CFG1_ALT1, - CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 - } - }, -}; - -int dram_init(void) -{ - int i; - u32 msize = 0; - u32 pdm360ng_init_seq[] = { - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_MICRON_INIT_DEV_OP, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_EM2, - CONFIG_SYS_DDRCMD_NOP, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_EM2, - CONFIG_SYS_DDRCMD_EM3, - CONFIG_SYS_DDRCMD_EN_DLL, - CONFIG_SYS_DDRCMD_RES_DLL, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_DDRCMD_RFSH, - CONFIG_SYS_MICRON_INIT_DEV_OP, - CONFIG_SYS_DDRCMD_OCD_DEFAULT, - CONFIG_SYS_DDRCMD_OCD_EXIT, - CONFIG_SYS_DDRCMD_PCHG_ALL, - CONFIG_SYS_DDRCMD_NOP - }; - - for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) { - msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq, - ARRAY_SIZE(pdm360ng_init_seq)); - if (msize == mddrc_config[i].size) - break; - } - - gd->ram_size = msize; - - return 0; -} - -static int set_lcd_brightness(char *); - -int misc_init_r(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - /* - * Re-configure flash setup using auto-detected info - */ - if (flash_info[1].size > 0) { - out_be32(&im->sysconf.lpcs1aw, - CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) | - CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size, - flash_info[1].size)); - sync_law(&im->sysconf.lpcs1aw); - /* - * Re-check to get correct base address - */ - flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1); - } else { - /* Disable Bank 1 */ - out_be32(&im->sysconf.lpcs1aw, 0x01000100); - sync_law(&im->sysconf.lpcs1aw); - } - - out_be32(&im->sysconf.lpcs0aw, - CSAW_START(gd->bd->bi_flashstart) | - CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size)); - sync_law(&im->sysconf.lpcs0aw); - - /* - * Re-check to get correct base address - */ - flash_get_size (gd->bd->bi_flashstart, 0); - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[0]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_FSL_DIU_FB - set_lcd_brightness(0); - /* Switch LCD-Backlight and LVDS-Interface on */ - setbits_be32(&im->gpio.gpdir, 0x01040000); - clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000); -#endif - - return 0; -} - -static iopin_t ioregs_init[] = { - /* FUNC1=LPC_CS4 */ - { - offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) | - IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=GPIO10 */ - { - offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC1=CAN3_TX */ - { - offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=GPIO14 */ - { - offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */ - /* DIU_LD22-DIU_LD23 */ - { - offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */ - /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */ - { - offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */ - /* VIU_DATA0-VIU_DATA2 */ - { - offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC2=FEC_TXD_0 */ - { - offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */ - /* VIU_DATA3, VIU_DATA4 */ - { - offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */ - /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */ - /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */ - { - offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */ - /* DIU_LD00-DIU_LD21 */ - { - offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1) - }, - /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */ - /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */ - { - offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC2=CAN3_RX */ - { - offsetof(struct ioctrl512x, io_control_irq1), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* Sets lowest slew on 2 CAN_TX Pins*/ - { - offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */ - /* CAN4_TX, CAN4_RX */ - { - offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */ - /* GPIO8, GPIO9 */ - { - offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */ - /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */ - { - offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */ - /* FEC_RXD_3, FEC_RXD_2 */ - { - offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=GPIO17 */ - { - offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */ - /* GPIO2, GPIO20, GPIO21 */ - { - offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC2=VIU_PIX_CLK */ - { - offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */ - /* GPIO24, GPIO25 */ - { - offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC1=NFC_CE2 */ - { - offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) | - IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */ - /* VIU_DATA5-VIU_DATA9 */ - { - offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */ - /* LPC_TSIZ1-LPC_TSIZ2 */ - { - offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=LPC_TS */ - { - offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC3=GPIO16 */ - { - offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */ - /* GPIO18-GPIO19, GPT7/GPIO7 */ - { - offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=GPIO0/GPT0 */ - { - offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */ - /* GPIO11, GPIO2, GPIO12, GPIO13 */ - { - offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0, - IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0) - }, - /* FUNC2=DIU_DE */ - { - offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - } -}; - -int checkboard (void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - puts("Board: PDM360NG\n"); - - /* initialize function mux & slew rate IO inter alia on IO Pins */ - - iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); - - /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */ - setbits_be32(&im->io_ctrl.io_control_gp, - (1 << 0) | /* GP_MUX7->GPIO7 */ - (1 << 5)); /* GP_MUX2->GPIO2 */ - - /* configure GPIO24 (VIU_CE), output/high */ - setbits_be32(&im->gpio.gpdir, 0x80); - setbits_be32(&im->gpio.gpdat, 0x80); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -#ifdef CONFIG_FDT_FIXUP_PARTITIONS -struct node_info nodes[] = { - { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, }, - { "cfi-flash", MTD_DEV_TYPE_NOR, }, -}; -#endif - -#if defined(CONFIG_VIDEO) -/* - * EDID block has been generated using Phoenix EDID Designer 1.3. - * This tool creates a text file containing: - * - * EDID BYTES: - * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F - * ------------------------------------------------ - * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00 - * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25 - * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 - * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80 - * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F - * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50 - * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF - * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4 - * - * Then this data has been manually converted to the char - * array below. - */ -static unsigned char edid_buf[128] = { - 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, - 0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00, - 0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78, - 0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25, - 0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C, - 0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80, - 0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18, - 0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F, - 0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50, - 0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A, - 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF, - 0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, - 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4, -}; -#endif - -int ft_board_setup(void *blob, bd_t *bd) -{ - u32 val[8]; - int rc, i = 0; - - ft_cpu_setup(blob, bd); -#ifdef CONFIG_FDT_FIXUP_PARTITIONS - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); -#endif -#if defined(CONFIG_VIDEO) - fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf); -#endif - - /* Fixup NOR FLASH mapping */ - val[i++] = 0; /* chip select number */ - val[i++] = 0; /* always 0 */ - val[i++] = gd->bd->bi_flashstart; - val[i++] = gd->bd->bi_flashsize; - - /* Fixup MRAM mapping */ - val[i++] = 2; /* chip select number */ - val[i++] = 0; /* always 0 */ - val[i++] = CONFIG_SYS_MRAM_BASE; - val[i++] = CONFIG_SYS_MRAM_SIZE; - - rc = fdt_find_and_setprop(blob, "/localbus", "ranges", - val, i * sizeof(u32), 1); - if (rc) - printf("Unable to update localbus ranges, err=%s\n", - fdt_strerror(rc)); - - /* Fixup reg property in NOR Flash node */ - i = 0; - val[i++] = 0; /* always 0 */ - val[i++] = 0; /* start at offset 0 */ - val[i++] = flash_info[0].size; /* size of Bank 0 */ - - /* Second Bank available? */ - if (flash_info[1].size > 0) { - val[i++] = 0; /* always 0 */ - val[i++] = flash_info[0].size; /* offset of Bank 1 */ - val[i++] = flash_info[1].size; /* size of Bank 1 */ - } - - rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg", - val, i * sizeof(u32), 1); - if (rc) - printf("Unable to update flash reg property, err=%s\n", - fdt_strerror(rc)); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -/* - * If argument is NULL, set the LCD brightness to the - * value from "brightness" environment variable. Set - * the LCD brightness to the value specified by the - * argument otherwise. Default brightness is zero. - */ -#define MAX_BRIGHTNESS 99 -static int set_lcd_brightness(char *brightness) -{ - struct stdio_dev *cop_port; - char *env; - char cmd_buf[20]; - int val = 0; - int cs = 0; - int len, i; - - if (brightness) { - val = simple_strtol(brightness, NULL, 10); - } else { - env = getenv("brightness"); - if (env) - val = simple_strtol(env, NULL, 10); - } - - if (val < 0) - val = 0; - - if (val > MAX_BRIGHTNESS) - val = MAX_BRIGHTNESS; - - sprintf(cmd_buf, "$SB;%04d;", val); - - len = strlen(cmd_buf); - for (i = 1; i <= len; i++) - cs += cmd_buf[i]; - - cs = (~cs + 1) & 0xff; - sprintf(cmd_buf + len, "%02X\n", cs); - - /* IO Coprocessor communication */ - cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE); - if (!cop_port) { - printf("Error: Can't open IO Coprocessor port.\n"); - return -1; - } - - debug("%s: cmd: %s", __func__, cmd_buf); - write_port(cop_port, cmd_buf); - /* - * Wait for transmission and maybe response data - * before closing the port. - */ - udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY); - memset(cmd_buf, 0, sizeof(cmd_buf)); - len = read_port(cop_port, cmd_buf, sizeof(cmd_buf)); - if (len) - printf("Error: %s\n", cmd_buf); - - close_port(4); - - return 0; -} - -static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag, - int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - return set_lcd_brightness(argv[1]); -} - -U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness, - "set LCD brightness", - "<brightness> - set LCD backlight level to <brightness>.\n" -); diff --git a/board/phytec/pcm030/Kconfig b/board/phytec/pcm030/Kconfig deleted file mode 100644 index 3a3eab8576..0000000000 --- a/board/phytec/pcm030/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PCM030 - -config SYS_BOARD - default "pcm030" - -config SYS_VENDOR - default "phytec" - -config SYS_CONFIG_NAME - default "pcm030" - -endif diff --git a/board/phytec/pcm030/MAINTAINERS b/board/phytec/pcm030/MAINTAINERS deleted file mode 100644 index 4e2ab0d64e..0000000000 --- a/board/phytec/pcm030/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -PCM030 BOARD -M: Jon Smirl <jonsmirl@gmail.com> -S: Maintained -F: board/phytec/pcm030/ -F: include/configs/pcm030.h -F: configs/pcm030_defconfig -F: configs/pcm030_LOWBOOT_defconfig diff --git a/board/phytec/pcm030/Makefile b/board/phytec/pcm030/Makefile deleted file mode 100644 index 2bb49dc7aa..0000000000 --- a/board/phytec/pcm030/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := pcm030.o diff --git a/board/phytec/pcm030/README b/board/phytec/pcm030/README deleted file mode 100644 index 05faab68c8..0000000000 --- a/board/phytec/pcm030/README +++ /dev/null @@ -1,42 +0,0 @@ -To build RAMBOOT, replace this section the main Makefile - -pcm030_config \ -pcm030_RAMBOOT_config \ -pcm030_LOWBOOT_config: unconfig - @ >include/config.h - @[ -z "$(findstring LOWBOOT_,$@)" ] || \ - { echo "CONFIG_SYS_TEXT_BASE = 0xFF000000" >board/phytec/pcm030/config.tmp ; \ - echo "... with LOWBOOT configuration" ; \ - } - @[ -z "$(findstring RAMBOOT_,$@)" ] || \ - { echo "CONFIG_SYS_TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\ - config.tmp ; \ - echo "... with RAMBOOT configuration" ; \ - echo "... remember to make sure that MBAR is already \ - switched to 0xF0000000 !!!" ; \ - } - @$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec - @ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1" - -Alternative SDRAM settings: - -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x715f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 - -/* Settings for XLB = 99 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714b0f00 -#define SDRAM_CONFIG1 0x63611730 -#define SDRAM_CONFIG2 0x47670000 - -The board ships default with the environment in EEPROM -Moving the environment to flash can be more reliable - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xfe0000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 diff --git a/board/phytec/pcm030/mt46v32m16-75.h b/board/phytec/pcm030/mt46v32m16-75.h deleted file mode 100644 index 47fc7c04bd..0000000000 --- a/board/phytec/pcm030/mt46v32m16-75.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * Eric Schumann, Phytec Messtechnik - * adapted for mt46v32m16-75 DDR-RAM - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ - -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x71500F00 -#define SDRAM_CONFIG1 0x73711930 -#define SDRAM_CONFIG2 0x47770000 - -#define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */ diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c deleted file mode 100644 index bdd980da91..0000000000 --- a/board/phytec/pcm030/pcm030.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2006 - * Eric Schumann, Phytec Messtechnik GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <asm/io.h> - -#include "mt46v32m16-75.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start(int hi_addr) -{ - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *)MPC5XXX_CDM; - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000000 | hi_addr_bit)); - - /* precharge all banks */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); - -#ifdef SDRAM_DDR - /* set mode register: extended mode */ - out_be32 (&sdram->mode, (SDRAM_EMODE)); - - /* set mode register: reset DLL */ - out_be32 (&sdram->mode, - (SDRAM_MODE | 0x04000000)); -#endif - - /* precharge all banks */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); - - /* auto refresh */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | 0x80000004 | hi_addr_bit)); - - /* set mode register */ - out_be32 (&sdram->mode, (SDRAM_MODE)); - - /* normal operation */ - out_be32 (&sdram->ctrl, - (SDRAM_CONTROL | hi_addr_bit)); - - /* set CDM clock enable register, set MPC5200B SDRAM bus */ - /* to reduced driver strength */ - out_be32 (&cdm->clock_enable, (0x00CFFFFF)); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make - * real use of CONFIG_SYS_SDRAM_BASE. The code does not - * work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - volatile struct mpc5xxx_mmap_ctl *mm = - (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; - volatile struct mpc5xxx_cdm *cdm = - (struct mpc5xxx_cdm *)MPC5XXX_CDM; - volatile struct mpc5xxx_sdram *sdram = - (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; - ulong dramsize = 0; - ulong dramsize2 = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - /* 256MB at 0x0 */ - out_be32 (&mm->sdram0, 0x0000001b); - /* disabled */ - out_be32 (&mm->sdram1, 0x10000000); - - /* setup config registers */ - out_be32 (&sdram->config1, SDRAM_CONFIG1); - out_be32 (&sdram->config2, SDRAM_CONFIG2); - -#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY) - /* set tap delay */ - out_be32 (&cdm->porcfg, SDRAM_TAPDELAY); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); - sdram_start(1); - test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - out_be32 (&mm->sdram0, - (0x13 + __builtin_ffs(dramsize >> 20) - 1)); - } else { - /* disabled */ - out_be32 (&mm->sdram0, 0); - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = in_be32(&mm->sdram0) & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = in_be32(&mm->sdram1) & 0xFF; - if (dramsize2 >= 0x13) - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - else - dramsize2 = 0; - -#endif /* CONFIG_SYS_RAMBOOT */ - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - -int checkboard(void) -{ - puts("Board: phyCORE-MPC5200B-tiny\n"); - return 0; -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) - -#define GPIO_PSC2_4 0x02000000UL - -void init_ide_reset(void) -{ - volatile struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - debug("init_ide_reset\n"); - - /* Configure PSC2_4 as GPIO output for ATA reset */ - setbits_be32(&wu_gpio->enable, GPIO_PSC2_4); - setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4); - /* Deassert reset */ - setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); -} - -void ide_set_reset(int idereset) -{ - volatile struct mpc5xxx_wu_gpio *wu_gpio = - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; - debug("ide_reset(%d)\n", idereset); - - if (idereset) { - clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); - /* Make a delay. MPC5200 spec says 25 usec min */ - udelay(500000); - } else - setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); -} -#endif /* defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) */ diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c index e923ddc2e2..37d0b85e0e 100644 --- a/board/qualcomm/dragonboard410c/dragonboard410c.c +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c @@ -53,8 +53,8 @@ int board_prepare_usb(enum usb_init_type type) printf("Failed to find usb_hub_reset_pm dt node.\n"); return node; } - ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0, - &hub_reset, 0); + ret = gpio_request_by_name_nodev(offset_to_ofnode(node), + "gpios", 0, &hub_reset, 0); if (ret < 0) { printf("Failed to request usb_hub_reset_pm gpio.\n"); return ret; @@ -69,8 +69,8 @@ int board_prepare_usb(enum usb_init_type type) printf("Failed to find usb_sw_sel_pm dt node.\n"); return 0; } - ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0, - &usb_sel, 0); + ret = gpio_request_by_name_nodev(offset_to_ofnode(node), + "gpios", 0, &usb_sel, 0); if (ret < 0) { printf("Failed to request usb_sw_sel_pm gpio.\n"); return ret; @@ -121,8 +121,8 @@ int misc_init_r(void) return 0; } - if (gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0, &resin, - 0)) { + if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0, + &resin, 0)) { printf("Failed to request key_vol_down button.\n"); return 0; } diff --git a/board/qualcomm/dragonboard410c/u-boot.lds b/board/qualcomm/dragonboard410c/u-boot.lds index 6e1c5a8a67..62ac4d7a60 100644 --- a/board/qualcomm/dragonboard410c/u-boot.lds +++ b/board/qualcomm/dragonboard410c/u-boot.lds @@ -43,6 +43,22 @@ SECTIONS . = ALIGN(8); + .efi_runtime : { + __efi_runtime_start = .; + *(efi_runtime_text) + *(efi_runtime_data) + __efi_runtime_stop = .; + } + + .efi_runtime_rel : { + __efi_runtime_rel_start = .; + *(.relaefi_runtime_text) + *(.relaefi_runtime_data) + __efi_runtime_rel_stop = .; + } + + . = ALIGN(8); + .image_copy_end : { *(.__image_copy_end) diff --git a/board/rockchip/evb_px5/Kconfig b/board/rockchip/evb_px5/Kconfig new file mode 100644 index 0000000000..9a04ee7e61 --- /dev/null +++ b/board/rockchip/evb_px5/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_PX5 + +config SYS_BOARD + default "evb_px5" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_px5" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_px5/MAINTAINERS b/board/rockchip/evb_px5/MAINTAINERS new file mode 100644 index 0000000000..5d09fbf0a9 --- /dev/null +++ b/board/rockchip/evb_px5/MAINTAINERS @@ -0,0 +1,6 @@ +PX5 EVB +M: Andy Yan <andy.yan@rock-chips.com> +S: Maintained +F: board/rockchip/evb_px5 +F: include/configs/evb_px5.h +F: configs/evb-px5_defconfig diff --git a/board/rockchip/evb_px5/Makefile b/board/rockchip/evb_px5/Makefile new file mode 100644 index 0000000000..f5aa5a9824 --- /dev/null +++ b/board/rockchip/evb_px5/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb-px5.o diff --git a/board/rockchip/evb_px5/README b/board/rockchip/evb_px5/README new file mode 100644 index 0000000000..de980f2f23 --- /dev/null +++ b/board/rockchip/evb_px5/README @@ -0,0 +1 @@ +see board/rockchip/sheep_rk3368/README diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c new file mode 100644 index 0000000000..54e62dbb6e --- /dev/null +++ b/board/rockchip/evb_px5/evb-px5.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2017 Andy Yan + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <fdtdec.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3368.h> + +DECLARE_GLOBAL_DATA_PTR; + +int mach_cpu_init(void) +{ + struct rk3368_pmu_grf *pmugrf; + int node; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rk3368-pmugrf"); + pmugrf = (struct rk3368_pmu_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); + + rk_clrsetreg(&pmugrf->gpio0d_iomux, + GPIO0D0_MASK | GPIO0D1_MASK | + GPIO0D2_MASK | GPIO0D3_MASK, + GPIO0D0_GPIO << GPIO0D0_SHIFT | + GPIO0D1_GPIO << GPIO0D1_SHIFT | + GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT | + GPIO0D3_UART4_SIN << GPIO0D3_SHIFT); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x40000000; + + return 0; +} + +int dram_init_banksize(void) +{ + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = 0x3fe00000; + + return 0; +} diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 9db604fa8c..2ee6e462a6 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -1,5 +1,5 @@ EVB-RK3328 -M: William Zhang <william.zhang@rock-chips.com> +M: Kever Yang <kever.yang@rock-chips.com> S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c index a7895cb251..0a26ed56b6 100644 --- a/board/rockchip/evb_rk3328/evb-rk3328.c +++ b/board/rockchip/evb_rk3328/evb-rk3328.c @@ -31,11 +31,6 @@ int dram_init_banksize(void) return 0; } -int usb_gadget_handle_interrupts(void) -{ - return 0; -} - int board_usb_init(int index, enum usb_init_type init) { return 0; diff --git a/board/rockchip/evb_rv1108/Kconfig b/board/rockchip/evb_rv1108/Kconfig new file mode 100644 index 0000000000..4a76e0b9fa --- /dev/null +++ b/board/rockchip/evb_rv1108/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RV1108 + +config SYS_BOARD + default "evb_rv1108" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rv1108" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_rv1108/MAINTAINERS b/board/rockchip/evb_rv1108/MAINTAINERS new file mode 100644 index 0000000000..94def320c4 --- /dev/null +++ b/board/rockchip/evb_rv1108/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RV1108 +M: Andy Yan <andy.yan@rock-chips.com> +S: Maintained +F: board/rockchip/evb_rv1108 +F: include/configs/evb_rv1108.h +F: configs/evb-rv1108_defconfig diff --git a/board/rockchip/evb_rv1108/Makefile b/board/rockchip/evb_rv1108/Makefile new file mode 100644 index 0000000000..dd99054d56 --- /dev/null +++ b/board/rockchip/evb_rv1108/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb_rv1108.o diff --git a/board/rockchip/evb_rv1108/README b/board/rockchip/evb_rv1108/README new file mode 100644 index 0000000000..58895960e9 --- /dev/null +++ b/board/rockchip/evb_rv1108/README @@ -0,0 +1,47 @@ +Here is the step-by-step to boot U-Boot on rv1108 evb. + +Get ddr init binary +============================================================================== + > git clone https://github.com/rockchip-linux/rkbin.git + > dd if=./rkbin/rv1x/rv1108ddr.bin of=ddr.bin bs=4 skip=1 + +Compile U-Boot +=========================== + > make CROSS_COMPILE=arm-linux-gnueabi- evb-rv1108_defconfig all + > ./tools/mkimage -n rv1108 -T rksd -d ddr.bin spl.bin + > cat spl.bin u-boot.bin > u-boot.img + +Flash the image by rkdeveloptool +================================ +rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git + +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + > rkdeveloptool db ./rkbin/rv1x/RV1108_usb_boot.bin + > rkdeveloptool wl 0x40 u-boot.img + > rkdeveloptool RD + +You should be able to get U-Boot log message from boot console: + +DDR Version V1.02 20170220 +In +400MHz +DDR3 +Bus Width=16 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=512MB +mach:2 +OUT + + +U-Boot 2017.05-00693-g3a5b171 (Jun 01 2017 - 17:37:53 +0800) + +Model: Rockchip RV1108 Evaluation board +DRAM: 128 MiB +APLL: 600000000 DPLL:792000000 GPLL:384000000 +MMC: +Using default environment + +In: serial@10210000 +Out: serial@10210000 +Err: serial@10210000 +Net: No ethernet found. +Hit any key to stop autoboot: 0 +=> diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c new file mode 100644 index 0000000000..fe37eac420 --- /dev/null +++ b/board/rockchip/evb_rv1108/evb_rv1108.c @@ -0,0 +1,52 @@ +/* + * (C)Copyright 2016 Rockchip Electronics Co., Ltd + * Authors: Andy Yan <andy.yan@rock-chips.com> + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <fdtdec.h> +#include <asm/arch/grf_rv1108.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +int mach_cpu_init(void) +{ + int node; + struct rv1108_grf *grf; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf"); + grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); + + /*evb board use UART2 m0 for debug*/ + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D2_MASK | GPIO2D1_MASK, + GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT | + GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT); + rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK); + + return 0; +} + + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x8000000; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0x60000000; + gd->bd->bi_dram[0].size = 0x8000000; + + return 0; +} diff --git a/board/rockchip/sheep_rk3368/Kconfig b/board/rockchip/sheep_rk3368/Kconfig new file mode 100644 index 0000000000..d39b5e8b1a --- /dev/null +++ b/board/rockchip/sheep_rk3368/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SHEEP + +config SYS_BOARD + default "sheep_rk3368" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "sheep_rk3368" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/sheep_rk3368/MAINTAINERS b/board/rockchip/sheep_rk3368/MAINTAINERS new file mode 100644 index 0000000000..cd5de9923e --- /dev/null +++ b/board/rockchip/sheep_rk3368/MAINTAINERS @@ -0,0 +1,6 @@ +RK3368 Sheep Board +M: Andy Yan <andy.yan@rock-chips.com> +S: Maintained +F: board/rockchip/sheep_rk3368 +F: include/configs/sheep_rk3368.h +F: configs/sheep-rk3368_defconfig diff --git a/board/rockchip/sheep_rk3368/Makefile b/board/rockchip/sheep_rk3368/Makefile new file mode 100644 index 0000000000..a38b9ced73 --- /dev/null +++ b/board/rockchip/sheep_rk3368/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += sheep_rk3368.o diff --git a/board/rockchip/sheep_rk3368/README b/board/rockchip/sheep_rk3368/README new file mode 100644 index 0000000000..2d078cbe5c --- /dev/null +++ b/board/rockchip/sheep_rk3368/README @@ -0,0 +1,44 @@ +Here is the step-by-step to boot to U-Boot on rk3368. + +Get miniloader and trust.img form rockchip vendor u-boot source code +============================================================================== + > git clone https://github.com/rockchip-linux/u-boot.git rockchip-uboot + > cd rockchip-uboot + > make rk3368_defconfig /*chose px5_defconfig if you run a px5 platform here*/ + > ./mkv8.sh + +Compile the upstream U-Boot +=========================== + > cd u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- sheep-rk3368_defconfig all + +Package u-boot for miniloader +================================ + > ../rockchip-uboot/tools/loaderimage --pack --uboot u-boot.bin u-boot.img + +Flash the image by rkdeveloptool +================================ +rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git + +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + > rkdeveloptool db ./rockchip-uboot/rk3368_loader_v2.00.256.bin + > rkdeveloptool wl 0x6000 ./rockchip-uboot/trust.img + > rkdeveloptool wl 0x4000 ./u-boot/u-boot.img + > rkdeveloptool RD + +You should be able to get U-Boot log message from boot console: + +U-Boot 2017.05-rc3-01094-g9ddd1e8-dirty (May 15 2017 - 15:57:23 +0800) + +Model: Rockchip sheep board +DRAM: 2 GiB +MMC: dwmmc@ff0f0000: 0 +Using default environment + +In: serial@ff690000 +Out: serial@ff690000 +Err: serial@ff690000 +Net: Net Initialization Skipped +No ethernet found. +Hit any key to stop autoboot: 0 +=> diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c new file mode 100644 index 0000000000..df1fd9d2c3 --- /dev/null +++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2017 Andy Yan + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3368.h> +#include <syscon.h> + +DECLARE_GLOBAL_DATA_PTR; + +int mach_cpu_init(void) +{ + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x80000000; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = 0x7fe00000; + + return 0; +} diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 79073d8aaa..f60dddac7b 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -26,6 +26,7 @@ #include <net.h> #endif #include <netdev.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index accf16f151..1469136295 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -25,6 +25,7 @@ #include <net.h> #endif #include <netdev.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index c1225800a9..e2620e3c04 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -25,6 +25,7 @@ #include <net.h> #endif #include <netdev.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/sagem/f@st1704/Kconfig b/board/sagem/f@st1704/Kconfig new file mode 100644 index 0000000000..4566fcc9c5 --- /dev/null +++ b/board/sagem/f@st1704/Kconfig @@ -0,0 +1,12 @@ +if BOARD_SAGEM_FAST1704 + +config SYS_BOARD + default "f@st1704" + +config SYS_VENDOR + default "sagem" + +config SYS_CONFIG_NAME + default "sagem_f@st1704" + +endif diff --git a/board/sagem/f@st1704/MAINTAINERS b/board/sagem/f@st1704/MAINTAINERS new file mode 100644 index 0000000000..72e1c5ccd0 --- /dev/null +++ b/board/sagem/f@st1704/MAINTAINERS @@ -0,0 +1,6 @@ +SAGEM F@ST1704 BOARD +M: Álvaro Fernández Rojas <noltari@gmail.com> +S: Maintained +F: board/sagem/f@st1704/ +F: include/configs/sagem_f@st1704.h +F: configs/sagem_f@st1704_ram_defconfig diff --git a/board/sagem/f@st1704/Makefile b/board/sagem/f@st1704/Makefile new file mode 100644 index 0000000000..a5f97f804e --- /dev/null +++ b/board/sagem/f@st1704/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += f@st1704.o diff --git a/board/sagem/f@st1704/f@st1704.c b/board/sagem/f@st1704/f@st1704.c new file mode 100644 index 0000000000..d181ca68a0 --- /dev/null +++ b/board/sagem/f@st1704/f@st1704.c @@ -0,0 +1,7 @@ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 17626966aa..88299f17e3 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -351,8 +351,8 @@ void reset_misc(void) if (node < 0) return; - gpio_request_by_name_nodev(gd->fdt_blob, node, "reset-gpio", 0, &gpio, - GPIOD_IS_OUT); + gpio_request_by_name_nodev(offset_to_ofnode(node), "reset-gpio", 0, + &gpio, GPIOD_IS_OUT); if (dm_gpio_is_valid(&gpio)) { /* diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index aec1f396b0..44f412db5d 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -45,7 +45,7 @@ static void board_enable_audio_codec(void) if (node <= 0) return; - ret = gpio_request_by_name_nodev(gd->fdt_blob, node, + ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "codec-enable-gpio", 0, &en_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); if (ret == -FDT_ERR_NOTFOUND) diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index dc4dead20b..b18eed2fac 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -18,6 +18,19 @@ #include <asm/gpio.h> #include <linux/input.h> #include <dm.h> +/* + * Use #ifdef to work around conflicting headers while we wait for this to be + * converted to driver model. + */ +#ifdef CONFIG_DM_PMIC_MAX77686 +#include <power/max77686_pmic.h> +#endif +#ifdef CONFIG_DM_PMIC_MAX8998 +#include <power/max8998_pmic.h> +#endif +#ifdef CONFIG_PMIC_MAX8997 +#include <power/max8997_pmic.h> +#endif #include <power/pmic.h> #include <mmc.h> diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 12593830e9..d0247ac257 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -17,6 +17,7 @@ #include <samsung/misc.h> #include <usb.h> #include <usb_mass_storage.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 79e127d99a..5d23844458 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -11,6 +11,7 @@ #include <asm/io.h> #include <asm/arch/sromc.h> #include <netdev.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index feb8a341be..cc6eaf7ad0 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -23,6 +23,7 @@ #include <libtizen.h> #include <samsung/misc.h> #include <usb_mass_storage.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/sandbox/MAINTAINERS b/board/sandbox/MAINTAINERS index 4dcbf4ba03..6d0790ccd1 100644 --- a/board/sandbox/MAINTAINERS +++ b/board/sandbox/MAINTAINERS @@ -18,3 +18,10 @@ S: Maintained F: board/sandbox/ F: include/configs/sandbox_spl.h F: configs/sandbox_spl_defconfig + +SANDBOX FLAT TREE BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/sandbox/ +F: include/configs/sandbox.h +F: configs/sandbox_flattree_defconfig diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 9cafcea53a..b967227411 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -28,6 +28,7 @@ #include <miiphy.h> #include <cpsw.h> #include <watchdog.h> +#include <asm/mach-types.h> #include "../common/factoryset.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 2773f5957e..3a8257cac3 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -131,8 +131,12 @@ int board_init(void) /* Toggle GPIO41 to reset onboard switch and phy */ clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9)); + /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */ + clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); + clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19)); mdelay(1); setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); + setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); mdelay(10); /* Init I2C IO expanders */ diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index 396b5bdf60..8f8132a31a 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -11,6 +11,7 @@ #include <nand.h> #include <asm/io.h> #include <linux/mtd/fsmc_nand.h> +#include <asm/mach-types.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 6f39ef1b40..d07dda34e9 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -12,6 +12,7 @@ #include <nand.h> #include <asm/io.h> #include <linux/mtd/fsmc_nand.h> +#include <asm/mach-types.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 52196afd17..66073f3715 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -12,6 +12,7 @@ #include <nand.h> #include <asm/io.h> #include <linux/mtd/fsmc_nand.h> +#include <asm/mach-types.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index 858a9cae76..2a54b8b323 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -11,6 +11,7 @@ #include <nand.h> #include <asm/io.h> #include <linux/mtd/fsmc_nand.h> +#include <asm/mach-types.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c index f8e9fddb0f..2c34ea1ad1 100644 --- a/board/spear/x600/x600.c +++ b/board/spear/x600/x600.c @@ -14,6 +14,7 @@ #include <phy.h> #include <rtc.h> #include <asm/io.h> +#include <asm/mach-types.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index d16d73fc97..8c8abf6a06 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -12,12 +12,12 @@ */ #include <common.h> +#include <dm.h> #include <asm/io.h> #include <asm/armv7m.h> #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> #include <asm/arch/fmc.h> -#include <dm/platdata.h> #include <dm/platform_data/serial_stm32.h> #include <asm/arch/stm32_periph.h> #include <asm/arch/stm32_defs.h> diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index dc3a9dcade..fc4c60c3a4 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -8,11 +8,12 @@ #include <common.h> #include <dm.h> #include <ram.h> +#include <spl.h> #include <asm/io.h> #include <asm/armv7m.h> #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> -#include <dm/platdata.h> +#include <asm/arch/fmc.h> #include <dm/platform_data/serial_stm32x7.h> #include <asm/arch/stm32_periph.h> #include <asm/arch/stm32_defs.h> @@ -36,16 +37,18 @@ int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size) } int dram_init(void) { - struct udevice *dev; int rv; fdt_addr_t mr_base, mr_size; +#ifndef CONFIG_SUPPORT_SPL + struct udevice *dev; rv = uclass_get_device(UCLASS_RAM, 0, &dev); if (rv) { debug("DRAM init failed: %d\n", rv); return rv; } +#endif rv = get_memory_base_size(&mr_base, &mr_size); if (rv) return rv; @@ -87,6 +90,37 @@ int board_early_init_f(void) } #endif +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + debug("SPL: booting kernel\n"); + /* break into full u-boot on 'c' */ + return serial_tstc() && serial_getc() == 'c'; +} +#endif + +int spl_dram_init(void) +{ + struct udevice *dev; + int rv; + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) + debug("DRAM init failed: %d\n", rv); + return rv; +} +void spl_board_init(void) +{ + spl_dram_init(); + preloader_console_init(); + arch_cpu_init(); /* to configure mpu for sdram rw permissions */ +} +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_XIP; +} + +#endif u32 get_board_rev(void) { return 0; @@ -101,7 +135,7 @@ int board_late_init(void) if (node < 0) return -1; - gpio_request_by_name_nodev(gd->fdt_blob, node, "led-gpio", 0, &gpio, + gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio, GPIOD_IS_OUT); if (dm_gpio_is_valid(&gpio)) { @@ -115,8 +149,8 @@ int board_late_init(void) if (node < 0) return -1; - gpio_request_by_name_nodev(gd->fdt_blob, node, "button-gpio", 0, &gpio, - GPIOD_IS_IN); + gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0, + &gpio, GPIOD_IS_IN); if (dm_gpio_is_valid(&gpio)) { if (dm_gpio_get_value(&gpio)) diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c index 6a19730069..85ac66ec3a 100644 --- a/board/st/stv0991/stv0991.c +++ b/board/st/stv0991/stv0991.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <dm.h> #include <miiphy.h> #include <asm/arch/stv0991_periph.h> #include <asm/arch/stv0991_defs.h> @@ -13,7 +14,6 @@ #include <asm/arch/gpio.h> #include <netdev.h> #include <asm/io.h> -#include <dm/platdata.h> #include <dm/platform_data/serial_pl01x.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index a512a201d0..e9f3e350d0 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -114,6 +114,11 @@ S: Maintained F: configs/Bananapi_M2_Ultra_defconfig F: arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +BANANAPI M64 +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/bananapi_m64_defconfig + COLOMBUS BOARD M: Maxime Ripard <maxime.ripard@free-electrons.com> S: Maintained @@ -237,11 +242,26 @@ M: Siarhei Siamashka <siarhei.siamashka@gmail.com> S: Maintained F: configs/MSI_Primo81_defconfig +NANOPI-M1 BOARD +M: Mylène Josserand <mylene.josserand@free-electrons.com> +S: Maintained +F: configs/nanopi_m1_defconfig + +NANOPI-M1 PLUS BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/nanopi_m1_plus_defconfig + NANOPI-NEO BOARD M: Jelle van der Waa <jelle@vdwaa.nl> S: Maintained F: configs/nanopi_neo_defconfig +NANOPI-NEO2 BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/nanopi_neo2_defconfig + NANOPI-NEO-AIR BOARD M: Jelle van der Waa <jelle@vdwaa.nl> S: Maintained @@ -252,16 +272,31 @@ M: FUKAUMI Naoki <naobsd@gmail.com> S: Maintained F: configs/Nintendo_NES_Classic_Edition_defconfig +ORANGEPI WIN/WIN PLUS BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/orangepi_win_defconfig + ORANGEPI ZERO BOARD M: Icenowy Zheng <icenowy@aosc.xyz> S: Maintained F: configs/orangepi_zero_defconfig +ORANGEPI ZERO PLUS 2 BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/orangepi_zero_plus2_defconfig + ORANGEPI PC 2 BOARD M: Andre Przywara <andre.przywara@arm.com> S: Maintained F: configs/orangepi_pc2_defconfig +ORANGEPI PRIME BOARD +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/orangepi_prime_defconfig + PINE64 BOARDS M: Andre Przywara <andre.przywara@arm.com> S: Maintained @@ -294,6 +329,11 @@ M: VishnuPatekar <vishnupatekar0510@gmail.com> S: Maintained F: configs/Sinovoip_BPI_M3_defconfig +SOPINE BOARD +M: Icenowy Zheng <icenowy@aosc.io> +S: Maintained +F: configs/sopine_baseboard_defconfig + SUNCHIP CX-A99 BOARD M: Rask Ingemann Lambertsen <rask@formelder.dk> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index f79bd5c62c..800f412b38 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -33,6 +33,7 @@ #include <nand.h> #include <net.h> #include <sy8106a.h> +#include <asm/setup.h> #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README index 1a8d02b480..250e3459a3 100644 --- a/board/theobroma-systems/puma_rk3399/README +++ b/board/theobroma-systems/puma_rk3399/README @@ -56,8 +56,7 @@ Package the image ================= > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl.img - > tools/mkimage -f board/theobroma/puma_rk3399/fit_spl_atf.its \ - -E rk3399_bl3x.itb + > make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb Flash the image =============== @@ -67,7 +66,7 @@ Copy the SPL to offset 32k and the FIT image containing the payloads card. > dd if=spl.img of=/dev/sdb seek=64 - > dd if=rk3399_bl3x.itb of=/dev/sdb seek=512 + > dd if=u-boot.itb of=/dev/sdb seek=512 After powering up the board (with the inserted SD card), you should see a U-Boot console on UART0 (115200n8). diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 0a8861a3b3..6fff3e1ae6 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -9,10 +9,15 @@ #include <ram.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> +#include <misc.h> +#include <asm/setup.h> #include <asm/arch/periph.h> #include <power/regulator.h> #include <u-boot/sha256.h> +#define RK3399_CPUID_OFF 0x7 +#define RK3399_CPUID_LEN 0x10 + DECLARE_GLOBAL_DATA_PTR; #define RK3399_CPUID_OFF 0x7 @@ -63,6 +68,119 @@ out: return 0; } +static void setup_macaddr(void) +{ +#if CONFIG_IS_ENABLED(CMD_NET) + int ret; + const char *cpuid = getenv("cpuid#"); + u8 hash[SHA256_SUM_LEN]; + int size = sizeof(hash); + u8 mac_addr[6]; + + /* Only generate a MAC address, if none is set in the environment */ + if (getenv("ethaddr")) + return; + + if (!cpuid) { + debug("%s: could not retrieve 'cpuid#'\n", __func__); + return; + } + + ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); + if (ret) { + debug("%s: failed to calculate SHA256\n", __func__); + return; + } + + /* Copy 6 bytes of the hash to base the MAC address on */ + memcpy(mac_addr, hash, 6); + + /* Make this a valid MAC address and set it */ + mac_addr[0] &= 0xfe; /* clear multicast bit */ + mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + eth_setenv_enetaddr("ethaddr", mac_addr); +#endif + + return; +} + +static void setup_serial(void) +{ +#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) + struct udevice *dev; + int ret, i; + u8 cpuid[RK3399_CPUID_LEN]; + u8 low[RK3399_CPUID_LEN/2], high[RK3399_CPUID_LEN/2]; + char cpuid_str[RK3399_CPUID_LEN * 2 + 1]; + u64 serialno; + char serialno_str[16]; + + /* retrieve the device */ + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(rockchip_efuse), &dev); + if (ret) { + debug("%s: could not find efuse device\n", __func__); + return; + } + + /* read the cpu_id range from the efuses */ + ret = misc_read(dev, RK3399_CPUID_OFF, &cpuid, sizeof(cpuid)); + if (ret) { + debug("%s: reading cpuid from the efuses failed\n", + __func__); + return; + } + + memset(cpuid_str, 0, sizeof(cpuid_str)); + for (i = 0; i < 16; i++) + sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); + + debug("cpuid: %s\n", cpuid_str); + + /* + * Mix the cpuid bytes using the same rules as in + * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c + */ + for (i = 0; i < 8; i++) { + low[i] = cpuid[1 + (i << 1)]; + high[i] = cpuid[i << 1]; + } + + serialno = crc32_no_comp(0, low, 8); + serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; + snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); + + setenv("cpuid#", cpuid_str); + setenv("serial#", serialno_str); +#endif + + return; +} + +int misc_init_r(void) +{ + setup_serial(); + setup_macaddr(); + + return 0; +} + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial_string; + u64 serial = 0; + + serial_string = getenv("serial#"); + + if (serial_string) + serial = simple_strtoull(serial_string, NULL, 16); + + serialnr->high = (u32)(serial >> 32); + serialnr->low = (u32)(serial & 0xffffffff); +} +#endif + int dram_init(void) { struct ram_info ram; diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 517965c0f0..0a16529b5f 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -26,6 +26,7 @@ #include <asm/io.h> #include <asm/emif.h> #include <asm/gpio.h> +#include <asm/omap_common.h> #include <asm/omap_sec_common.h> #include <asm/omap_mmc.h> #include <i2c.h> @@ -343,14 +344,6 @@ static void scale_vcores_bone(int freq) if (board_is_bone_lt()) freq = MPUPLL_M_1000; - if (freq == MPUPLL_M_1000) { - usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; - mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; - } else { - usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; - mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; - } - switch (freq) { case MPUPLL_M_1000: mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; @@ -358,15 +351,16 @@ static void scale_vcores_bone(int freq) break; case MPUPLL_M_800: mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; - usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; break; case MPUPLL_M_720: mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV; - usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; break; case MPUPLL_M_600: case MPUPLL_M_500: case MPUPLL_M_300: + default: mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV; usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; break; @@ -469,7 +463,7 @@ void scale_vcores(void) gpi2c_init(); freq = am335x_get_efuse_mpu_max_freq(cdev); - if (board_is_bone()) + if (board_is_beaglebonex()) scale_vcores_bone(freq); else scale_vcores_generic(freq); diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h index 48c139a817..e13fcff02a 100644 --- a/board/ti/am335x/board.h +++ b/board/ti/am335x/board.h @@ -39,6 +39,11 @@ static inline int board_is_bbg1(void) return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4); } +static inline int board_is_beaglebonex(void) +{ + return board_is_bone() || board_is_bone_lt() || board_is_bbg1(); +} + static inline int board_is_evm_sk(void) { return board_ti_is("A335X_SK"); diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index f44103d4d6..54f40e64a4 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -20,6 +20,7 @@ #include <asm/arch/ddr_defs.h> #include <asm/arch/gpio.h> #include <asm/emif.h> +#include <asm/omap_common.h> #include "../common/board_detect.h" #include "board.h" #include <power/pmic.h> @@ -421,6 +422,13 @@ void scale_vcores_generic(u32 m) printf("%s failure\n", __func__); return; } + + /* Set DCDC3 (DDR) voltage */ + if (tps65218_voltage_update(TPS65218_DCDC3, + TPS65218_DCDC3_VOLT_SEL_1350MV)) { + printf("%s failure\n", __func__); + return; + } } void scale_vcores_idk(u32 m) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 3be697a6ea..bf8c8e1a67 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -343,6 +343,54 @@ struct vcores_data am572x_idk_volts = { .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, }; +struct vcores_data am571x_idk_volts = { + .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, + .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, + .mpu.pmic = &tps659038, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + + .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, + .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, + .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, + .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, + .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45, + .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, + + .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, + .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, + .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, + .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, + .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS6, + .gpu.pmic = &tps659038, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, + + .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, + .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS7, + .core.pmic = &tps659038, + + .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, + .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, + .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, + .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, + .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS45, + .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, +}; + int get_voltrail_opp(int rail_offset) { int opp; @@ -452,6 +500,8 @@ void vcores_init(void) { if (board_is_am572x_idk()) *omap_vcores = &am572x_idk_volts; + else if (board_is_am571x_idk()) + *omap_vcores = &am571x_idk_volts; else *omap_vcores = &beagle_x15_volts; } @@ -573,6 +623,7 @@ int board_late_init(void) val); omap_die_id_serial(); + omap_set_fastboot_vars(); am57x_idk_lcd_detect(); @@ -593,8 +644,8 @@ void set_muxconf_regs(void) void recalibrate_iodelay(void) { const struct pad_conf_entry *pconf; - const struct iodelay_cfg_entry *iod; - int pconf_sz, iod_sz; + const struct iodelay_cfg_entry *iod, *delta_iod; + int pconf_sz, iod_sz, delta_iod_sz = 0; int ret; if (board_is_am572x_idk()) { @@ -646,6 +697,9 @@ void recalibrate_iodelay(void) if (am571x_idk_needs_lcd()) { pconf = core_padconf_array_vout_am571x_idk; pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk); + delta_iod = iodelay_cfg_array_am571x_idk_4port; + delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port); + } else { pconf = core_padconf_array_icss1eth_am571x_idk; pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk); @@ -655,6 +709,10 @@ void recalibrate_iodelay(void) /* Setup IOdelay configuration */ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz); + if (delta_iod_sz) + ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod, + delta_iod_sz); + err: /* Closeup.. remove isolation */ __recalibrate_iodelay_end(ret); diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index aff274c74f..b4a71bd7c8 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -67,8 +67,8 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */ {GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */ {GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */ - {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */ - {VIN1B_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1b_clk1.gpio2_31 */ + {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */ + {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */ {VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */ {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */ {VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */ @@ -87,14 +87,14 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */ {VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */ - {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */ + {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.pr1_uart0_cts_n */ {VIN2A_VSYNC0, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */ - {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */ - {VIN2A_D1, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */ - {VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */ - {VIN2A_D3, (M8 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */ - {VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */ - {VIN2A_D5, (M8 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */ + {VIN2A_D0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d0.pr1_uart0_rxd */ + {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */ + {VIN2A_D2, (M8 | PIN_INPUT_PULLUP)}, /* vin2a_d2.uart10_rxd */ + {VIN2A_D3, (M8 | PIN_OUTPUT)}, /* vin2a_d3.uart10_txd */ + {VIN2A_D4, (M8 | PIN_INPUT_PULLUP)}, /* vin2a_d4.uart10_ctsn */ + {VIN2A_D5, (M8 | PIN_OUTPUT_PULLUP)}, /* vin2a_d5.uart10_rtsn */ {VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */ {VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */ {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */ @@ -113,40 +113,12 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ - {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */ - {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */ {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */ - {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */ - {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */ - {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */ - {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */ - {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */ - {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */ - {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */ - {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */ - {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */ - {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */ - {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */ - {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */ - {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */ - {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */ - {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */ - {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */ - {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */ - {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */ - {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */ - {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */ - {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */ - {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */ - {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */ - {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */ - {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */ - {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */ - {MDIO_MCLK, (M0 | PIN_OUTPUT)}, /* mdio_mclk.mdio_mclk */ - {MDIO_D, (M0 | PIN_INPUT)}, /* mdio_d.mdio_d */ + {MDIO_MCLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */ {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */ - {UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */ - {UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */ + {UART3_RXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_rxd.gpio5_18 */ + {UART3_TXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_txd.gpio5_19 */ {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ @@ -159,8 +131,8 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ - {USB1_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb1_drvvbus.usb1_drvvbus */ - {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN)}, /* usb2_drvvbus.usb2_drvvbus */ + {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */ {GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */ {GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */ {GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */ @@ -169,48 +141,36 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */ {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */ {MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */ - {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */ + {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_fsx.i2c3_scl */ {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */ {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */ - {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.i2c5_sda */ - {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_axr1.i2c5_scl */ + {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */ + {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ - {MCASP1_AXR8, (M14 | PIN_INPUT)}, /* mcasp1_axr8.gpio5_10 */ - {MCASP1_AXR9, (M14 | PIN_INPUT)}, /* mcasp1_axr9.gpio5_11 */ - {MCASP1_AXR10, (M14 | PIN_INPUT)}, /* mcasp1_axr10.gpio5_12 */ - {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr11.gpio4_17 */ - {MCASP1_AXR12, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */ - {MCASP1_AXR13, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr13.mcasp7_axr1 */ - {MCASP1_AXR14, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */ - {MCASP1_AXR15, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */ - {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */ - {MCASP2_FSX, (M0 | PIN_INPUT)}, /* mcasp2_fsx.mcasp2_fsx */ - {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */ - {MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */ - {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */ - {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */ - {MCASP2_AXR2, (M0 | PIN_INPUT)}, /* mcasp2_axr2.mcasp2_axr2 */ - {MCASP2_AXR3, (M0 | PIN_INPUT)}, /* mcasp2_axr3.mcasp2_axr3 */ - {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */ - {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */ - {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */ - {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.mcasp2_axr7 */ + {MCASP1_AXR8, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr8.gpio5_10 */ + {MCASP1_AXR9, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr9.gpio5_11 */ + {MCASP1_AXR10, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr10.gpio5_12 */ + {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */ + {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */ + {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr13.mcasp7_axr1 */ + {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */ + {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */ {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ - {MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */ - {MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */ - {MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */ + {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */ + {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */ + {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr1.mcasp3_axr1 */ {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_aclkx.uart8_rxd */ - {MCASP4_FSX, (M3 | PIN_OUTPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */ - {MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */ + {MCASP4_FSX, (M3 | PIN_OUTPUT)}, /* mcasp4_fsx.uart8_txd */ + {MCASP4_AXR0, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr0.uart8_ctsn */ {MCASP4_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */ {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_aclkx.uart9_rxd */ - {MCASP5_FSX, (M3 | PIN_OUTPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */ - {MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */ + {MCASP5_FSX, (M3 | PIN_OUTPUT)}, /* mcasp5_fsx.uart9_txd */ + {MCASP5_AXR0, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr0.uart9_ctsn */ {MCASP5_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ @@ -218,7 +178,7 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ - {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */ + {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */ {GPIO6_10, (M10 | PIN_OUTPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */ {GPIO6_11, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ {MMC3_CLK, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_clk.mmc3_clk */ @@ -227,31 +187,31 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat1.mmc3_dat1 */ {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat2.mmc3_dat2 */ {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat3.mmc3_dat3 */ - {MMC3_DAT4, (M1 | PIN_OUTPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */ - {MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */ - {MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */ - {MMC3_DAT7, (M1 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */ + {MMC3_DAT4, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat4.mmc3_dat4 */ + {MMC3_DAT5, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat5.mmc3_dat5 */ + {MMC3_DAT6, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat6.mmc3_dat6 */ + {MMC3_DAT7, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat7.mmc3_dat7 */ {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */ {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */ {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */ {SPI1_CS0, (M14 | PIN_INPUT)}, /* spi1_cs0.gpio7_10 */ {SPI1_CS1, (M14 | PIN_INPUT)}, /* spi1_cs1.gpio7_11 */ - {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP)}, /* spi1_cs3.hdmi1_cec */ + {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */ - {SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */ - {SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */ - {SPI2_CS0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_cs0.gpio7_17 */ - {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ - {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */ - {UART1_RXD, (M0 | PIN_INPUT_PULLUP)}, /* uart1_rxd.uart1_rxd */ - {UART1_TXD, (M0 | PIN_OUTPUT_PULLDOWN)}, /* uart1_txd.uart1_txd */ + {SPI2_D1, (M14 | PIN_INPUT_SLEW)}, /* spi2_d1.gpio7_15 */ + {SPI2_D0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_d0.gpio7_16 */ + {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */ + {DCAN1_TX, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */ + {DCAN1_RX, (M0 | PIN_INPUT | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */ + {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */ + {UART1_TXD, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.uart1_txd */ {UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.gpio7_24 */ {UART1_RTSN, (M14 | PIN_INPUT)}, /* uart1_rtsn.gpio7_25 */ {UART2_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_rxd.gpio7_26 */ {UART2_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.gpio7_27 */ {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */ - {UART2_RTSN, (M1 | PIN_OUTPUT_PULLDOWN)}, /* uart2_rtsn.uart3_txd */ + {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */ {I2C1_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_sda.i2c1_sda */ {I2C1_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_scl.i2c1_scl */ {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */ @@ -263,7 +223,7 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */ {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */ - {TDI, (M0 | PIN_INPUT_PULLUP)}, /* tdi.tdi */ + {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */ {TDO, (M0 | PIN_OUTPUT)}, /* tdo.tdo */ {TCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* tclk.tclk */ {TRSTN, (M0 | PIN_INPUT)}, /* trstn.trstn */ @@ -275,11 +235,67 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = { }; const struct pad_conf_entry core_padconf_array_delta_x15_sr1_1[] = { - {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */ + {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */ + {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_de.vout1_de */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d23.vout1_d23 */ }; const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0[] = { {VIN1A_CLK0, (M14 | PIN_INPUT)}, /* vin1a_clk0.gpio2_30 */ + {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */ }; const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { @@ -302,16 +318,16 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */ {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */ {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */ - {GPMC_A19, (M1 | PIN_INPUT)}, /* gpmc_a19.mmc2_dat4 */ - {GPMC_A20, (M1 | PIN_INPUT)}, /* gpmc_a20.mmc2_dat5 */ - {GPMC_A21, (M1 | PIN_INPUT)}, /* gpmc_a21.mmc2_dat6 */ - {GPMC_A22, (M1 | PIN_INPUT)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ - {GPMC_A24, (M1 | PIN_INPUT)}, /* gpmc_a24.mmc2_dat0 */ - {GPMC_A25, (M1 | PIN_INPUT)}, /* gpmc_a25.mmc2_dat1 */ - {GPMC_A26, (M1 | PIN_INPUT)}, /* gpmc_a26.mmc2_dat2 */ - {GPMC_A27, (M1 | PIN_INPUT)}, /* gpmc_a27.mmc2_dat3 */ - {GPMC_CS1, (M1 | PIN_INPUT)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */ {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */ {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */ @@ -351,37 +367,37 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ - {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */ - {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */ + {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */ {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */ - {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */ - {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */ - {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */ - {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */ - {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */ - {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */ - {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */ - {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */ - {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */ - {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */ - {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */ - {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */ - {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */ - {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */ - {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */ - {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */ - {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */ - {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */ - {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */ - {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */ - {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */ - {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */ - {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */ - {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */ - {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */ - {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */ - {MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN)}, /* mdio_mclk.mdio_mclk */ - {MDIO_D, (M0 | PIN_INPUT)}, /* mdio_d.mdio_d */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_SLEW)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */ {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ @@ -394,8 +410,8 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ - {USB1_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb1_drvvbus.usb1_drvvbus */ - {USB2_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb2_drvvbus.usb2_drvvbus */ + {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */ {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */ {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */ {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ @@ -404,50 +420,50 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */ {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */ {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */ - {MCASP1_FSX, (M11 | PIN_INPUT)}, /* mcasp1_fsx.pr2_mdio_data */ + {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */ {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */ {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */ - {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.pr2_mii0_rxer */ - {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ + {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */ + {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */ {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */ {MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */ {MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */ {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */ {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */ - {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr8.pr2_mii0_txen */ - {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr9.pr2_mii0_txd3 */ - {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr10.pr2_mii0_txd2 */ - {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr11.pr2_mii0_txd1 */ - {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr12.pr2_mii0_txd0 */ - {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ - {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr14.pr2_mii0_rxdv */ - {MCASP1_AXR15, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ + {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */ + {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */ + {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */ + {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */ + {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */ + {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ + {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */ + {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */ - {MCASP2_FSX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ - {MCASP2_AXR2, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ - {MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr3.pr2_mii0_rxlink */ + {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ + {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ + {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */ {MCASP2_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp2_axr4.gpio1_4 */ {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */ {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */ {MCASP2_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp2_axr7.gpio1_5 */ {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */ - {MCASP3_FSX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.pr2_mii0_col */ - {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr0.pr2_mii1_rxer */ - {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr1.pr2_mii1_rxlink */ + {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */ + {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */ + {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */ {MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */ {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */ - {MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */ + {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */ {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */ {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ - {MMC1_CMD, (M0 | PIN_INPUT)}, /* mmc1_cmd.mmc1_cmd */ - {MMC1_DAT0, (M0 | PIN_INPUT)}, /* mmc1_dat0.mmc1_dat0 */ - {MMC1_DAT1, (M0 | PIN_INPUT)}, /* mmc1_dat1.mmc1_dat1 */ - {MMC1_DAT2, (M0 | PIN_INPUT)}, /* mmc1_dat2.mmc1_dat2 */ - {MMC1_DAT3, (M0 | PIN_INPUT)}, /* mmc1_dat3.mmc1_dat3 */ - {MMC1_SDCD, (M14 | PIN_INPUT)}, /* mmc1_sdcd.gpio6_27 */ - {MMC1_SDWP, (M14 | PIN_INPUT)}, /* mmc1_sdwp.gpio6_28 */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */ + {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */ {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */ {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */ {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */ @@ -465,16 +481,16 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */ {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ - {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP)}, /* spi1_cs3.hdmi1_cec */ + {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */ + {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */ + {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */ + {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */ {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */ - {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */ - {SPI2_D1, (M0 | PIN_OUTPUT)}, /* spi2_d1.spi2_d1 */ - {SPI2_D0, (M0 | PIN_INPUT)}, /* spi2_d0.spi2_d0 */ - {SPI2_CS0, (M0 | PIN_OUTPUT)}, /* spi2_cs0.spi2_cs0 */ - {UART1_RXD, (M14 | PIN_OUTPUT)}, /* uart1_rxd.gpio7_22 */ - {UART1_TXD, (M14 | PIN_OUTPUT)}, /* uart1_txd.gpio7_23 */ + {UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */ + {UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.gpio7_23 */ {UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */ {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */ {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */ @@ -490,7 +506,7 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */ {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */ - {TDI, (M0 | PIN_INPUT_PULLUP)}, /* tdi.tdi */ + {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */ {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */ {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */ {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */ @@ -498,29 +514,30 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = { {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */ {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */ {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */ + {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */ {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */ }; const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = { - {GPMC_A0, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a0.vin1b_d0 */ - {GPMC_A1, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a1.vin1b_d1 */ - {GPMC_A2, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a2.vin1b_d2 */ - {GPMC_A3, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE11)}, /* gpmc_a3.vin1b_d3 */ - {GPMC_A4, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE11)}, /* gpmc_a4.vin1b_d4 */ - {GPMC_A5, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a5.vin1b_d5 */ - {GPMC_A6, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a6.vin1b_d6 */ - {GPMC_A7, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a7.vin1b_d7 */ - {GPMC_A8, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a8.vin1b_hsync1 */ - {GPMC_A9, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a9.vin1b_vsync1 */ - {GPMC_A10, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a10.vin1b_clk1 */ - {GPMC_A11, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a11.vin1b_de1 */ - {GPMC_A12, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a12.vin1b_fld1 */ - {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */ - {GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */ - {GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */ - {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */ - {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN) | MANUAL_MODE}, /* gpmc_a17.qspi1_d1 */ - {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */ + {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin1b_d0 */ + {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin1b_d1 */ + {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin1b_d2 */ + {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin1b_d3 */ + {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin1b_d4 */ + {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin1b_d5 */ + {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin1b_d6 */ + {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin1b_d7 */ + {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin1b_hsync1 */ + {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin1b_vsync1 */ + {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin1b_clk1 */ + {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin1b_de1 */ + {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin1b_fld1 */ + {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */ + {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */ + {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */ + {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */ + {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */ + {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ @@ -531,234 +548,230 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = { {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ - {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */ - {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */ - {GPMC_CS3, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.gpio2_21 */ - {GPMC_CLK, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_clk.gpio2_22 */ - {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */ - {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */ - {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */ - {GPMC_BEN0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.gpio2_26 */ - {GPMC_BEN1, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_ben1.gpio2_27 */ - {GPMC_WAIT0, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */ + {GPMC_CS0, (M14 | PIN_OUTPUT)}, /* gpmc_cs0.gpio2_19 */ + {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */ + {GPMC_CS3, (M14 | PIN_OUTPUT)}, /* gpmc_cs3.gpio2_21 */ + {GPMC_CLK, (M14 | PIN_INPUT)}, /* gpmc_clk.gpio2_22 */ + {GPMC_ADVN_ALE, (M14 | PIN_OUTPUT)}, /* gpmc_advn_ale.gpio2_23 */ + {GPMC_OEN_REN, (M14 | PIN_OUTPUT)}, /* gpmc_oen_ren.gpio2_24 */ + {GPMC_WEN, (M14 | PIN_OUTPUT)}, /* gpmc_wen.gpio2_25 */ + {GPMC_BEN0, (M14 | PIN_OUTPUT)}, /* gpmc_ben0.gpio2_26 */ + {GPMC_BEN1, (M14 | PIN_OUTPUT)}, /* gpmc_ben1.gpio2_27 */ + {GPMC_WAIT0, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */ {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */ {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */ {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */ - {VIN2A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_vsync0.gpio4_0 */ - {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */ - {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */ - {VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.eCAP1_in_PWM1_out */ - {VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */ - {VIN2A_D11, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d11.pr1_mdio_data */ - {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ - {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ - {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ - {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ - {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ - {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_VSYNC0, (M14 | PIN_OUTPUT)}, /* vin2a_vsync0.gpio4_0 */ + {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */ + {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */ + {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */ + {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */ + {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */ + {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ - {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ - {VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */ - {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ - {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */ - {RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)}, /* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */ - {UART3_RXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_rxd.gpio5_18 */ - {UART3_TXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_txd.gpio5_19 */ - {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ - {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ - {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ - {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ - {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ - {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */ + {MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */ + {UART3_RXD, (M14 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* uart3_rxd.gpio5_18 */ + {UART3_TXD, (M14 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* uart3_txd.gpio5_19 */ + {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ - {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},/* rgmii0_rxctl.rgmii0_rxctl */ - {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ - {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ - {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ - {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ - {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ - {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ - {GPIO6_14, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_14.gpio6_14 */ - {GPIO6_15, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_15.gpio6_15 */ - {GPIO6_16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6_16 */ - {XREF_CLK0, (M11 | PIN_INPUT)}, /* xref_clk0.pr2_mii1_col */ - {XREF_CLK1, (M11 | PIN_INPUT_PULLUP)}, /* xref_clk1.pr2_mii1_crs */ - {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */ - {XREF_CLK3, (M15 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.Driveroff */ - {MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */ - {MCASP1_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.pr2_mdio_data */ - {MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.gpio5_0 */ - {MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.gpio5_1 */ - {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.pr2_mii0_rxer */ - {MCASP1_AXR1, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ - {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ - {MCASP1_AXR3, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr3.gpio5_5 */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */ + {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */ + {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ + {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */ + {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */ + {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */ + {XREF_CLK3, (M7 | PIN_INPUT)}, /* xref_clk3.hdq0 */ + {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */ + {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */ + {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */ + {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */ + {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */ + {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ + {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ - {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ - {MCASP1_AXR6, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr6.gpio5_8 */ - {MCASP1_AXR7, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr7.gpio5_9 */ - {MCASP1_AXR8, (M11 | PIN_OUTPUT)}, /* mcasp1_axr8.pr2_mii0_txen */ - {MCASP1_AXR9, (M11 | PIN_OUTPUT)}, /* mcasp1_axr9.pr2_mii0_txd3 */ - {MCASP1_AXR10, (M11 | PIN_OUTPUT)}, /* mcasp1_axr10.pr2_mii0_txd2 */ - {MCASP1_AXR11, (M11 | PIN_OUTPUT)}, /* mcasp1_axr11.pr2_mii0_txd1 */ - {MCASP1_AXR12, (M11 | PIN_OUTPUT)}, /* mcasp1_axr12.pr2_mii0_txd0 */ - {MCASP1_AXR13, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ - {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr14.pr2_mii0_rxdv */ - {MCASP1_AXR15, (M11 | PIN_INPUT)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ - {MCASP2_ACLKX, (M11 | PIN_INPUT)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */ - {MCASP2_FSX, (M11 | PIN_INPUT)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ - {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.Driveroff */ - {MCASP2_FSR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.Driveroff */ - {MCASP2_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.Driveroff */ - {MCASP2_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.Driveroff */ - {MCASP2_AXR2, (M11 | PIN_INPUT)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ - {MCASP2_AXR3, (M11 | PIN_INPUT)}, /* mcasp2_axr3.pr2_mii0_rxlink */ - {MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.gpio1_4 */ - {MCASP2_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.gpio6_7 */ - {MCASP2_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.gpio2_29 */ - {MCASP2_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.gpio1_5 */ - {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_aclkx.pr2_mii0_crs */ - {MCASP3_FSX, (M11 | PIN_INPUT)}, /* mcasp3_fsx.pr2_mii0_col */ - {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr0.pr2_mii1_rxer */ - {MCASP3_AXR1, (M11 | PIN_INPUT)}, /* mcasp3_axr1.pr2_mii1_rxlink */ - {MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.spi3_sclk */ - {MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.spi3_d1 */ - {MCASP4_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.Driveroff */ - {MCASP4_AXR1, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr1.spi3_cs0 */ - {MCASP5_ACLKX, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */ - {MCASP5_FSX, (M12 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.pr2_pru1_gpi2 */ - {MCASP5_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.Driveroff */ - {MCASP5_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr1.Driveroff */ + {MCASP1_AXR5, (M14 | PIN_INPUT)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */ + {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */ + {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */ + {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */ + {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */ + {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ + {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */ + {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ + {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */ + {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ + {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ + {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */ + {MCASP2_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp2_axr4.gpio1_4 */ + {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */ + {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */ + {MCASP2_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp2_axr7.gpio1_5 */ + {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */ + {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */ + {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */ + {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */ + {MCASP4_ACLKX, (M2 | PIN_OUTPUT)}, /* mcasp4_aclkx.spi3_sclk */ + {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */ + {MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */ + {MCASP5_AXR0, (M4 | PIN_INPUT)}, /* mcasp5_axr0.uart3_rxd */ + {MCASP5_AXR1, (M4 | PIN_OUTPUT)}, /* mcasp5_axr1.uart3_txd */ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ - {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */ - {MMC1_SDWP, (M0 | PIN_OUTPUT)}, /* mmc1_sdwp.mmc1_sdwp */ - {GPIO6_10, (M11 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.pr2_mii_mt1_clk */ - {GPIO6_11, (M11 | PIN_OUTPUT)}, /* gpio6_11.pr2_mii1_txen */ - {MMC3_CLK, (M11 | PIN_OUTPUT)}, /* mmc3_clk.pr2_mii1_txd3 */ - {MMC3_CMD, (M11 | PIN_OUTPUT)}, /* mmc3_cmd.pr2_mii1_txd2 */ - {MMC3_DAT0, (M11 | PIN_OUTPUT)}, /* mmc3_dat0.pr2_mii1_txd1 */ - {MMC3_DAT1, (M11 | PIN_OUTPUT)}, /* mmc3_dat1.pr2_mii1_txd0 */ - {MMC3_DAT2, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat2.pr2_mii_mr1_clk */ + {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */ + {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */ + {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */ + {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */ + {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */ + {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */ + {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */ + {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */ + {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */ {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */ - {MMC3_DAT4, (M11 | PIN_INPUT)}, /* mmc3_dat4.pr2_mii1_rxd3 */ - {MMC3_DAT5, (M11 | PIN_INPUT)}, /* mmc3_dat5.pr2_mii1_rxd2 */ - {MMC3_DAT6, (M11 | PIN_INPUT)}, /* mmc3_dat6.pr2_mii1_rxd1 */ - {MMC3_DAT7, (M11 | PIN_INPUT)}, /* mmc3_dat7.pr2_mii1_rxd0 */ - {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */ - {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */ - {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */ - {SPI1_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs0.gpio7_10 */ - {SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs1.gpio7_11 */ - {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ - {SPI2_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.spi2_sclk */ - {SPI2_D1, (M0 | PIN_INPUT_SLEW)}, /* spi2_d1.spi2_d1 */ - {SPI2_D0, (M0 | PIN_INPUT_SLEW)}, /* spi2_d0.spi2_d0 */ - {SPI2_CS0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */ + {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */ + {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */ + {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */ + {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */ + {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */ + {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */ + {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */ + {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ + {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */ + {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */ + {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */ + {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */ + {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */ {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */ - {UART1_RXD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */ - {UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.gpio7_24 */ - {UART1_RTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_rtsn.gpio7_25 */ - {UART2_RXD, (M0 | PIN_INPUT_PULLUP)}, /* uart2_rxd.uart2_rxd */ - {UART2_TXD, (M0 | PIN_INPUT_PULLUP)}, /* uart2_txd.uart2_txd */ - {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */ - {UART2_RTSN, (M1 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.uart3_txd */ - {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */ - {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */ - {WAKEUP0, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup0.Wakeup0 */ - {WAKEUP3, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup3.Wakeup3 */ - {ON_OFF, (M0 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */ - {RTC_PORZ, (M0 | PIN_OUTPUT)}, /* rtc_porz.rtc_porz */ + {UART1_RXD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */ + {UART1_CTSN, (M14 | PIN_OUTPUT)}, /* uart1_ctsn.gpio7_24 */ + {UART1_RTSN, (M14 | PIN_OUTPUT)}, /* uart1_rtsn.gpio7_25 */ + {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */ + {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */ + {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */ + {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */ + {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */ + {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */ + {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */ + {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */ {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */ - {TDO, (M0 | PIN_INPUT_PULLUP)}, /* tdo.tdo */ + {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */ {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */ - {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */ - {RTCK, (M0 | PIN_INPUT)}, /* rtck.rtck */ - {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */ - {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */ - {RESETN, (M0 | PIN_OUTPUT_PULLUP)}, /* resetn.resetn */ - {RSTOUTN, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rstoutn.rstoutn */ + {TRSTN, (M0 | PIN_INPUT)}, /* trstn.trstn */ + {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */ + {EMU0, (M0 | PIN_INPUT)}, /* emu0.emu0 */ + {EMU1, (M0 | PIN_INPUT)}, /* emu1.emu1 */ + {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */ + {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */ }; const struct pad_conf_entry core_padconf_array_icss1eth_am571x_idk[] = { /* PR1 MII0 */ - {VOUT1_D8, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.pr1_mii_mt0_clk */ - {VOUT1_D9, (M13 | PIN_OUTPUT)}, /* vout1_d9.pr1_mii0_txd3 */ - {VOUT1_D10, (M13 | PIN_OUTPUT)}, /* vout1_d10.pr1_mii0_txd2 */ - {VOUT1_D11, (M13 | PIN_OUTPUT)}, /* vout1_d11.pr1_mii0_txen */ - {VOUT1_D12, (M13 | PIN_OUTPUT)}, /* vout1_d12.pr1_mii0_txd1 */ - {VOUT1_D13, (M13 | PIN_OUTPUT)}, /* vout1_d13.pr1_mii0_txd0 */ - {VOUT1_D14, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.pr1_mii_mr0_clk */ + {VOUT1_D8, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d8.pr1_mii_mt0_clk */ + {VOUT1_D9, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d9.pr1_mii0_txd3 */ + {VOUT1_D10, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d10.pr1_mii0_txd2 */ + {VOUT1_D11, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d11.pr1_mii0_txen */ + {VOUT1_D12, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d12.pr1_mii0_txd1 */ + {VOUT1_D13, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d13.pr1_mii0_txd0 */ + {VOUT1_D14, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d14.pr1_mii_mr0_clk */ {VOUT1_D15, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.pr1_mii0_rxdv */ - {VOUT1_D16, (M12 | PIN_INPUT)}, /* vout1_d16.pr1_mii0_rxd3 */ - {VOUT1_D17, (M12 | PIN_INPUT)}, /* vout1_d17.pr1_mii0_rxd2 */ - {VOUT1_D18, (M12 | PIN_INPUT)}, /* vout1_d18.pr1_mii0_rxd1 */ - {VOUT1_D19, (M12 | PIN_INPUT)}, /* vout1_d19.pr1_mii0_rxd0 */ + {VOUT1_D16, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.pr1_mii0_rxd3 */ + {VOUT1_D17, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.pr1_mii0_rxd2 */ + {VOUT1_D18, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.pr1_mii0_rxd1 */ + {VOUT1_D19, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.pr1_mii0_rxd0 */ {VOUT1_D20, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d20.pr1_mii0_rxer */ - {VOUT1_D21, (M12 | PIN_INPUT)}, /* vout1_d21.pr1_mii0_rxlink */ - {VOUT1_D22, (M12 | PIN_INPUT)}, /* vout1_d22.pr1_mii0_col */ - {VOUT1_D23, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d23.pr1_mii0_crs */ + {VOUT1_D21, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.pr1_mii0_rxlink */ + {VOUT1_D22, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.pr1_mii0_col */ + {VOUT1_D23, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.pr1_mii0_crs */ /* PR1 MII1 */ - {VIN2A_D3, (M12 | PIN_INPUT)}, /* vin2a_d3.pr1_mi1_col */ - {VIN2A_D4, (M13 | PIN_OUTPUT)}, /* vin2a_d4.pr1_mii1_txd1 */ - {VIN2A_D5, (M13 | PIN_OUTPUT)}, /* vin2a_d5.pr1_mii1_txd0 */ - {VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.pr1_mii_mt1_clk */ - {VIN2A_D7, (M11 | PIN_OUTPUT)}, /* vin2a_d7.pr1_mii1_txen */ - {VIN2A_D8, (M11 | PIN_OUTPUT)}, /* vin2a_d8.pr1_mii1_txd3 */ - {VIN2A_D9, (M11 | PIN_OUTPUT)}, /* vin2a_d9.pr1_mii1_txd2 */ + {VIN2A_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_mii1_col */ + {VIN2A_D4, (M13 | PIN_OUTPUT_PULLUP)}, /* vin2a_d4.pr1_mii1_txd1 */ + {VIN2A_D5, (M13 | PIN_OUTPUT_PULLUP)}, /* vin2a_d5.pr1_mii1_txd0 */ + {VIN2A_D6, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d6.pr1_mii_mt1_clk */ + {VIN2A_D7, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d7.pr1_mii1_txen */ + {VIN2A_D8, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d8.pr1_mii1_txd3 */ + {VIN2A_D9, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d9.pr1_mii1_txd2 */ {VOUT1_VSYNC, (M12 | PIN_INPUT_PULLUP)}, /* vout1_vsync.pr1_mii1_rxer */ - {VOUT1_D0, (M12 | PIN_INPUT)}, /* vout1_d0.pr1_mii1_rxlink */ - {VOUT1_D1, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d1.pr1_mii1_crs */ - {VOUT1_D2, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.pr1_mii_mr1_clk */ + {VOUT1_D0, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d0.pr1_mii1_rxlink */ + {VOUT1_D1, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.pr1_mii1_crs */ + {VOUT1_D2, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d2.pr1_mii_mr1_clk */ {VOUT1_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.pr1_mii1_rxdv */ - {VOUT1_D4, (M12 | PIN_INPUT)}, /* vout1_d4.pr1_mii1_rxd3 */ - {VOUT1_D5, (M12 | PIN_INPUT)}, /* vout1_d5.pr1_mii1_rxd2 */ - {VOUT1_D6, (M12 | PIN_INPUT)}, /* vout1_d6.pr1_mii1_rxd1 */ - {VOUT1_D7, (M12 | PIN_INPUT)}, /* vout1_d7.pr1_mii1_rxd0 */ + {VOUT1_D4, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.pr1_mii1_rxd3 */ + {VOUT1_D5, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.pr1_mii1_rxd2 */ + {VOUT1_D6, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.pr1_mii1_rxd1 */ + {VOUT1_D7, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.pr1_mii1_rxd0 */ }; const struct pad_conf_entry core_padconf_array_vout_am571x_idk[] = { - {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */ - {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */ - {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */ - {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */ - {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */ - {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */ - {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */ - {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */ - {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */ - {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */ - {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */ - {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */ - {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */ - {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */ - {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */ - {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */ - {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */ - {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */ - {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */ - {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */ - {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */ - {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */ - {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */ - {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */ - {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */ - {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */ - {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */ - {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */ + {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_de.vout1_de */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d23.vout1_d23 */ + + {MCASP5_ACLKX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpi1 */ + {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */ + {UART2_RXD, (M0 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */ + {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */ + {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */ }; const struct pad_conf_entry early_padconf[] = { @@ -798,6 +811,36 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = { {0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */ {0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */ {0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */ + {0x0378, 0, 0}, /* CFG_GPMC_CS3_IN */ + {0x0678, 406, 0}, /* CFG_MMC3_CLK_IN */ + {0x0680, 659, 0}, /* CFG_MMC3_CLK_OUT */ + {0x0684, 0, 0}, /* CFG_MMC3_CMD_IN */ + {0x0688, 0, 0}, /* CFG_MMC3_CMD_OEN */ + {0x068C, 0, 0}, /* CFG_MMC3_CMD_OUT */ + {0x0690, 130, 0}, /* CFG_MMC3_DAT0_IN */ + {0x0694, 0, 0}, /* CFG_MMC3_DAT0_OEN */ + {0x0698, 0, 0}, /* CFG_MMC3_DAT0_OUT */ + {0x069C, 169, 0}, /* CFG_MMC3_DAT1_IN */ + {0x06A0, 0, 0}, /* CFG_MMC3_DAT1_OEN */ + {0x06A4, 0, 0}, /* CFG_MMC3_DAT1_OUT */ + {0x06A8, 0, 0}, /* CFG_MMC3_DAT2_IN */ + {0x06AC, 0, 0}, /* CFG_MMC3_DAT2_OEN */ + {0x06B0, 0, 0}, /* CFG_MMC3_DAT2_OUT */ + {0x06B4, 457, 0}, /* CFG_MMC3_DAT3_IN */ + {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */ + {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */ + {0x06C0, 702, 0}, /* CFG_MMC3_DAT4_IN */ + {0x06C4, 0, 0}, /* CFG_MMC3_DAT4_OEN */ + {0x06C8, 0, 0}, /* CFG_MMC3_DAT4_OUT */ + {0x06CC, 738, 0}, /* CFG_MMC3_DAT5_IN */ + {0x06D0, 0, 0}, /* CFG_MMC3_DAT5_OEN */ + {0x06D4, 0, 0}, /* CFG_MMC3_DAT5_OUT */ + {0x06D8, 856, 0}, /* CFG_MMC3_DAT6_IN */ + {0x06DC, 0, 0}, /* CFG_MMC3_DAT6_OEN */ + {0x06E0, 0, 0}, /* CFG_MMC3_DAT6_OUT */ + {0x06E4, 610, 0}, /* CFG_MMC3_DAT7_IN */ + {0x06E8, 0, 0}, /* CFG_MMC3_DAT7_OEN */ + {0x06EC, 0, 0}, /* CFG_MMC3_DAT7_OUT */ {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ @@ -815,7 +858,7 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = { {0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */ {0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */ {0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */ - {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */ {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */ {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ @@ -871,6 +914,18 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = { {0x06B4, 474, 0}, /* CFG_MMC3_DAT3_IN */ {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */ {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */ + {0x06C0, 792, 0}, /* CFG_MMC3_DAT4_IN */ + {0x06C4, 0, 0}, /* CFG_MMC3_DAT4_OEN */ + {0x06C8, 0, 0}, /* CFG_MMC3_DAT4_OUT */ + {0x06CC, 782, 0}, /* CFG_MMC3_DAT5_IN */ + {0x06D0, 0, 0}, /* CFG_MMC3_DAT5_OEN */ + {0x06D4, 0, 0}, /* CFG_MMC3_DAT5_OUT */ + {0x06D8, 942, 0}, /* CFG_MMC3_DAT6_IN */ + {0x06DC, 0, 0}, /* CFG_MMC3_DAT6_OEN */ + {0x06E0, 0, 0}, /* CFG_MMC3_DAT6_OUT */ + {0x06E4, 636, 0}, /* CFG_MMC3_DAT7_IN */ + {0x06E8, 0, 0}, /* CFG_MMC3_DAT7_OEN */ + {0x06EC, 0, 0}, /* CFG_MMC3_DAT7_OUT */ {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */ {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */ {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */ @@ -895,6 +950,34 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = { {0x0AE0, 192, 836}, /* CFG_VIN2A_D21_IN */ {0x0AEC, 294, 669}, /* CFG_VIN2A_D22_IN */ {0x0AF8, 50, 700}, /* CFG_VIN2A_D23_IN */ + {0x0B9C, 0, 706}, /* CFG_VOUT1_CLK_OUT */ + {0x0BA8, 2313, 0}, /* CFG_VOUT1_D0_OUT */ + {0x0BB4, 2199, 0}, /* CFG_VOUT1_D10_OUT */ + {0x0BC0, 2266, 0}, /* CFG_VOUT1_D11_OUT */ + {0x0BCC, 3159, 0}, /* CFG_VOUT1_D12_OUT */ + {0x0BD8, 2100, 0}, /* CFG_VOUT1_D13_OUT */ + {0x0BE4, 2229, 0}, /* CFG_VOUT1_D14_OUT */ + {0x0BF0, 2202, 0}, /* CFG_VOUT1_D15_OUT */ + {0x0BFC, 2084, 0}, /* CFG_VOUT1_D16_OUT */ + {0x0C08, 2195, 0}, /* CFG_VOUT1_D17_OUT */ + {0x0C14, 2342, 0}, /* CFG_VOUT1_D18_OUT */ + {0x0C20, 2463, 0}, /* CFG_VOUT1_D19_OUT */ + {0x0C2C, 2439, 0}, /* CFG_VOUT1_D1_OUT */ + {0x0C38, 2304, 0}, /* CFG_VOUT1_D20_OUT */ + {0x0C44, 2103, 0}, /* CFG_VOUT1_D21_OUT */ + {0x0C50, 2145, 0}, /* CFG_VOUT1_D22_OUT */ + {0x0C5C, 1932, 0}, /* CFG_VOUT1_D23_OUT */ + {0x0C68, 2200, 0}, /* CFG_VOUT1_D2_OUT */ + {0x0C74, 2355, 0}, /* CFG_VOUT1_D3_OUT */ + {0x0C80, 3215, 0}, /* CFG_VOUT1_D4_OUT */ + {0x0C8C, 2314, 0}, /* CFG_VOUT1_D5_OUT */ + {0x0C98, 2238, 0}, /* CFG_VOUT1_D6_OUT */ + {0x0CA4, 2381, 0}, /* CFG_VOUT1_D7_OUT */ + {0x0CB0, 2138, 0}, /* CFG_VOUT1_D8_OUT */ + {0x0CBC, 2383, 0}, /* CFG_VOUT1_D9_OUT */ + {0x0CC8, 1984, 0}, /* CFG_VOUT1_DE_OUT */ + {0x0CE0, 1947, 0}, /* CFG_VOUT1_HSYNC_OUT */ + {0x0CEC, 2739, 0}, /* CFG_VOUT1_VSYNC_OUT */ }; const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = { @@ -921,68 +1004,113 @@ const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = { {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ {0x0590, 1000, 4200}, /* CFG_MCASP5_ACLKX_OUT */ {0x05AC, 800, 3800}, /* CFG_MCASP5_FSX_IN */ - {0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */ - {0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */ - {0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */ - {0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */ - {0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */ - {0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */ - {0x0740, 90, 70}, /* CFG_RGMII0_TXC_OUT */ - {0x074C, 70, 70}, /* CFG_RGMII0_TXCTL_OUT */ - {0x0758, 180, 70}, /* CFG_RGMII0_TXD0_OUT */ - {0x0764, 35, 70}, /* CFG_RGMII0_TXD1_OUT */ - {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */ - {0x077C, 180, 70}, /* CFG_RGMII0_TXD3_OUT */ - {0x0A70, 65, 70}, /* CFG_VIN2A_D12_OUT */ - {0x0A7C, 125, 70}, /* CFG_VIN2A_D13_OUT */ - {0x0A88, 0, 70}, /* CFG_VIN2A_D14_OUT */ - {0x0A94, 0, 70}, /* CFG_VIN2A_D15_OUT */ - {0x0AA0, 65, 70}, /* CFG_VIN2A_D16_OUT */ - {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ - {0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */ - {0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */ - {0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */ - {0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */ - {0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */ - {0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */ + {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 139, 1081}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 195, 1100}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 239, 1216}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 89, 0}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 15, 125}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 339, 162}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 146, 94}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 0, 27}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 291, 205}, /* CFG_RGMII0_TXD3_OUT */ + {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 219, 101}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 92, 58}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 135, 100}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 154, 101}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 78, 27}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 411, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 0, 382}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 320, 750}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 192, 836}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 294, 669}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 50, 700}, /* CFG_VIN2A_D23_IN */ {0x0B30, 0, 0}, /* CFG_VIN2A_D5_OUT */ + {0x0B9C, 1126, 751}, /* CFG_VOUT1_CLK_OUT */ + {0x0BA8, 395, 0}, /* CFG_VOUT1_D0_OUT */ + {0x0BB4, 282, 0}, /* CFG_VOUT1_D10_OUT */ + {0x0BC0, 348, 0}, /* CFG_VOUT1_D11_OUT */ + {0x0BCC, 1240, 0}, /* CFG_VOUT1_D12_OUT */ + {0x0BD8, 182, 0}, /* CFG_VOUT1_D13_OUT */ + {0x0BE4, 311, 0}, /* CFG_VOUT1_D14_OUT */ + {0x0BF0, 285, 0}, /* CFG_VOUT1_D15_OUT */ + {0x0BFC, 166, 0}, /* CFG_VOUT1_D16_OUT */ + {0x0C08, 278, 0}, /* CFG_VOUT1_D17_OUT */ + {0x0C14, 425, 0}, /* CFG_VOUT1_D18_OUT */ + {0x0C20, 516, 0}, /* CFG_VOUT1_D19_OUT */ + {0x0C2C, 521, 0}, /* CFG_VOUT1_D1_OUT */ + {0x0C38, 386, 0}, /* CFG_VOUT1_D20_OUT */ + {0x0C44, 111, 0}, /* CFG_VOUT1_D21_OUT */ + {0x0C50, 227, 0}, /* CFG_VOUT1_D22_OUT */ + {0x0C5C, 0, 0}, /* CFG_VOUT1_D23_OUT */ + {0x0C68, 282, 0}, /* CFG_VOUT1_D2_OUT */ + {0x0C74, 438, 0}, /* CFG_VOUT1_D3_OUT */ + {0x0C80, 1298, 0}, /* CFG_VOUT1_D4_OUT */ + {0x0C8C, 397, 0}, /* CFG_VOUT1_D5_OUT */ + {0x0C98, 321, 0}, /* CFG_VOUT1_D6_OUT */ + {0x0CA4, 155, 309}, /* CFG_VOUT1_D7_OUT */ + {0x0CB0, 212, 0}, /* CFG_VOUT1_D8_OUT */ + {0x0CBC, 466, 0}, /* CFG_VOUT1_D9_OUT */ + {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */ + {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */ + {0x0CEC, 139, 701}, /* CFG_VOUT1_VSYNC_OUT */ }; const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = { - {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ - {0x0150, 2062, 2277}, /* CFG_GPMC_A14_IN */ - {0x015C, 1960, 2289}, /* CFG_GPMC_A15_IN */ - {0x0168, 2058, 2386}, /* CFG_GPMC_A16_IN */ - {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */ - {0x0174, 2062, 2350}, /* CFG_GPMC_A17_IN */ - {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */ - {0x0374, 121, 0}, /* CFG_GPMC_CS2_OUT */ - {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */ - {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */ - {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */ - {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */ - {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */ - {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */ - {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */ - {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */ - {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */ - {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */ - {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */ - {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */ - {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */ - {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */ - {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */ - {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */ - {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */ - {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */ - {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */ - {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */ - {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */ - {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */ - {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */ - {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */ - {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */ + {0x0114, 1873, 702}, /* CFG_GPMC_A0_IN */ + {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */ + {0x012C, 1851, 1011}, /* CFG_GPMC_A11_IN */ + {0x0138, 2009, 601}, /* CFG_GPMC_A12_IN */ + {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ + {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */ + {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */ + {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */ + {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */ + {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */ + {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */ + {0x0198, 1629, 772}, /* CFG_GPMC_A1_IN */ + {0x0204, 1734, 898}, /* CFG_GPMC_A2_IN */ + {0x0210, 1757, 1076}, /* CFG_GPMC_A3_IN */ + {0x021C, 1794, 893}, /* CFG_GPMC_A4_IN */ + {0x0228, 1726, 853}, /* CFG_GPMC_A5_IN */ + {0x0234, 1792, 612}, /* CFG_GPMC_A6_IN */ + {0x0240, 2117, 610}, /* CFG_GPMC_A7_IN */ + {0x024C, 1758, 653}, /* CFG_GPMC_A8_IN */ + {0x0258, 1705, 899}, /* CFG_GPMC_A9_IN */ + {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ + {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */ + {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */ }; +const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk_4port[] = { + {0x0588, 2100, 1959}, /* CFG_MCASP5_ACLKX_IN */ + {0x05AC, 2100, 1780}, /* CFG_MCASP5_FSX_IN */ + {0x0B30, 0, 400}, /* CFG_VIN2A_D5_OUT */ +}; #endif #endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 00d127e21b..887b577b6a 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -443,13 +443,13 @@ int misc_init_r(void) printf("Recognized BeagleBoardToys WiFi board\n"); MUX_BBTOYS_WIFI() setenv("buddy", "bbtoys-wifi"); - break;; + break; case BBTOYS_VGA: printf("Recognized BeagleBoardToys VGA board\n"); - break;; + break; case BBTOYS_LCD: printf("Recognized BeagleBoardToys LCD board\n"); - break;; + break; case BCT_BRETTL3: printf("Recognized bct electronic GmbH brettl3 board\n"); break; diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index 1187cf5433..c21eb8c2d2 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -18,6 +18,7 @@ config TI_COMMON_CMD_OPTIONS bool "Enable cmd options on TI platforms" imply CMD_ASKENV imply CMD_BOOTZ + imply CRC32_VERIFY if ARCH_KEYSTONE imply CMD_DFU if USB_GADGET_DOWNLOAD imply CMD_DHCP imply CMD_EEPROM @@ -26,6 +27,7 @@ config TI_COMMON_CMD_OPTIONS imply CMD_EXT4_WRITE imply CMD_FASTBOOT if FASTBOOT imply CMD_FAT + imply FAT_WRITE if CMD_FAT imply CMD_FS_GENERIC imply CMD_GPIO imply CMD_GPT diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 8c02addd08..7d36f03fa1 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -561,6 +561,7 @@ int board_late_init(void) setenv("boot_fit", "1"); omap_die_id_serial(); + omap_set_fastboot_vars(); #endif return 0; } diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 21aec8f065..f0bd31d6f7 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -79,29 +79,29 @@ static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = { [SPD400] = {MAIN_PLL, 125, 3, 2}, [SPD600] = {MAIN_PLL, 125, 2, 2}, [SPD800] = {MAIN_PLL, 250, 3, 2}, - [SPD900] = {TETRIS_PLL, 187, 2, 2}, - [SPD1000] = {TETRIS_PLL, 104, 1, 2}, + [SPD900] = {MAIN_PLL, 187, 2, 2}, + [SPD1000] = {MAIN_PLL, 104, 1, 2}, }, [SYSCLK_24MHz] = { [SPD400] = {MAIN_PLL, 100, 3, 2}, [SPD600] = {MAIN_PLL, 300, 6, 2}, [SPD800] = {MAIN_PLL, 200, 3, 2}, - [SPD900] = {TETRIS_PLL, 75, 1, 2}, - [SPD1000] = {TETRIS_PLL, 250, 3, 2}, + [SPD900] = {MAIN_PLL, 75, 1, 2}, + [SPD1000] = {MAIN_PLL, 250, 3, 2}, }, [SYSCLK_25MHz] = { [SPD400] = {MAIN_PLL, 32, 1, 2}, [SPD600] = {MAIN_PLL, 48, 1, 2}, [SPD800] = {MAIN_PLL, 64, 1, 2}, - [SPD900] = {TETRIS_PLL, 72, 1, 2}, - [SPD1000] = {TETRIS_PLL, 80, 1, 2}, + [SPD900] = {MAIN_PLL, 72, 1, 2}, + [SPD1000] = {MAIN_PLL, 80, 1, 2}, }, [SYSCLK_26MHz] = { [SPD400] = {MAIN_PLL, 400, 13, 2}, [SPD600] = {MAIN_PLL, 230, 5, 2}, [SPD800] = {MAIN_PLL, 123, 2, 2}, - [SPD900] = {TETRIS_PLL, 69, 1, 2}, - [SPD1000] = {TETRIS_PLL, 384, 5, 2}, + [SPD900] = {MAIN_PLL, 69, 1, 2}, + [SPD1000] = {MAIN_PLL, 384, 5, 2}, }, }; diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index b6cc417333..4b25cc2d7c 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -24,6 +24,7 @@ #include <sata.h> #include <usb.h> #include <asm/gpio.h> +#include <asm/mach-types.h> #include <asm/arch/clock.h> #include <asm/arch/ehci.h> #include <asm/ehci-omap.h> diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 72aabb242c..6ffb53c4c6 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -6,6 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <asm/mach-types.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/clock.h> diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c index b6bf16236f..577e60f875 100644 --- a/board/ti/ti816x/evm.c +++ b/board/ti/ti816x/evm.c @@ -24,12 +24,14 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#if defined(CONFIG_NAND) + gpmc_init(); +#endif return 0; } #ifdef CONFIG_SPL_BUILD - static struct module_pin_mux mmc_pin_mux[] = { { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) }, { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) }, @@ -41,176 +43,68 @@ static struct module_pin_mux mmc_pin_mux[] = { { -1 }, }; -const struct dmm_lisa_map_regs evm_lisa_map_regs = { - .dmm_lisa_map_0 = 0x00000000, - .dmm_lisa_map_1 = 0x00000000, - .dmm_lisa_map_2 = 0x80640300, - .dmm_lisa_map_3 = 0xC0640320, -}; - -/* - * DDR2 related definitions - */ -#ifdef CONFIG_TI816X_EVM_DDR2 -static struct ddr_data ddr2_data = { - .datardsratio0 = ((0x40<<10) | (0x40<<0)), - .datawdsratio0 = ((0x4A<<10) | (0x4A<<0)), - .datawiratio0 = ((0x0<<10) | (0x0<<0)), - .datagiratio0 = ((0x0<<10) | (0x0<<0)), - .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)), - .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)), -}; - -static struct cmd_control ddr2_ctrl = { - .cmd0csratio = 0x80, - .cmd0iclkout = 0x00, - - .cmd1csratio = 0x80, - .cmd1iclkout = 0x00, - - .cmd2csratio = 0x80, - .cmd2iclkout = 0x00, - -}; - -static struct emif_regs ddr2_emif0_regs = { - .sdram_config = 0x43801A3A, - .ref_ctrl = 0x10000C30, - .sdram_tim1 = 0x0AAB15E2, - .sdram_tim2 = 0x423631D2, - .sdram_tim3 = 0x0080032F, - .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */ -}; +void set_uart_mux_conf(void) {} -static struct emif_regs ddr2_emif1_regs = { - .sdram_config = 0x43801A3A, - .ref_ctrl = 0x10000C30, - .sdram_tim1 = 0x0AAB15E2, - .sdram_tim2 = 0x423631D2, - .sdram_tim3 = 0x0080032F, - .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */ -}; -#endif +void set_mux_conf_regs(void) +{ + configure_module_pin_mux(mmc_pin_mux); +} /* - * DDR3 related definitions + * EMIF Paramters. Refer the EMIF register documentation and the + * memory datasheet for details. This is for 796 MHz. */ - -#if defined(CONFIG_TI816X_DDR_PLL_400) -#define RD_DQS 0x03B -#define WR_DQS 0x0A6 -#define RD_DQS_GATE 0x12A -#define EMIF_SDCFG 0x62A41032 -#define EMIF_SDREF 0x10000C30 -#define EMIF_TIM1 0x0CCCE524 -#define EMIF_TIM2 0x30308023 -#define EMIF_TIM3 0x009F82CF -#define EMIF_PHYCFG 0x0000010B -#elif defined(CONFIG_TI816X_DDR_PLL_531) -#define RD_DQS 0x039 -#define WR_DQS 0x0B4 -#define RD_DQS_GATE 0x13D -#define EMIF_SDCFG 0x62A51832 -#define EMIF_SDREF 0x1000102E -#define EMIF_TIM1 0x0EF136AC -#define EMIF_TIM2 0x30408063 -#define EMIF_TIM3 0x009F83AF -#define EMIF_PHYCFG 0x0000010C -#elif defined(CONFIG_TI816X_DDR_PLL_675) -#define RD_DQS 0x039 -#define WR_DQS 0x091 -#define RD_DQS_GATE 0x196 -#define EMIF_SDCFG 0x62A63032 -#define EMIF_SDREF 0x10001491 -#define EMIF_TIM1 0x13358875 -#define EMIF_TIM2 0x5051806C -#define EMIF_TIM3 0x009F84AF -#define EMIF_PHYCFG 0x0000010F -#elif defined(CONFIG_TI816X_DDR_PLL_796) -#define RD_DQS 0x035 -#define WR_DQS 0x093 -#define RD_DQS_GATE 0x1B3 -#define EMIF_SDCFG 0x62A73832 -#define EMIF_SDREF 0x10001841 -#define EMIF_TIM1 0x1779C9FE -#define EMIF_TIM2 0x50608074 -#define EMIF_TIM3 0x009F857F -#define EMIF_PHYCFG 0x00000110 -#endif - -static struct ddr_data ddr3_data = { - .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)), - .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)), - .datawiratio0 = ((0x20<<10) | 0x20<<0), - .datagiratio0 = ((0x20<<10) | 0x20<<0), - .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), - .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), +#define EMIF_TIM1 0x1779C9FE +#define EMIF_TIM2 0x50608074 +#define EMIF_TIM3 0x009F857F +#define EMIF_SDREF 0x10001841 +#define EMIF_SDCFG 0x62A73832 +#define EMIF_PHYCFG 0x00000110 +static const struct emif_regs ddr3_emif_regs = { + .sdram_config = EMIF_SDCFG, + .ref_ctrl = EMIF_SDREF, + .sdram_tim1 = EMIF_TIM1, + .sdram_tim2 = EMIF_TIM2, + .sdram_tim3 = EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, }; static const struct cmd_control ddr3_ctrl = { .cmd0csratio = 0x100, .cmd0iclkout = 0x001, - .cmd1csratio = 0x100, .cmd1iclkout = 0x001, - .cmd2csratio = 0x100, .cmd2iclkout = 0x001, }; -static const struct emif_regs ddr3_emif0_regs = { - .sdram_config = EMIF_SDCFG, - .ref_ctrl = EMIF_SDREF, - .sdram_tim1 = EMIF_TIM1, - .sdram_tim2 = EMIF_TIM2, - .sdram_tim3 = EMIF_TIM3, - .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, +/* These values are obtained from the CCS app */ +#define RD_DQS_GATE (0x1B3) +#define RD_DQS (0x35) +#define WR_DQS (0x93) +static struct ddr_data ddr3_data = { + .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)), + .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)), + .datawiratio0 = ((0x20<<10) | 0x20<<0), + .datagiratio0 = ((0x20<<10) | 0x20<<0), + .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), + .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), }; -static const struct emif_regs ddr3_emif1_regs = { - .sdram_config = EMIF_SDCFG, - .ref_ctrl = EMIF_SDREF, - .sdram_tim1 = EMIF_TIM1, - .sdram_tim2 = EMIF_TIM2, - .sdram_tim3 = EMIF_TIM3, - .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, +static const struct dmm_lisa_map_regs evm_lisa_map_regs = { + .dmm_lisa_map_0 = 0x00000000, + .dmm_lisa_map_1 = 0x00000000, + .dmm_lisa_map_2 = 0x80640300, + .dmm_lisa_map_3 = 0xC0640320, }; -void set_uart_mux_conf(void) {} - -void set_mux_conf_regs(void) -{ - configure_module_pin_mux(mmc_pin_mux); -} - void sdram_init(void) { - config_dmm(&evm_lisa_map_regs); - -#ifdef CONFIG_TI816X_EVM_DDR2 - if (CONFIG_TI816X_USE_EMIF0) { - ddr2_emif0_regs.emif_ddr_phy_ctlr_1 = - (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); - config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, - 0); - } - - if (CONFIG_TI816X_USE_EMIF1) { - ddr2_emif1_regs.emif_ddr_phy_ctlr_1 = - (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); - config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, - 1); - } -#endif - -#ifdef CONFIG_TI816X_EVM_DDR3 - if (CONFIG_TI816X_USE_EMIF0) - config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, - 0); - - if (CONFIG_TI816X_USE_EMIF1) - config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, - 1); -#endif + /* + * Pass in our DDR3 config information and that we have 2 EMIFs to + * configure. + */ + config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs, + &evm_lisa_map_regs, 2); } #endif /* CONFIG_SPL_BUILD */ diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c new file mode 100644 index 0000000000..ec0cc7d19d --- /dev/null +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c @@ -0,0 +1,227 @@ +/* + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. + * (c) Copyright 2016 Topic Embedded Products. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "../ps7_init_gpl.h" + +static unsigned long ps7_pll_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000002U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x00113220U), + EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x00024000U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000004U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_clock_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00302301U), + EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100141U), + EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100141U), + EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000C01U), + EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000601U), + EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001803U), + EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000C03U), + EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U), + EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000601U), + EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0xF8000190, 0x03F03F30U, 0x00100600U), + EMIT_MASKWRITE(0xF80001A0, 0x03F03F30U, 0x00101800U), + EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FC4C4DU), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U), + EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004281AU), + EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U), + EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U), + EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U), + EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U), + EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U), + EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U), + EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003482CU), + EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00033032U), + EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0002E81FU), + EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x0002F81AU), + EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ACU), + EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B2U), + EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009FU), + EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009AU), + EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000127U), + EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000121U), + EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000010FU), + EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000113U), + EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000ECU), + EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F2U), + EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DFU), + EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DAU), + EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x1002E080U), + EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U), + EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0xF8000B74, 0x00002000U), + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0xF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +static unsigned long ps7_mio_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000E60U), + EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U), + EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_EXIT(), +}; + +static unsigned long ps7_post_config_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt b/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt new file mode 100644 index 0000000000..db6e642890 --- /dev/null +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt @@ -0,0 +1,61 @@ +0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?) +0xf8000700 0x202 +0xf8000704 0x202 +0xf8000708 0x202 +0xf800070c 0x202 +0xf8000710 0x202 +0xf8000714 0x202 +0xf8000718 0x202 +0xf800071c 0x200 +0xf8000720 0x202 +0xf8000724 0x202 +0xf8000728 0x202 +0xf800072c 0x202 +0xf8000730 0x202 +0xf8000734 0x202 +0xf8000738 0x12e1 +0xf800073c 0x12e0 +0xf8000740 0x1200 +0xf8000744 0x1200 +0xf8000748 0x1200 +0xf800074c 0x1200 +0xf8000750 0x1200 +0xf8000754 0x1200 +0xf8000758 0x1200 +0xf800075c 0x1200 +0xf8000760 0x1200 +0xf8000764 0x200 +0xf8000768 0x1200 +0xf800076c 0x200 +0xf8000770 0x304 +0xf8000774 0x305 +0xf8000778 0x304 +0xf800077c 0x305 +0xf8000780 0x304 +0xf8000784 0x304 +0xf8000788 0x304 +0xf800078c 0x304 +0xf8000790 0x305 +0xf8000794 0x304 +0xf8000798 0x304 +0xf800079c 0x304 +0xf80007a0 0x380 +0xf80007a4 0x380 +0xf80007a8 0x380 +0xf80007ac 0x380 +0xf80007b0 0x380 +0xf80007b4 0x380 +0xf80007b8 0x1200 +0xf80007bc 0x1200 +0xf80007c0 0x1240 +0xf80007c4 0x1240 +0xf80007c8 0x1240 +0xf80007cc 0x1240 +0xf80007d0 0x1200 +0xf80007d4 0x1200 +0xf8000830 0x380037 +0xf8000834 0x3a0039 +0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz) +0xE000D000 0x800238C1 // QSPI config - divide-by-2 +0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay +0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 45f1d5de39..7c49ddfc4b 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <dm.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> #include <asm/arch/mxc_hdmi.h> diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index d070677054..69467ca895 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <dm.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> #include <asm/arch/imx-regs.h> diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c index 8e948545e3..85afecff94 100644 --- a/board/toradex/colibri_pxa270/colibri_pxa270.c +++ b/board/toradex/colibri_pxa270/colibri_pxa270.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <dm.h> #include <asm/arch/hardware.h> #include <asm/arch/pxa.h> #include <asm/arch/regs-mmc.h> @@ -18,6 +19,7 @@ #include <netdev.h> #include <serial.h> #include <usb.h> +#include <asm/mach-types.h> #include "../common/tdx-common.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 0014ce80a1..68ec4369ad 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -23,6 +23,7 @@ #include <malloc.h> #include <mmc.h> #include <nand.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; @@ -110,7 +111,7 @@ static int tdx_cfg_block_mmc_storage(u8 *config_block, int write) ret = -ENODEV; goto out; } - if (part != mmc->block_dev.hwpart) { + if (part != mmc_get_blk_desc(mmc)->hwpart) { if (blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part)) { puts("MMC partition switch failed\n"); ret = -ENODEV; diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index 2c6fc409c1..0d267877fa 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -9,6 +9,7 @@ #include <libfdt.h> #include "tdx-cfg-block.h" +#include <asm/setup.h> #include "tdx-common.h" #ifdef CONFIG_TDX_CFG_BLOCK diff --git a/board/tqc/tqm5200/Kconfig b/board/tqc/tqm5200/Kconfig deleted file mode 100644 index 738dc80551..0000000000 --- a/board/tqc/tqm5200/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if TARGET_CHARON - -config SYS_BOARD - default "tqm5200" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "charon" - -endif - -if TARGET_TQM5200 - -config SYS_BOARD - default "tqm5200" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM5200" - -endif diff --git a/board/tqc/tqm5200/MAINTAINERS b/board/tqc/tqm5200/MAINTAINERS deleted file mode 100644 index 12d143d73f..0000000000 --- a/board/tqc/tqm5200/MAINTAINERS +++ /dev/null @@ -1,23 +0,0 @@ -TQM5200 BOARD -#M: - -S: Maintained -F: board/tqc/tqm5200/ -F: include/configs/aev.h -F: configs/aev_defconfig -F: include/configs/TQM5200.h -F: configs/cam5200_defconfig -F: configs/cam5200_niosflash_defconfig -F: configs/fo300_defconfig -F: configs/MiniFAP_defconfig -F: configs/TQM5200_defconfig -F: configs/TQM5200_B_defconfig -F: configs/TQM5200_B_HIGHBOOT_defconfig -F: configs/TQM5200_STK100_defconfig -F: configs/TQM5200S_defconfig -F: configs/TQM5200S_HIGHBOOT_defconfig - -CHARON BOARD -M: Heiko Schocher <hs@denx.de> -S: Maintained -F: include/configs/charon.h -F: configs/charon_defconfig diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile deleted file mode 100644 index f7c97b72c8..0000000000 --- a/board/tqc/tqm5200/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := tqm5200.o cmd_stk52xx.o cam5200_flash.o diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c deleted file mode 100644 index c3ae5c010b..0000000000 --- a/board/tqc/tqm5200/cam5200_flash.c +++ /dev/null @@ -1,768 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <asm/processor.h> - -#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) - -#if 0 -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif - -#define swap16(x) __swab16(x) - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * CAM5200 is a TQM5200B based board. Additionally it also features - * a NIOS cpu. The NIOS CPU peripherals are accessible through MPC5xxx - * Local Bus on CS5. This includes 32 bit wide RAM and SRAM as well as - * 16 bit wide flash device. Big Endian order on a 32 bit CS5 makes - * access to flash chip slightly more complicated as additional byte - * swapping is necessary within each 16 bit wide flash 'word'. - * - * This driver's task is to handle both flash devices: 32 bit TQM5200B - * flash chip and 16 bit NIOS cpu flash chip. In the below - * flash_addr_table table we use least significant address bit to mark - * 16 bit flash bank and two sets of routines *_32 and *_16 to handle - * specifics of both flashes. - */ -static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = { - {CONFIG_SYS_BOOTCS_START, CONFIG_SYS_CS5_START | 1} -}; - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static int write_word_32(flash_info_t * info, ulong dest, ulong data); -static int write_word_16(flash_info_t * info, ulong dest, ulong data); -static int flash_erase_32(flash_info_t * info, int s_first, int s_last); -static int flash_erase_16(flash_info_t * info, int s_first, int s_last); -static ulong flash_get_size_32(vu_long * addr, flash_info_t * info); -static ulong flash_get_size_16(vu_long * addr, flash_info_t * info); -#endif - -void flash_print_info(flash_info_t * info) -{ - int i, k; - int size, erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_S29GL128N: - printf ("S29GL128N (256 Mbit, uniform sector size)\n"); - break; - case FLASH_AM320B: - printf ("29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf ("29LV320T (32 Mbit, top boot sect)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - - printf(" %08lX%s%s", info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf("\n"); - return; -} - - -/* - * The following code cannot be run from FLASH! - */ -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - - DEBUGF("get_size: FLASH ADDR %08lx\n", addr); - - /* bit 0 used for big flash marking */ - if ((ulong)addr & 0x1) - return flash_get_size_16((vu_long *)((ulong)addr & 0xfffffffe), info); - else - return flash_get_size_32(addr, info); -} - -static ulong flash_get_size_32(vu_long * addr, flash_info_t * info) -#else -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -#endif -{ - short i; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case AMD_ID_MIRROR: - DEBUGF("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", - addr[14], addr[15]); - switch(addr[14]) { - case AMD_ID_GL128N_2: - if (addr[15] != AMD_ID_GL128N_3) { - DEBUGF("Chip: S29GL128N -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - DEBUGF("Chip: S29GL128N\n"); - info->flash_id += FLASH_S29GL128N; - info->sector_count = 128; - info->size = 0x02000000; - } - break; - default: - info->flash_id = FLASH_UNKNOWN; - return(0); - } - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00040000); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_32(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) { - return flash_erase_16(info, s_first, s_last); - } else { - return flash_erase_32(info, s_first, s_last); - } -} - -static int flash_erase_32(flash_info_t * info, int s_first, int s_last) -#else -int flash_erase(flash_info_t * info, int s_first, int s_last) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) - printf("- Warning: %d protected sectors will not be erased!", prot); - - printf("\n"); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_32(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - if ((rc = write_word(info, wp, data)) != 0) - return (rc); - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - if ((rc = write_word(info, wp, data)) != 0) - return (rc); - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return (0); - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static int write_word(flash_info_t * info, ulong dest, ulong data) -{ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) { - return write_word_16(info, dest, data); - } else { - return write_word_32(info, dest, data); - } -} - -static int write_word_32(flash_info_t * info, ulong dest, ulong data) -#else -static int write_word(flash_info_t * info, ulong dest, ulong data) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; - ulong *datap = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = - (volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap; - ulong start; - int i, flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return (2); - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - } - - return (0); -} - -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV - -#undef CONFIG_SYS_FLASH_WORD_SIZE -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size_16(vu_long * addr, flash_info_t * info) -{ - short i; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr); - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90009000; - udelay(1000); - - value = swap16(addr2[0]); - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = swap16(addr2[1]); /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000a000; - info->start[6] = base + 0x0000c000; - info->start[7] = base + 0x0000e000; - - for (i = 8; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000) - 0x00070000; - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000a000; - info->start[i--] = base + info->size - 0x0000c000; - info->start[i--] = base + info->size - 0x0000e000; - - for (; i >= 0; i--) - info->start[i] = base + i * 0x00010000; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; - - return (info->size); -} - -static int wait_for_DQ7_16(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -static int flash_erase_16(flash_info_t * info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) - printf("- Warning: %d protected sectors will not be erased!", prot); - - printf("\n"); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000; /* sector erase */ - - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_16(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; /* reset bank */ - - printf(" done\n"); - return 0; -} - -static int write_word_16(flash_info_t * info, ulong dest, ulong data) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; - ulong *datap = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = - (volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - if ((dest2[i] & swap16(data2[i])) != swap16(data2[i])) - return (2); - } - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA000A000; - - dest2[i] = swap16(data2[i]); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) != - (swap16(data2[i]) & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} -#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) - continue; - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], - &flash_info[i]); - - flash_info[i].size = size_b[i]; - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i+1, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[i]); -#if defined(CONFIG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#if defined(CONFIG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#endif -#endif - total_b += flash_info[i].size; - } - - return total_b; -} -#endif /* if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) */ diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c deleted file mode 100644 index dc22ee4024..0000000000 --- a/board/tqc/tqm5200/cmd_stk52xx.c +++ /dev/null @@ -1,1228 +0,0 @@ -/* - * (C) Copyright 2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * STK52XX specific functions - */ -/*#define DEBUG*/ - -#include <common.h> -#include <command.h> -#include <console.h> - -#if defined(CONFIG_CMD_BSP) - -#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) -#define DEFAULT_VOL 45 -#define DEFAULT_FREQ 500 -#define DEFAULT_DURATION 200 -#define LEFT 1 -#define RIGHT 2 -#define LEFT_RIGHT 3 -#define BL_OFF 0 -#define BL_ON 1 - -#define SM501_GPIO_CTRL_LOW 0x00000008UL -#define SM501_GPIO_CTRL_HIGH 0x0000000CUL -#define SM501_POWER_MODE0_GATE 0x00000040UL -#define SM501_POWER_MODE1_GATE 0x00000048UL -#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL -#define SM501_GPIO_DATA_LOW 0x00010000UL -#define SM501_GPIO_DATA_HIGH 0x00010004UL -#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL -#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL -#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL - -static int i2s_squarewave(unsigned long duration, unsigned int freq, - unsigned int channel); -static int i2s_sawtooth(unsigned long duration, unsigned int freq, - unsigned int channel); -static void spi_init(void); -static int spi_transmit(unsigned char data); -static void pcm1772_write_reg(unsigned char addr, unsigned char data); -static void set_attenuation(unsigned char attenuation); - -static void spi_init(void) -{ - struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - /* PSC3 as SPI and GPIOs */ - gpio->port_config &= 0xFFFFF0FF; - gpio->port_config |= 0x00000800; - /* - * Its important to use the correct order when initializing the - * registers - */ - spi->ddr = 0x0F; /* set all SPI pins as output */ - spi->pdr = 0x08; /* set SS high */ - spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */ - spi->cr2 = 0x00; /* normal operation */ - spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */ -} - -static int spi_transmit(unsigned char data) -{ - struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; - - spi->dr = data; - /* wait for SPI transmission completed */ - while (!(spi->sr & 0x80)) { - if (spi->sr & 0x40) { /* if write collision occurred */ - int dummy; - - /* do dummy read to clear status register */ - dummy = spi->dr; - printf("SPI write collision: dr=0x%x\n", dummy); - return -1; - } - } - return (spi->dr); -} - -static void pcm1772_write_reg(unsigned char addr, unsigned char data) -{ - struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; - - spi->pdr = 0x00; /* Set SS low */ - spi_transmit(addr); - spi_transmit(data); - /* wait some time to meet MS# hold time of PCM1772 */ - udelay (1); - spi->pdr = 0x08; /* set SS high */ -} - -static void set_attenuation(unsigned char attenuation) -{ - pcm1772_write_reg(0x01, attenuation); /* left channel */ - debug ("PCM1772 attenuation left set to %d.\n", attenuation); - pcm1772_write_reg(0x02, attenuation); /* right channel */ - debug ("PCM1772 attenuation right set to %d.\n", attenuation); -} - -void amplifier_init(void) -{ - static int init_done = 0; - int i; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - /* Do this only once, because of the long time delay */ - if (!init_done) { - /* configure PCM1772 audio format as I2S */ - pcm1772_write_reg(0x03, 0x01); - /* enable audio amplifier */ - gpio->sint_gpioe |= 0x02; /* PSC3_5 as GPIO */ - gpio->sint_ode &= ~0x02; /* PSC3_5 is not open Drain */ - gpio->sint_dvo &= ~0x02; /* PSC3_5 is LOW */ - gpio->sint_ddr |= 0x02; /* PSC3_5 as output */ - /* - * wait some time to allow amplifier to recover from shutdown - * mode. - */ - for(i = 0; i < 350; i++) - udelay(1000); - /* - * The used amplifier (LM4867) has a so called "pop and click" - * elmination filter. The input signal of the amplifier must - * exceed a certain level once after power up to activate the - * generation of the output signal. This is achieved by - * sending a low frequent (nearly inaudible) sawtooth with a - * sufficient signal level. - */ - set_attenuation(50); - i2s_sawtooth (200, 5, LEFT_RIGHT); - init_done = 1; - } -} - -static void i2s_init(void) -{ - unsigned long i; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; - - gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */ - psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); - psc->sicr = 0x22E00000; /* 16 bit data; I2S */ - - *(vu_long *)(CONFIG_SYS_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK - * 5.617 MHz */ - *(vu_long *)(CONFIG_SYS_MBAR + 0x214) |= 0x00000040; /* CDM clock enable - * register */ - psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */ - psc->ctur = 0x0F; /* 16 bit frame width */ - - for (i = 0; i < 128; i++) - psc->psc_buffer_32 = 0; /* clear tx fifo */ -} - -static int i2s_play_wave(unsigned long addr, unsigned long len) -{ - unsigned long i; - unsigned char *wave_file = (uchar *)addr + 44; /* quick'n dirty: skip - * wav header*/ - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; - - /* - * play wave file in memory; bytes/words are be swapped - */ - psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); - - for(i = 0;i < (len / 4); i++) { - unsigned char swapped[4]; - unsigned long *p = (unsigned long*)swapped; - - swapped[3] = *wave_file++; - swapped[2] = *wave_file++; - swapped[1] = *wave_file++; - swapped[0] = *wave_file++; - - psc->psc_buffer_32 = *p; - - while (psc->tfnum > 400) { - if(ctrlc()) - return 0; - } - } - while (psc->tfnum > 0); /* wait for fifo empty */ - udelay (100); - psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); - return 0; -} - -static int i2s_sawtooth(unsigned long duration, unsigned int freq, - unsigned int channel) -{ - long i,j; - unsigned long data; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; - - psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); - - /* - * Generate sawtooth. Start with middle level up to highest level. Then - * go to lowest level and back to middle level. - */ - for(j = 0; j < ((duration * freq) / 1000); j++) { - for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4)))) { - data = (i & 0xFFFF); - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) { - data = (i & 0xFFFF); - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) { - data = (i & 0xFFFF); - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - } - while (psc->tfnum > 0); /* wait for fifo empty */ - udelay (100); - psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); - - return 0; -} - -static int i2s_squarewave(unsigned long duration, unsigned int freq, - unsigned int channel) -{ - long i,j; - unsigned long data; - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; - - psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); - - /* - * Generate sqarewave. Start with high level, duty cycle 1:1. - */ - for(j = 0; j < ((duration * freq) / 1000); j++) { - for(i = 0; i < (44100/(freq*2)); i ++) { - data = 0x7FFF; - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - for(i = 0; i < (44100/(freq*2)); i ++) { - data = 0x8000; - /* data format: right data left data) */ - if (channel == LEFT_RIGHT) - data |= (data<<16); - if (channel == RIGHT) - data = (data<<16); - psc->psc_buffer_32 = data; - while (psc->tfnum > 400); - } - } - while (psc->tfnum > 0); /* wait for fifo empty */ - udelay (100); - psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); - - return 0; -} - -static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned long reg, val, duration; - char *tmp; - unsigned int freq, channel; - unsigned char volume; - int rcode = 1; - -#ifdef CONFIG_STK52XX_REV100 - printf ("Revision 100 of STK52XX not supported!\n"); - return 1; -#endif - spi_init(); - i2s_init(); - amplifier_init(); - - if ((tmp = getenv ("volume")) != NULL) { - volume = simple_strtoul (tmp, NULL, 10); - } else { - volume = DEFAULT_VOL; - } - set_attenuation(volume); - - switch (argc) { - case 0: - case 1: - return cmd_usage(cmdtp); - case 2: - if (strncmp(argv[1],"saw",3) == 0) { - printf ("Play sawtooth\n"); - rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ, - LEFT_RIGHT); - return rcode; - } else if (strncmp(argv[1],"squ",3) == 0) { - printf ("Play squarewave\n"); - rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, - LEFT_RIGHT); - return rcode; - } - - return cmd_usage(cmdtp); - case 3: - if (strncmp(argv[1],"saw",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - printf ("Play sawtooth\n"); - rcode = i2s_sawtooth (duration, DEFAULT_FREQ, - LEFT_RIGHT); - return rcode; - } else if (strncmp(argv[1],"squ",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - printf ("Play squarewave\n"); - rcode = i2s_squarewave (duration, DEFAULT_FREQ, - LEFT_RIGHT); - return rcode; - } - return cmd_usage(cmdtp); - case 4: - if (strncmp(argv[1],"saw",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); - printf ("Play sawtooth\n"); - rcode = i2s_sawtooth (duration, freq, - LEFT_RIGHT); - return rcode; - } else if (strncmp(argv[1],"squ",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); - printf ("Play squarewave\n"); - rcode = i2s_squarewave (duration, freq, - LEFT_RIGHT); - return rcode; - } else if (strcmp(argv[1],"pcm1772") == 0) { - reg = simple_strtoul(argv[2], NULL, 10); - val = simple_strtoul(argv[3], NULL, 10); - printf("Set PCM1772 %lu. %lu\n", reg, val); - pcm1772_write_reg((uchar)reg, (uchar)val); - return 0; - } - return cmd_usage(cmdtp); - case 5: - if (strncmp(argv[1],"saw",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); - if (strncmp(argv[4],"l",1) == 0) - channel = LEFT; - else if (strncmp(argv[4],"r",1) == 0) - channel = RIGHT; - else - channel = LEFT_RIGHT; - printf ("Play squarewave\n"); - rcode = i2s_sawtooth (duration, freq, - channel); - return rcode; - } else if (strncmp(argv[1],"squ",3) == 0) { - duration = simple_strtoul(argv[2], NULL, 10); - freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); - if (strncmp(argv[4],"l",1) == 0) - channel = LEFT; - else if (strncmp(argv[4],"r",1) == 0) - channel = RIGHT; - else - channel = LEFT_RIGHT; - printf ("Play squarewave\n"); - rcode = i2s_squarewave (duration, freq, - channel); - return rcode; - } - return cmd_usage(cmdtp); - } - printf ("Usage:\nsound cmd [arg1] [arg2] ...\n"); - return 1; -} - -static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned long length, addr; - unsigned char volume; - int rcode = 1; - char *tmp; - -#ifdef CONFIG_STK52XX_REV100 - printf ("Revision 100 of STK52XX not supported!\n"); - return 1; -#endif - spi_init(); - i2s_init(); - amplifier_init(); - - switch (argc) { - - case 3: - length = simple_strtoul(argv[2], NULL, 16); - addr = simple_strtoul(argv[1], NULL, 16); - break; - - case 2: - if ((tmp = getenv ("filesize")) != NULL) { - length = simple_strtoul (tmp, NULL, 16); - } else { - puts ("No filesize provided\n"); - return 1; - } - addr = simple_strtoul(argv[1], NULL, 16); - - case 1: - if ((tmp = getenv ("filesize")) != NULL) { - length = simple_strtoul (tmp, NULL, 16); - } else { - puts ("No filesize provided\n"); - return 1; - } - if ((tmp = getenv ("loadaddr")) != NULL) { - addr = simple_strtoul (tmp, NULL, 16); - } else { - puts ("No loadaddr provided\n"); - return 1; - } - break; - - default: - printf("Usage:\nwav <addr> <length[s]\n"); - return 1; - break; - } - - if ((tmp = getenv ("volume")) != NULL) { - volume = simple_strtoul (tmp, NULL, 10); - } else { - volume = DEFAULT_VOL; - } - set_attenuation(volume); - - printf("Play wave file at %lX with length %lX\n", addr, length); - rcode = i2s_play_wave(addr, length); - - return rcode; -} - -static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned char volume; - unsigned int channel; - int rcode; - char *tmp; - -#ifdef CONFIG_STK52XX_REV100 - printf ("Revision 100 of STK52XX not supported!\n"); - return 1; -#endif - spi_init(); - i2s_init(); - amplifier_init(); - - switch (argc) { - case 0: - case 1: - channel = LEFT_RIGHT; - break; - case 2: - if (strncmp(argv[1],"l",1) == 0) - channel = LEFT; - else if (strncmp(argv[1],"r",1) == 0) - channel = RIGHT; - else - channel = LEFT_RIGHT; - break; - default: - return cmd_usage(cmdtp); - } - - if ((tmp = getenv ("volume")) != NULL) { - volume = simple_strtoul (tmp, NULL, 10); - } else { - volume = DEFAULT_VOL; - } - set_attenuation(volume); - - printf("Beep on "); - if (channel == LEFT) - printf ("left "); - else if (channel == RIGHT) - printf ("right "); - else - printf ("left and right "); - printf ("channel\n"); - - rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel); - - return rcode; -} -#endif - -#if defined(CONFIG_STK52XX) -void led_init(void) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - /* configure PSC3 for SPI and GPIO */ - gpio->port_config &= ~(0x00000F00); - gpio->port_config |= 0x00000800; - - gpio->simple_gpioe &= ~(0x00000F00); - gpio->simple_gpioe |= 0x00000F00; - - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000F00; - - /* configure timer 4-7 for simple GPIO output */ - gpt->gpt4.emsr |= 0x00000024; - gpt->gpt5.emsr |= 0x00000024; - gpt->gpt6.emsr |= 0x00000024; - gpt->gpt7.emsr |= 0x00000024; - -#ifndef CONFIG_TQM5200S - /* enable SM501 GPIO control (in both power modes) */ - *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - - /* configure SM501 gpio pins 24-27 as output */ - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24); - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24); - - /* configure SM501 gpio pins 48-51 as output */ - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16); -#endif /* !CONFIG_TQM5200S */ -} - -/* - * return 1 if led number unknown - * return 0 else - */ -int do_led(char * const argv[]) -{ - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - switch (simple_strtoul(argv[2], NULL, 10)) { - - case 0: - if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 8); - } else { - gpio->simple_dvo &= ~(1 << 8); - } - break; - - case 1: - if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 9); - } else { - gpio->simple_dvo &= ~(1 << 9); - } - break; - - case 2: - if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 10); - } else { - gpio->simple_dvo &= ~(1 << 10); - } - break; - - case 3: - if (strcmp (argv[3], "on") == 0) { - gpio->simple_dvo |= (1 << 11); - } else { - gpio->simple_dvo &= ~(1 << 11); - } - break; - - case 4: - if (strcmp (argv[3], "on") == 0) { - gpt->gpt4.emsr |= (1 << 4); - } else { - gpt->gpt4.emsr &= ~(1 << 4); - } - break; - - case 5: - if (strcmp (argv[3], "on") == 0) { - gpt->gpt5.emsr |= (1 << 4); - } else { - gpt->gpt5.emsr &= ~(1 << 4); - } - break; - - case 6: - if (strcmp (argv[3], "on") == 0) { - gpt->gpt6.emsr |= (1 << 4); - } else { - gpt->gpt6.emsr &= ~(1 << 4); - } - break; - - case 7: - if (strcmp (argv[3], "on") == 0) { - gpt->gpt7.emsr |= (1 << 4); - } else { - gpt->gpt7.emsr &= ~(1 << 4); - } - break; -#ifndef CONFIG_TQM5200S - case 24: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= - (0x1 << 24); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= - ~(0x1 << 24); - } - break; - - case 25: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= - (0x1 << 25); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= - ~(0x1 << 25); - } - break; - - case 26: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= - (0x1 << 26); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= - ~(0x1 << 26); - } - break; - - case 27: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= - (0x1 << 27); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= - ~(0x1 << 27); - } - break; - - case 48: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - (0x1 << 16); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~(0x1 << 16); - } - break; - - case 49: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - (0x1 << 17); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~(0x1 << 17); - } - break; - - case 50: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - (0x1 << 18); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~(0x1 << 18); - } - break; - - case 51: - if (strcmp (argv[3], "on") == 0) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - (0x1 << 19); - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~(0x1 << 19); - } - break; -#endif /* !CONFIG_TQM5200S */ - default: - printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]); - return 1; - } - - return 0; -} -#endif - -#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) -/* - * return 1 on CAN initialization failure - * return 0 if no failure - */ -int can_init(void) -{ - static int init_done = 0; - int i; - struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900); - struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980); - - /* GPIO configuration of the CAN pins is done in TQM5200.h */ - - if (!init_done) { - /* init CAN 1 */ - can1->canctl1 |= 0x80; /* CAN enable */ - udelay(100); - - i = 0; - can1->canctl0 |= 0x02; /* sleep mode */ - /* wait until sleep mode reached */ - while (!(can1->canctl1 & 0x02)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN1 initialize error, " - "can not enter sleep mode!\n", - __FUNCTION__); - return 1; - } - } - i = 0; - can1->canctl0 = 0x01; /* enter init mode */ - /* wait until init mode reached */ - while (!(can1->canctl1 & 0x01)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN1 initialize error, " - "can not enter init mode!\n", - __FUNCTION__); - return 1; - } - } - can1->canctl1 = 0x80; - can1->canctl1 |= 0x40; - can1->canbtr0 = 0x0F; - can1->canbtr1 = 0x7F; - can1->canidac &= ~(0x30); - can1->canidar1 = 0x00; - can1->canidar3 = 0x00; - can1->canidar5 = 0x00; - can1->canidar7 = 0x00; - can1->canidmr0 = 0xFF; - can1->canidmr1 = 0xFF; - can1->canidmr2 = 0xFF; - can1->canidmr3 = 0xFF; - can1->canidmr4 = 0xFF; - can1->canidmr5 = 0xFF; - can1->canidmr6 = 0xFF; - can1->canidmr7 = 0xFF; - - i = 0; - can1->canctl0 &= ~(0x01); /* leave init mode */ - can1->canctl0 &= ~(0x02); - /* wait until init and sleep mode left */ - while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN1 initialize error, " - "can not leave init/sleep mode!\n", - __FUNCTION__); - return 1; - } - } - - /* init CAN 2 */ - can2->canctl1 |= 0x80; /* CAN enable */ - udelay(100); - - i = 0; - can2->canctl0 |= 0x02; /* sleep mode */ - /* wait until sleep mode reached */ - while (!(can2->canctl1 & 0x02)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN2 initialize error, " - "can not enter sleep mode!\n", - __FUNCTION__); - return 1; - } - } - i = 0; - can2->canctl0 = 0x01; /* enter init mode */ - /* wait until init mode reached */ - while (!(can2->canctl1 & 0x01)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN2 initialize error, " - "can not enter init mode!\n", - __FUNCTION__); - return 1; - } - } - can2->canctl1 = 0x80; - can2->canctl1 |= 0x40; - can2->canbtr0 = 0x0F; - can2->canbtr1 = 0x7F; - can2->canidac &= ~(0x30); - can2->canidar1 = 0x00; - can2->canidar3 = 0x00; - can2->canidar5 = 0x00; - can2->canidar7 = 0x00; - can2->canidmr0 = 0xFF; - can2->canidmr1 = 0xFF; - can2->canidmr2 = 0xFF; - can2->canidmr3 = 0xFF; - can2->canidmr4 = 0xFF; - can2->canidmr5 = 0xFF; - can2->canidmr6 = 0xFF; - can2->canidmr7 = 0xFF; - can2->canctl0 &= ~(0x01); /* leave init mode */ - can2->canctl0 &= ~(0x02); - - i = 0; - /* wait until init mode left */ - while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) { - udelay(10); - i++; - if (i == 10) { - printf ("%s: CAN2 initialize error, " - "can not leave init/sleep mode!\n", - __FUNCTION__); - return 1; - } - } - init_done = 1; - } - return 0; -} - -/* - * return 1 on CAN failure - * return 0 if no failure - */ -int do_can(char * const argv[]) -{ - int i; - struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900); - struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980); - - /* send a message on CAN1 */ - can1->cantbsel = 0x01; - can1->cantxfg.idr[0] = 0x55; - can1->cantxfg.idr[1] = 0x00; - can1->cantxfg.idr[1] &= ~0x8; - can1->cantxfg.idr[1] &= ~0x10; - can1->cantxfg.dsr[0] = 0xCC; - can1->cantxfg.dlr = 1; - can1->cantxfg.tbpr = 0; - can1->cantflg = 0x01; - - i = 0; - while ((can1->cantflg & 0x01) == 0) { - i++; - if (i == 10) { - printf ("%s: CAN1 send timeout, " - "can not send message!\n", - __FUNCTION__); - return 1; - } - udelay(1000); - } - udelay(1000); - - i = 0; - while (!(can2->canrflg & 0x01)) { - i++; - if (i == 10) { - printf ("%s: CAN2 receive timeout, " - "no message received!\n", - __FUNCTION__); - return 1; - } - udelay(1000); - } - - if (can2->canrxfg.dsr[0] != 0xCC) { - printf ("%s: CAN2 receive error, " - "data mismatch!\n", - __FUNCTION__); - return 1; - } - - /* send a message on CAN2 */ - can2->cantbsel = 0x01; - can2->cantxfg.idr[0] = 0x55; - can2->cantxfg.idr[1] = 0x00; - can2->cantxfg.idr[1] &= ~0x8; - can2->cantxfg.idr[1] &= ~0x10; - can2->cantxfg.dsr[0] = 0xCC; - can2->cantxfg.dlr = 1; - can2->cantxfg.tbpr = 0; - can2->cantflg = 0x01; - - i = 0; - while ((can2->cantflg & 0x01) == 0) { - i++; - if (i == 10) { - printf ("%s: CAN2 send error, " - "can not send message!\n", - __FUNCTION__); - return 1; - } - udelay(1000); - } - udelay(1000); - - i = 0; - while (!(can1->canrflg & 0x01)) { - i++; - if (i == 10) { - printf ("%s: CAN1 receive timeout, " - "no message received!\n", - __FUNCTION__); - return 1; - } - udelay(1000); - } - - if (can1->canrxfg.dsr[0] != 0xCC) { - printf ("%s: CAN1 receive error 0x%02x\n", - __FUNCTION__, (can1->canrxfg.dsr[0])); - return 1; - } - - return 0; -} - -/* - * return 1 if rs232 port unknown - * return 2 on txd/rxd failure (only rs232 2) - * return 3 on rts/cts failure - * return 0 if no failure - */ -int do_rs232(char * const argv[]) -{ - int error_status = 0; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; - - switch (simple_strtoul(argv[2], NULL, 10)) { - - case 1: - /* check RTS <-> CTS loop */ - /* set rts to 0 */ - psc1->op1 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 0) { - error_status = 3; - printf ("%s: failure at rs232_1, cts status is %d " - "(should be 0)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - - /* set rts to 1 */ - psc1->op0 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 1) { - error_status = 3; - printf ("%s: failure at rs232_1, cts status is %d " - "(should be 1)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - - break; - - case 2: - /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000500; - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000200) { - error_status = 2; - printf ("%s: failure at rs232_2, rxd status is %d " - "(should be 1)\n", - __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000000) { - error_status = 2; - printf ("%s: failure at rs232_2, rxd status is %d " - "(should be 0)\n", - __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000800) { - error_status = 3; - printf ("%s: failure at rs232_2, cts status is %d " - "(should be 1)\n", - __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000000) { - error_status = 3; - printf ("%s: failure at rs232_2, cts status is %d " - "(should be 0)\n", - __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - - /* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */ - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000F00; - break; - - default: - printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); - error_status = 1; - break; - } - - return error_status; -} - -#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S) -static void sm501_backlight (unsigned int state) -{ - if (state == BL_ON) { - *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |= - (1 << 26) | (1 << 27); - } else if (state == BL_OFF) - *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= - ~((1 << 26) | (1 << 27)); -} -#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */ - -int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int rcode; - -#ifdef CONFIG_STK52XX_REV100 - printf ("Revision 100 of STK52XX not supported!\n"); - return 1; -#endif -#if defined(CONFIG_STK52XX) - led_init(); -#endif - can_init(); - - switch (argc) { - - case 0: - case 1: - break; - - case 2: - if (strncmp (argv[1], "can", 3) == 0) { - rcode = do_can (argv); - if (rcode == 0) - printf ("OK\n"); - else - printf ("Error\n"); - return rcode; - } - break; - - case 3: - if (strncmp (argv[1], "rs232", 3) == 0) { - rcode = do_rs232 (argv); - if (rcode == 0) - printf ("OK\n"); - else - printf ("Error\n"); - return rcode; -#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S) - } else if (strncmp (argv[1], "backlight", 4) == 0) { - if (strncmp (argv[2], "on", 2) == 0) { - sm501_backlight (BL_ON); - return 0; - } - else if (strncmp (argv[2], "off", 3) == 0) { - sm501_backlight (BL_OFF); - return 0; - } -#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */ - } - break; - -#if defined(CONFIG_STK52XX) - case 4: - if (strcmp (argv[1], "led") == 0) { - return (do_led (argv)); - } - break; -#endif - - default: - break; - } - - printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n"); - return 1; -} - - -U_BOOT_CMD( - sound , 5, 1, cmd_sound, - "Sound sub-system", - "saw [duration] [freq] [channel]\n" - " - generate sawtooth for 'duration' ms with frequency 'freq'\n" - " on left \"l\" or right \"r\" channel\n" - "sound square [duration] [freq] [channel]\n" - " - generate squarewave for 'duration' ms with frequency 'freq'\n" - " on left \"l\" or right \"r\" channel\n" - "pcm1772 reg val" -); - -U_BOOT_CMD( - wav , 3, 1, cmd_wav, - "play wav file", - "[addr] [bytes]\n" - " - play wav file at address 'addr' with length 'bytes'" -); - -U_BOOT_CMD( - beep , 2, 1, cmd_beep, - "play short beep", - "[channel]\n" - " - play short beep on \"l\"eft or \"r\"ight channel" -); -#endif /* CONFIG_STK52XX || CONFIG_FO300 */ - -#if defined(CONFIG_STK52XX) -U_BOOT_CMD( - fkt , 4, 1, cmd_fkt, - "Function test routines", - "led number on/off\n" - " - 'number's like printed on STK52XX board\n" - "fkt can\n" - " - loopback plug for X83 required\n" - "fkt rs232 number\n" - " - loopback plug(s) for X2 required" -#ifndef CONFIG_TQM5200S - "\n" - "fkt backlight on/off\n" - " - switch backlight on or off" -#endif /* !CONFIG_TQM5200S */ -); -#elif defined(CONFIG_FO300) -U_BOOT_CMD( - fkt , 3, 1, cmd_fkt, - "Function test routines", - "fkt can\n" - " - loopback plug for X16/X29 required\n" - "fkt rs232 number\n" - " - loopback plug(s) for X21/X22 required" -); -#endif -#endif diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h deleted file mode 100644 index 3d9979664f..0000000000 --- a/board/tqc/tqm5200/mt48lc16m16a2-75.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ -/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ -#define SDRAM_CONFIG2 0x8AD70000 -/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c deleted file mode 100644 index cb99afdb90..0000000000 --- a/board/tqc/tqm5200/tqm5200.c +++ /dev/null @@ -1,875 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004-2006 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <console.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <asm/processor.h> -#include <libfdt.h> -#include <netdev.h> -#include <video.h> - -#ifdef CONFIG_VIDEO_SM501 -#include <sm501.h> -#endif - -#if defined(CONFIG_MPC5200_DDR) -#include "mt46v16m16-75.h" -#else -#include "mt48lc16m16a2-75.h" -#endif - -#ifdef CONFIG_OF_LIBFDT -#include <fdt_support.h> -#endif /* CONFIG_OF_LIBFDT */ - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_PS2MULT -void ps2mult_early_init(void); -#endif - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \ - defined(CONFIG_VIDEO) -/* - * EDID block has been generated using Phoenix EDID Designer 1.3. - * This tool creates a text file containing: - * - * EDID BYTES: - * - * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F - * ------------------------------------------------ - * 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00 - * 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00 - * 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01 - * 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00 - * 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 - * 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 - * 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 - * 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17 - * - * Then this data has been manually converted to the char - * array below. - */ -static unsigned char edid_buf[128] = { - 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, - 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, -}; -#endif - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | - hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif - -/* - * ATTENTION: Although partially referenced dram_init does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; - -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - -#if defined(CONFIG_TQM5200_B) - gd->ram_size = dramsize + dramsize2; -#else - gd->ram_size = dramsize; -#endif /* CONFIG_TQM5200_B */ - - return 0; -} - -int checkboard (void) -{ -#if defined(CONFIG_TQM5200S) -# define MODULE_NAME "TQM5200S" -#else -# define MODULE_NAME "TQM5200" -#endif - -#if defined(CONFIG_STK52XX) -# define CARRIER_NAME "STK52xx" -#elif defined(CONFIG_CAM5200) -# define CARRIER_NAME "CAM5200" -#elif defined(CONFIG_FO300) -# define CARRIER_NAME "FO300" -#elif defined(CONFIG_CHARON) -# define CARRIER_NAME "CHARON" -#else -# error "UNKNOWN" -#endif - - puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n" - " on a " CARRIER_NAME " carrier board\n"); - - return 0; -} - -#undef MODULE_NAME -#undef CARRIER_NAME - -void flash_preinit(void) -{ - /* - * Now, when we are in RAM, enable flash write - * access for detection process. - * Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ -} - - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) - -#if defined (CONFIG_MINIFAP) -#define SM501_POWER_MODE0_GATE 0x00000040UL -#define SM501_POWER_MODE1_GATE 0x00000048UL -#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL -#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL -#define SM501_GPIO_DATA_HIGH 0x00010004UL -#define SM501_GPIO_51 0x00080000UL -#endif /* CONFIG MINIFAP */ - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - -#if defined (CONFIG_MINIFAP) - /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */ - - /* enable GPIO control (in both power modes) */ - *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= - POWER_MODE_GATE_GPIO_PWM_I2C; - /* configure GPIO51 as output */ - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= - SM501_GPIO_51; -#else - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; - - /* by default the ATA reset is de-asserted */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; -#endif -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - -#if defined (CONFIG_MINIFAP) - if (idereset) { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= - ~SM501_GPIO_51; - } else { - *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= - SM501_GPIO_51; - } -#else - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; - } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; - } -#endif -} -#endif - -#ifdef CONFIG_POST -/* - * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 - * is left open, no keypress is detected. - */ -int post_hotkeys_pressed(void) -{ -#ifdef CONFIG_STK52XX - struct mpc5xxx_gpio *gpio; - - gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; - - /* - * Configure PSC6_0 through PSC6_3 as GPIO. - */ - gpio->port_config &= ~(0x00700000); - - /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ - gpio->simple_gpioe |= 0x20000000; - - /* Configure GPIO_IRDA_1 as input */ - gpio->simple_ddr &= ~(0x20000000); - - return ((gpio->simple_ival & 0x20000000) ? 0 : 1); -#else - return 0; -#endif -} -#endif - -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ - - extern int usb_cpu_init(void); - -#ifdef CONFIG_PS2MULT - ps2mult_early_init(); -#endif /* CONFIG_PS2MULT */ - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) - /* Low level USB init, required for proper kernel operation */ - usb_cpu_init(); -#endif - - return (0); -} -#endif - -#ifdef CONFIG_FO300 -int silent_boot (void) -{ - vu_long timer3_status; - - /* Configure GPT3 as GPIO input */ - *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004; - - /* Read in TIMER_3 pin status */ - timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS; - -#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED - /* Force silent console mode if S1 switch - * is in closed position (TIMER_3 pin status is LOW). */ - if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0) - return 1; -#else - /* Force silent console mode if S1 switch - * is in open position (TIMER_3 pin status is HIGH). */ - if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1) - return 1; -#endif - - return 0; -} - -int board_early_init_f (void) -{ - if (silent_boot()) - gd->flags |= GD_FLG_SILENT; - - return 0; -} -#endif /* CONFIG_FO300 */ - -#if defined(CONFIG_CHARON) -#include <i2c.h> -#include <asm/io.h> - -/* The TFP410 registers */ -#define TFP410_REG_VEN_ID_L 0x00 -#define TFP410_REG_VEN_ID_H 0x01 -#define TFP410_REG_DEV_ID_L 0x02 -#define TFP410_REG_DEV_ID_H 0x03 -#define TFP410_REG_REV_ID 0x04 - -#define TFP410_REG_CTL_1_MODE 0x08 -#define TFP410_REG_CTL_2_MODE 0x09 -#define TFP410_REG_CTL_3_MODE 0x0A - -#define TFP410_REG_CFG 0x0B - -#define TFP410_REG_DE_DLY 0x32 -#define TFP410_REG_DE_CTL 0x33 -#define TFP410_REG_DE_TOP 0x34 -#define TFP410_REG_DE_CNT_L 0x36 -#define TFP410_REG_DE_CNT_H 0x37 -#define TFP410_REG_DE_LIN_L 0x38 -#define TFP410_REG_DE_LIN_H 0x39 - -#define TFP410_REG_H_RES_L 0x3A -#define TFP410_REG_H_RES_H 0x3B -#define TFP410_REG_V_RES_L 0x3C -#define TFP410_REG_V_RES_H 0x3D - -static int tfp410_read_reg(int reg, uchar *buf) -{ - puts("Error reading the chip.\n"); - return -ENOSYS; -} - -static int tfp410_write_reg(int reg, uchar buf) -{ - puts("Error writing the chip.\n"); - return -ENOSYS; -} - -typedef struct _tfp410_config { - int reg; - uchar val; -}TFP410_CONFIG; - -static TFP410_CONFIG tfp410_configtbl[] = { - {TFP410_REG_CTL_1_MODE, 0x37}, - {TFP410_REG_CTL_2_MODE, 0x20}, - {TFP410_REG_CTL_3_MODE, 0x80}, - {TFP410_REG_DE_DLY, 0x90}, - {TFP410_REG_DE_CTL, 0x00}, - {TFP410_REG_DE_TOP, 0x23}, - {TFP410_REG_DE_CNT_H, 0x02}, - {TFP410_REG_DE_CNT_L, 0x80}, - {TFP410_REG_DE_LIN_H, 0x01}, - {TFP410_REG_DE_LIN_L, 0xe0}, - {-1, 0}, -}; - -static int charon_last_stage_init(void) -{ - volatile struct mpc5xxx_lpb *lpb = - (struct mpc5xxx_lpb *) MPC5XXX_LPB; - uchar buf; - int i = 0; - - /* check version */ - if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0) - return -1; - if (!(buf & 0x04)) - return -1; - if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0) - return -1; - if (!(buf & 0x10)) - return -1; - /* OK, now init the chip */ - while (tfp410_configtbl[i].reg != -1) { - int ret; - - ret = tfp410_write_reg(tfp410_configtbl[i].reg, - tfp410_configtbl[i].val); - if (ret != 0) - return -1; - i++; - } - printf("TFP410 initialized.\n"); - - /* set deadcycle for cs3 to 0 */ - setbits_be32(&lpb->cs_deadcycle, 0xffffcfff); - return 0; -} -#endif - -int last_stage_init (void) -{ - /* - * auto scan for really existing devices and re-set chip select - * configuration. - */ - u16 save, tmp; - int restore; - - /* - * Check for SRAM and SRAM size - */ - - /* save original SRAM content */ - save = *(volatile u16 *)CONFIG_SYS_CS2_START; - restore = 1; - - /* write test pattern to SRAM */ - *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5; - __asm__ volatile ("sync"); - /* - * Put a different pattern on the data lines: otherwise they may float - * long enough to read back what we wrote. - */ - tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; - if (tmp == 0xA5A5) - puts ("!! possible error in SRAM detection\n"); - - if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) { - /* no SRAM at all, disable cs */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); - *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; - *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; - restore = 0; - __asm__ volatile ("sync"); - } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) { - /* make sure that we access a mirrored address */ - *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111; - __asm__ volatile ("sync"); - if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) { - /* SRAM size = 512 kByte */ - *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, - 0x80000); - __asm__ volatile ("sync"); - puts ("SRAM: 512 kB\n"); - } - else - puts ("!! possible error in SRAM detection\n"); - } else { - puts ("SRAM: 1 MB\n"); - } - /* restore origianl SRAM content */ - if (restore) { - *(volatile u16 *)CONFIG_SYS_CS2_START = save; - __asm__ volatile ("sync"); - } - -#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */ - /* - * Check for Grafic Controller - */ - - /* save origianl FB content */ - save = *(volatile u16 *)CONFIG_SYS_CS1_START; - restore = 1; - - /* write test pattern to FB memory */ - *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; - __asm__ volatile ("sync"); - /* - * Put a different pattern on the data lines: otherwise they may float - * long enough to read back what we wrote. - */ - tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; - if (tmp == 0xA5A5) - puts ("!! possible error in grafic controller detection\n"); - - if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { - /* no grafic controller at all, disable cs */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); - *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; - *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF; - restore = 0; - __asm__ volatile ("sync"); - } else { - puts ("VGA: SMI501 (Voyager) with 8 MB\n"); - } - /* restore origianl FB content */ - if (restore) { - *(volatile u16 *)CONFIG_SYS_CS1_START = save; - __asm__ volatile ("sync"); - } - -#ifdef CONFIG_FO300 - if (silent_boot()) { - setenv("bootdelay", "0"); - disable_ctrlc(1); - } -#endif -#endif /* !CONFIG_TQM5200S */ - -#if defined(CONFIG_CHARON) - charon_last_stage_init(); -#endif - return 0; -} - -#ifdef CONFIG_VIDEO_SM501 - -#ifdef CONFIG_FO300 -#define DISPLAY_WIDTH 800 -#else -#define DISPLAY_WIDTH 640 -#endif -#define DISPLAY_HEIGHT 480 - -#ifdef CONFIG_VIDEO_SM501_8BPP -#error CONFIG_VIDEO_SM501_8BPP not supported. -#endif /* CONFIG_VIDEO_SM501_8BPP */ - -#ifdef CONFIG_VIDEO_SM501_16BPP -#error CONFIG_VIDEO_SM501_16BPP not supported. -#endif /* CONFIG_VIDEO_SM501_16BPP */ -#ifdef CONFIG_VIDEO_SM501_32BPP -static const SMI_REGS init_regs [] = -{ -#if 0 /* CRT only */ - {0x00004, 0x0}, - {0x00048, 0x00021807}, - {0x0004C, 0x10090a01}, - {0x00054, 0x1}, - {0x00040, 0x00021807}, - {0x00044, 0x10090a01}, - {0x00054, 0x0}, - {0x80200, 0x00010000}, - {0x80204, 0x0}, - {0x80208, 0x0A000A00}, - {0x8020C, 0x02fa027f}, - {0x80210, 0x004a028b}, - {0x80214, 0x020c01df}, - {0x80218, 0x000201e9}, - {0x80200, 0x00013306}, -#else /* panel + CRT */ -#ifdef CONFIG_FO300 - {0x00004, 0x0}, - {0x00048, 0x00021807}, - {0x0004C, 0x301a0a01}, - {0x00054, 0x1}, - {0x00040, 0x00021807}, - {0x00044, 0x091a0a01}, - {0x00054, 0x0}, - {0x80000, 0x0f013106}, - {0x80004, 0xc428bb17}, - {0x8000C, 0x00000000}, - {0x80010, 0x0C800C80}, - {0x80014, 0x03200000}, - {0x80018, 0x01e00000}, - {0x8001C, 0x00000000}, - {0x80020, 0x01e00320}, - {0x80024, 0x042a031f}, - {0x80028, 0x0086034a}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201ea}, - {0x80200, 0x00010000}, -#else - {0x00004, 0x0}, - {0x00048, 0x00021807}, - {0x0004C, 0x091a0a01}, - {0x00054, 0x1}, - {0x00040, 0x00021807}, - {0x00044, 0x091a0a01}, - {0x00054, 0x0}, - {0x80000, 0x0f013106}, - {0x80004, 0xc428bb17}, - {0x8000C, 0x00000000}, - {0x80010, 0x0a000a00}, - {0x80014, 0x02800000}, - {0x80018, 0x01e00000}, - {0x8001C, 0x00000000}, - {0x80020, 0x01e00280}, - {0x80024, 0x02fa027f}, - {0x80028, 0x004a028b}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201e9}, - {0x80200, 0x00010000}, -#endif /* #ifdef CONFIG_FO300 */ -#endif - {0, 0} -}; -#endif /* CONFIG_VIDEO_SM501_32BPP */ - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { - strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); -#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \ - defined(CONFIG_STK52XX) - } else if (line_number == 2) { -#if defined (CONFIG_CHARON) - strcpy (info, " on a CHARON carrier board"); -#endif -#if defined (CONFIG_STK52XX) - strcpy (info, " on a STK52xx carrier board"); -#endif -#if defined (CONFIG_FO300) - strcpy (info, " on a FO300 carrier board"); -#endif -#endif - } - else { - info [0] = '\0'; - } -} -#endif - -/* - * Returns SM501 register base address. First thing called in the - * driver. Checks if SM501 is physically present. - */ -unsigned int board_video_init (void) -{ - u16 save, tmp; - int restore, ret; - - /* - * Check for Grafic Controller - */ - - /* save origianl FB content */ - save = *(volatile u16 *)CONFIG_SYS_CS1_START; - restore = 1; - - /* write test pattern to FB memory */ - *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; - __asm__ volatile ("sync"); - /* - * Put a different pattern on the data lines: otherwise they may float - * long enough to read back what we wrote. - */ - tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; - if (tmp == 0xA5A5) - puts ("!! possible error in grafic controller detection\n"); - - if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { - /* no grafic controller found */ - restore = 0; - ret = 0; - } else { - ret = SM501_MMIO_BASE; - } - - if (restore) { - *(volatile u16 *)CONFIG_SYS_CS1_START = save; - __asm__ volatile ("sync"); - } - return ret; -} - -/* - * Returns SM501 framebuffer address - */ -unsigned int board_video_get_fb (void) -{ - return SM501_FB_BASE; -} - -/* - * Called after initializing the SM501 and before clearing the screen. - */ -void board_validate_screen (unsigned int base) -{ -} - -/* - * Return a pointer to the initialization sequence. - */ -const SMI_REGS *board_get_regs (void) -{ - return init_regs; -} - -int board_get_width (void) -{ - return DISPLAY_WIDTH; -} - -int board_get_height (void) -{ - return DISPLAY_HEIGHT; -} - -#endif /* CONFIG_VIDEO_SM501 */ - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#if defined(CONFIG_VIDEO) - fdt_add_edid(blob, "smi,sm501", edid_buf); -#endif - - return 0; -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ - -#if defined(CONFIG_RESET_PHY_R) -#include <miiphy.h> - -void reset_phy(void) -{ - /* init Micrel KSZ8993 PHY */ - miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09); -} -#endif - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Built in FEC comes first */ - return pci_eth_init(bis); -} diff --git a/board/tqc/tqm8xx/Kconfig b/board/tqc/tqm8xx/Kconfig deleted file mode 100644 index 857fedb8be..0000000000 --- a/board/tqc/tqm8xx/Kconfig +++ /dev/null @@ -1,155 +0,0 @@ -if TARGET_TQM823L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM823L" - -endif - -if TARGET_TQM823M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM823M" - -endif - -if TARGET_TQM850L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM850L" - -endif - -if TARGET_TQM850M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM850M" - -endif - -if TARGET_TQM855L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM855L" - -endif - -if TARGET_TQM855M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM855M" - -endif - -if TARGET_TQM860L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM860L" - -endif - -if TARGET_TQM860M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM860M" - -endif - -if TARGET_TQM862L - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM862L" - -endif - -if TARGET_TQM862M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM862M" - -endif - -if TARGET_TQM866M - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM866M" - -endif - -if TARGET_TQM885D - -config SYS_BOARD - default "tqm8xx" - -config SYS_VENDOR - default "tqc" - -config SYS_CONFIG_NAME - default "TQM885D" - -endif diff --git a/board/tqc/tqm8xx/MAINTAINERS b/board/tqc/tqm8xx/MAINTAINERS deleted file mode 100644 index f3ddc6a530..0000000000 --- a/board/tqc/tqm8xx/MAINTAINERS +++ /dev/null @@ -1,31 +0,0 @@ -TQM8XX BOARD -M: Wolfgang Denk <wd@denx.de> -S: Maintained -F: board/tqc/tqm8xx/ -F: include/configs/TQM823L.h -F: configs/TQM823L_defconfig -F: configs/TQM823L_LCD_defconfig -F: include/configs/TQM823M.h -F: configs/TQM823M_defconfig -F: include/configs/TQM850L.h -F: configs/TQM850L_defconfig -F: include/configs/TQM850M.h -F: configs/TQM850M_defconfig -F: include/configs/TQM855L.h -F: configs/TQM855L_defconfig -F: include/configs/TQM855M.h -F: configs/TQM855M_defconfig -F: include/configs/TQM860L.h -F: configs/TQM860L_defconfig -F: include/configs/TQM860M.h -F: configs/TQM860M_defconfig -F: include/configs/TQM862L.h -F: configs/TQM862L_defconfig -F: include/configs/TQM862M.h -F: configs/TQM862M_defconfig -F: include/configs/TQM866M.h -F: configs/TQM866M_defconfig -F: include/configs/TQM885D.h -F: configs/TQM885D_defconfig -F: configs/TTTech_defconfig -F: configs/wtk_defconfig diff --git a/board/tqc/tqm8xx/Makefile b/board/tqc/tqm8xx/Makefile deleted file mode 100644 index 2651a2f99f..0000000000 --- a/board/tqc/tqm8xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = tqm8xx.o load_sernum_ethaddr.o diff --git a/board/tqc/tqm8xx/load_sernum_ethaddr.c b/board/tqc/tqm8xx/load_sernum_ethaddr.c deleted file mode 100644 index 0070da1fb8..0000000000 --- a/board/tqc/tqm8xx/load_sernum_ethaddr.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -/*----------------------------------------------------------------------- - * Process Hardware Information Block: - * - * If we boot on a system fresh from factory, check if the Hardware - * Information Block exists and save the information it contains. - * - * The TQM8xxL / TQM82xx Hardware Information Block is defined as - * follows: - * - located in first flash bank - * - starts at offset 0x0003FFC0 - * - size 0x00000040 - * - * Internal structure: - * - sequence of ASCII character strings - * - fields separated by a single space character (0x20) - * - last field terminated by NUL character (0x00) - * - remaining space filled with NUL characters (0x00) - * - * Fields in Hardware Information Block: - * 1) Module Type - * 2) Serial Number - * 3) First MAC Address - * 4) Number of additional MAC addresses - */ - -void load_sernum_ethaddr (void) -{ - unsigned char *hwi; - unsigned char serial [CONFIG_SYS_HWINFO_SIZE]; - unsigned char ethaddr[CONFIG_SYS_HWINFO_SIZE]; - unsigned short ih, is, ie, part; - - hwi = (unsigned char *)(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET); - ih = is = ie = 0; - - if (*((unsigned long *)hwi) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { - return; - } - - part = 1; - - /* copy serial # / MAC address */ - while ((hwi[ih] != '\0') && (ih < CONFIG_SYS_HWINFO_SIZE)) { - if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */ - return; - } - switch (part) { - default: /* Copy serial # */ - if (hwi[ih] == ' ') { - ++part; - } - serial[is++] = hwi[ih]; - break; - case 3: /* Copy MAC address */ - if (hwi[ih] == ' ') { - ++part; - break; - } - ethaddr[ie++] = hwi[ih]; - if ((ie % 3) == 2) - ethaddr[ie++] = ':'; - break; - } - ++ih; - } - serial[is] = '\0'; - if (ie && ethaddr[ie-1] == ':') - --ie; - ethaddr[ie] = '\0'; - - /* set serial# and ethaddr if not yet defined */ - if (getenv("serial#") == NULL) { - setenv ((char *)"serial#", (char *)serial); - } - - if (getenv("ethaddr") == NULL) { - setenv ((char *)"ethaddr", (char *)ethaddr); - } -} diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c deleted file mode 100644 index 58bd7fae47..0000000000 --- a/board/tqc/tqm8xx/tqm8xx.c +++ /dev/null @@ -1,677 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <hwconfig.h> -#include <mpc8xx.h> -#ifdef CONFIG_PS2MULT -#include <ps2mult.h> -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#endif - -extern flash_info_t flash_info[]; /* FLASH chips info */ - -DECLARE_GLOBAL_DATA_PTR; - -static long int dram_size (long int, long int *, long int); - -#define _NOT_USED_ 0xFFFFFFFF - -/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */ -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, - 0x1FF5FC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44, - 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Test TQ ID string (TQM8xx...) - * If present, check for "L" type (no second DRAM bank), - * otherwise "L" type is assumed as default. - * - * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else. - */ - -int checkboard (void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - puts ("Board: "); - - if (l < 0 || strncmp(buf, "TQM8", 4)) { - puts ("### No HW ID - assuming TQM8xxL\n"); - return (0); - } - - if ((buf[6] == 'L')) { /* a TQM8xxL type */ - gd->board_type = 'L'; - } - - if ((buf[6] == 'M')) { /* a TQM8xxM type */ - gd->board_type = 'M'; - } - - if ((buf[6] == 'D')) { /* a TQM885D type */ - gd->board_type = 'D'; - } - - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc (buf[i]); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int dram_init(void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9, size10; - long int size_b0 = 0; - long int size_b1 = 0; - int board_type = gd->board_type; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - /* - * The following value is used as an address (i.e. opcode) for - * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If - * the port size is 32bit the SDRAM does NOT "see" the lower two - * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for - * MICRON SDRAMs: - * -> 0 00 010 0 010 - * | | | | +- Burst Length = 4 - * | | | +----- Burst Type = Sequential - * | | +------- CAS Latency = 2 - * | +----------- Operating Mode = Standard - * +-------------- Write Burst Mode = Programmed Burst Length - */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - -#ifndef CONFIG_CAN_DRIVER - if ((board_type != 'L') && - (board_type != 'M') && - (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - } -#endif /* CONFIG_CAN_DRIVER */ - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay (1); - -#ifndef CONFIG_CAN_DRIVER - if ((board_type != 'L') && - (board_type != 'M') && - (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ - memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */ - udelay (1); - } -#endif /* CONFIG_CAN_DRIVER */ - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20); - - udelay(1000); - -#if defined(CONFIG_SYS_MAMR_10COL) - /* - * try 10 column mode - */ - size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20); -#else - size10 = 0; -#endif /* CONFIG_SYS_MAMR_10COL */ - - if ((size8 < size10) && (size9 < size10)) { - size_b0 = size10; - } else if ((size8 < size9) && (size10 < size9)) { - size_b0 = size9; - memctl->memc_mamr = CONFIG_SYS_MAMR_9COL; - udelay (500); - } else { - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); - } - debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20); - -#ifndef CONFIG_CAN_DRIVER - if ((board_type != 'L') && - (board_type != 'M') && - (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ - /* - * Check Bank 1 Memory Size - * use current column settings - * [9 column SDRAM may also be used in 8 column mode, - * but then only half the real size will be used.] - */ - size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM, - SDRAM_MAX_SIZE); - debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20); - } else { - size_b1 = 0; - } -#endif /* CONFIG_CAN_DRIVER */ - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - - memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b0 > 0) { - /* - * Position Bank 0 immediately above Bank 1 - */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b1; - } else { - unsigned long reg; - - /* - * No bank 0 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - } else { /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or3 = - ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br3 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) - + size_b0; - } else { - unsigned long reg; - -#ifndef CONFIG_CAN_DRIVER - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br3 = 0; -#endif /* CONFIG_CAN_DRIVER */ - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - } - - udelay (10000); - -#ifdef CONFIG_CAN_DRIVER - /* UPM initialization for CAN @ CLKOUT <= 66 MHz */ - - /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CONFIG_SYS_OR3_CAN; - memctl->memc_br3 = CONFIG_SYS_BR3_CAN; - - /* Initialize MBMR */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFCC04; - memctl->memc_mcr = 0x0100 | UPMB; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMB; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMB; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMB; - - memctl->memc_mdr = 0xFFFFDC07; - memctl->memc_mcr = 0x0104 | UPMB; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCCC04; - memctl->memc_mcr = 0x0118 | UPMB; - - memctl->memc_mdr = 0xCFFCDC04; - memctl->memc_mcr = 0x0119 | UPMB; - - memctl->memc_mdr = 0x3FFCC000; - memctl->memc_mcr = 0x011A | UPMB; - - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x011B | UPMB; - - memctl->memc_mdr = 0xFFFDC405; - memctl->memc_mcr = 0x011C | UPMB; -#endif /* CONFIG_CAN_DRIVER */ - -#ifdef CONFIG_ISP1362_USB - /* Initialize OR5 / BR5 */ - memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362; - memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362; -#endif /* CONFIG_ISP1362_USB */ - gd->ram_size = size_b0 + size_b1; - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_MISC_INIT_R -extern void load_sernum_ethaddr(void); -int misc_init_r (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - load_sernum_ethaddr(); - -#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ - int scy, trlx, flash_or_timing, clk_diff; - - scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; - if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { - trlx = OR_TRLX; - scy *= 2; - } else { - trlx = 0; - } - - /* - * We assume that each 10MHz of bus clock require 1-clk SCY - * adjustment. - */ - clk_diff = (gd->bus_clk / 1000000) - 50; - - /* - * We need proper rounding here. This is what the "+5" and "-5" - * are here for. - */ - if (clk_diff >= 0) - scy += (clk_diff + 5) / 10; - else - scy += (clk_diff - 5) / 10; - - /* - * For bus frequencies above 50MHz, we want to use relaxed timing - * (OR_TRLX). - */ - if (gd->bus_clk >= 50000000) - trlx = OR_TRLX; - else - trlx = 0; - - if (trlx) - scy /= 2; - - if (scy > 0xf) - scy = 0xf; - if (scy < 1) - scy = 1; - - flash_or_timing = (scy << 4) | trlx | - (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); - - memctl->memc_or0 = - flash_or_timing | (-flash_info[0].size & OR_AM_MSK); -#else - memctl->memc_or0 = - CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK); -#endif - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - debug ("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - if (flash_info[1].size) { -#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ - memctl->memc_or1 = flash_or_timing | - (-flash_info[1].size & 0xFFFF8000); -#else - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | - (-flash_info[1].size & 0xFFFF8000); -#endif - memctl->memc_br1 = - ((CONFIG_SYS_FLASH_BASE + - flash_info[0]. - size) & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - debug ("## BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - } - -# ifdef CONFIG_IDE_LED - /* Configure PA15 as output port */ - immap->im_ioport.iop_padir |= 0x0001; - immap->im_ioport.iop_paodr |= 0x0001; - immap->im_ioport.iop_papar &= ~0x0001; - immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */ -# endif - - return (0); -} -#endif /* CONFIG_MISC_INIT_R */ - - -# ifdef CONFIG_IDE_LED -void ide_led (uchar led, uchar status) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* We have one led for both pcmcia slots */ - if (status) { /* led on */ - immap->im_ioport.iop_padat |= 0x0001; - } else { - immap->im_ioport.iop_padat &= ~0x0001; - } -} -# endif - -#ifdef CONFIG_LCD_INFO -#include <lcd.h> -#include <version.h> -#include <timestamp.h> - -void lcd_show_board_info(void) -{ - char temp[32]; - - lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME); - lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n"); - lcd_printf (" Wolfgang DENK, wd@denx.de\n"); -#ifdef CONFIG_LCD_INFO_BELOW_LOGO - lcd_printf ("MPC823 CPU at %s MHz\n", - strmhz(temp, gd->cpu_clk)); - lcd_printf (" %ld MB RAM, %ld MB Flash\n", - gd->ram_size >> 20, - gd->bd->bi_flashsize >> 20 ); -#else - /* leave one blank line */ - lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n", - strmhz(temp, gd->cpu_clk), - gd->ram_size >> 20, - gd->bd->bi_flashsize >> 20 ); -#endif /* CONFIG_LCD_INFO_BELOW_LOGO */ -} -#endif /* CONFIG_LCD_INFO */ - -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -int fdt_set_node_and_value (void *blob, - char *nodename, - char *regname, - void *var, - int size) -{ - int ret = 0; - int nodeoffset = 0; - - nodeoffset = fdt_path_offset (blob, nodename); - if (nodeoffset >= 0) { - ret = fdt_setprop (blob, nodeoffset, regname, var, - size); - if (ret < 0) { - printf("ft_blob_update(): " - "cannot set %s/%s property; err: %s\n", - nodename, regname, fdt_strerror (ret)); - } - } else { - printf("ft_blob_update(): " - "cannot find %s node err:%s\n", - nodename, fdt_strerror (nodeoffset)); - } - return ret; -} - -int fdt_del_node_name (void *blob, char *nodename) -{ - int ret = 0; - int nodeoffset = 0; - - nodeoffset = fdt_path_offset (blob, nodename); - if (nodeoffset >= 0) { - ret = fdt_del_node (blob, nodeoffset); - if (ret < 0) { - printf("%s: cannot delete %s; err: %s\n", - __func__, nodename, fdt_strerror (ret)); - } - } else { - printf("%s: cannot find %s node err:%s\n", - __func__, nodename, fdt_strerror (nodeoffset)); - } - return ret; -} - -int fdt_del_prop_name (void *blob, char *nodename, char *propname) -{ - int ret = 0; - int nodeoffset = 0; - - nodeoffset = fdt_path_offset (blob, nodename); - if (nodeoffset >= 0) { - ret = fdt_delprop (blob, nodeoffset, propname); - if (ret < 0) { - printf("%s: cannot delete %s %s; err: %s\n", - __func__, nodename, propname, - fdt_strerror (ret)); - } - } else { - printf("%s: cannot find %s node err:%s\n", - __func__, nodename, fdt_strerror (nodeoffset)); - } - return ret; -} - -/* - * update "brg" property in the blob - */ -void ft_blob_update (void *blob, bd_t *bd) -{ - uchar enetaddr[6]; - ulong brg_data = 0; - - /* BRG */ - brg_data = cpu_to_be32(bd->bi_busfreq); - fdt_set_node_and_value(blob, - "/soc/cpm", "brg-frequency", - &brg_data, sizeof(brg_data)); - - /* MAC addr */ - if (eth_getenv_enetaddr("ethaddr", enetaddr)) { - fdt_set_node_and_value(blob, - "ethernet0", "local-mac-address", - enetaddr, sizeof(u8) * 6); - } - - if (hwconfig_arg_cmp("fec", "off")) { - /* no FEC on this plattform, delete DTS nodes */ - fdt_del_node_name (blob, "ethernet1"); - fdt_del_node_name (blob, "mdio1"); - /* also the aliases entries */ - fdt_del_prop_name (blob, "/aliases", "ethernet1"); - fdt_del_prop_name (blob, "/aliases", "mdio1"); - } else { - /* adjust local-mac-address for FEC ethernet */ - if (eth_getenv_enetaddr("eth1addr", enetaddr)) { - fdt_set_node_and_value(blob, - "ethernet1", "local-mac-address", - enetaddr, sizeof(u8) * 6); - } - } -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - ft_blob_update(blob, bd); - - return 0; -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds deleted file mode 100644 index 44dfafae29..0000000000 --- a/board/tqc/tqm8xx/u-boot.lds +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2000-2012 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - arch/powerpc/cpu/mpc8xx/built-in.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - board/tqc/tqm8xx/built-in.o (.text*) - disk/built-in.o (.text*) - drivers/net/built-in.o (.text*) - drivers/built-in.o (.text.pcmcia_on) - drivers/built-in.o (.text.pcmcia_hardware_enable) - - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.ppcenv*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/v38b/Kconfig b/board/v38b/Kconfig deleted file mode 100644 index 653bfc1c3b..0000000000 --- a/board/v38b/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_V38B - -config SYS_BOARD - default "v38b" - -config SYS_CONFIG_NAME - default "v38b" - -endif diff --git a/board/v38b/MAINTAINERS b/board/v38b/MAINTAINERS deleted file mode 100644 index d1a6ae6b2f..0000000000 --- a/board/v38b/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -V38B BOARD -#M: - -S: Maintained -F: board/v38b/ -F: include/configs/v38b.h -F: configs/v38b_defconfig diff --git a/board/v38b/Makefile b/board/v38b/Makefile deleted file mode 100644 index a20a5ef0e9..0000000000 --- a/board/v38b/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := v38b.o ethaddr.o diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c deleted file mode 100644 index 982998fadc..0000000000 --- a/board/v38b/ethaddr.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> - -/* For the V38B board the pin is GPIO_PSC_6 */ -#define GPIO_PIN GPIO_PSC6_0 - -#define NO_ERROR 0 -#define ERR_NO_NUMBER 1 -#define ERR_BAD_NUMBER 2 - -static int is_high(void); -static int check_device(void); -static void io_out(int value); -static void io_input(void); -static void io_output(void); -static void init_gpio(void); -static void read_byte(unsigned char *data); -static void write_byte(unsigned char command); - -void read_2501_memory(unsigned char *psernum, unsigned char *perr); -void board_get_enetaddr(uchar *enetaddr); - - -static int is_high() -{ - return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN); -} - -static void io_out(int value) -{ - if (value) - *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN; - else - *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN; -} - -static void io_input() -{ - *((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN; - udelay(3); /* allow input to settle */ -} - -static void io_output() -{ - *((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN; -} - -static void init_gpio() -{ - *((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */ -} - -void read_2501_memory(unsigned char *psernum, unsigned char *perr) -{ -#define NBYTES 28 - unsigned char crcval, i; - unsigned char buf[NBYTES]; - - *perr = 0; - crcval = 0; - - for (i = 0; i < NBYTES; i++) - buf[i] = 0; - - if (!check_device()) - *perr = ERR_NO_NUMBER; - else { - *perr = NO_ERROR; - write_byte(0xCC); /* skip ROM (0xCC) */ - write_byte(0xF0); /* Read memory command 0xF0 */ - write_byte(0x00); /* Address TA1=0, TA2=0 */ - write_byte(0x00); - read_byte(&crcval); /* Read CRC of address and command */ - - for (i = 0; i < NBYTES; i++) - read_byte(&buf[i]); - } - if (strncmp((const char *) &buf[11], "MAREL IEEE 802.3", 16)) { - *perr = ERR_BAD_NUMBER; - psernum[0] = 0x00; - psernum[1] = 0xE0; - psernum[2] = 0xEE; - psernum[3] = 0xFF; - psernum[4] = 0xFF; - psernum[5] = 0xFF; - } else { - psernum[0] = 0x00; - psernum[1] = 0xE0; - psernum[2] = 0xEE; - psernum[3] = buf[7]; - psernum[4] = buf[6]; - psernum[5] = buf[5]; - } -} - -static int check_device() -{ - int found; - - io_output(); - io_out(0); - udelay(500); /* must be at least 480 us low pulse */ - - io_input(); - udelay(60); - - found = (is_high() == 0) ? 1 : 0; - udelay(500); /* must be at least 480 us low pulse */ - - return found; -} - -static void write_byte(unsigned char command) -{ - char i; - - for (i = 0; i < 8; i++) { - /* 1 us to 15 us low pulse starts bit slot */ - /* Start with high pulse for 3 us */ - io_input(); - udelay(3); - - io_out(0); - io_output(); - udelay(3); - - if (command & 0x01) { - /* 60 us high for 1-bit */ - io_input(); - udelay(60); - } else - /* 60 us low for 0-bit */ - udelay(60); - /* Leave pin as input */ - io_input(); - - command = command >> 1; - } -} - -static void read_byte(unsigned char *data) -{ - unsigned char i, rdat = 0; - - for (i = 0; i < 8; i++) { - /* read one bit from one-wire device */ - - /* 1 - 15 us low starts bit slot */ - io_out(0); - io_output(); - udelay(0); - - /* allow line to be pulled high */ - io_input(); - - /* delay 10 us */ - udelay(10); - - /* now sample input status */ - if (is_high()) - rdat = (rdat >> 1) | 0x80; - else - rdat = rdat >> 1; - - udelay(60); /* at least 60 us */ - } - /* copy the return value */ - *data = rdat; -} - -void board_get_enetaddr(uchar *enetaddr) -{ - unsigned char sn[6], err = NO_ERROR; - - init_gpio(); - - read_2501_memory(sn, &err); - - if (err == NO_ERROR) { - sprintf((char *)enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x", - sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]); - printf("MAC address: %s\n", enetaddr); - setenv("ethaddr", (char *)enetaddr); - } else { - sprintf((char *)enetaddr, "00:01:02:03:04:05"); - printf("Error reading MAC address.\n"); - printf("Setting default to %s\n", enetaddr); - setenv("ethaddr", (char *)enetaddr); - } -} diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c deleted file mode 100644 index e680b7b8ff..0000000000 --- a/board/v38b/v38b.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <net.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif /* SDRAM_DDR */ - - /* precharge all banks */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); -} -#endif /* !CONFIG_SYS_RAMBOOT */ - - -int dram_init(void) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; - -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif /* SDRAM_DDR */ - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - else - *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else - dramsize2 = test2; - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) - dramsize2 = 0; - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - else - *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - else - dramsize2 = 0; - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - *(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - - gd->ram_size = dramsize + dramsize2; - - return 0; -} - - -int checkboard (void) -{ - puts("Board: MarelV38B\n"); - return 0; -} - -int board_early_init_f(void) -{ -#ifdef CONFIG_HW_WATCHDOG - /* - * Enable and configure the direction (output) of PSC3_9 - watchdog - * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's - * Manual. - */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; -#endif /* CONFIG_HW_WATCHDOG */ - return 0; -} - -int board_early_init_r(void) -{ - /* - * Now, when we are in RAM, enable flash write access for the - * detection process. Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - - /* - * Enable GPIO_WKUP_7 to "read the status of the actual power - * situation". Default direction is input, so no need to set it - * explicitly. - */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7; - return 0; -} - -extern void board_get_enetaddr(uchar *enetaddr); -int misc_init_r(void) -{ - uchar enetaddr[6]; - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - return 0; -} - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) -void init_ide_reset(void) -{ - debug("init_ide_reset\n"); - - /* Configure PSC1_4 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; - *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; - /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; -} - - -void ide_set_reset(int idereset) -{ - debug("ide_reset(%d)\n", idereset); - - if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; - /* Make a delay. MPC5200 spec says 25 usec min */ - udelay(500000); - } else - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; -} -#endif - - -#ifdef CONFIG_HW_WATCHDOG -void hw_watchdog_reset(void) -{ - /* - * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog - * we need a positive or negative transition on WDI i.e., our PSC3_9. - */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9; -} -#endif /* CONFIG_HW_WATCHDOG */ diff --git a/board/xilinx/zynqmp/sleep.h b/board/xilinx/zynqmp/sleep.h new file mode 100644 index 0000000000..a962319ffd --- /dev/null +++ b/board/xilinx/zynqmp/sleep.h @@ -0,0 +1 @@ +/* Intentionally empty file for psu_init* */ diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h index 6bbc000da8..679d234b07 100644 --- a/board/xilinx/zynqmp/xil_io.h +++ b/board/xilinx/zynqmp/xil_io.h @@ -33,12 +33,9 @@ int Xil_In32(unsigned long addr) return readl(addr); } -void mask_delay(u32 delay); void usleep(u32 sleep) { udelay(sleep); } -int mask_poll(u32 add, u32 mask); -int mask_pollOnValue(u32 add, u32 mask, u32 value); #endif /* XIL_IO_H */ diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 3849b5885d..51a3d9f276 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -113,6 +113,14 @@ static char *zynqmp_get_silicon_idcode_name(void) } #endif +int board_early_init_f(void) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP) + zynqmp_pmufw_version(); +#endif + return 0; +} + #define ZYNQMP_VERSION_SIZE 9 int board_init(void) diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index e81d6ff18d..8a15c30c0b 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -16,6 +16,7 @@ #include <spi.h> #include <asm/io.h> #include <usb.h> +#include <asm/mach-types.h> DECLARE_GLOBAL_DATA_PTR; |