diff options
Diffstat (limited to 'board')
116 files changed, 1894 insertions, 3574 deletions
diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS b/board/AndesTech/ax25-ae350/MAINTAINERS index b0a99e4ac4..feed5d1298 100644 --- a/board/AndesTech/ax25-ae350/MAINTAINERS +++ b/board/AndesTech/ax25-ae350/MAINTAINERS @@ -5,3 +5,5 @@ F: board/AndesTech/ax25-ae350/ F: include/configs/ax25-ae350.h F: configs/ae350_rv32_defconfig F: configs/ae350_rv64_defconfig +F: configs/ae350_rv32_xip_defconfig +F: configs/ae350_rv64_xip_defconfig diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index d343453f22..3d65ce7b75 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -67,10 +67,6 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) void *board_fdt_blob_setup(void) { - void **ptr = (void *)&prior_stage_fdt_address; - if (fdt_magic(*ptr) == FDT_MAGIC) - return (void *)*ptr; - return (void *)CONFIG_SYS_FDT_BASE; } diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 8a4872343b..3818e3752a 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -16,10 +16,6 @@ #include <fdt_support.h> #include <environment.h> -#ifdef CONFIG_WDT_ARMADA_37XX -#include <wdt.h> -#endif - #include "mox_sp.h" #define MAX_MOX_MODULES 10 diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 4c08f810a2..ad6e29021e 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -18,40 +18,38 @@ #include <dm/uclass.h> #include <fdt_support.h> #include <time.h> - -#ifdef CONFIG_ATSHA204A # include <atsha204a-i2c.h> -#endif - -#ifdef CONFIG_WDT_ORION -# include <wdt.h> -#endif #include "../drivers/ddr/marvell/a38x/ddr3_init.h" #include <../serdes/a38x/high_speed_env_spec.h> DECLARE_GLOBAL_DATA_PTR; -#define OMNIA_I2C_EEPROM_DM_NAME "i2c@11000->i2cmux@70->i2c@0" -#define OMNIA_I2C_EEPROM 0x54 -#define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0 -#define OMNIA_I2C_EEPROM_ADDRLEN 2 +#define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0" + +#define OMNIA_I2C_MCU_CHIP_ADDR 0x2a +#define OMNIA_I2C_MCU_CHIP_LEN 1 + +#define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54 +#define OMNIA_I2C_EEPROM_CHIP_LEN 2 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 -#define OMNIA_I2C_MCU_DM_NAME "i2c@11000->i2cmux@70->i2c@0" -#define OMNIA_I2C_MCU_ADDR_STATUS 0x1 -#define OMNIA_I2C_MCU_SATA 0x20 -#define OMNIA_I2C_MCU_CARDDET 0x10 -#define OMNIA_I2C_MCU 0x2a -#define OMNIA_I2C_MCU_WDT_ADDR 0x0b +enum mcu_commands { + CMD_GET_STATUS_WORD = 0x01, + CMD_GET_RESET = 0x09, + CMD_WATCHDOG_STATE = 0x0b, +}; + +enum status_word_bits { + CARD_DET_STSBIT = 0x0010, + MSATA_IND_STSBIT = 0x0020, +}; #define OMNIA_ATSHA204_OTP_VERSION 0 #define OMNIA_ATSHA204_OTP_SERIAL 1 #define OMNIA_ATSHA204_OTP_MAC0 3 #define OMNIA_ATSHA204_OTP_MAC1 4 -#define MVTWSI_ARMADA_DEBUG_REG 0x8c - /* * Those values and defines are taken from the Marvell U-Boot version * "u-boot-2013.01-2014_T3.0" @@ -87,48 +85,97 @@ static struct serdes_map board_serdes_map_sata[] = { {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} }; -static bool omnia_detect_sata(void) +static struct udevice *omnia_get_i2c_chip(const char *name, uint addr, + uint offset_len) { struct udevice *bus, *dev; - int ret, retry = 3; - u16 mode; - - puts("SERDES0 card detect: "); + int ret; - if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { - puts("Cannot find MCU bus!\n"); - return false; + ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus); + if (ret) { + printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n", + OMNIA_I2C_BUS_NAME, ret); + return NULL; } - ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); + ret = i2c_get_chip(bus, addr, offset_len, &dev); if (ret) { - puts("Cannot get MCU chip!\n"); - return false; + printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n", + name, ret); + return NULL; } - for (; retry > 0; --retry) { - ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2); - if (!ret) - break; - } + return dev; +} + +static int omnia_mcu_read(u8 cmd, void *buf, int len) +{ + struct udevice *chip; + + chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR, + OMNIA_I2C_MCU_CHIP_LEN); + if (!chip) + return -ENODEV; + + return dm_i2c_read(chip, cmd, buf, len); +} - if (!retry) { - puts("I2C read failed! Default PEX\n"); +#ifndef CONFIG_SPL_BUILD +static int omnia_mcu_write(u8 cmd, const void *buf, int len) +{ + struct udevice *chip; + + chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR, + OMNIA_I2C_MCU_CHIP_LEN); + if (!chip) + return -ENODEV; + + return dm_i2c_write(chip, cmd, buf, len); +} + +static bool disable_mcu_watchdog(void) +{ + int ret; + + puts("Disabling MCU watchdog... "); + + ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1); + if (ret) { + printf("omnia_mcu_write failed: %i\n", ret); return false; } - if (!(mode & OMNIA_I2C_MCU_CARDDET)) { - puts("NONE\n"); + puts("disabled\n"); + + return true; +} +#endif + +static bool omnia_detect_sata(void) +{ + int ret; + u16 stsword; + + puts("MiniPCIe/mSATA card detection... "); + + ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword)); + if (ret) { + printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n", + ret); return false; } - if (mode & OMNIA_I2C_MCU_SATA) { - puts("SATA\n"); - return true; - } else { - puts("PEX\n"); + if (!(stsword & CARD_DET_STSBIT)) { + puts("none\n"); return false; } + + if (stsword & MSATA_IND_STSBIT) + puts("mSATA\n"); + else + puts("MiniPCIe\n"); + + return stsword & MSATA_IND_STSBIT ? true : false; } int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) @@ -153,48 +200,63 @@ struct omnia_eeprom { static bool omnia_read_eeprom(struct omnia_eeprom *oep) { - struct udevice *bus, *dev; - int ret, crc, retry = 3; + struct udevice *chip; + u32 crc; + int ret; + + chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR, + OMNIA_I2C_EEPROM_CHIP_LEN); - if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) { - puts("Cannot find EEPROM bus\n"); + if (!chip) return false; - } - ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev); + ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep)); if (ret) { - puts("Cannot get EEPROM chip\n"); + printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret); return false; } - for (; retry > 0; --retry) { - ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom)); - if (ret) - continue; - - if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { - puts("I2C EEPROM missing magic number!\n"); - continue; - } - - crc = crc32(0, (unsigned char *) oep, - sizeof(struct omnia_eeprom) - 4); - if (crc == oep->crc) { - break; - } else { - printf("CRC of EEPROM memory config failed! " - "calc=0x%04x saved=0x%04x\n", crc, oep->crc); - } + if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { + printf("bad EEPROM magic number (%08x, should be %08x)\n", + oep->magic, OMNIA_I2C_EEPROM_MAGIC); + return false; } - if (!retry) { - puts("I2C EEPROM read failed!\n"); + crc = crc32(0, (void *)oep, sizeof(*oep) - 4); + if (crc != oep->crc) { + printf("bad EEPROM CRC (stored %08x, computed %08x)\n", + oep->crc, crc); return false; } return true; } +static int omnia_get_ram_size_gb(void) +{ + static int ram_size; + struct omnia_eeprom oep; + + if (!ram_size) { + /* Get the board config from EEPROM */ + if (omnia_read_eeprom(&oep)) { + debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize); + + if (oep.ramsize == 0x2) + ram_size = 2; + else + ram_size = 1; + } else { + /* Hardcoded fallback */ + puts("Memory config from EEPROM read failed!\n"); + puts("Falling back to default 1 GiB!\n"); + ram_size = 1; + } + } + + return ram_size; +} + /* * Define the DDR layout / topology here in the board file. This will * be used by the DDR3 init code in the SPL U-Boot version to configure @@ -246,37 +308,10 @@ static struct mv_ddr_topology_map board_topology_map_2g = { struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) { - static int mem = 0; - struct omnia_eeprom oep; - - /* Get the board config from EEPROM */ - if (mem == 0) { - if(!omnia_read_eeprom(&oep)) - goto out; - - printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize); - - if (oep.ramsize == 0x2) - mem = 2; - else - mem = 1; - } - -out: - /* Hardcoded fallback */ - if (mem == 0) { - puts("WARNING: Memory config from EEPROM read failed.\n"); - puts("Falling back to default 1GiB map.\n"); - mem = 1; - } - - /* Return the board topology as defined in the board code */ - if (mem == 1) - return &board_topology_map_1g; - if (mem == 2) + if (omnia_get_ram_size_gb() == 2) return &board_topology_map_2g; - - return &board_topology_map_1g; + else + return &board_topology_map_1g; } #ifndef CONFIG_SPL_BUILD @@ -293,12 +328,47 @@ static int set_regdomain(void) printf("Regdomain set to %s\n", rd); return env_set("regdomain", rd); } + +/* + * default factory reset bootcommand on Omnia first sets all the front LEDs + * to green and then tries to load the rescue image from SPI flash memory and + * boot it + */ +#define OMNIA_FACTORY_RESET_BOOTCMD \ + "i2c dev 2; " \ + "i2c mw 0x2a.1 0x3 0x1c 1; " \ + "i2c mw 0x2a.1 0x4 0x1c 1; " \ + "mw.l 0x01000000 0x00ff000c; " \ + "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \ + "setenv bootargs \"$bootargs omniarescue=$omnia_reset\"; " \ + "sf probe; " \ + "sf read 0x1000000 0x100000 0x700000; " \ + "bootm 0x1000000; " \ + "bootz 0x1000000" + +static void handle_reset_button(void) +{ + int ret; + u8 reset_status; + + ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1); + if (ret) { + printf("omnia_mcu_read failed: %i, reset status unknown!\n", + ret); + return; + } + + env_set_ulong("omnia_reset", reset_status); + + if (reset_status) { + printf("RESET button was pressed, overwriting bootcmd!\n"); + env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD); + } +} #endif int board_early_init_f(void) { - u32 i2c_debug_reg; - /* Configure MPP */ writel(0x11111111, MVEBU_MPP_BASE + 0x00); writel(0x11111111, MVEBU_MPP_BASE + 0x04); @@ -321,59 +391,16 @@ int board_early_init_f(void) writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); - /* - * Disable I2C debug mode blocking 0x64 I2C address. - * Note: that would be redundant once Turris Omnia migrates to DM_I2C, - * because the mvtwsi driver includes equivalent code. - */ - i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); - i2c_debug_reg &= ~(1<<18); - writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); - return 0; } -#ifndef CONFIG_SPL_BUILD -static bool disable_mcu_watchdog(void) -{ - struct udevice *bus, *dev; - int ret, retry = 3; - uchar buf[1] = {0x0}; - - if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { - puts("Cannot find MCU bus! Can not disable MCU WDT.\n"); - return false; - } - - ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); - if (ret) { - puts("Cannot get MCU chip! Can not disable MCU WDT.\n"); - return false; - } - - for (; retry > 0; --retry) - if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1)) - break; - - if (retry <= 0) { - puts("I2C MCU watchdog failed to disable!\n"); - return false; - } - - return true; -} -#endif - int board_init(void) { - /* adress of boot parameters */ + /* address of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; #ifndef CONFIG_SPL_BUILD - if (disable_mcu_watchdog()) - puts("Disabled MCU startup watchdog.\n"); - - set_regdomain(); + disable_mcu_watchdog(); #endif return 0; @@ -383,17 +410,17 @@ int board_late_init(void) { #ifndef CONFIG_SPL_BUILD set_regdomain(); + handle_reset_button(); #endif return 0; } -#ifdef CONFIG_ATSHA204A static struct udevice *get_atsha204a_dev(void) { - static struct udevice *dev = NULL; + static struct udevice *dev; - if (dev != NULL) + if (dev) return dev; if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { @@ -403,14 +430,12 @@ static struct udevice *get_atsha204a_dev(void) return dev; } -#endif int checkboard(void) { u32 version_num, serial_num; int err = 1; -#ifdef CONFIG_ATSHA204A struct udevice *dev = get_atsha204a_dev(); if (dev) { @@ -420,13 +445,13 @@ int checkboard(void) err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, OMNIA_ATSHA204_OTP_VERSION, - (u8 *) &version_num); + (u8 *)&version_num); if (err) goto out; err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, OMNIA_ATSHA204_OTP_SERIAL, - (u8 *) &serial_num); + (u8 *)&serial_num); if (err) goto out; @@ -434,13 +459,13 @@ int checkboard(void) } out: -#endif - + printf("Turris Omnia:\n"); + printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024); if (err) - printf("Board: Turris Omnia (ver N/A). SN: N/A\n"); + printf(" Serial Number: unknown\n"); else - printf("Board: Turris Omnia SNL %08X%08X\n", - be32_to_cpu(version_num), be32_to_cpu(serial_num)); + printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num), + be32_to_cpu(serial_num)); return 0; } @@ -458,7 +483,6 @@ static void increment_mac(u8 *mac) int misc_init_r(void) { -#ifdef CONFIG_ATSHA204A int err; struct udevice *dev = get_atsha204a_dev(); u8 mac0[4], mac1[4], mac[6]; @@ -503,8 +527,6 @@ int misc_init_r(void) eth_env_set_enetaddr("eth2addr", mac); out: -#endif - return 0; } diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its new file mode 100644 index 0000000000..adae997213 --- /dev/null +++ b/board/altera/arria10-socdk/fit_spl_fpga.its @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 + /* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +/dts-v1/; + +/ { + description = "FIT image with FPGA bistream"; + #address-cells = <1>; + + images { + fpga-periph-1 { + description = "FPGA peripheral bitstream"; + data = /incbin/("../../../ghrd_10as066n2.periph.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + + fpga-core-1 { + description = "FPGA core bitstream"; + data = /incbin/("../../../ghrd_10as066n2.core.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + }; + + configurations { + default = "config-1"; + config-1 { + description = "Boot with FPGA early IO release config"; + fpga = "fpga-periph-1", "fpga-core-1"; + }; + }; +}; diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index 04e9eab272..2939389de3 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -161,18 +161,18 @@ static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = { }; static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = { - .p0_mpwldectrl0 = 0x0011000E, - .p0_mpwldectrl1 = 0x000E001B, - .p1_mpwldectrl0 = 0x00190015, - .p1_mpwldectrl1 = 0x00070018, - .p0_mpdgctrl0 = 0x42720306, - .p0_mpdgctrl1 = 0x026F0266, - .p1_mpdgctrl0 = 0x4273030A, - .p1_mpdgctrl1 = 0x02740240, - .p0_mprddlctl = 0x45393B3E, - .p1_mprddlctl = 0x403A3747, - .p0_mpwrdlctl = 0x40434541, - .p1_mpwrdlctl = 0x473E4A3B, + .p0_mpwldectrl0 = 0x001a001a, + .p0_mpwldectrl1 = 0x00260015, + .p0_mpdgctrl0 = 0x030c0320, + .p0_mpdgctrl1 = 0x03100304, + .p0_mprddlctl = 0x432e3538, + .p0_mpwrdlctl = 0x363f423d, + .p1_mpwldectrl0 = 0x0006001e, + .p1_mpwldectrl1 = 0x00050015, + .p1_mpdgctrl0 = 0x031c0324, + .p1_mpdgctrl1 = 0x030c0258, + .p1_mprddlctl = 0x3834313f, + .p1_mpwrdlctl = 0x47374a42, }; static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = { @@ -482,6 +482,29 @@ static void setup_iomux_usb(void) SETUP_IOMUX_PADS(usb_pads); } +/* Perform DDR DRAM calibration */ +static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + int ret = 0; + +#ifdef CONFIG_MX6_DDRCAL + udelay(100); + ret = mmdc_do_write_level_calibration(sysinfo); + if (ret) { + printf("DDR3: Write level calibration error [%d]\n", ret); + return ret; + } + + ret = mmdc_do_dqs_calibration(sysinfo); + if (ret) { + printf("DDR3: DQS calibration error [%d]\n", ret); + return ret; + } +#endif /* CONFIG_MX6_DDRCAL */ + + return ret; +} + /* DRAM */ static void dhcom_spl_dram_init(void) @@ -509,8 +532,7 @@ static void dhcom_spl_dram_init(void) } /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + spl_dram_perform_cal(&dhcom_ddr_64bit); } else if (is_cpu_type(MXC_CPU_MX6DL)) { mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs, @@ -528,8 +550,7 @@ static void dhcom_spl_dram_init(void) } /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + spl_dram_perform_cal(&dhcom_ddr_64bit); } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs, @@ -552,8 +573,7 @@ static void dhcom_spl_dram_init(void) } /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_32bit); + spl_dram_perform_cal(&dhcom_ddr_32bit); } } diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c index 3abc514412..0de1f4243e 100644 --- a/board/elgin/elgin_rv1108/elgin_rv1108.c +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -7,8 +7,8 @@ #include <common.h> #include <asm/io.h> #include <fdtdec.h> -#include <asm/arch/grf_rv1108.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/grf_rv1108.h> +#include <asm/arch-rockchip/hardware.h> #include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index cf057e7de6..20ea6dc59b 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -14,7 +14,8 @@ config SYS_CONFIG_NAME config SYS_TEXT_BASE default 0x80000000 if !RISCV_SMODE - default 0x80200000 if RISCV_SMODE + default 0x80200000 if RISCV_SMODE && ARCH_RV64I + default 0x80400000 if RISCV_SMODE && ARCH_RV32I config BOARD_SPECIFIC_OPTIONS # dummy def_bool y diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig new file mode 100644 index 0000000000..93d7d5f9c5 --- /dev/null +++ b/board/freescale/imx8qm_mek/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8QM_MEK + +config SYS_BOARD + default "imx8qm_mek" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qm_mek" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8qm_mek/MAINTAINERS b/board/freescale/imx8qm_mek/MAINTAINERS new file mode 100644 index 0000000000..115830df19 --- /dev/null +++ b/board/freescale/imx8qm_mek/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8QM MEK BOARD +M: Peng Fan <peng.fan@nxp.com> +S: Maintained +F: board/freescale/imx8qm_mek/ +F: include/configs/imx8qm_mek.h +F: configs/imx8qm_mek_defconfig diff --git a/board/freescale/imx8qm_mek/Makefile b/board/freescale/imx8qm_mek/Makefile new file mode 100644 index 0000000000..bc9a1260bd --- /dev/null +++ b/board/freescale/imx8qm_mek/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qm_mek.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README new file mode 100644 index 0000000000..c3523801ae --- /dev/null +++ b/board/freescale/imx8qm_mek/README @@ -0,0 +1,57 @@ +U-Boot for the NXP i.MX8QM EVK board + +Quick Start +=========== + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +====================================== + +$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ cd imx-atf/ +$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga +$ make PLAT=imx8qm bl31 + +Get scfw_tcm.bin and ahab-container.img +============================== + +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin +$ chmod +x imx-sc-firmware-1.1.bin +$ ./imx-sc-firmware-1.1.bin +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin +$ chmod +x firmware-imx-8.0.bin +$ ./firmware-imx-8.0.bin + +Copy the following binaries to U-Boot folder: + +$ cp imx-atf/build/imx8qm/release/bl31.bin . +$ cp u-boot/u-boot.bin . + +Copy the following firmwares U-Boot folder : + +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img . +$ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin . + +Build U-Boot +============ +$ export ATF_LOAD_ADDR=0x80000000 +$ export BL33_LOAD_ADDR=0x80020000 +$ make imx8qm_mek_defconfig +$ make flash.bin +$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984 + +Flash the binary into the SD card +================================= + +Burn the flash.bin binary to SD card offset 32KB: + +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 + +Boot +==== +Set Boot switch SW2: 1100. diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c new file mode 100644 index 0000000000..e69efc4dd6 --- /dev/null +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <errno.h> +#include <linux/libfdt.h> +#include <environment.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + int ret; + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + + /* Power up UART0 */ + ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (ret) + return ret; + + ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); + if (ret) + return ret; + + /* Enable UART0 clock root */ + ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); + if (ret) + return ret; + + setup_iomux_uart(); + + sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON); + + return 0; +} + +#if IS_ENABLED(CONFIG_DM_GPIO) +static void board_gpio_init(void) +{ + /* TODO */ +} +#else +static inline void board_gpio_init(void) {} +#endif + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +void build_info(void) +{ + u32 sc_build = 0, sc_commit = 0; + + /* Get SCFW build and commit id */ + sc_misc_build_info(-1, &sc_build, &sc_commit); + if (!sc_build) { + printf("SCFW does not support build info\n"); + sc_commit = 0; /* Display 0 when the build info is not supported*/ + } + printf("Build: SCFW %x\n", sc_commit); +} + +int checkboard(void) +{ + puts("Board: iMX8QM MEK\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + /* Power up base board */ + sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON); + + board_gpio_init(); + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "MEK"); + env_set("board_rev", "iMX8QM"); +#endif + + return 0; +} diff --git a/board/freescale/imx8qm_mek/imximage.cfg b/board/freescale/imx8qm_mek/imximage.cfg new file mode 100644 index 0000000000..7dc6b93eb5 --- /dev/null +++ b/board/freescale/imx8qm_mek/imximage.cfg @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-mek-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c new file mode 100644 index 0000000000..95ce9f37e8 --- /dev/null +++ b/board/freescale/imx8qm_mek/spl.c @@ -0,0 +1,75 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <spl.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <dm/lists.h> + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + int offset; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd"); + while (offset != -FDT_ERR_NOTFOUND) { + lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset), + NULL, true); + offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, + "nxp,imx8-pd"); + } + + uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c index 95ce9f37e8..cb4006eb2a 100644 --- a/board/freescale/imx8qxp_mek/spl.c +++ b/board/freescale/imx8qxp_mek/spl.c @@ -18,7 +18,6 @@ DECLARE_GLOBAL_DATA_PTR; void spl_board_init(void) { struct udevice *dev; - int offset; uclass_find_first_device(UCLASS_MISC, &dev); @@ -27,21 +26,6 @@ void spl_board_init(void) continue; } - offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd"); - while (offset != -FDT_ERR_NOTFOUND) { - lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset), - NULL, true); - offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, - "nxp,imx8-pd"); - } - - uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); - - for (; dev; uclass_find_next_device(&dev)) { - if (device_probe(dev)) - continue; - } - arch_cpu_init(); board_early_init_f(); diff --git a/board/google/Kconfig b/board/google/Kconfig index d98a5e818f..679a0f1023 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -52,6 +52,14 @@ config TARGET_CHROMEBOOK_SAMUS Chrome OS EC connected on LPC, and it provides a 2560x1700 high resolution touch-enabled LCD display. +config TARGET_CHROMEBOOK_SAMUS_TPL + bool "Chromebook samus booting from TPL" + help + This is a version of Samus which boots into TPL, then to SPL and + U-Boot proper. This is useful where verified boot must select + between different A/B versions of SPL/U-Boot, to allow upgrading of + almost all U-Boot code in the field. + endchoice source "board/google/chromebook_link/Kconfig" diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig index afbfe53deb..90c23cba1b 100644 --- a/board/google/chromebook_samus/Kconfig +++ b/board/google/chromebook_samus/Kconfig @@ -1,4 +1,4 @@ -if TARGET_CHROMEBOOK_SAMUS +if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL config SYS_BOARD default "chromebook_samus" @@ -10,7 +10,8 @@ config SYS_SOC default "broadwell" config SYS_CONFIG_NAME - default "chromebook_samus" + default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS + default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL config SYS_TEXT_BASE default 0xffe00000 @@ -39,3 +40,12 @@ config SYS_CAR_SIZE default 0x40000 endif + +if TARGET_CHROMEBOOK_SAMUS_TPL + +config BOARD_SPECIFIC_OPTIONS_TPL # dummy + def_bool y + select SPL + select TPL + +endif diff --git a/board/google/chromebook_samus/MAINTAINERS b/board/google/chromebook_samus/MAINTAINERS index 5500e46b40..ca4b16500a 100644 --- a/board/google/chromebook_samus/MAINTAINERS +++ b/board/google/chromebook_samus/MAINTAINERS @@ -4,3 +4,10 @@ S: Maintained F: board/google/chromebook_samus/ F: include/configs/chromebook_samus.h F: configs/chromebook_samus_defconfig + +CHROMEBOOK SAMUS TPL BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/google/chromebook_samus/ +F: include/configs/chromebook_samus.h +F: configs/chromebook_samus_tpl_defconfig diff --git a/board/k+p/bootscripts/tpcboot.cmd b/board/k+p/bootscripts/tpcboot.cmd index 0576e81140..b81494dd1b 100644 --- a/board/k+p/bootscripts/tpcboot.cmd +++ b/board/k+p/bootscripts/tpcboot.cmd @@ -27,6 +27,12 @@ setenv miscadj " if test '${boardsoc}' = 'imx53'; then setenv bootargs '${bootargs} di=${dig_in} key1=${key1}'; fi;" +setenv nfsadj " +if test '${boardsoc}' = 'imx53'; then + if test '${boardtype}' = 'hsc'; then + setenv bootargs '${bootargs} dsa_core.blacklist=yes'; + fi; +fi;" setenv boot_fitImage " setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb'; setenv itbcfg "\"#\${fdt_conf}\""; @@ -72,6 +78,7 @@ setenv boot_nfs " if run download_kernel; then run nfsargs; run addip; + run nfsadj; setenv bootargs '${bootargs}' console=${console}; run boot_fitImage; diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c index becb6a63fa..b447e13461 100644 --- a/board/k+p/kp_imx53/kp_imx53.c +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -13,14 +13,10 @@ #include <asm/arch/iomux-mx53.h> #include <asm/arch/clock.h> #include <asm/gpio.h> -#include <mmc.h> -#include <fsl_esdhc.h> #include <power/pmic.h> #include <fsl_pmic.h> #include "kp_id_rev.h" -#define VBUS_PWR_EN IMX_GPIO_NR(7, 8) -#define PHY_nRST IMX_GPIO_NR(7, 6) #define BOOSTER_OFF IMX_GPIO_NR(2, 23) #define LCD_BACKLIGHT IMX_GPIO_NR(1, 1) #define KEY1 IMX_GPIO_NR(2, 26) @@ -45,59 +41,6 @@ int dram_init_banksize(void) return 0; } -#ifdef CONFIG_USB_EHCI_MX5 -int board_ehci_hcd_init(int port) -{ - gpio_request(VBUS_PWR_EN, "VBUS_PWR_EN"); - gpio_direction_output(VBUS_PWR_EN, 1); - return 0; -} -#endif - -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[] = { - {MMC_SDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; /* eMMC is always present */ -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(bd_t *bis) -{ - int ret; - - static const iomux_v3_cfg_t sd3_pads[] = { - NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), - }; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads)); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); - if (ret) - return ret; - - return 0; -} -#endif - static int power_init(void) { struct udevice *dev; @@ -168,17 +111,6 @@ int board_init(void) return 0; } -void eth_phy_reset(void) -{ - gpio_request(PHY_nRST, "PHY_nRST"); - gpio_direction_output(PHY_nRST, 1); - udelay(50); - gpio_set_value(PHY_nRST, 0); - udelay(400); - gpio_set_value(PHY_nRST, 1); - udelay(50); -} - void board_disable_display(void) { gpio_request(LCD_BACKLIGHT, "LCD_BACKLIGHT"); @@ -210,8 +142,6 @@ int board_late_init(void) if (ret) printf("Error %d reading EEPROM content!\n", ret); - eth_phy_reset(); - show_eeprom(); read_board_id(); diff --git a/board/mikrotik/crs305-1g-4s/.gitignore b/board/mikrotik/crs305-1g-4s/.gitignore new file mode 100644 index 0000000000..775b9346b8 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/.gitignore @@ -0,0 +1 @@ +kwbimage.cfg diff --git a/board/mikrotik/crs305-1g-4s/MAINTAINERS b/board/mikrotik/crs305-1g-4s/MAINTAINERS new file mode 100644 index 0000000000..3823489600 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/MAINTAINERS @@ -0,0 +1,7 @@ +CRS305-1G-4S BOARD +M: Luka Kovacic <me@lukakovacic.xyz> +S: Maintained +F: board/mikrotik/crs305-1g-4s/ +F: include/configs/crs305-1g-4s.h +F: configs/crs305-1g-4s_defconfig +F: arch/arm/dts/armada-xp-crs305-1g-4s.dts diff --git a/board/mikrotik/crs305-1g-4s/Makefile b/board/mikrotik/crs305-1g-4s/Makefile new file mode 100644 index 0000000000..895331beb8 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Stefan Roese <sr@denx.de> + +obj-y := crs305-1g-4s.o +extra-y := kwbimage.cfg + +quiet_cmd_sed = SED $@ + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F) + +SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|" +$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ + include/config/auto.conf + $(call if_changed,sed) diff --git a/board/mikrotik/crs305-1g-4s/README b/board/mikrotik/crs305-1g-4s/README new file mode 100644 index 0000000000..f420aabfbf --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/README @@ -0,0 +1,23 @@ +MikroTik CRS305-1G-4S+IN +======================== + +CRS305-1G-4S+IN is a 4x SFP+ switch with a Gigabit Ethernet port for management. +Specifications: + - Marvell Prestera 98DX3236 switch with an integrated ARMv7 CPU + - 512 MB DDR3 RAM + - UART @ 115200bps + - 4x SFP+ + - Gigabit Ethernet (AR8033) + - 16 MB SPI flash (Winbond 25Q128JVSM) + +Currently supported hardware: + - UART boot (using kwboot) and console + - SPI boot, environment and load kernel + +Planned: + - Gigabit Ethernet support + +Getting binary.0 +================ +binary.0 (DDR3 init phase) can be retrieved/extracted from the integrated bootloader on the SPI flash. +Then binary.0 can be replaced with the extracted blob. diff --git a/board/mikrotik/crs305-1g-4s/binary.0 b/board/mikrotik/crs305-1g-4s/binary.0 new file mode 100644 index 0000000000..8dd687286a --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/binary.0 @@ -0,0 +1,11 @@ +-------- +WARNING: +-------- +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. diff --git a/board/mikrotik/crs305-1g-4s/crs305-1g-4s.c b/board/mikrotik/crs305-1g-4s/crs305-1g-4s.c new file mode 100644 index 0000000000..d1d1f40092 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/crs305-1g-4s.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Stefan Roese <sr@denx.de> + */ + +#include <common.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * These values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-2016_T1.0.eng_drop_v6" + */ +#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) \ + | BIT(6) | BIT(12) | BIT(13) \ + | BIT(16) | BIT(17) | BIT(20) \ + | BIT(29) | BIT(30))) +#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0)) +#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) \ + | BIT(6) | BIT(12) | BIT(13) \ + | BIT(16) | BIT(17) | BIT(20) \ + | BIT(29) | BIT(30)) +#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0 +#define DB_DX_AC3_GPP_POL_LOW 0x0 +#define DB_DX_AC3_GPP_POL_MID 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00142222, MVEBU_MPP_BASE + 0x00); + writel(0x11122000, MVEBU_MPP_BASE + 0x04); + writel(0x44444004, MVEBU_MPP_BASE + 0x08); + writel(0x14444444, MVEBU_MPP_BASE + 0x0c); + writel(0x00000001, MVEBU_MPP_BASE + 0x10); + + /* + * MVEBU_GPIO0_BASE is the User LED + * MVEBU_GPIO1_BASE is the Reset Button (currently not used) + */ + + /* Set GPP Out value */ + writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + /* writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); */ + + /* Set GPP Polarity */ + writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + /* writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); */ + + /* Set GPP Out Enable */ + writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + /* writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); */ + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: " CONFIG_SYS_BOARD "\n"); + + return 0; +} diff --git a/board/mikrotik/crs305-1g-4s/kwbimage.cfg.in b/board/mikrotik/crs305-1g-4s/kwbimage.cfg.in new file mode 100644 index 0000000000..2dbbbd0246 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/kwbimage.cfg.in @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/mikrotik/crs305-1g-4s/binary.0 0000005b 00000068 diff --git a/board/mpr2/Kconfig b/board/mpr2/Kconfig deleted file mode 100644 index 54176e8f6f..0000000000 --- a/board/mpr2/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MPR2 - -config SYS_BOARD - default "mpr2" - -config SYS_CONFIG_NAME - default "mpr2" - -endif diff --git a/board/mpr2/MAINTAINERS b/board/mpr2/MAINTAINERS deleted file mode 100644 index beedf8dda6..0000000000 --- a/board/mpr2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPR2 BOARD -M: Mark Jonas <mark.jonas@de.bosch.com> -S: Maintained -F: board/mpr2/ -F: include/configs/mpr2.h -F: configs/mpr2_defconfig diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile deleted file mode 100644 index 6a71803ac7..0000000000 --- a/board/mpr2/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007 -# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> -# -# Copyright (C) 2007 -# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -# -# Copyright (C) 2007 -# Kenati Technologies, Inc. -# -# (C) Copyright 2008 -# Mark Jonas <mark.jonas@de.bosch.com> -# -# board/mpr2/Makefile -# - -obj-y := mpr2.o -extra-y += lowlevel_init.o diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S deleted file mode 100644 index e34a7a9a17..0000000000 --- a/board/mpr2/lowlevel_init.S +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 - * Mark Jonas <mark.jonas@de.bosch.com> - * - * (C) Copyright 2007 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * board/mpr2/lowlevel_init.S - */ -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - -/* - * Set frequency multipliers and dividers in FRQCR. - */ - write16 WTCSR_A, WTCSR_D - - write16 WTCNT_A, WTCNT_D - - write16 FRQCR_A, FRQCR_D - -/* - * Setup CS0 (Flash). - */ - write32 CS0BCR_A, CS0BCR_D - - write32 CS0WCR_A, CS0WCR_D - -/* - * Setup CS3 (SDRAM). - */ - write32 CS3BCR_A, CS3BCR_D - - write32 CS3WCR_A, CS3WCR_D - - write32 SDCR_A, SDCR_D1 - - write32 RTCSR_A, RTCSR_D - - write32 RTCNT_A, RTCNT_D - - write32 RTCOR_A, RTCOR_D - - write32 SDCR_A, SDCR_D2 - - mov.l SDMR3_A, r1 - mov.l SDMR3_D, r0 - add r0, r1 - mov #0, r0 - mov.w r0, @r1 - - rts - nop - - .align 4 - -/* - * Configuration for MPR2 A.3 through A.7 - */ - -/* - * PLL Settings - */ -FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ -WTCNT_D: .word 0x5A00 /* start counting at zero */ -WTCSR_D: .word 0xA507 /* divide by 4096 */ -.align 2 -/* - * Spansion S29GL256N11 @ 48 MHz - */ -/* 1 idle cycle inserted, normal space, 16 bit */ -CS0BCR_D: .long 0x12490400 -/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ -CS0WCR_D: .long 0x00000340 - -/* - * Samsung K4S511632B-UL75 @ 48 MHz - * Micron MT48LC32M16A2-75 @ 48 MHz - */ -/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ -CS3BCR_D: .long 0x10004400 -/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ -CS3WCR_D: .long 0x00000091 -/* no refresh, 13 rows, 10 cols, NO bank active mode */ -SDCR_D1: .long 0x00000012 -SDCR_D2: .long 0x00000812 /* refresh */ -RTCSR_D: .long 0xA55A0008 /* 1/4, once */ -RTCNT_D: .long 0xA55A005D /* count 93 */ -RTCOR_D: .long 0xa55a005d /* count 93 */ -/* mode register CL2, burst read and SINGLE WRITE */ -SDMR3_D: .long 0x440 - -/* - * Registers - */ - -FRQCR_A: .long 0xA415FF80 -WTCNT_A: .long 0xA415FF84 -WTCSR_A: .long 0xA415FF86 - -#define BSC_BASE 0xA4FD0000 -CS0BCR_A: .long BSC_BASE + 0x04 -CS3BCR_A: .long BSC_BASE + 0x0C -CS0WCR_A: .long BSC_BASE + 0x24 -CS3WCR_A: .long BSC_BASE + 0x2C -SDCR_A: .long BSC_BASE + 0x44 -RTCSR_A: .long BSC_BASE + 0x48 -RTCNT_A: .long BSC_BASE + 0x4C -RTCOR_A: .long BSC_BASE + 0x50 -SDMR3_A: .long BSC_BASE + 0x5000 diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c deleted file mode 100644 index 9eb04907a4..0000000000 --- a/board/mpr2/mpr2.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 - * Mark Jonas <mark.jonas@de.bosch.com> - * - * board/mpr2/mpr2.c - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> - -int checkboard(void) -{ - puts("BOARD: MPR2\n"); - return 0; -} - -int board_init(void) -{ - /* - * For MPR2 A.3 through A.7 - */ - - /* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */ - __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */ - __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */ - - /* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */ - __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */ - __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - - /* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */ - __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */ - __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - - /* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */ - __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */ - __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - - /* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */ - __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */ - __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ - - /* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */ - __raw_writew(0xAABC, PSELA); /* 10 10 10 10 10 11 11 00 */ - - /* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */ - __raw_writew(0x3C00, PSELB); /* 0 0 11 11 0 0 00000000 */ - - /* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */ - __raw_writew(0x0000, PSELC); /* 00 00 00 00 00000000 */ - - /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */ - __raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */ - - /* OTH: (00) Other fuction - * GPO: (01) General Purpose Output - * GPI: (11) General Purpose Input - * GPI+: (10) General Purpose Input with internal pull-up - *------------------------------------------------------- - * A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); - * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); */ - __raw_writew(0x5555, PACR); /* 01 01 01 01 01 01 01 01 */ - - /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); - * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); */ - __raw_writew(0x5555, PBCR); /* 01 01 01 01 01 01 01 01 */ - - /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); - * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; */ - __raw_writew(0x5500, PCCR); /* 01 01 01 01 00 00 00 00 */ - - /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); - * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); */ - __raw_writew(0x5555, PDCR); /* 01 01 01 01 01 01 01 01 */ - - /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; - * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; */ - __raw_writew(0x2800, PECR); /* 00 10 10 00 00 00 00 00 */ - - /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; - * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); */ - __raw_writew(0x0002, PFCR); /* 00 00 00 00 00 00 00 10 */ - - /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2); - * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); */ - __raw_writew(0x03D5, PGCR); /* 00 00 00 11 11 01 01 01 */ - - /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); - * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; */ - __raw_writew(0x0050, PHCR); /* 00 00 00 00 01 01 00 00 */ - - /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; - * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; */ - __raw_writew(0x0000, PJCR); /* 00 00 00 00 00 00 00 00 */ - - /* K7 (x); K6 (x); K5 (x); K4 (x) - * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nc); K0 PINT4(FLASH_READY); */ - __raw_writew(0x00FB, PKCR); /* 00 00 00 00 11 11 10 11 */ - - /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; - * L3 TCK; L2 (x); L1 (x); L0 (x); */ - __raw_writew(0x0000, PLCR); /* 00 00 00 00 00 00 00 00 */ - - /* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); M4 GPO(LAN_RESET); - * M3 GPO(BUZZER); M2 GPO(LCD_BL); M1 CS5B(CAN3_CS); M0 GPI+(nc); */ - __raw_writew(0x5552, PMCR); /* 01 01 01 01 01 01 00 10 */ - __raw_writeb(0xF0, PMDR); /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */ - - /* P7 (x); P6 (x); P5 (x); P4 GPO(on pullup); - * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ); */ - __raw_writew(0x0100, PPCR); /* 00 00 00 01 00 00 00 00 */ - __raw_writeb(0x10, PPDR); /* no current flow through pullup */ - - /* R7 A25; R6 A24; R5 A23; R4 A22; - * R3 A21; R2 A20; R1 A19; R0 A0; */ - __raw_writew(0x0000, PRCR); /* 00 00 00 00 00 00 00 00 */ - - /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); - * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; */ - __raw_writew(0x0140, PSCR); /* 00 00 00 01 01 00 00 00 */ - - /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; - * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG); */ - __raw_writew(0x0001, PTCR); /* 00 00 00 00 00 00 00 01 */ - - /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); - * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; */ - __raw_writew(0x0240, PUCR); /* 00 00 00 10 01 00 00 00 */ - - /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); - * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); */ - __raw_writew(0x0142, PVCR); /* 00 00 00 01 01 00 00 10 */ - - return 0; -} diff --git a/board/ms7720se/Kconfig b/board/ms7720se/Kconfig deleted file mode 100644 index 83313279b3..0000000000 --- a/board/ms7720se/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MS7720SE - -config SYS_BOARD - default "ms7720se" - -config SYS_CONFIG_NAME - default "ms7720se" - -endif diff --git a/board/ms7720se/MAINTAINERS b/board/ms7720se/MAINTAINERS deleted file mode 100644 index 96a80f4e31..0000000000 --- a/board/ms7720se/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MS7720SE BOARD -M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> -S: Maintained -F: board/ms7720se/ -F: include/configs/ms7720se.h -F: configs/ms7720se_defconfig diff --git a/board/ms7720se/Makefile b/board/ms7720se/Makefile deleted file mode 100644 index d3a8e19d0b..0000000000 --- a/board/ms7720se/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007 -# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> -# -# Copyright (C) 2007 -# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -# -# Copyright (C) 2007 -# Kenati Technologies, Inc. -# -# board/ms7720se/Makefile -# - -obj-y := ms7720se.o -extra-y += lowlevel_init.o diff --git a/board/ms7720se/lowlevel_init.S b/board/ms7720se/lowlevel_init.S deleted file mode 100644 index 871d6a81d5..0000000000 --- a/board/ms7720se/lowlevel_init.S +++ /dev/null @@ -1,184 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - */ - -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - write16 WTCSR_A, WTCSR_D - - write16 WTCNT_A, WTCNT_D - - write16 FRQCR_A, FRQCR_D - - write16 UCLKCR_A, UCLKCR_D - - write32 CMNCR_A, CMNCR_D - - write32 CMNCR_A, CMNCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS2BCR_A, CS2BCR_D - - write32 CS3BCR_A, CS3BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5ABCR_A, CS5ABCR_D - - write32 CS5BBCR_A, CS5BBCR_D - - write32 CS6ABCR_A, CS6ABCR_D - - write32 CS6BBCR_A, CS6BBCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS2WCR_A, CS2WCR_D - - write32 CS3WCR_A, CS3WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5AWCR_A, CS5AWCR_D - - write32 CS5BWCR_A, CS5BWCR_D - - write32 CS6AWCR_A, CS6AWCR_D - - write32 CS6BWCR_A, CS6BWCR_D - - write32 SDCR_A, SDCR_D1 - - write32 RTCSR_A, RTCSR_D - - write32 RTCNT_A RTCNT_D - - write32 RTCOR_A, RTCOR_D - - write32 SDCR_A, SDCR_D2 - - write16 SDMR3_A, SDMR3_D - - write16 PCCR_A, PCCR_D - - write16 PDCR_A, PDCR_D - - write16 PECR_A, PECR_D - - write16 PGCR_A, PGCR_D - - write16 PHCR_A, PHCR_D - - write16 PPCR_A, PPCR_D - - write16 PTCR_A, PTCR_D - - write16 PVCR_A, PVCR_D - - write16 PSELA_A, PSELA_D - - write32 CCR_A, CCR_D - - write8 LED_A, LED_D - - rts - nop - - .align 4 - -FRQCR_A: .long 0xA415FF80 /* FRQCR Address */ -WTCNT_A: .long 0xA415FF84 -WTCSR_A: .long 0xA415FF86 -UCLKCR_A: .long 0xA40A0008 -FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ -WTCNT_D: .word 0x5A00 -WTCSR_D: .word 0xA506 -UCLKCR_D: .word 0xA5C0 - -#define BSC_BASE 0xA4FD0000 -CMNCR_A: .long BSC_BASE -CS0BCR_A: .long BSC_BASE + 0x04 -CS2BCR_A: .long BSC_BASE + 0x08 -CS3BCR_A: .long BSC_BASE + 0x0C -CS4BCR_A: .long BSC_BASE + 0x10 -CS5ABCR_A: .long BSC_BASE + 0x14 -CS5BBCR_A: .long BSC_BASE + 0x18 -CS6ABCR_A: .long BSC_BASE + 0x1C -CS6BBCR_A: .long BSC_BASE + 0x20 -CS0WCR_A: .long BSC_BASE + 0x24 -CS2WCR_A: .long BSC_BASE + 0x28 -CS3WCR_A: .long BSC_BASE + 0x2C -CS4WCR_A: .long BSC_BASE + 0x30 -CS5AWCR_A: .long BSC_BASE + 0x34 -CS5BWCR_A: .long BSC_BASE + 0x38 -CS6AWCR_A: .long BSC_BASE + 0x3C -CS6BWCR_A: .long BSC_BASE + 0x40 -SDCR_A: .long BSC_BASE + 0x44 -RTCSR_A: .long BSC_BASE + 0x48 -RTCNT_A: .long BSC_BASE + 0x4C -RTCOR_A: .long BSC_BASE + 0x50 -SDMR3_A: .long BSC_BASE + 0x58C0 - -CMNCR_D: .long 0x00000010 -CS0BCR_D: .long 0x36DB0400 -CS2BCR_D: .long 0x36DB0400 -CS3BCR_D: .long 0x36DB4600 -CS4BCR_D: .long 0x36DB0400 -CS5ABCR_D: .long 0x36DB0400 -CS5BBCR_D: .long 0x36DB0200 -CS6ABCR_D: .long 0x36DB0400 -CS6BBCR_D: .long 0x36DB0400 -CS0WCR_D: .long 0x00000B01 -CS2WCR_D: .long 0x00000500 -CS3WCR_D: .long 0x00006D1B -CS4WCR_D: .long 0x00000500 -CS5AWCR_D: .long 0x00000500 -CS5BWCR_D: .long 0x00000500 -CS6AWCR_D: .long 0x00000500 -CS6BWCR_D: .long 0x00000500 -SDCR_D1: .long 0x00000011 -RTCSR_D: .long 0xA55A0010 -RTCNT_D: .long 0xA55A001F -RTCOR_D: .long 0xA55A001F -SDMR3_D: .word 0x0000 -.align 2 -SDCR_D2: .long 0x00000811 - -#define PFC_BASE 0xA4050100 -PCCR_A: .long PFC_BASE + 0x04 -PDCR_A: .long PFC_BASE + 0x06 -PECR_A: .long PFC_BASE + 0x08 -PGCR_A: .long PFC_BASE + 0x0C -PHCR_A: .long PFC_BASE + 0x0E -PPCR_A: .long PFC_BASE + 0x18 -PTCR_A: .long PFC_BASE + 0x1E -PVCR_A: .long PFC_BASE + 0x22 -PSELA_A: .long PFC_BASE + 0x24 - -PCCR_D: .word 0x0000 -PDCR_D: .word 0x0000 -PECR_D: .word 0x0000 -PGCR_D: .word 0x0000 -PHCR_D: .word 0x0000 -PPCR_D: .word 0x00AA -PTCR_D: .word 0x0280 -PVCR_D: .word 0x0000 -PSELA_D: .word 0x0000 -.align 2 - -CCR_A: .long 0xFFFFFFEC -!CCR_D: .long 0x0000000D -CCR_D: .long 0x0000000B - -LED_A: .long 0xB6800000 -LED_D: .long 0xFF diff --git a/board/ms7720se/ms7720se.c b/board/ms7720se/ms7720se.c deleted file mode 100644 index a35f72e83b..0000000000 --- a/board/ms7720se/ms7720se.c +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * Copyright (C) 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * Copyright (C) 2007 - * Kenati Technologies, Inc. - * - * board/ms7720se/ms7720se.c - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> - -#define LED_BASE 0xB0800000 - -int checkboard(void) -{ - puts("BOARD: Hitachi UL MS7720SE\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -void led_set_state(unsigned short value) -{ - outw(value & 0xFF, LED_BASE); -} diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c index 807c717e33..114f7fd9d9 100644 --- a/board/mscc/luton/luton.c +++ b/board/mscc/luton/luton.c @@ -6,8 +6,7 @@ #include <common.h> #include <asm/io.h> #include <led.h> - -DECLARE_GLOBAL_DATA_PTR; +#include <miiphy.h> enum { BOARD_TYPE_PCB090 = 0xAABBCD00, @@ -36,6 +35,16 @@ int board_early_init_r(void) return 0; } +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, 0, 31, 0x10); + phy_write(phydev, 0, 18, 0x80A0); + while (phy_read(phydev, 0, 18) & 0x8000) + ; + phy_write(phydev, 0, 31, 0); + return 0; +} + static void do_board_detect(void) { u32 chipid = (readl(BASE_DEVCPU_GCB + CHIP_ID) >> 12) & 0xFFFF; diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index 532d06f000..bcae8fa50c 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -11,6 +11,7 @@ #include <spi.h> #include <led.h> #include <wait_bit.h> +#include <miiphy.h> DECLARE_GLOBAL_DATA_PTR; @@ -42,6 +43,20 @@ void mscc_switch_reset(bool enter) mscc_gpio_set_alternate(19, 0); } +int board_phy_config(struct phy_device *phydev) +{ + if (gd->board_type == BOARD_TYPE_PCB123) + return 0; + + phy_write(phydev, 0, 31, 0x10); + phy_write(phydev, 0, 18, 0x80F0); + while (phy_read(phydev, 0, 18) & 0x8000) + ; + phy_write(phydev, 0, 31, 0); + + return 0; +} + void board_debug_uart_init(void) { /* too early for the pinctrl driver, so configure the UART pins here */ diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c index 24ee5e528d..da7f55620d 100644 --- a/board/mscc/serval/serval.c +++ b/board/mscc/serval/serval.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/io.h> #include <led.h> +#include <miiphy.h> enum { BOARD_TYPE_PCB106 = 0xAABBCD00, @@ -27,6 +28,17 @@ int board_early_init_r(void) return 0; } +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, 0, 31, 0x10); + phy_write(phydev, 0, 18, 0x80F0); + while (phy_read(phydev, 0, 18) & 0x8000) + ; + phy_write(phydev, 0, 14, 0x800); + phy_write(phydev, 0, 31, 0); + return 0; +} + static void do_board_detect(void) { u16 gpio_in_reg; @@ -42,10 +54,10 @@ static void do_board_detect(void) gd->board_type = BOARD_TYPE_PCB106; else gd->board_type = BOARD_TYPE_PCB105; - mscc_phy_wr(1, 16, 15, 0); } else { gd->board_type = BOARD_TYPE_PCB105; } + mscc_phy_wr(1, 16, 31, 0x0); } #if defined(CONFIG_MULTI_DTB_FIT) diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c index 5d8b79eee3..60429e4529 100644 --- a/board/renesas/ebisu/ebisu.c +++ b/board/renesas/ebisu/ebisu.c @@ -43,17 +43,37 @@ int board_init(void) return 0; } +/* + * If the firmware passed a device tree use it for U-Boot DRAM setup. + */ +extern u64 rcar_atf_boot_args[]; + int dram_init(void) { - if (fdtdec_setup_mem_size_base() != 0) - return -EINVAL; + const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); + const void *blob; - return 0; + /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ + if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) + blob = atf_fdt_blob; + else + blob = gd->fdt_blob; + + return fdtdec_setup_mem_size_base_fdt(blob); } int dram_init_banksize(void) { - fdtdec_setup_memory_banksize(); + const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); + const void *blob; + + /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ + if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) + blob = atf_fdt_blob; + else + blob = gd->fdt_blob; + + fdtdec_setup_memory_banksize_fdt(blob); return 0; } diff --git a/board/renesas/ecovec/Kconfig b/board/renesas/ecovec/Kconfig deleted file mode 100644 index 08cde83356..0000000000 --- a/board/renesas/ecovec/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ECOVEC - -config SYS_BOARD - default "ecovec" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "ecovec" - -endif diff --git a/board/renesas/ecovec/MAINTAINERS b/board/renesas/ecovec/MAINTAINERS deleted file mode 100644 index 439b528de9..0000000000 --- a/board/renesas/ecovec/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -ECOVEC BOARD -M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> -M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -S: Maintained -F: board/renesas/ecovec/ -F: include/configs/ecovec.h -F: configs/ecovec_defconfig diff --git a/board/renesas/ecovec/Makefile b/board/renesas/ecovec/Makefile deleted file mode 100644 index aae3f70813..0000000000 --- a/board/renesas/ecovec/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> -# - -obj-y := ecovec.o -extra-y += lowlevel_init.o diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c deleted file mode 100644 index 6b6c5dc559..0000000000 --- a/board/renesas/ecovec/ecovec.c +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2009, 2011 Renesas Solutions Corp. - * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com> - * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - */ - -#include <common.h> -#include <command.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <i2c.h> -#include <netdev.h> - -/* USB power management register */ -#define UPONCR0 0xA40501D4 - -int checkboard(void) -{ - puts("BOARD: ecovec\n"); - return 0; -} - -static void debug_led(u8 led) -{ - /* PDGR[0-4] is debug LED */ - outb((inb(PGDR) & ~0x0F) | (led & 0x0F), PGDR); -} - -int board_late_init(void) -{ - u8 mac[6]; - char env_mac[18]; - - udelay(1000); - - /* SH-Eth (PLCR, PNCR, PXCR, PSELx )*/ - outw(inw(PLCR) & ~0xFFF0, PLCR); - outw(inw(PNCR) & ~0x000F, PNCR); - outw(inw(PXCR) & ~0x0FC0, PXCR); - outw((inw(PSELB) & ~0x030F) | 0x020A, PSELB); - outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC); - outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE); - - debug_led(1 << 3); - - outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2); - - i2c_set_bus_num(1); /* Use I2C 1 */ - - /* Read MAC address */ - i2c_read(0x50, 0x10, 0, mac, 6); - - /* Set MAC address */ - sprintf(env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - env_set("ethaddr", env_mac); - - debug_led(0x0F); - - return 0; -} - -int board_init(void) -{ - - /* LED (PTG) */ - outw((inw(PGCR) & ~0xFF) | 0x55, PGCR); - outw((inw(HIZCRA) & ~0x02), HIZCRA); - - debug_led(1 << 0); - - /* SCIF0 (PTF, PTM) */ - outw(inw(PFCR) & ~0x30, PFCR); - outw(inw(PMCR) & ~0x0C, PMCR); - outw((inw(PSELA) & ~0x40) | 0x40, PSELA); - - debug_led(1 << 1); - - /* RMII (PTA) */ - outw((inw(PACR) & ~0x0C) | 0x04, PACR); - outb((inb(PADR) & ~0x02) | 0x02, PADR); - - debug_led(1 << 2); - - /* USB host */ - outw((inw(PBCR) & ~0x300) | 0x100, PBCR); - outb((inb(PBDR) & ~0x10) | 0x10, PBDR); - outl(inl(MSTPCR2) & ~0x100000, MSTPCR2); - outw(0x0600, UPONCR0); - - debug_led(1 << 3); - - /* debug switch */ - outw((inw(PVCR) & ~0x03) | 0x02 , PVCR); - - return 0; -} diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S deleted file mode 100644 index adad932316..0000000000 --- a/board/renesas/ecovec/lowlevel_init.S +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com> - * - * board/renesas/ecovec/lowlevel_init.S - */ - -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> -#include <configs/ecovec.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - /* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */ - mov.l PVDR_A, r1 - mov.l PVDR_D, r2 - mov.b @r1, r0 - tst r0, r2 - bt 1f - mov.l JUMP_A, r1 - jmp @r1 - nop - -1: - /* Disable watchdog */ - write16 RWTCSR_A, RWTCSR_D - - /* MMU Disable */ - write32 MMUCR_A, MMUCR_D - - /* Setup clocks */ - write32 PLLCR_A, PLLCR_D - write32 FRQCRA_A, FRQCRA_D - write32 FRQCRB_A, FRQCRB_D - - wait_timer TIMER_D - - write32 MMSELR_A, MMSELR_D - - /* Srtup BSC */ - write32 CMNCR_A, CMNCR_D - write32 CS0BCR_A, CS0BCR_D - write32 CS0WCR_A, CS0WCR_D - - wait_timer TIMER_D - - /* Setup SDRAM */ - write32 DBPDCNT0_A, DBPDCNT0_D0 - write32 DBCONF_A, DBCONF_D - write32 DBTR0_A, DBTR0_D - write32 DBTR1_A, DBTR1_D - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D - write32 DBKIND_A, DBKIND_D - write32 DBCKECNT_A, DBCKECNT_D - - wait_timer TIMER_D - - write32 DBCMDCNT_A, DBCMDCNT_D0 - write32 DBMRCNT_A, DBMRCNT_D0 - write32 DBMRCNT_A, DBMRCNT_D1 - write32 DBMRCNT_A, DBMRCNT_D2 - write32 DBMRCNT_A, DBMRCNT_D3 - write32 DBCMDCNT_A, DBCMDCNT_D0 - write32 DBCMDCNT_A, DBCMDCNT_D1 - write32 DBCMDCNT_A, DBCMDCNT_D1 - write32 DBMRCNT_A, DBMRCNT_D4 - write32 DBMRCNT_A, DBMRCNT_D5 - write32 DBMRCNT_A, DBMRCNT_D6 - - wait_timer TIMER_D - - write32 DBEN_A, DBEN_D - write32 DBRFPDN1_A, DBRFPDN1_D - write32 DBRFPDN2_A, DBRFPDN2_D - write32 DBCMDCNT_A, DBCMDCNT_D0 - - - /* Dummy read */ - mov.l DUMMY_A ,r1 - synco - mov.l @r1, r0 - synco - - mov.l SDRAM_A ,r1 - synco - mov.l @r1, r0 - synco - wait_timer TIMER_D - - add #4, r1 - synco - mov.l @r1, r0 - synco - wait_timer TIMER_D - - add #4, r1 - synco - mov.l @r1, r0 - synco - wait_timer TIMER_D - - add #4, r1 - synco - mov.l @r1, r0 - synco - wait_timer TIMER_D - - write32 DBCMDCNT_A, DBCMDCNT_D0 - write32 DBCMDCNT_A, DBCMDCNT_D1 - write32 DBPDCNT0_A, DBPDCNT0_D1 - write32 DBRFPDN0_A, DBRFPDN0_D - - wait_timer TIMER_D - - write32 CCR_A, CCR_D - - stc sr, r0 - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - - .align 2 - -PVDR_A: .long PVDR -PVDR_D: .long 0x00000001 -JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR -TIMER_D: .long 64 -RWTCSR_A: .long RWTCSR -RWTCSR_D: .long 0x0000A507 -MMUCR_A: .long MMUCR -MMUCR_D: .long 0x00000004 -PLLCR_A: .long PLLCR -PLLCR_D: .long 0x00004000 -FRQCRA_A: .long FRQCRA -FRQCRA_D: .long 0x8E003508 -FRQCRB_A: .long FRQCRB -FRQCRB_D: .long 0x0 -MMSELR_A: .long MMSELR -MMSELR_D: .long 0xA5A50000 -CMNCR_A: .long CMNCR -CMNCR_D: .long 0x00000013 -CS0BCR_A: .long CS0BCR -CS0BCR_D: .long 0x11110400 -CS0WCR_A: .long CS0WCR -CS0WCR_D: .long 0x00000440 -DBPDCNT0_A: .long DBPDCNT0 -DBPDCNT0_D0: .long 0x00000181 -DBPDCNT0_D1: .long 0x00000080 -DBCONF_A: .long DBCONF -DBCONF_D: .long 0x015B0002 -DBTR0_A: .long DBTR0 -DBTR0_D: .long 0x03061502 -DBTR1_A: .long DBTR1 -DBTR1_D: .long 0x02020102 -DBTR2_A: .long DBTR2 -DBTR2_D: .long 0x01090305 -DBTR3_A: .long DBTR3 -DBTR3_D: .long 0x00000002 -DBKIND_A: .long DBKIND -DBKIND_D: .long 0x00000005 -DBCKECNT_A: .long DBCKECNT -DBCKECNT_D: .long 0x00000001 -DBCMDCNT_A: .long DBCMDCNT -DBCMDCNT_D0:.long 0x2 -DBCMDCNT_D1:.long 0x4 -DBMRCNT_A: .long DBMRCNT -DBMRCNT_D0: .long 0x00020000 -DBMRCNT_D1: .long 0x00030000 -DBMRCNT_D2: .long 0x00010040 -DBMRCNT_D3: .long 0x00000532 -DBMRCNT_D4: .long 0x00000432 -DBMRCNT_D5: .long 0x000103C0 -DBMRCNT_D6: .long 0x00010040 -DBEN_A: .long DBEN -DBEN_D: .long 0x01 -DBRFPDN0_A: .long DBRFPDN0 -DBRFPDN1_A: .long DBRFPDN1 -DBRFPDN2_A: .long DBRFPDN2 -DBRFPDN0_D: .long 0x00010000 -DBRFPDN1_D: .long 0x00000613 -DBRFPDN2_D: .long 0x238C003A -SDRAM_A: .long 0xa8000000 -DUMMY_A: .long 0x0c400000 -CCR_A: .long CCR -CCR_D: .long 0x0000090B -SR_MASK_D: .long 0xEFFFFF0F diff --git a/board/renesas/rsk7264/Kconfig b/board/renesas/grpeach/Kconfig index 755d2896fb..00dc496b86 100644 --- a/board/renesas/rsk7264/Kconfig +++ b/board/renesas/grpeach/Kconfig @@ -1,12 +1,12 @@ -if TARGET_RSK7264 +if TARGET_GRPEACH config SYS_BOARD - default "rsk7264" + default "grpeach" config SYS_VENDOR default "renesas" config SYS_CONFIG_NAME - default "rsk7264" + default "grpeach" endif diff --git a/board/renesas/grpeach/MAINTAINERS b/board/renesas/grpeach/MAINTAINERS new file mode 100644 index 0000000000..4ab7773b0a --- /dev/null +++ b/board/renesas/grpeach/MAINTAINERS @@ -0,0 +1,6 @@ +GRPEACH BOARD +M: Marek Vasut <marek.vasut@gmail.com> +S: Maintained +F: board/renesas/grpeach/ +F: include/configs/grpeach.h +F: configs/grpeach_defconfig diff --git a/board/renesas/grpeach/Makefile b/board/renesas/grpeach/Makefile new file mode 100644 index 0000000000..48e185ce3e --- /dev/null +++ b/board/renesas/grpeach/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 Renesas Electronics +# Copyright (C) 2017 Chris Brandt +# +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := grpeach.o +obj-y += lowlevel_init.o diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c new file mode 100644 index 0000000000..4f901eea71 --- /dev/null +++ b/board/renesas/grpeach/grpeach.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) Chris Brandt + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> + +#define RZA1_WDT_BASE 0xfcfe0000 +#define WTCSR 0x00 +#define WTCNT 0x02 +#define WRCSR 0x04 + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + return -EINVAL; + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +void reset_cpu(ulong addr) +{ + /* Dummy read (must read WRCSR:WOVF at least once before clearing) */ + readb(RZA1_WDT_BASE + WRCSR); + + writew(0xa500, RZA1_WDT_BASE + WRCSR); + writew(0x5a5f, RZA1_WDT_BASE + WRCSR); + writew(0x5a00, RZA1_WDT_BASE + WTCNT); + writew(0xa578, RZA1_WDT_BASE + WTCSR); + + for (;;) + asm volatile("wfi"); +} diff --git a/board/renesas/grpeach/lowlevel_init.S b/board/renesas/grpeach/lowlevel_init.S new file mode 100644 index 0000000000..9a66dfa6c6 --- /dev/null +++ b/board/renesas/grpeach/lowlevel_init.S @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Renesas Electronics + * Copyright (C) 2017 Chris Brandt + */ +#include <config.h> +#include <version.h> +#include <asm/macro.h> + +/* Watchdog Registers */ +#define RZA1_WDT_BASE 0xFCFE0000 +#define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */ +#define WTCNT (RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */ +#define WRCSR (RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */ + +/* Standby controller registers (chapter 55) */ +#define RZA1_STBCR_BASE 0xFCFE0020 +#define STBCR1 (RZA1_STBCR_BASE + 0x00) +#define STBCR2 (RZA1_STBCR_BASE + 0x04) +#define STBCR3 (RZA1_STBCR_BASE + 0x400) +#define STBCR4 (RZA1_STBCR_BASE + 0x404) +#define STBCR5 (RZA1_STBCR_BASE + 0x408) +#define STBCR6 (RZA1_STBCR_BASE + 0x40c) +#define STBCR7 (RZA1_STBCR_BASE + 0x410) +#define STBCR8 (RZA1_STBCR_BASE + 0x414) +#define STBCR9 (RZA1_STBCR_BASE + 0x418) +#define STBCR10 (RZA1_STBCR_BASE + 0x41c) +#define STBCR11 (RZA1_STBCR_BASE + 0x420) +#define STBCR12 (RZA1_STBCR_BASE + 0x424) +#define STBCR13 (RZA1_STBCR_BASE + 0x450) + +/* Clock Registers */ +#define RZA1_FRQCR_BASE 0xFCFE0010 +#define FRQCR (RZA1_FRQCR_BASE + 0x00) +#define FRQCR2 (RZA1_FRQCR_BASE + 0x04) + +#define SYSCR1 0xFCFE0400 /* System control register 1 */ +#define SYSCR2 0xFCFE0404 /* System control register 2 */ +#define SYSCR3 0xFCFE0408 /* System control register 3 */ + +/* Disable WDT */ +#define WTCSR_D 0xA518 +#define WTCNT_D 0x5A00 + +/* Enable all peripheral clocks */ +#define STBCR3_D 0x00000000 +#define STBCR4_D 0x00000000 +#define STBCR5_D 0x00000000 +#define STBCR6_D 0x00000000 +#define STBCR7_D 0x00000024 +#define STBCR8_D 0x00000005 +#define STBCR9_D 0x00000000 +#define STBCR10_D 0x00000000 +#define STBCR11_D 0x000000c0 +#define STBCR12_D 0x000000f0 + +/* + * Set all system clocks to full speed. + * On reset, the CPU will be running at 1/2 speed. + * In the Hardware Manual, see Table 6.3 Settable Frequency Ranges + */ +#define FRQCR_D 0x0035 +#define FRQCR2_D 0x0001 + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + /* PL310 init */ + write32 0x3fffff80, 0x00000001 + + /* Disable WDT */ + write16 WTCSR, WTCSR_D + write16 WTCNT, WTCNT_D + + /* Set clocks */ + write16 FRQCR, FRQCR_D + write16 FRQCR2, FRQCR2_D + + /* Enable all peripherals(Standby Control) */ + write8 STBCR3, STBCR3_D + write8 STBCR4, STBCR4_D + write8 STBCR5, STBCR5_D + write8 STBCR6, STBCR6_D + write8 STBCR7, STBCR7_D + write8 STBCR8, STBCR8_D + write8 STBCR9, STBCR9_D + write8 STBCR10, STBCR10_D + write8 STBCR11, STBCR11_D + write8 STBCR12, STBCR12_D + + /* For serial booting, enable read ahead caching to speed things up */ +#define DRCR_0 0x3FEFA00C + write32 DRCR_0, 0x00010100 /* Read Burst ON, Length=2 */ + + /* Enable all internal RAM */ + write8 SYSCR1, 0xFF + write8 SYSCR2, 0xFF + write8 SYSCR3, 0xFF + + nop + /* back to arch calling code */ + mov pc, lr + + .align 4 diff --git a/board/renesas/rsk7203/Kconfig b/board/renesas/rsk7203/Kconfig deleted file mode 100644 index 10b8786411..0000000000 --- a/board/renesas/rsk7203/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_RSK7203 - -config SYS_BOARD - default "rsk7203" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "rsk7203" - -endif diff --git a/board/renesas/rsk7203/MAINTAINERS b/board/renesas/rsk7203/MAINTAINERS deleted file mode 100644 index 18d36634cf..0000000000 --- a/board/renesas/rsk7203/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -RSK7203 BOARD -M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> -M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -S: Maintained -F: board/renesas/rsk7203/ -F: include/configs/rsk7203.h -F: configs/rsk7203_defconfig diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile deleted file mode 100644 index 545079e99e..0000000000 --- a/board/renesas/rsk7203/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007,2008 Nobuhiro Iwamatsu -# Copyright (C) 2008 Renesas Solutions Corp. -# -# u-boot/board/rsk7203/Makefile -# - -obj-y := rsk7203.o -extra-y += lowlevel_init.o diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S deleted file mode 100644 index f82dd7dc05..0000000000 --- a/board/renesas/rsk7203/lowlevel_init.S +++ /dev/null @@ -1,199 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - */ -#include <config.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* Cache setting */ - write32 CCR1_A ,CCR1_D - - /* ConfigurePortPins */ - write16 PECRL3_A, PECRL3_D - - write16 PCCRL4_A, PCCRL4_D0 - - write16 PECRL4_A, PECRL4_D0 - - write16 PEIORL_A, PEIORL_D0 - - write16 PCIORL_A, PCIORL_D - - write16 PFCRH2_A, PFCRH2_D - - write16 PFCRH3_A, PFCRH3_D - - write16 PFCRH1_A, PFCRH1_D - - write16 PFIORH_A, PFIORH_D - - write16 PECRL1_A, PECRL1_D0 - - write16 PEIORL_A, PEIORL_D1 - - /* Configure Operating Frequency */ - write16 WTCSR_A, WTCSR_D0 - - write16 WTCSR_A, WTCSR_D1 - - write16 WTCNT_A, WTCNT_D - - /* Set clock mode*/ - write16 FRQCR_A, FRQCR_D - - /* Configure Bus And Memory */ -init_bsc_cs0: - write16 PCCRL4_A, PCCRL4_D1 - - write16 PECRL1_A, PECRL1_D1 - - write32 CMNCR_A, CMNCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS0WCR_A, CS0WCR_D - -init_bsc_cs1: - write16 PECRL4_A, PECRL4_D1 - - write32 CS1WCR_A, CS1WCR_D - -init_sdram: - write16 PCCRL2_A, PCCRL2_D - - write16 PCCRL4_A, PCCRL4_D2 - - write16 PCCRL1_A, PCCRL1_D - - write16 PCCRL3_A, PCCRL3_D - - write32 CS3BCR_A, CS3BCR_D - - write32 CS3WCR_A, CS3WCR_D - - write32 SDCR_A, SDCR_D - - write32 RTCOR_A, RTCOR_D - - write32 RTCSR_A, RTCSR_D - - /* wait 200us */ - mov.l REPEAT_D, r3 - mov #0, r2 -repeat0: - add #1, r2 - cmp/hs r3, r2 - bf repeat0 - nop - - mov.l SDRAM_MODE, r1 - mov #0, r0 - mov.l r0, @r1 - - nop - rts - - .align 4 - -CCR1_A: .long CCR1 -CCR1_D: .long 0x0000090B -PCCRL4_A: .long 0xFFFE3910 -PCCRL4_D0: .word 0x0000 -.align 2 -PECRL4_A: .long 0xFFFE3A10 -PECRL4_D0: .word 0x0000 -.align 2 -PECRL3_A: .long 0xFFFE3A12 -PECRL3_D: .word 0x0000 -.align 2 -PEIORL_A: .long 0xFFFE3A06 -PEIORL_D0: .word 0x1C00 -PEIORL_D1: .word 0x1C02 -PCIORL_A: .long 0xFFFE3906 -PCIORL_D: .word 0x4000 -.align 2 -PFCRH2_A: .long 0xFFFE3A8C -PFCRH2_D: .word 0x0000 -.align 2 -PFCRH3_A: .long 0xFFFE3A8A -PFCRH3_D: .word 0x0000 -.align 2 -PFCRH1_A: .long 0xFFFE3A8E -PFCRH1_D: .word 0x0000 -.align 2 -PFIORH_A: .long 0xFFFE3A84 -PFIORH_D: .word 0x0729 -.align 2 -PECRL1_A: .long 0xFFFE3A16 -PECRL1_D0: .word 0x0033 -.align 2 - - -WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .word 0xA518 -WTCSR_D1: .word 0xA51D -WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .word 0x5A84 -.align 2 -FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .word 0x0104 -.align 2 - -PCCRL4_D1: .word 0x0010 -PECRL1_D1: .word 0x0133 - -CMNCR_A: .long 0xFFFC0000 -CMNCR_D: .long 0x00001810 -CS0BCR_A: .long 0xFFFC0004 -CS0BCR_D: .long 0x10000400 -CS0WCR_A: .long 0xFFFC0028 -CS0WCR_D: .long 0x00000B41 -PECRL4_D1: .word 0x0100 -.align 2 -CS1WCR_A: .long 0xFFFC002C -CS1WCR_D: .long 0x00000B01 -PCCRL4_D2: .word 0x0011 -.align 2 -PCCRL3_A: .long 0xFFFE3912 -PCCRL3_D: .word 0x0011 -.align 2 -PCCRL2_A: .long 0xFFFE3914 -PCCRL2_D: .word 0x1111 -.align 2 -PCCRL1_A: .long 0xFFFE3916 -PCCRL1_D: .word 0x1010 -.align 2 -PDCRL4_A: .long 0xFFFE3990 -PDCRL4_D: .word 0x0011 -.align 2 -PDCRL3_A: .long 0xFFFE3992 -PDCRL3_D: .word 0x00011 -.align 2 -PDCRL2_A: .long 0xFFFE3994 -PDCRL2_D: .word 0x1111 -.align 2 -PDCRL1_A: .long 0xFFFE3996 -PDCRL1_D: .word 0x1000 -.align 2 -CS3BCR_A: .long 0xFFFC0010 -CS3BCR_D: .long 0x00004400 -CS3WCR_A: .long 0xFFFC0034 -CS3WCR_D: .long 0x00002892 -SDCR_A: .long 0xFFFC004C -SDCR_D: .long 0x00000809 -RTCOR_A: .long 0xFFFC0058 -RTCOR_D: .long 0xA55A0041 -RTCSR_A: .long 0xFFFC0050 -RTCSR_D: .long 0xa55a0010 - -SDRAM_MODE: .long 0xFFFC5040 -REPEAT_D: .long 0x00009C40 diff --git a/board/renesas/rsk7203/rsk7203.c b/board/renesas/rsk7203/rsk7203.c deleted file mode 100644 index 780c1866be..0000000000 --- a/board/renesas/rsk7203/rsk7203.c +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * u-boot/board/rsk7203/rsk7203.c - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -int checkboard(void) -{ - puts("BOARD: Renesas Technology RSK7203\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -/* - * The RSK board has the SMSC9118 wired up 'incorrectly'. - * Byte-swapping is necessary, and so poor performance is inevitable. - * This problem cannot evade by the swap function of CHIP, this can - * evade by software Byte-swapping. - * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push - * functions necessary to solve this problem. - */ -u32 pkt_data_pull(struct eth_device *dev, u32 addr) -{ - volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); - return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ - | swab16(*(addr_16 + 1)); -} - -void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) -{ - addr += dev->iobase; - *(volatile u16 *)(addr + 2) = swab16((u16)val); - *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/renesas/rsk7264/MAINTAINERS b/board/renesas/rsk7264/MAINTAINERS deleted file mode 100644 index f6202b70d9..0000000000 --- a/board/renesas/rsk7264/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -RSK7264 BOARD -M: Phil Edworthy <phil.edworthy@renesas.com> -S: Maintained -F: board/renesas/rsk7264/ -F: include/configs/rsk7264.h -F: configs/rsk7264_defconfig diff --git a/board/renesas/rsk7264/Makefile b/board/renesas/rsk7264/Makefile deleted file mode 100644 index 4efcf5cba9..0000000000 --- a/board/renesas/rsk7264/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Renesas Electronics Europe Ltd. -# - -obj-y := rsk7264.o -extra-y += lowlevel_init.o diff --git a/board/renesas/rsk7264/lowlevel_init.S b/board/renesas/rsk7264/lowlevel_init.S deleted file mode 100644 index 75c251b716..0000000000 --- a/board/renesas/rsk7264/lowlevel_init.S +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Renesas Electronics Europe Ltd. - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * Based on board/renesas/rsk7203/lowlevel_init.S - */ -#include <config.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* Cache setting */ - write32 CCR1_A ,CCR1_D - - /* io_set_cpg */ - write8 STBCR3_A, STBCR3_D - write8 STBCR4_A, STBCR4_D - write8 STBCR5_A, STBCR5_D - write8 STBCR6_A, STBCR6_D - write8 STBCR7_A, STBCR7_D - write8 STBCR8_A, STBCR8_D - - /* ConfigurePortPins */ - - /* Leaving LED1 ON for sanity test */ - write16 PJCR1_A, PJCR1_D1 - write16 PJCR2_A, PJCR2_D - write16 PJIOR0_A, PJIOR0_D1 - write16 PJDR0_A, PJDR0_D - write16 PJPR0_A, PJPR0_D - - /* Configure EN_PIN & RS_PIN */ - write16 PGCR2_A, PGCR2_D - write16 PGIOR0_A, PGIOR0_D - - /* Configure the port pins connected to UART */ - write16 PJCR1_A, PJCR1_D2 - write16 PJIOR0_A, PJIOR0_D2 - - /* Configure Operating Frequency */ - write16 WTCSR_A, WTCSR_D0 - write16 WTCSR_A, WTCSR_D1 - write16 WTCNT_A, WTCNT_D - - /* Control of RESBANK */ - write16 IBNR_A, IBNR_D - /* Enable SCIF3 module */ - write16 STBCR4_A, STBCR4_D - - /* Set clock mode*/ - write16 FRQCR_A, FRQCR_D - - /* Configure Bus And Memory */ -init_bsc_cs0: - -pfc_settings: - write16 PCCR2_A, PCCR2_D - write16 PCCR1_A, PCCR1_D - write16 PCCR0_A, PCCR0_D - - write16 PBCR0_A, PBCR0_D - write16 PBCR1_A, PBCR1_D - write16 PBCR2_A, PBCR2_D - write16 PBCR3_A, PBCR3_D - write16 PBCR4_A, PBCR4_D - write16 PBCR5_A, PBCR5_D - - write16 PDCR0_A, PDCR0_D - write16 PDCR1_A, PDCR1_D - write16 PDCR2_A, PDCR2_D - write16 PDCR3_A, PDCR3_D - - write32 CS0WCR_A, CS0WCR_D - write32 CS0BCR_A, CS0BCR_D - -init_bsc_cs2: - write16 PJCR0_A, PJCR0_D - write32 CS2WCR_A, CS2WCR_D - -init_sdram: - write32 CS3BCR_A, CS3BCR_D - write32 CS3WCR_A, CS3WCR_D - write32 SDCR_A, SDCR_D - write32 RTCOR_A, RTCOR_D - write32 RTCSR_A, RTCSR_D - - /* wait 200us */ - mov.l REPEAT_D, r3 - mov #0, r2 -repeat0: - add #1, r2 - cmp/hs r3, r2 - bf repeat0 - nop - - mov.l SDRAM_MODE, r1 - mov #0, r0 - mov.l r0, @r1 - - nop - rts - - .align 4 - -CCR1_A: .long CCR1 -CCR1_D: .long 0x0000090B -FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .word 0x1003 -.align 2 -STBCR3_A: .long 0xFFFE0408 -STBCR3_D: .long 0x00000002 -STBCR4_A: .long 0xFFFE040C -STBCR4_D: .word 0x0000 -.align 2 -STBCR5_A: .long 0xFFFE0410 -STBCR5_D: .long 0x00000010 -STBCR6_A: .long 0xFFFE0414 -STBCR6_D: .long 0x00000002 -STBCR7_A: .long 0xFFFE0418 -STBCR7_D: .long 0x0000002A -STBCR8_A: .long 0xFFFE041C -STBCR8_D: .long 0x0000007E -PJCR1_A: .long 0xFFFE390C -PJCR1_D1: .word 0x0000 -PJCR1_D2: .word 0x0022 -PJCR2_A: .long 0xFFFE390A -PJCR2_D: .word 0x0000 -.align 2 -PJIOR0_A: .long 0xFFFE3912 -PJIOR0_D1: .word 0x0FC0 -PJIOR0_D2: .word 0x0FE0 -PJDR0_A: .long 0xFFFE3916 -PJDR0_D: .word 0x0FBF -.align 2 -PJPR0_A: .long 0xFFFE391A -PJPR0_D: .long 0x00000FBF -PGCR2_A: .long 0xFFFE38CA -PGCR2_D: .word 0x0000 -.align 2 -PGIOR0_A: .long 0xFFFE38D2 -PGIOR0_D: .word 0x03F0 -.align 2 -WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .word 0x0000 -WTCSR_D1: .word 0x0000 -WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .word 0x0000 -.align 2 -PCCR0_A: .long 0xFFFE384E -PDCR0_A: .long 0xFFFE386E -PDCR1_A: .long 0xFFFE386C -PDCR2_A: .long 0xFFFE386A -PDCR3_A: .long 0xFFFE3868 -PBCR0_A: .long 0xFFFE382E -PBCR1_A: .long 0xFFFE382C -PBCR2_A: .long 0xFFFE382A -PBCR3_A: .long 0xFFFE3828 -PBCR4_A: .long 0xFFFE3826 -PBCR5_A: .long 0xFFFE3824 -PCCR0_D: .word 0x1111 -PDCR0_D: .word 0x1111 -PDCR1_D: .word 0x1111 -PDCR2_D: .word 0x1111 -PDCR3_D: .word 0x1111 -PBCR0_D: .word 0x1110 -PBCR1_D: .word 0x1111 -PBCR2_D: .word 0x1111 -PBCR3_D: .word 0x1111 -PBCR4_D: .word 0x1111 -PBCR5_D: .word 0x0111 -.align 2 -CS0WCR_A: .long 0xFFFC0028 -CS0WCR_D: .long 0x00000B41 -CS0BCR_A: .long 0xFFFC0004 -CS0BCR_D: .long 0x10000400 -PJCR0_A: .long 0xFFFE390E -PJCR0_D: .word 0x3300 -.align 2 -CS2WCR_A: .long 0xFFFC0030 -CS2WCR_D: .long 0x00000B01 -PCCR2_A: .long 0xFFFE384A -PCCR2_D: .word 0x0001 -.align 2 -PCCR1_A: .long 0xFFFE384C -PCCR1_D: .word 0x1111 -.align 2 -CS3BCR_A: .long 0xFFFC0010 -CS3BCR_D: .long 0x00004400 -CS3WCR_A: .long 0xFFFC0034 -CS3WCR_D: .long 0x0000288A -SDCR_A: .long 0xFFFC004C -SDCR_D: .long 0x00000812 -RTCOR_A: .long 0xFFFC0058 -RTCOR_D: .long 0xA55A0046 -RTCSR_A: .long 0xFFFC0050 -RTCSR_D: .long 0xA55A0010 -IBNR_A: .long 0xFFFE080E -IBNR_D: .word 0x0000 -.align 2 -SDRAM_MODE: .long 0xFFFC5040 -REPEAT_D: .long 0x00000085 diff --git a/board/renesas/rsk7264/rsk7264.c b/board/renesas/rsk7264/rsk7264.c deleted file mode 100644 index 8f3b157bf7..0000000000 --- a/board/renesas/rsk7264/rsk7264.c +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 Renesas Electronics Europe Ltd. - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * Based on u-boot/board/rsk7264/rsk7203.c - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -int checkboard(void) -{ - puts("BOARD: Renesas Technology RSK7264\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -/* - * The RSK board has the SMSC89218 wired up 'incorrectly'. - * Byte-swapping is necessary, and so poor performance is inevitable. - * This problem cannot evade by the swap function of CHIP, this can - * evade by software Byte-swapping. - * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push - * functions necessary to solve this problem. - */ -u32 pkt_data_pull(struct eth_device *dev, u32 addr) -{ - volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); - return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ - | swab16(*(addr_16 + 1)); -} - -void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) -{ - addr += dev->iobase; - *(volatile u16 *)(addr + 2) = swab16((u16)val); - *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/renesas/rsk7269/Kconfig b/board/renesas/rsk7269/Kconfig deleted file mode 100644 index ab5cd0e38f..0000000000 --- a/board/renesas/rsk7269/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_RSK7269 - -config SYS_BOARD - default "rsk7269" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "rsk7269" - -endif diff --git a/board/renesas/rsk7269/MAINTAINERS b/board/renesas/rsk7269/MAINTAINERS deleted file mode 100644 index 698fbdb1df..0000000000 --- a/board/renesas/rsk7269/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -RSK7269 BOARD -#M: - -S: Maintained -F: board/renesas/rsk7269/ -F: include/configs/rsk7269.h -F: configs/rsk7269_defconfig diff --git a/board/renesas/rsk7269/Makefile b/board/renesas/rsk7269/Makefile deleted file mode 100644 index c4371f99fb..0000000000 --- a/board/renesas/rsk7269/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2012 Renesas Electronics Europe Ltd. -# Copyright (C) 2012 Phil Edworthy -# - -obj-y := rsk7269.o -extra-y += lowlevel_init.o diff --git a/board/renesas/rsk7269/lowlevel_init.S b/board/renesas/rsk7269/lowlevel_init.S deleted file mode 100644 index b7ce60b46d..0000000000 --- a/board/renesas/rsk7269/lowlevel_init.S +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Renesas Electronics Europe Ltd. - * Copyright (C) 2012 Phil Edworthy - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * Based on board/renesas/rsk7264/lowlevel_init.S - */ -#include <config.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* Flush and enable caches (data cache in write-through mode) */ - write32 CCR1_A ,CCR1_D - - /* Disable WDT */ - write16 WTCSR_A, WTCSR_D - write16 WTCNT_A, WTCNT_D - - /* Disable Register Bank interrupts */ - write16 IBNR_A, IBNR_D - - /* Set clocks based on 13.225MHz xtal */ - write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */ - - /* Enable all peripherals */ - write8 STBCR3_A, STBCR3_D - write8 STBCR4_A, STBCR4_D - write8 STBCR5_A, STBCR5_D - write8 STBCR6_A, STBCR6_D - write8 STBCR7_A, STBCR7_D - write8 STBCR8_A, STBCR8_D - write8 STBCR9_A, STBCR9_D - write8 STBCR10_A, STBCR10_D - - /* SCIF7 and IIC2 */ - write16 PJCR3_A, PJCR3_D /* TXD7 */ - write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */ - - /* Configure bus (CS0) */ - write16 PFCR3_A, PFCR3_D /* A24 */ - write16 PFCR2_A, PFCR2_D /* A23 and CS1# */ - write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */ - write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */ - write32 CS0WCR_A, CS0WCR_D - write32 CS0BCR_A, CS0BCR_D - - /* Configure SDRAM (CS3) */ - write16 PCCR2_A, PCCR2_D /* CS3# */ - write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */ - write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */ - write32 CS3BCR_A, CS3BCR_D - write32 CS3WCR_A, CS3WCR_D - write32 SDCR_A, SDCR_D - write32 RTCOR_A, RTCOR_D - write32 RTCSR_A, RTCSR_D - - /* Configure ethernet (CS1) */ - write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */ - write16 PHCR0_A, PHCR0_D - write16 PFCR2_A, PFCR2_D /* CS1# */ - write32 CS1BCR_A, CS1BCR_D /* Big endian */ - write32 CS1WCR_A, CS1WCR_D /* 1 cycle */ - write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */ - write16 PJIOR1_A, PJIOR1_D - - /* wait 200us */ - mov.l REPEAT_D, r3 - mov #0, r2 -repeat0: - add #1, r2 - cmp/hs r3, r2 - bf repeat0 - nop - - mov.l SDRAM_MODE, r1 - mov #0, r0 - mov.l r0, @r1 - - nop - rts - - .align 4 - -CCR1_A: .long CCR1 -CCR1_D: .long 0x0000090B - -STBCR3_A: .long 0xFFFE0408 -STBCR4_A: .long 0xFFFE040C -STBCR5_A: .long 0xFFFE0410 -STBCR6_A: .long 0xFFFE0414 -STBCR7_A: .long 0xFFFE0418 -STBCR8_A: .long 0xFFFE041C -STBCR9_A: .long 0xFFFE0440 -STBCR10_A: .long 0xFFFE0444 -STBCR3_D: .long 0x0000001A -STBCR4_D: .long 0x00000000 -STBCR5_D: .long 0x00000000 -STBCR6_D: .long 0x00000000 -STBCR7_D: .long 0x00000012 -STBCR8_D: .long 0x00000009 -STBCR9_D: .long 0x00000000 -STBCR10_D: .long 0x00000010 - -WTCSR_A: .long 0xFFFE0000 -WTCNT_A: .long 0xFFFE0002 -WTCSR_D: .word 0xA518 -WTCNT_D: .word 0x5A00 - -IBNR_A: .long 0xFFFE080E -IBNR_D: .word 0x0000 -.align 2 -FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .word 0x0015 -.align 2 - -PJCR3_A: .long 0xFFFE3908 -PJCR3_D: .word 0x5000 -.align 2 -PECR1_A: .long 0xFFFE388C -PECR1_D: .word 0x2011 -.align 2 - -PFCR3_A: .long 0xFFFE38A8 -PFCR2_A: .long 0xFFFE38AA -PBCR5_A: .long 0xFFFE3824 -PFCR3_D: .word 0x0010 -PFCR2_D: .word 0x0101 -PBCR5_D: .word 0x0111 -.align 2 -CS0WCR_A: .long 0xFFFC0028 -CS0WCR_D: .long 0x00000341 -CS0BCR_A: .long 0xFFFC0004 -CS0BCR_D: .long 0x00000400 - -PCCR2_A: .long 0xFFFE384A -PCCR1_A: .long 0xFFFE384C -PCCR0_A: .long 0xFFFE384E -PCCR2_D: .word 0x0001 -PCCR1_D: .word 0x1111 -PCCR0_D: .word 0x1111 -.align 2 -CS3BCR_A: .long 0xFFFC0010 -CS3BCR_D: .long 0x00004400 -CS3WCR_A: .long 0xFFFC0034 -CS3WCR_D: .long 0x00004912 -SDCR_A: .long 0xFFFC004C -SDCR_D: .long 0x00000811 -RTCOR_A: .long 0xFFFC0058 -RTCOR_D: .long 0xA55A0035 -RTCSR_A: .long 0xFFFC0050 -RTCSR_D: .long 0xA55A0010 -.align 2 -SDRAM_MODE: .long 0xFFFC5460 -REPEAT_D: .long 0x000033F1 - -PHCR1_A: .long 0xFFFE38EC -PHCR0_A: .long 0xFFFE38EE -PHCR1_D: .word 0x2222 -PHCR0_D: .word 0x2222 -.align 2 -CS1BCR_A: .long 0xFFFC0008 -CS1BCR_D: .long 0x00000400 -CS1WCR_A: .long 0xFFFC002C -CS1WCR_D: .long 0x00000080 -PJDR1_A: .long 0xFFFE3914 -PJDR1_D: .word 0x0000 -.align 2 -PJIOR1_A: .long 0xFFFE3910 -PJIOR1_D: .word 0x8000 -.align 2 diff --git a/board/renesas/rsk7269/rsk7269.c b/board/renesas/rsk7269/rsk7269.c deleted file mode 100644 index 223234eb24..0000000000 --- a/board/renesas/rsk7269/rsk7269.c +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Renesas Electronics Europe Ltd. - * Copyright (C) 2012 Phil Edworthy - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * Based on u-boot/board/rsk7264/rsk7264.c - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -int checkboard(void) -{ - puts("BOARD: Renesas RSK7269\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -/* - * The RSK board has the SMSC89218 wired up 'incorrectly'. - * Byte-swapping is necessary, and so poor performance is inevitable. - * This problem cannot evade by the swap function of CHIP, this can - * evade by software Byte-swapping. - * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push - * functions necessary to solve this problem. - */ -u32 pkt_data_pull(struct eth_device *dev, u32 addr) -{ - volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); - return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ - | swab16(*(addr_16 + 1)); -} - -void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) -{ - addr += dev->iobase; - *(volatile u16 *)(addr + 2) = swab16((u16)val); - *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 8f0247e046..1db08fce6a 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -69,17 +69,37 @@ int board_init(void) return 0; } +/* + * If the firmware passed a device tree use it for U-Boot DRAM setup. + */ +extern u64 rcar_atf_boot_args[]; + int dram_init(void) { - if (fdtdec_setup_mem_size_base() != 0) - return -EINVAL; + const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); + const void *blob; - return 0; + /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ + if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) + blob = atf_fdt_blob; + else + blob = gd->fdt_blob; + + return fdtdec_setup_mem_size_base_fdt(blob); } int dram_init_banksize(void) { - fdtdec_setup_memory_banksize(); + const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); + const void *blob; + + /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ + if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) + blob = atf_fdt_blob; + else + blob = gd->fdt_blob; + + fdtdec_setup_memory_banksize_fdt(blob); return 0; } diff --git a/board/renesas/sh7757lcr/README.sh7757lcr b/board/renesas/sh7757lcr/README.sh7757lcr index 3e9c1c1a1e..9453839d2c 100644 --- a/board/renesas/sh7757lcr/README.sh7757lcr +++ b/board/renesas/sh7757lcr/README.sh7757lcr @@ -20,7 +20,7 @@ configuration for This board: You can select the configuration as follows: - - make sh7785lcr_config + - make sh7757lcr_config This board specific command: diff --git a/board/renesas/sh7785lcr/Kconfig b/board/renesas/sh7785lcr/Kconfig deleted file mode 100644 index e204c76ef5..0000000000 --- a/board/renesas/sh7785lcr/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SH7785LCR - -config SYS_BOARD - default "sh7785lcr" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "sh7785lcr" - -endif diff --git a/board/renesas/sh7785lcr/MAINTAINERS b/board/renesas/sh7785lcr/MAINTAINERS deleted file mode 100644 index 17578e036a..0000000000 --- a/board/renesas/sh7785lcr/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -SH7785LCR BOARD -#M: - -S: Maintained -F: board/renesas/sh7785lcr/ -F: include/configs/sh7785lcr.h -F: configs/sh7785lcr_defconfig -F: configs/sh7785lcr_32bit_defconfig diff --git a/board/renesas/sh7785lcr/Makefile b/board/renesas/sh7785lcr/Makefile deleted file mode 100644 index ba00657d7e..0000000000 --- a/board/renesas/sh7785lcr/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> -# - -obj-y := sh7785lcr.o selfcheck.o rtl8169_mac.o -extra-y += lowlevel_init.o diff --git a/board/renesas/sh7785lcr/README.sh7785lcr b/board/renesas/sh7785lcr/README.sh7785lcr deleted file mode 100644 index 56455fc162..0000000000 --- a/board/renesas/sh7785lcr/README.sh7785lcr +++ /dev/null @@ -1,123 +0,0 @@ -======================================== -Renesas Technology R0P7785LC0011RL board -======================================== - -This board specification: -========================= - -The R0P7785LC0011RL(board config name:sh7785lcr) has the following device: - - - SH7785 (SH-4A) - - DDR2-SDRAM 512MB - - NOR Flash 64MB - - 2D Graphic controller - - SATA controller - - Ethernet controller - - USB host/peripheral controller - - SD controller - - I2C controller - - RTC - -This board has 2 physical memory maps. It can be changed with DIP switch(S2-5). - - phys address | S2-5 = OFF | S2-5 = ON - -------------------------------+---------------+--------------- - 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash - 0x04000000 - 0x05ffffff(CS1) | PLD | PLD - 0x06000000 - 0x07ffffff(CS1) | reserved | I2C - 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM - 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM - 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 - 0x14000000 - 0x17ffffff(CS5) | I2C | USB - 0x18000000 - 0x1bffffff(CS6) | reserved | SD - 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) - - -configuration for This board: -============================= - -You can choose configuration as follows: - - - make sh7785lcr_config - - make sh7785lcr_32bit_config - -When you use "make sh7785lcr_config", there is build U-Boot for 29-bit -address mode. This mode can use 128MB DDR-SDRAM. - -When you use "make sh7785lcr_32bit_config", there is build U-Boot for 32-bit -extended address mode. This mode can use 384MB DDR-SDRAM. And if you run -"pmb" command, this mode can use 512MB DDR-SDRAM. - - * 32-bit extended address mode PMB mapping * - a) on start-up - virt | phys | size | device - -------------+---------------+---------------+--------------- - 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable) - 0xa0000000 | 0x00000000 | 64MB | NOR Flash - 0xa4000000 | 0x04000000 | 16MB | PLD - 0xa6000000 | 0x08000000 | 16MB | USB - 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable) - - b) after "pmb" command - virt | phys | size | device - -------------+---------------+---------------+--------------- - 0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable) - 0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable) - - -This board specific command: -============================ - -This board has the following its specific command: - - - hwtest - - printmac - - setmac - - pmb (sh7785lcr_32bit_config only) - - -1. hwtest - -This is self-check command. This command has the following options: - - - all : test all hardware - - pld : output PLD version - - led : turn on LEDs - - dipsw : test DIP switch - - sm107 : output SM107 version - - net : check RTL8110 ID - - sata : check SiI3512 ID - - net : output PCI slot device ID - -i.e) -=> hwtest led -turn on LEDs 3, 5, 7, 9 -turn on LEDs 4, 6, 8, 10 - -=> hwtest net -Ethernet OK - - -2. printmac - -This command outputs MAC address of this board. - -i.e) -=> printmac -MAC = 00:00:87:**:**:** - - -3. setmac - -This command writes MAC address of this board. - -i.e) -=> setmac 00:00:87:**:**:** - - -4. pmb - -This command change PMB for DDR-SDRAM all mapping. However you cannot use -NOR Flash and USB Host on U-Boot when you run this command. -i.e) -=> pmb diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S deleted file mode 100644 index 658ebbaaeb..0000000000 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ /dev/null @@ -1,361 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - */ -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> - -#include <asm/processor.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - wait_timer WAIT_200US - wait_timer WAIT_200US - - /*------- LBSC -------*/ - write32 MMSELR_A, MMSELR_D - - /*------- DBSC2 -------*/ - write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D - write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D - write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D - write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D - write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1 - write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2 - wait_timer WAIT_200US - - write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H - wait_timer WAIT_200US - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1 - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF - write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2 - wait_timer WAIT_200US - - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2 - write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1 - - write32 DBSC2_DBEN_A, DBSC2_DBEN_D - write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D - write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D - write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D - wait_timer WAIT_200US - - /*------- GPIO -------*/ - write16 PACR_A, PXCR_D - write16 PBCR_A, PXCR_D - write16 PCCR_A, PXCR_D - write16 PDCR_A, PXCR_D - write16 PECR_A, PXCR_D - write16 PFCR_A, PXCR_D - write16 PGCR_A, PXCR_D - write16 PHCR_A, PHCR_D - write16 PJCR_A, PJCR_D - write16 PKCR_A, PKCR_D - write16 PLCR_A, PXCR_D - write16 PMCR_A, PMCR_D - write16 PNCR_A, PNCR_D - write16 PPCR_A, PXCR_D - write16 PQCR_A, PXCR_D - write16 PRCR_A, PXCR_D - - write8 PEPUPR_A, PEPUPR_D - write8 PHPUPR_A, PHPUPR_D - write8 PJPUPR_A, PJPUPR_D - write8 PKPUPR_A, PKPUPR_D - write8 PLPUPR_A, PLPUPR_D - write8 PMPUPR_A, PMPUPR_D - write8 PNPUPR_A, PNPUPR_D - write16 PPUPR1_A, PPUPR1_D - write16 PPUPR2_A, PPUPR2_D - write16 P1MSELR_A, P1MSELR_D - write16 P2MSELR_A, P2MSELR_D - - /*------- LBSC -------*/ - write32 BCR_A, BCR_D - write32 CS0BCR_A, CS0BCR_D - write32 CS0WCR_A, CS0WCR_D - write32 CS1BCR_A, CS1BCR_D - write32 CS1WCR_A, CS1WCR_D - write32 CS4BCR_A, CS4BCR_D - write32 CS4WCR_A, CS4WCR_D - - mov.l PASCR_A, r0 - mov.l @r0, r2 - mov.l PASCR_32BIT_MODE, r1 - tst r1, r2 - bt lbsc_29bit - - write32 CS2BCR_A, CS_USB_BCR_D - write32 CS2WCR_A, CS_USB_WCR_D - write32 CS3BCR_A, CS_SD_BCR_D - write32 CS3WCR_A, CS_SD_WCR_D - write32 CS5BCR_A, CS_I2C_BCR_D - write32 CS5WCR_A, CS_I2C_WCR_D - write32 CS6BCR_A, CS0BCR_D - write32 CS6WCR_A, CS0WCR_D - bra lbsc_end - nop - -lbsc_29bit: - write32 CS5BCR_A, CS_USB_BCR_D - write32 CS5WCR_A, CS_USB_WCR_D - write32 CS6BCR_A, CS_SD_BCR_D - write32 CS6WCR_A, CS_SD_WCR_D - -lbsc_end: -#if defined(CONFIG_SH_32BIT) - /*------- set PMB -------*/ - write32 PASCR_A, PASCR_29BIT_D - write32 MMUCR_A, MMUCR_D - - /***************************************************************** - * ent virt phys v sz c wt - * 0 0xa0000000 0x00000000 1 64M 0 0 - * 1 0xa4000000 0x04000000 1 16M 0 0 - * 2 0xa6000000 0x08000000 1 16M 0 0 - * 9 0x88000000 0x48000000 1 128M 1 1 - * 10 0x90000000 0x50000000 1 128M 1 1 - * 11 0x98000000 0x58000000 1 128M 1 1 - * 13 0xa8000000 0x48000000 1 128M 0 0 - * 14 0xb0000000 0x50000000 1 128M 0 0 - * 15 0xb8000000 0x58000000 1 128M 0 0 - */ - write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D - write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D - write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D - write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D - write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D - write32 PMB_DATA_USB_A, PMB_DATA_USB_D - write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D - write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D - write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D - write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D - write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D - write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D - write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D - write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D - write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D - write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D - write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D - write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D - - write32 PASCR_A, PASCR_INIT - mov.l DUMMY_ADDR, r0 - icbi @r0 -#endif - - write32 CCR_A, CCR_D - - rts - nop - - .align 4 - -/*------- GPIO -------*/ -/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */ -PXCR_D: .word 0x0000 - -PHCR_D: .word 0x00c0 -PJCR_D: .word 0xc3fc -PKCR_D: .word 0x03ff -PMCR_D: .word 0xffff -PNCR_D: .word 0xf0c3 - -PEPUPR_D: .long 0xff -PHPUPR_D: .long 0x00 -PJPUPR_D: .long 0x00 -PKPUPR_D: .long 0x00 -PLPUPR_D: .long 0x00 -PMPUPR_D: .long 0xfc -PNPUPR_D: .long 0x00 -PPUPR1_D: .word 0xffbf -PPUPR2_D: .word 0xff00 -P1MSELR_D: .word 0x3780 -P2MSELR_D: .word 0x0000 - -#define GPIO_BASE 0xffe70000 -PACR_A: .long GPIO_BASE + 0x00 -PBCR_A: .long GPIO_BASE + 0x02 -PCCR_A: .long GPIO_BASE + 0x04 -PDCR_A: .long GPIO_BASE + 0x06 -PECR_A: .long GPIO_BASE + 0x08 -PFCR_A: .long GPIO_BASE + 0x0a -PGCR_A: .long GPIO_BASE + 0x0c -PHCR_A: .long GPIO_BASE + 0x0e -PJCR_A: .long GPIO_BASE + 0x10 -PKCR_A: .long GPIO_BASE + 0x12 -PLCR_A: .long GPIO_BASE + 0x14 -PMCR_A: .long GPIO_BASE + 0x16 -PNCR_A: .long GPIO_BASE + 0x18 -PPCR_A: .long GPIO_BASE + 0x1a -PQCR_A: .long GPIO_BASE + 0x1c -PRCR_A: .long GPIO_BASE + 0x1e -PEPUPR_A: .long GPIO_BASE + 0x48 -PHPUPR_A: .long GPIO_BASE + 0x4e -PJPUPR_A: .long GPIO_BASE + 0x50 -PKPUPR_A: .long GPIO_BASE + 0x52 -PLPUPR_A: .long GPIO_BASE + 0x54 -PMPUPR_A: .long GPIO_BASE + 0x56 -PNPUPR_A: .long GPIO_BASE + 0x58 -PPUPR1_A: .long GPIO_BASE + 0x60 -PPUPR2_A: .long GPIO_BASE + 0x62 -P1MSELR_A: .long GPIO_BASE + 0x80 -P2MSELR_A: .long GPIO_BASE + 0x82 - -MMSELR_A: .long 0xfc400020 -#if defined(CONFIG_SH_32BIT) -MMSELR_D: .long 0xa5a50005 -#else -MMSELR_D: .long 0xa5a50002 -#endif - -/*------- DBSC2 -------*/ -#define DBSC2_BASE 0xfe800000 -DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c -DBSC2_DBEN_A: .long DBSC2_BASE + 0x10 -DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14 -DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20 -DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30 -DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34 -DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38 -DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40 -DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44 -DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48 -DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c -DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50 -DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54 -DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60 -DDR_DUMMY_ACCESS_A: .long 0x40000000 - -DBSC2_DBCONF_D: .long 0x00630002 -DBSC2_DBTR0_D: .long 0x050b1f04 -DBSC2_DBTR1_D: .long 0x00040204 -DBSC2_DBTR2_D: .long 0x02100308 -DBSC2_DBFREQ_D1: .long 0x00000000 -DBSC2_DBFREQ_D2: .long 0x00000100 -DBSC2_DBDICODTOCD_D:.long 0x000f0907 - -DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003 -DBSC2_DBCMDCNT_D_PALL: .long 0x00000002 -DBSC2_DBCMDCNT_D_REF: .long 0x00000004 - -DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000 -DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000 -DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006 -DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386 -DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952 -DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852 - -DBSC2_DBEN_D: .long 0x00000001 - -DBSC2_DBPDCNT0_D3: .long 0x00000080 -DBSC2_DBRFCNT1_D: .long 0x00000926 -DBSC2_DBRFCNT2_D: .long 0x00fe00fe -DBSC2_DBRFCNT0_D: .long 0x00010000 - -WAIT_200US: .long 33333 - -/*------- LBSC -------*/ -PASCR_A: .long 0xff000070 -PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */ - -BCR_A: .long BCR -CS0BCR_A: .long CS0BCR -CS0WCR_A: .long CS0WCR -CS1BCR_A: .long CS1BCR -CS1WCR_A: .long CS1WCR -CS2BCR_A: .long CS2BCR -CS2WCR_A: .long CS2WCR -CS3BCR_A: .long CS3BCR -CS3WCR_A: .long CS3WCR -CS4BCR_A: .long CS4BCR -CS4WCR_A: .long CS4WCR -CS5BCR_A: .long CS5BCR -CS5WCR_A: .long CS5WCR -CS6BCR_A: .long CS6BCR -CS6WCR_A: .long CS6WCR - -BCR_D: .long 0x80000003 -CS0BCR_D: .long 0x22222340 -CS0WCR_D: .long 0x00111118 -CS1BCR_D: .long 0x11111100 -CS1WCR_D: .long 0x33333303 -CS4BCR_D: .long 0x11111300 -CS4WCR_D: .long 0x00101012 - -/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */ -CS_USB_BCR_D: .long 0x11111200 -CS_USB_WCR_D: .long 0x00020005 - -/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ -CS_SD_BCR_D: .long 0x00000300 -CS_SD_WCR_D: .long 0x00030108 - -/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */ -CS_I2C_BCR_D: .long 0x11111100 -CS_I2C_WCR_D: .long 0x00000003 - -#if defined(CONFIG_SH_32BIT) -/*------- set PMB -------*/ -PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0) -PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1) -PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2) -PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9) -PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10) -PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11) -PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13) -PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14) -PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15) - -PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0) -PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4) -PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6) -PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) -PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90) -PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98) -PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) -PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0) -PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8) - -PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0) -PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1) -PMB_DATA_USB_A: .long PMB_DATA_BASE(2) -PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9) -PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10) -PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11) -PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13) -PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14) -PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15) - -/* ppn ub v s1 s0 c wt */ -PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1) -PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1) -PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1) -PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1) -PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) -PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1) -PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1) - -DUMMY_ADDR: .long 0xa0000000 -PASCR_29BIT_D: .long 0x00000000 -PASCR_INIT: .long 0x80000080 /* check booting mode */ -MMUCR_A: .long 0xff000010 -MMUCR_D: .long 0x00000004 /* clear ITLB */ -#endif /* CONFIG_SH_32BIT */ - -CCR_A: .long 0xff00001c -CCR_D: .long 0x0000090b diff --git a/board/renesas/sh7785lcr/rtl8169.h b/board/renesas/sh7785lcr/rtl8169.h deleted file mode 100644 index 51240e6d62..0000000000 --- a/board/renesas/sh7785lcr/rtl8169.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - */ - -#define PCIREG_8(_adr) (*(volatile unsigned char *)(_adr)) -#define PCIREG_32(_adr) (*(volatile unsigned long *)(_adr)) -#define PCI_PAR PCIREG_32(0xfe0401c0) -#define PCI_PDR PCIREG_32(0xfe040220) -#define PCI_CR PCIREG_32(0xfe040100) -#define PCI_CONF1 PCIREG_32(0xfe040004) - -#define HIGH 1 -#define LOW 0 - -#define PCI_PROG 0x80 -#define PCI_EEP_ADDRESS (unsigned short)0x0007 -#define PCI_MAC_ADDRESS_SIZE 3 - -#define TIME1 100 -#define TIME2 20000 - -#define BIT_DUMMY 0 -#define MAC_EEP_READ 1 -#define MAC_EEP_WRITE 2 -#define MAC_EEP_ERACE 3 -#define MAC_EEP_EWEN 4 -#define MAC_EEP_EWDS 5 - -/* RTL8169 */ -const unsigned short EEPROM_W_Data_8169_A[] = { - 0x8129, 0x10ec, 0x8169, 0x1154, 0x032b, - 0x4020, 0xa101 -}; -const unsigned short EEPROM_W_Data_8169_B[] = { - 0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 -}; diff --git a/board/renesas/sh7785lcr/rtl8169_mac.c b/board/renesas/sh7785lcr/rtl8169_mac.c deleted file mode 100644 index 68c324113f..0000000000 --- a/board/renesas/sh7785lcr/rtl8169_mac.c +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - */ - -#include <common.h> -#include "rtl8169.h" - -static unsigned char *PCI_MEMR; - -static void mac_delay(unsigned int cnt) -{ - udelay(cnt); -} - -static void mac_pci_setup(void) -{ - unsigned long pci_data; - - PCI_PAR = 0x00000010; - PCI_PDR = 0x00001000; - PCI_PAR = 0x00000004; - pci_data = PCI_PDR; - PCI_PDR = pci_data | 0x00000007; - PCI_PAR = 0x00000010; - - PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0); -} - -static void EECS(int level) -{ - unsigned char data = *PCI_MEMR; - - if (level) - *PCI_MEMR = data | 0x08; - else - *PCI_MEMR = data & 0xf7; -} - -static void EECLK(int level) -{ - unsigned char data = *PCI_MEMR; - - if (level) - *PCI_MEMR = data | 0x04; - else - *PCI_MEMR = data & 0xfb; -} - -static void EEDI(int level) -{ - unsigned char data = *PCI_MEMR; - - if (level) - *PCI_MEMR = data | 0x02; - else - *PCI_MEMR = data & 0xfd; -} - -static inline void sh7785lcr_bitset(unsigned short bit) -{ - if (bit) - EEDI(HIGH); - else - EEDI(LOW); - - EECLK(LOW); - mac_delay(TIME1); - EECLK(HIGH); - mac_delay(TIME1); - EEDI(LOW); -} - -static inline unsigned char sh7785lcr_bitget(void) -{ - unsigned char bit; - - EECLK(LOW); - mac_delay(TIME1); - bit = *PCI_MEMR & 0x01; - EECLK(HIGH); - mac_delay(TIME1); - - return bit; -} - -static inline void sh7785lcr_setcmd(unsigned char command) -{ - sh7785lcr_bitset(BIT_DUMMY); - switch (command) { - case MAC_EEP_READ: - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - break; - case MAC_EEP_WRITE: - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - sh7785lcr_bitset(1); - break; - case MAC_EEP_ERACE: - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - break; - case MAC_EEP_EWEN: - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - sh7785lcr_bitset(0); - break; - case MAC_EEP_EWDS: - sh7785lcr_bitset(1); - sh7785lcr_bitset(0); - sh7785lcr_bitset(0); - break; - default: - break; - } -} - -static inline unsigned short sh7785lcr_getdt(void) -{ - unsigned short data = 0; - int i; - - sh7785lcr_bitget(); /* DUMMY */ - for (i = 0 ; i < 16 ; i++) { - data <<= 1; - data |= sh7785lcr_bitget(); - } - return data; -} - -static inline void sh7785lcr_setadd(unsigned short address) -{ - sh7785lcr_bitset(address & 0x0020); /* A5 */ - sh7785lcr_bitset(address & 0x0010); /* A4 */ - sh7785lcr_bitset(address & 0x0008); /* A3 */ - sh7785lcr_bitset(address & 0x0004); /* A2 */ - sh7785lcr_bitset(address & 0x0002); /* A1 */ - sh7785lcr_bitset(address & 0x0001); /* A0 */ -} - -static inline void sh7785lcr_setdata(unsigned short data) -{ - sh7785lcr_bitset(data & 0x8000); - sh7785lcr_bitset(data & 0x4000); - sh7785lcr_bitset(data & 0x2000); - sh7785lcr_bitset(data & 0x1000); - sh7785lcr_bitset(data & 0x0800); - sh7785lcr_bitset(data & 0x0400); - sh7785lcr_bitset(data & 0x0200); - sh7785lcr_bitset(data & 0x0100); - sh7785lcr_bitset(data & 0x0080); - sh7785lcr_bitset(data & 0x0040); - sh7785lcr_bitset(data & 0x0020); - sh7785lcr_bitset(data & 0x0010); - sh7785lcr_bitset(data & 0x0008); - sh7785lcr_bitset(data & 0x0004); - sh7785lcr_bitset(data & 0x0002); - sh7785lcr_bitset(data & 0x0001); -} - -static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address, - unsigned int count) -{ - unsigned int i; - - for (i = 0; i < count; i++) { - EECS(HIGH); - EEDI(LOW); - mac_delay(TIME1); - - sh7785lcr_setcmd(MAC_EEP_WRITE); - sh7785lcr_setadd(address++); - sh7785lcr_setdata(*(data + i)); - - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - mac_delay(TIME2); - } -} - -static void sh7785lcr_macerase(void) -{ - unsigned int i; - unsigned short pci_address = 7; - - for (i = 0; i < 3; i++) { - EECS(HIGH); - EEDI(LOW); - mac_delay(TIME1); - sh7785lcr_setcmd(MAC_EEP_ERACE); - sh7785lcr_setadd(pci_address++); - mac_delay(TIME1); - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - } - - mac_delay(TIME2); - - printf("\n\nErace End\n"); - for (i = 0; i < 10; i++) - mac_delay(TIME2); -} - -static void sh7785lcr_macwrite(unsigned short *data) -{ - sh7785lcr_macerase(); - - sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7); - sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); - sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54); -} - -void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count) -{ - unsigned int i; - unsigned short wk; - - for (i = 0 ; i < count; i++) { - EECS(HIGH); - EEDI(LOW); - mac_delay(TIME1); - sh7785lcr_setcmd(MAC_EEP_READ); - sh7785lcr_setadd(address++); - wk = sh7785lcr_getdt(); - - *buf++ = (unsigned char)(wk & 0xff); - *buf++ = (unsigned char)((wk >> 8) & 0xff); - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - } -} - -static void sh7785lcr_macadrd(unsigned char *buf) -{ - *PCI_MEMR = PCI_PROG; - - sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE); -} - -static void sh7785lcr_eepewen(void) -{ - *PCI_MEMR = PCI_PROG; - mac_delay(TIME1); - EECS(LOW); - EECLK(LOW); - EEDI(LOW); - EECS(HIGH); - mac_delay(TIME1); - - sh7785lcr_setcmd(MAC_EEP_EWEN); - sh7785lcr_bitset(1); - sh7785lcr_bitset(1); - sh7785lcr_bitset(BIT_DUMMY); - sh7785lcr_bitset(BIT_DUMMY); - sh7785lcr_bitset(BIT_DUMMY); - sh7785lcr_bitset(BIT_DUMMY); - - EECLK(LOW); - EEDI(LOW); - EECS(LOW); - mac_delay(TIME1); -} - -void mac_write(unsigned short *data) -{ - mac_pci_setup(); - sh7785lcr_eepewen(); - sh7785lcr_macwrite(data); -} - -void mac_read(void) -{ - unsigned char data[6]; - - mac_pci_setup(); - sh7785lcr_macadrd(data); - printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n", - data[0], data[1], data[2], data[3], data[4], data[5]); -} - -int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int i; - unsigned char mac[6]; - char *s, *e; - - if (argc != 2) - return cmd_usage(cmdtp); - - s = argv[1]; - - for (i = 0; i < 6; i++) { - mac[i] = s ? simple_strtoul(s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; - } - mac_write((unsigned short *)mac); - - return 0; -} - -U_BOOT_CMD( - setmac, 2, 1, do_set_mac, - "write MAC address for RTL8110SCL", - "\n" - "setmac <mac address> - write MAC address for RTL8110SCL" -); - -int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc != 1) - return cmd_usage(cmdtp); - - mac_read(); - - return 0; -} - -U_BOOT_CMD( - printmac, 1, 1, do_print_mac, - "print MAC address for RTL8110", - "\n" - " - print MAC address for RTL8110" -); diff --git a/board/renesas/sh7785lcr/selfcheck.c b/board/renesas/sh7785lcr/selfcheck.c deleted file mode 100644 index c5f469342d..0000000000 --- a/board/renesas/sh7785lcr/selfcheck.c +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - */ - -#include <common.h> -#include <console.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/pci.h> - -#if defined(CONFIG_CPU_32BIT) -#define NOCACHE_OFFSET 0x00000000 -#else -#define NOCACHE_OFFSET 0xa0000000 -#endif -#define PLD_LEDCR (0x04000008 + NOCACHE_OFFSET) -#define PLD_SWSR (0x0400000a + NOCACHE_OFFSET) -#define PLD_VERSR (0x0400000c + NOCACHE_OFFSET) - -#define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET) - -static void test_pld(void) -{ - printf("PLD version = %04x\n", readb(PLD_VERSR)); -} - -static void test_sm107(void) -{ - printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID)); -} - -static void test_led(void) -{ - printf("turn on LEDs 3, 5, 7, 9\n"); - writeb(0x55, PLD_LEDCR); - mdelay(2000); - printf("turn on LEDs 4, 6, 8, 10\n"); - writeb(0xaa, PLD_LEDCR); - mdelay(2000); - writeb(0x00, PLD_LEDCR); -} - -static void test_dipsw(void) -{ - printf("Please DIPSW set = B'0101\n"); - while (readb(PLD_SWSR) != 0x05) { - if (ctrlc()) - return; - } - printf("Please DIPSW set = B'1010\n"); - while (readb(PLD_SWSR) != 0x0A) { - if (ctrlc()) - return; - } - printf("DIPSW OK\n"); -} - -static void test_net(void) -{ - unsigned long data; - - writel(0x80000000, 0xfe0401c0); - data = readl(0xfe040220); - if (data == 0x816910ec) - printf("Ethernet OK\n"); - else - printf("Ethernet NG, data = %08x\n", (unsigned int)data); -} - -static void test_sata(void) -{ - unsigned long data; - - writel(0x80000800, 0xfe0401c0); - data = readl(0xfe040220); - if (data == 0x35121095) - printf("SATA OK\n"); - else - printf("SATA NG, data = %08x\n", (unsigned int)data); -} - -static void test_pci(void) -{ - writel(0x80001800, 0xfe0401c0); - printf("PCI CN1 ID = %08x\n", readl(0xfe040220)); - - writel(0x80001000, 0xfe0401c0); - printf("PCI CN2 ID = %08x\n", readl(0xfe040220)); -} - -int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *cmd; - - if (argc != 2) - return cmd_usage(cmdtp); - - cmd = argv[1]; - switch (cmd[0]) { - case 'a': /* all */ - test_pld(); - test_led(); - test_dipsw(); - test_sm107(); - test_net(); - test_sata(); - test_pci(); - break; - case 'p': /* pld or pci */ - if (cmd[1] == 'l') - test_pld(); - else - test_pci(); - break; - case 'l': /* led */ - test_led(); - break; - case 'd': /* dipsw */ - test_dipsw(); - break; - case 's': /* sm107 or sata */ - if (cmd[1] == 'm') - test_sm107(); - else - test_sata(); - break; - case 'n': /* net */ - test_net(); - break; - default: - return cmd_usage(cmdtp); - } - - return 0; -} - -U_BOOT_CMD( - hwtest, 2, 1, do_hw_test, - "hardware test for R0P7785LC0011RL board", - "\n" - "hwtest all - test all hardware\n" - "hwtest pld - output PLD version\n" - "hwtest led - turn on LEDs\n" - "hwtest dipsw - test DIP switch\n" - "hwtest sm107 - output SM107 version\n" - "hwtest net - check RTL8110 ID\n" - "hwtest sata - check SiI3512 ID\n" - "hwtest pci - output PCI slot device ID" -); diff --git a/board/renesas/sh7785lcr/sh7785lcr.c b/board/renesas/sh7785lcr/sh7785lcr.c deleted file mode 100644 index 1874334814..0000000000 --- a/board/renesas/sh7785lcr/sh7785lcr.c +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/pci.h> -#include <netdev.h> - -int checkboard(void) -{ - puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -static struct pci_controller hose; -void pci_init_board(void) -{ - pci_sh7780_init(&hose); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} - -#if defined(CONFIG_SH_32BIT) -int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - /* clear ITLB */ - writel(0x00000004, 0xff000010); - - /* delete PMB for peripheral */ - writel(0, PMB_ADDR_BASE(0)); - writel(0, PMB_DATA_BASE(0)); - writel(0, PMB_ADDR_BASE(1)); - writel(0, PMB_DATA_BASE(1)); - writel(0, PMB_ADDR_BASE(2)); - writel(0, PMB_DATA_BASE(2)); - - /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ - writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8)); - writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8)); - writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12)); - writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12)); - - return 0; -} - -U_BOOT_CMD( - pmb, 1, 1, do_pmb, - "pmb - PMB setting\n", - "\n" - " - PMB setting for all SDRAM mapping" -); -#endif diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index 9785107e56..faf19c3580 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -68,17 +68,37 @@ int board_init(void) return 0; } +/* + * If the firmware passed a device tree use it for U-Boot DRAM setup. + */ +extern u64 rcar_atf_boot_args[]; + int dram_init(void) { - if (fdtdec_setup_mem_size_base() != 0) - return -EINVAL; + const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); + const void *blob; - return 0; + /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ + if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) + blob = atf_fdt_blob; + else + blob = gd->fdt_blob; + + return fdtdec_setup_mem_size_base_fdt(blob); } int dram_init_banksize(void) { - fdtdec_setup_memory_banksize(); + const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]); + const void *blob; + + /* Check if ATF passed us DTB. If not, fall back to builtin DTB. */ + if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) + blob = atf_fdt_blob; + else + blob = gd->fdt_blob; + + fdtdec_setup_memory_banksize_fdt(blob); return 0; } diff --git a/board/rockchip/evb_rk3036/evb_rk3036.c b/board/rockchip/evb_rk3036/evb_rk3036.c index d5acc4fe27..8c606463e4 100644 --- a/board/rockchip/evb_rk3036/evb_rk3036.c +++ b/board/rockchip/evb_rk3036/evb_rk3036.c @@ -6,8 +6,8 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/uart.h> -#include <asm/arch/sdram_rk3036.h> +#include <asm/arch-rockchip/uart.h> +#include <asm/arch-rockchip/sdram_rk3036.h> void get_ddr_config(struct rk3036_ddr_config *config) { diff --git a/board/rockchip/evb_rk3229/README b/board/rockchip/evb_rk3229/README new file mode 100644 index 0000000000..93328c75b2 --- /dev/null +++ b/board/rockchip/evb_rk3229/README @@ -0,0 +1,72 @@ +Get the Source and prebuild binary +================================== + + > mkdir ~/evb_rk3229 + > cd ~/evb_rk3229 + > git clone git://git.denx.de/u-boot.git + > git clone https://github.com/OP-TEE/optee_os.git + > git clone https://github.com/rockchip-linux/rkbin.git + > git clone https://github.com/rockchip-linux/rkdeveloptool.git + +Compile the OP-TEE +=============== + + > cd optee_os + > make clean + > make CROSS_COMPILE_ta_arm32=arm-none-eabi- PLATFORM=rockchip-rk322x + Get tee.bin in this step, copy it to U-Boot root dir: + > cp out/arm-plat-rockchip/core/tee-pager.bin ../u-boot/tee.bin + +Compile the U-Boot +================== + + > cd ../u-boot + > export CROSS_COMPILE=arm-linux-gnueabihf- + > export ARCH=arm + > make evb-rk3229_defconfig + > make + > make u-boot.itb + + Get tpl/u-boot-tpl.bin, spl/u-boot-spl.bin and u-boot.itb in this step. + +Compile the rkdeveloptool +======================= + Follow instructions in latest README + > cd ../rkflashtool + > autoreconf -i + > ./configure + > make + > sudo make install + + Get rkdeveloptool in you Host in this step. + +Both origin binaries and Tool are ready now, choose either option 1 or +option 2 to deploy U-Boot. + +Package the image +================= + + > cd ../u-boot + > tools/mkimage -n rk322x -T rksd -d tpl/u-boot-spl.bin idbloader.img + > cat spl/u-boot-spl.bin >> idbloader.img + + Get idbloader.img in this step. + +Flash the image to eMMC +======================= +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + > cd .. + > rkdeveloptool db rkbin/rk32/rk322x_loader_v1.04.232.bin + > rkdeveloptool wl 64 u-boot/idbloader.img + > rkdeveloptool wl 0x4000 u-boot/u-boot.itb + > rkdeveloptool rd + +Flash the image to SD card +========================== + > dd if=u-boot/idbloader.img of=/dev/sdb seek=64 + > dd if=u-boot/u-boot.itb of=/dev/sdb seek=16384 + +You should be able to get U-Boot log message with OP-TEE boot info. + +For more detail, please reference to: +http://opensource.rock-chips.com/wiki_Boot_option diff --git a/board/rockchip/evb_rk3229/evb_rk3229.c b/board/rockchip/evb_rk3229/evb_rk3229.c index 63c84fccfe..c64c62f7b0 100644 --- a/board/rockchip/evb_rk3229/evb_rk3229.c +++ b/board/rockchip/evb_rk3229/evb_rk3229.c @@ -6,5 +6,5 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/uart.h> +#include <asm/arch-rockchip/uart.h> diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index caad30641e..f55c92f80c 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -5,3 +5,22 @@ F: board/rockchip/evb_rk3399 F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig F: configs/firefly-rk3399_defconfig + +NANOPC-T4 +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/nanopc-t4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi + +NANOPI-M4 +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/nanopi-m4-rk3399_defconfig +F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi + +ORANGEPI-RK3399 +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/orangepi-rk3399_defconfig +F: arch/arm/dts/rk3399-u-boot.dtsi +F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index 3e9e83f3ad..bf2ad98c47 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -7,7 +7,7 @@ #include <dm.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> #include <spl.h> diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c index 107929ee8a..457b110cd5 100644 --- a/board/rockchip/evb_rv1108/evb_rv1108.c +++ b/board/rockchip/evb_rv1108/evb_rv1108.c @@ -7,8 +7,8 @@ #include <common.h> #include <asm/io.h> #include <fdtdec.h> -#include <asm/arch/grf_rv1108.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/grf_rv1108.h> +#include <asm/arch-rockchip/hardware.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/rockchip/kylin_rk3036/kylin_rk3036.c b/board/rockchip/kylin_rk3036/kylin_rk3036.c index 3a2f08354f..2faeab9baf 100644 --- a/board/rockchip/kylin_rk3036/kylin_rk3036.c +++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c @@ -6,8 +6,8 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/uart.h> -#include <asm/arch/sdram_rk3036.h> +#include <asm/arch-rockchip/uart.h> +#include <asm/arch-rockchip/sdram_rk3036.h> #include <asm/gpio.h> void get_ddr_config(struct rk3036_ddr_config *config) diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c index ea22cb985f..9bb93c7d16 100644 --- a/board/rockchip/sheep_rk3368/sheep_rk3368.c +++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c @@ -4,8 +4,8 @@ */ #include <common.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3368.h> #include <syscon.h> int mach_cpu_init(void) diff --git a/board/shmin/Kconfig b/board/shmin/Kconfig deleted file mode 100644 index 467580c67b..0000000000 --- a/board/shmin/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_SHMIN - -config SYS_BOARD - default "shmin" - -config SYS_CONFIG_NAME - default "shmin" - -endif diff --git a/board/shmin/MAINTAINERS b/board/shmin/MAINTAINERS deleted file mode 100644 index 5dee37bdf7..0000000000 --- a/board/shmin/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -SHMIN BOARD -M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> -M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -S: Maintained -F: board/shmin/ -F: include/configs/shmin.h -F: configs/shmin_defconfig diff --git a/board/shmin/Makefile b/board/shmin/Makefile deleted file mode 100644 index 697fc20fa4..0000000000 --- a/board/shmin/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2010 Nobuhiro Iwamatsu -# Copyright (C) 2008 Renesas Solutions Corp. -# -# u-boot/board/shmin/Makefile -# - -obj-y := shmin.o -extra-y += lowlevel_init.o diff --git a/board/shmin/lowlevel_init.S b/board/shmin/lowlevel_init.S deleted file mode 100644 index e4b6ae0b13..0000000000 --- a/board/shmin/lowlevel_init.S +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008, 2010 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - */ - -#include <config.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* Use setting of original bootloader */ - rts - nop - .align 2 diff --git a/board/shmin/shmin.c b/board/shmin/shmin.c deleted file mode 100644 index 91918e9383..0000000000 --- a/board/shmin/shmin.c +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 - 2010 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * - * board/shmin/shmin.c - * - * Copy board_flash_get_legacy() from board/freescale/m54455evb/m54455evb.c - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <netdev.h> - -int checkboard(void) -{ - puts("BOARD: T-SH7706LAN "); - if(readb(0xb0008006) == 0xab) - puts("v2\n"); - else - puts("v1\n"); - return 0; -} - -int board_init(void) -{ - writew(0x2980, BCR2); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return ne2k_register(); -} - -void led_set_state(unsigned short value) -{ - -} - -#if defined(CONFIG_FLASH_CFI_LEGACY) -#include <flash.h> -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - int sect[] = CONFIG_SYS_ATMEL_SECT; - int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ; - int i, j, k; - - if (base != CONFIG_SYS_ATMEL_BASE) - return 0; - - info->flash_id = 0x01000000; - info->portwidth = 1; - info->chipwidth = 1; - info->buffer_size = 1; - info->erase_blk_tout = 16384; - info->write_tout = 2; - info->buffer_write_tout = 5; - info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */ - info->cmd_reset = 0x00F0; - info->interface = FLASH_CFI_X8; - info->legacy_unlock = 0; - info->manufacturer_id = (u16) ATM_MANUFACT; - info->device_id = ATM_ID_LV040; - info->device_id2 = 0; - info->ext_addr = 0; - info->cfi_version = 0x3133; - info->cfi_offset = 0x0000; - info->addr_unlock1 = 0x00000555; - info->addr_unlock2 = 0x000002AA; - info->name = "CFI conformant"; - info->size = 0; - info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT; - info->start[0] = base; - - for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) { - info->size += sect[i] * sectsz[i]; - for (j = 0; j < sect[i]; j++, k++) { - info->start[k + 1] = info->start[k] + sectsz[i]; - info->protect[k] = 0; - } - } - - return 1; -} -#endif /* CONFIG_FLASH_CFI_LEGACY */ diff --git a/board/siemens/taurus/Kconfig b/board/siemens/taurus/Kconfig index cf71e4ce56..28816bc1a0 100644 --- a/board/siemens/taurus/Kconfig +++ b/board/siemens/taurus/Kconfig @@ -9,4 +9,20 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "taurus" +choice + prompt "Board Type AXM/TAURUS" + default BOARD_AXM + +config BOARD_AXM + bool "AXM board type" + help + Select this, if you want to build for AXM board. + +config BOARD_TAURUS + bool "TAURUS board type" + help + Select this, if you want to build for TAURUS board. + +endchoice + endif diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 8396ce502b..6ea97eb4e8 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -197,11 +197,11 @@ void mem_init(void) /* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/ if (ram_size == 0x800) { - printf("\n\r 64MB"); + printf("\n\r 64MB\n"); sdramc_configure(AT91_SDRAMC_NC_9); } else { /* Size already initialized */ - printf("\n\r 128MB"); + printf("\n\r 128MB\n"); } } #endif @@ -282,24 +282,6 @@ int board_early_init_f(void) return 0; } -/* FIXME gpio code here need to handle through DM_GPIO */ -#ifndef CONFIG_DM_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1); -} -#endif - #ifdef CONFIG_USB_GADGET_AT91 #include <linux/usb/at91_udc.h> @@ -347,17 +329,6 @@ int dram_init(void) return 0; } -#ifndef CONFIG_DM_ETH -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); -#endif - return rc; -} -#endif - #if !defined(CONFIG_SPL_BUILD) #if defined(CONFIG_BOARD_AXM) /* diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 338f374e56..bdd1854197 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -166,6 +166,12 @@ M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained F: configs/bananapi_m64_defconfig +BEELINK GS1 +M: Clément Péron <peron.clem@gmail.com> +S: Maintained +F: configs/beelink_gs1_defconfig +F: arch/arm/dts/sun50i-h6-beelink-gs1.dts + COLOMBUS BOARD M: Maxime Ripard <maxime.ripard@bootlin.com> S: Maintained @@ -352,6 +358,12 @@ S: Maintained F: configs/A20-Olimex-SOM204-EVB_defconfig F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +OLIMEX TERES-I BOARD +M: Jonas Smedegaard <dr@jones.dk> +M: Icenowy Zheng <icenowy@aosc.io> +S: Maintained +F: configs/teres_i_defconfig + ORANGEPI LITE2 BOARD M: Jagan Teki <jagan@amarulasolutions.com> S: Maintained diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 767d13dfe5..e63b19df6e 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -13,10 +13,8 @@ #include <asm/mach-imx/mxc_i2c.h> #include <asm/io.h> #include <common.h> -#include <fsl_esdhc.h> #include <i2c.h> #include <miiphy.h> -#include <mmc.h> #include <netdev.h> #include <usb.h> #include <power/pmic.h> @@ -28,9 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) - #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) @@ -126,20 +121,6 @@ static iomux_v3_cfg_t const uart5_pads[] = { MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; -static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { - MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - #ifdef CONFIG_FEC_MXC static iomux_v3_cfg_t const fec1_pads[] = { MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), @@ -165,7 +146,7 @@ static iomux_v3_cfg_t const fec1_pads[] = { static void setup_iomux_fec(void) { imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - + gpio_request(FEC1_RST_GPIO, "phy_rst"); gpio_direction_output(FEC1_RST_GPIO, 0); udelay(500); gpio_set_value(FEC1_RST_GPIO, 1); @@ -224,25 +205,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* Assume uSDHC3 emmc is always present */ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - imx_iomux_v3_setup_multiple_pads( - usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - int board_early_init_f(void) { setup_iomux_uart(); @@ -291,6 +253,8 @@ static iomux_v3_cfg_t const lcd_pads[] = { void setup_lcd(void) { imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness"); + gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable"); /* Set Brightness to high */ gpio_direction_output(IMX_GPIO_NR(1, 11) , 1); /* Set LCD enable to high */ diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index 8c3443875d..92a46463db 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -5,11 +5,15 @@ * Author: Richard Hu <richard.hu@technexion.com> */ +#include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/mx7-pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch-mx7/mx7-ddr.h> +#include <asm/mach-imx/iomux-v3.h> #include <asm/gpio.h> +#include <fsl_esdhc.h> #include <spl.h> #if defined(CONFIG_SPL_BUILD) @@ -119,4 +123,38 @@ void board_init_f(ulong dummy) void reset_cpu(ulong addr) { } + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* Assume uSDHC3 emmc is always present */ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} #endif diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c index e207535df0..6cd5a5f18e 100644 --- a/board/theobroma-systems/lion_rk3368/lion_rk3368.c +++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c @@ -6,9 +6,9 @@ #include <dm.h> #include <ram.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3368.h> +#include <asm/arch-rockchip/timer.h> #include <syscon.h> int mach_cpu_init(void) diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 573e691457..c6b509c109 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -15,11 +15,11 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/setup.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> #include <u-boot/sha256.h> diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 04f4b8e693..37a599768b 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -399,7 +399,6 @@ void enable_board_pin_mux(void) configure_module_pin_mux(mii1_pin_mux); } /* Beaglebone LT pinmux */ - configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); #if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT) configure_module_pin_mux(nand_pin_mux); diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 536c5b88ed..d29a22cf05 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -244,7 +244,7 @@ const struct emif_regs ddr3_emif_regs_400Mhz_production = { .read_idle_ctrl = 0x00050000, .zq_config = 0x50074BE4, .temp_alert_config = 0x0, - .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_phy_ctlr_1 = 0x00048008, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x00000066, .emif_ddr_ext_phy_ctrl_3 = 0x00000091, diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig index d4b36dbb42..98172c28f5 100644 --- a/board/ti/am65x/Kconfig +++ b/board/ti/am65x/Kconfig @@ -11,6 +11,7 @@ config TARGET_AM654_A53_EVM bool "TI K3 based AM654 EVM running on A53" select ARM64 select SOC_K3_AM6 + select SYS_DISABLE_DCACHE_OPS config TARGET_AM654_R5_EVM bool "TI K3 based AM654 EVM running on R5" diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h index 89c49f9e4f..6aa785ea42 100644 --- a/board/ti/ks2_evm/mux-k2g.h +++ b/board/ti/ks2_evm/mux-k2g.h @@ -126,22 +126,22 @@ struct pin_cfg k2g_evm_pin_cfg[] = { { 71, MODE(0) }, /* MMC1POW TP124 */ /* EMAC */ - { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */ - { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */ + { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */ { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */ + { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */ + { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */ { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */ - { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */ - { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */ - { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */ - { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */ + { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */ { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */ + { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */ + { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */ + { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */ + { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */ { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */ - { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */ - { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */ /* MDIO */ - { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */ { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */ + { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */ /* PWM */ { 73, MODE(4) }, /* SOC_EHRPWM3A */ @@ -350,22 +350,22 @@ struct pin_cfg k2g_ice_evm_pin_cfg[] = { { 135, MODE(0) }, /* SOC_QSPI_CSN0 */ /* EMAC */ - { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */ - { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */ + { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */ { 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */ + { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */ + { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */ { 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */ - { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */ - { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */ - { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */ - { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */ + { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */ { 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */ + { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */ + { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */ + { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */ + { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */ { 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */ - { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */ - { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */ /* MDIO */ - { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */ { 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */ + { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */ { MAX_PIN_N, } }; diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS index 7cda555984..626c1f94f9 100644 --- a/board/toradex/colibri-imx6ull/MAINTAINERS +++ b/board/toradex/colibri-imx6ull/MAINTAINERS @@ -1,6 +1,5 @@ Colibri iMX6ULL M: Stefan Agner <stefan.agner@toradex.com> -M: Toradex ARM Support <support.arm@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c index fcb49a0718..21addaf6ed 100644 --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Toradex AG + * Copyright (C) 2018-2019 Toradex AG */ #include <common.h> + #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> #include <asm/arch/imx-regs.h> @@ -14,47 +15,30 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/io.h> -#include <common.h> #include <dm.h> #include <dm/platform_data/serial_mxc.h> #include <fdt_support.h> -#include <fsl_esdhc.h> #include <imx_thermal.h> #include <jffs2/load_kernel.h> #include <linux/sizes.h> -#include <mmc.h> #include <miiphy.h> #include <mtd_node.h> #include <netdev.h> -#include <usb.h> -#include <usb/ehci-ci.h> + #include "../common/tdx-common.h" +#include "../common/tdx-cfg-block.h" DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_40ohm) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm) - #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ PAD_CTL_DSE_48ohm) +#define MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR 0x2290040 + #define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP) -#define USB_CDET_GPIO IMX_GPIO_NR(7, 14) - int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -62,56 +46,13 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RTS_B__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_CTS_B__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -#ifdef CONFIG_FSL_ESDHC -static iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#endif - -static iomux_v3_cfg_t const usb_cdet_pads[] = { - MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - #ifdef CONFIG_NAND_MXS -static iomux_v3_cfg_t const gpmi_pads[] = { - MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), -}; - static void setup_gpmi_nand(void) { - imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); - setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); } -#endif +#endif /* CONFIG_NAND_MXS */ #ifdef CONFIG_VIDEO_MXS static iomux_v3_cfg_t const lcd_pads[] = { @@ -168,100 +109,24 @@ static int setup_lcd(void) #endif #ifdef CONFIG_FEC_MXC -static iomux_v3_cfg_t const fec2_pads[] = { - MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, - MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), - MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), - MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static void setup_iomux_fec(void) -{ - imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); -} -#endif - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -#ifdef CONFIG_FSL_ESDHC - -#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) - -static struct fsl_esdhc_cfg usdhc_cfg[] = { - {USDHC1_BASE_ADDR, 0, 4}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int i, ret; - - /* USDHC1 is mmc0 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} -#endif - -#ifdef CONFIG_FEC_MXC - static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; - setup_iomux_fec(); - /* provide the PHY clock from the i.MX 6 */ ret = enable_fec_anatop_clock(1, ENET_50MHZ); if (ret) return ret; - /* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */ + /* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + /* give new Ethernet PHY power save mode circuitry time to settle */ + mdelay(300); + return 0; } @@ -271,14 +136,7 @@ int board_phy_config(struct phy_device *phydev) phydev->drv->config(phydev); return 0; } -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} +#endif /* CONFIG_FEC_MXC */ int board_init(void) { @@ -297,11 +155,6 @@ int board_init(void) setup_lcd(); #endif -#ifdef CONFIG_USB_EHCI_MX6 - imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); - gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); -#endif - return 0; } @@ -317,10 +170,23 @@ static const struct boot_mode board_boot_modes[] = { int board_late_init(void) { - int minc, maxc; - - if (get_cpu_temp_grade(&minc, &maxc) != TEMP_COMMERCIAL) +#ifdef CONFIG_TDX_CFG_BLOCK + /* + * If we have a valid config block and it says we are a module with + * Wi-Fi/Bluetooth make sure we use the -wifi device tree. + */ + if (tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT_IT || + tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT) env_set("variant", "-wifi"); +#endif + + /* + * Disable output driver of PAD CCM_PMIC_STBY_REQ. This prevents the + * SOC to request for a lower voltage during sleep. This is necessary + * because the voltage is changing too slow for the SOC to wake up + * properly. + */ + __raw_writel(0x8080, MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR); #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); @@ -362,41 +228,6 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif -#ifdef CONFIG_USB_EHCI_MX6 -static iomux_v3_cfg_t const usb_otg2_pads[] = { - MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -int board_ehci_hcd_init(int port) -{ - switch (port) { - case 0: - break; - case 1: - imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, - ARRAY_SIZE(usb_otg2_pads)); - break; - default: - return -EINVAL; - } - return 0; -} - -int board_usb_phy_mode(int port) -{ - switch (port) { - case 0: - if (gpio_get_value(USB_CDET_GPIO)) - return USB_INIT_DEVICE; - else - return USB_INIT_HOST; - case 1: - default: - return USB_INIT_HOST; - } -} -#endif - static struct mxc_serial_platdata mxc_serial_plat = { .reg = (struct mxc_uart *)UART1_BASE, .use_dte = 1, diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS index f55f8045f4..cd0f9c9b2d 100644 --- a/board/toradex/colibri_imx7/MAINTAINERS +++ b/board/toradex/colibri_imx7/MAINTAINERS @@ -1,6 +1,5 @@ Colibri iMX7 M: Stefan Agner <stefan.agner@toradex.com> -M: Toradex ARM Support <support.arm@toradex.com> W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index 3ee2b33152..66b2150986 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -1,7 +1,7 @@ Colibri VFxx M: Stefan Agner <stefan.agner@toradex.com> W: http://developer.toradex.com/software/linux/linux-software -W: https://www.toradex.com/community +W: https://www.toradex.com/community S: Maintained F: board/toradex/colibri_vf/ F: include/configs/colibri_vf.h diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index b90077bedc..f69c4433b2 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -1,12 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (c) 2016 Toradex, Inc. + * Copyright (c) 2016-2019 Toradex, Inc. */ #include <common.h> #include "tdx-cfg-block.h" -#if defined(CONFIG_TARGET_APALIS_IMX6) || defined(CONFIG_TARGET_COLIBRI_IMX6) +#if defined(CONFIG_TARGET_APALIS_IMX6) || \ + defined(CONFIG_TARGET_COLIBRI_IMX6) || \ + defined(CONFIG_TARGET_COLIBRI_IMX8QXP) #include <asm/arch/sys_proto.h> #else #define is_cpu_type(cpu) (0) @@ -92,12 +94,22 @@ const char * const toradex_modules[] = { [34] = "Apalis TK1 2GB", [35] = "Apalis iMX6 Dual 1GB IT", [36] = "Colibri iMX6ULL 256MB", - [37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / Bluetooth", - [38] = "Colibri iMX8X", + [37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT", + [38] = "Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT", [39] = "Colibri iMX7 Dual 1GB (eMMC)", - [40] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth IT", + [40] = "Colibri iMX6ULL 512MB Wi-Fi / BT IT", [41] = "Colibri iMX7 Dual 512MB EPDC", [42] = "Apalis TK1 4GB", + [43] = "Colibri T20 512MB IT SETEK", + [44] = "Colibri iMX6ULL 512MB IT", + [45] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth", + [46] = "Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT", + [47] = "Apalis iMX8 QuadMax 4GB IT", + [48] = "Apalis iMX8 QuadPlus 2GB Wi-Fi / BT", + [49] = "Apalis iMX8 QuadPlus 2GB", + [50] = "Colibri iMX8 QuadXPlus 2GB IT", + [51] = "Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth", + [52] = "Colibri iMX8 DualX 1GB", }; #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC @@ -277,6 +289,9 @@ static int get_cfgblock_interactive(void) char it = 'n'; int len; + /* Unknown module by default */ + tdx_hw_tag.prodid = 0; + if (cpu_is_pxa27x()) sprintf(message, "Is the module the 312 MHz version? [y/N] "); else @@ -287,34 +302,56 @@ static int get_cfgblock_interactive(void) soc = env_get("soc"); if (!strcmp("mx6", soc)) { -#ifdef CONFIG_MACH_TYPE - if (it == 'y' || it == 'Y') +#ifdef CONFIG_TARGET_APALIS_IMX6 + if (it == 'y' || it == 'Y') { if (is_cpu_type(MXC_CPU_MX6Q)) tdx_hw_tag.prodid = APALIS_IMX6Q_IT; else tdx_hw_tag.prodid = APALIS_IMX6D_IT; - else + } else { if (is_cpu_type(MXC_CPU_MX6Q)) tdx_hw_tag.prodid = APALIS_IMX6Q; else tdx_hw_tag.prodid = APALIS_IMX6D; -#else - if (it == 'y' || it == 'Y') + } +#elif CONFIG_TARGET_COLIBRI_IMX6 + if (it == 'y' || it == 'Y') { if (is_cpu_type(MXC_CPU_MX6DL)) tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT; - else + else if (is_cpu_type(MXC_CPU_MX6SOLO)) tdx_hw_tag.prodid = COLIBRI_IMX6S_IT; - else + } else { if (is_cpu_type(MXC_CPU_MX6DL)) tdx_hw_tag.prodid = COLIBRI_IMX6DL; - else + else if (is_cpu_type(MXC_CPU_MX6SOLO)) tdx_hw_tag.prodid = COLIBRI_IMX6S; -#endif /* CONFIG_MACH_TYPE */ - } else if (!strcmp("imx7d", soc)) { + } +#elif CONFIG_TARGET_COLIBRI_IMX6ULL + char wb = 'n'; + + sprintf(message, "Does the module have Wi-Fi / Bluetooth? " \ + "[y/N] "); + len = cli_readline(message); + wb = console_buffer[0]; + if (it == 'y' || it == 'Y') { + if (wb == 'y' || wb == 'Y') + tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT_IT; + else + tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT; + } else { + if (wb == 'y' || wb == 'Y') + tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT; + else + tdx_hw_tag.prodid = COLIBRI_IMX6ULL; + } +#endif + } else if (!strcmp("imx7d", soc)) tdx_hw_tag.prodid = COLIBRI_IMX7D; - } else if (!strcmp("imx7s", soc)) { + else if (!strcmp("imx7s", soc)) tdx_hw_tag.prodid = COLIBRI_IMX7S; - } else if (!strcmp("tegra20", soc)) { + else if (is_cpu_type(MXC_CPU_IMX8QXP)) + tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT; + else if (!strcmp("tegra20", soc)) { if (it == 'y' || it == 'Y') if (gd->ram_size == 0x10000000) tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT; @@ -330,8 +367,9 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ; else tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ; + } #ifdef CONFIG_MACH_TYPE - } else if (!strcmp("tegra30", soc)) { + else if (!strcmp("tegra30", soc)) { if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) { if (it == 'y' || it == 'Y') tdx_hw_tag.prodid = APALIS_T30_IT; @@ -346,8 +384,9 @@ static int get_cfgblock_interactive(void) else tdx_hw_tag.prodid = COLIBRI_T30; } + } #endif /* CONFIG_MACH_TYPE */ - } else if (!strcmp("tegra124", soc)) { + else if (!strcmp("tegra124", soc)) { tdx_hw_tag.prodid = APALIS_TK1_2GB; } else if (!strcmp("vf500", soc)) { if (it == 'y' || it == 'Y') @@ -359,7 +398,9 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_VF61_IT; else tdx_hw_tag.prodid = COLIBRI_VF61; - } else { + } + + if (!tdx_hw_tag.prodid) { printf("Module type not detectable due to unknown SoC\n"); return -1; } @@ -373,7 +414,7 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.ver_minor = console_buffer[2] - '0'; tdx_hw_tag.ver_assembly = console_buffer[3] - 'A'; - if (cpu_is_pxa27x() && (tdx_hw_tag.ver_major == 1)) + if (cpu_is_pxa27x() && tdx_hw_tag.ver_major == 1) tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ - COLIBRI_PXA270_V1_312MHZ); @@ -441,7 +482,8 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc, * On NAND devices, recreation is only allowed if the page is * empty (config block invalid...) */ - printf("NAND erase block %d need to be erased before creating a Toradex config block\n", + printf("NAND erase block %d need to be erased before creating" \ + " a Toradex config block\n", CONFIG_TDX_CFG_BLOCK_OFFSET / get_nand_dev_by_index(0)->erasesize); goto out; @@ -450,7 +492,8 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc, * On NOR devices, recreation is only allowed if the sector is * empty and write protection is off (config block invalid...) */ - printf("NOR sector at offset 0x%02x need to be erased and unprotected before creating a Toradex config block\n", + printf("NOR sector at offset 0x%02x need to be erased and " \ + "unprotected before creating a Toradex config block\n", CONFIG_TDX_CFG_BLOCK_OFFSET); goto out; #else diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index da60e789a7..bfdc8b7f70 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -25,42 +25,54 @@ enum { COLIBRI_PXA270_V1_520MHZ, COLIBRI_PXA320, COLIBRI_PXA300, - COLIBRI_PXA310, + COLIBRI_PXA310, /* 5 */ COLIBRI_PXA320_IT, COLIBRI_PXA300_XT, COLIBRI_PXA270_312MHZ, COLIBRI_PXA270_520MHZ, - COLIBRI_VF50, /* not currently on sale */ - COLIBRI_VF61, + COLIBRI_VF50, /* 10 */ + COLIBRI_VF61, /* not currently on sale */ COLIBRI_VF61_IT, COLIBRI_VF50_IT, COLIBRI_IMX6S, - COLIBRI_IMX6DL, + COLIBRI_IMX6DL, /* 15 */ COLIBRI_IMX6S_IT, COLIBRI_IMX6DL_IT, + /* 18 */ + /* 19 */ COLIBRI_T20_256MB = 20, COLIBRI_T20_512MB, COLIBRI_T20_512MB_IT, COLIBRI_T30, COLIBRI_T20_256MB_IT, - APALIS_T30_2GB, + APALIS_T30_2GB, /* 25 */ APALIS_T30_1GB, APALIS_IMX6Q, APALIS_IMX6Q_IT, APALIS_IMX6D, - COLIBRI_T30_IT, + COLIBRI_T30_IT, /* 30 */ APALIS_T30_IT, COLIBRI_IMX7S, COLIBRI_IMX7D, APALIS_TK1_2GB, - APALIS_IMX6D_IT, + APALIS_IMX6D_IT, /* 35 */ COLIBRI_IMX6ULL, - APALIS_IMX8QM, /* 37 */ - COLIBRI_IMX8X, + APALIS_IMX8QM_WIFI_BT_IT, + COLIBRI_IMX8QXP_WIFI_BT_IT, COLIBRI_IMX7D_EMMC, COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */ COLIBRI_IMX7D_EPDC, - APALIS_TK1_4GB, + APALIS_TK1_4GB, /* not currently on sale */ + COLIBRI_T20_512MB_IT_SETEK, + COLIBRI_IMX6ULL_IT, + COLIBRI_IMX6ULL_WIFI_BT, /* 45 */ + APALIS_IMX8QXP_WIFI_BT_IT, + APALIS_IMX8QM_IT, + APALIS_IMX8QP_WIFI_BT, + APALIS_IMX8QP, + COLIBRI_IMX8QXP_IT, /* 50 */ + COLIBRI_IMX8DX_WIFI_BT, + COLIBRI_IMX8DX, }; extern const char * const toradex_modules[]; diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index d3775b2219..0f5ef3a09a 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -7,7 +7,7 @@ #include <dm.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> #include <spl.h> diff --git a/board/variscite/dart_6ul/Kconfig b/board/variscite/dart_6ul/Kconfig new file mode 100644 index 0000000000..1765af1d82 --- /dev/null +++ b/board/variscite/dart_6ul/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DART_6UL + +config SYS_BOARD + default "dart_6ul" + +config SYS_VENDOR + default "variscite" + +config SYS_CONFIG_NAME + default "dart_6ul" + +endif diff --git a/board/variscite/dart_6ul/MAINTAINERS b/board/variscite/dart_6ul/MAINTAINERS new file mode 100644 index 0000000000..339f93fa66 --- /dev/null +++ b/board/variscite/dart_6ul/MAINTAINERS @@ -0,0 +1,8 @@ +MX6UL_DART BOARD +M: Parthiban Nallathambi <parthitce@gmail.com> +S: Maintained +F: arch/arm/dts/imx6ull-dart-6ul.dts +F: arch/arm/dts/imx6ull-dart-6ul.dtsi +F: board/variscite/dart_6ul/ +F: configs/variscite_dart6ul_defconfig +F: include/configs/dart_6ul.h diff --git a/board/variscite/dart_6ul/Makefile b/board/variscite/dart_6ul/Makefile new file mode 100644 index 0000000000..48aa361bf2 --- /dev/null +++ b/board/variscite/dart_6ul/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := dart_6ul.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/variscite/dart_6ul/README b/board/variscite/dart_6ul/README new file mode 100644 index 0000000000..d76b997e22 --- /dev/null +++ b/board/variscite/dart_6ul/README @@ -0,0 +1,41 @@ +How to use U-Boot on variscite DART-6UL Evaluation Kit +------------------------------------------------------ + +- Configure and build U-Boot for DART-6UL iMX6ULL: + + $ make mrproper + $ make variscite_dart6ul_defconfig + $ make + + This will generate SPL and u-boot-dtb.img images. + +Boot from MMC/SD: +- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card: + + $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 0 + +Boot from eMMC: +- if bootpart is not enabled by default, to enable under Linux + echo 0 >/sys/block/mmcblk1boot0/force_ro + mmc bootpart enable 1 1 /dev/mmcblk1boot0 + +- Flash the SPL and u-boot-dtb.img to mmcblk1boot0 + $ sudo dd if=SPL of=/dev/mmcblk1boot0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk1boot0 bs=1k seek=69; sync + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 1 + +- Connect the Serial cable to UART0 and the PC for the console. + +- Insert the micro SD card in the board and power it up. + +- U-Boot messages should come up. diff --git a/board/variscite/dart_6ul/dart_6ul.c b/board/variscite/dart_6ul/dart_6ul.c new file mode 100644 index 0000000000..4765595af1 --- /dev/null +++ b/board/variscite/dart_6ul/dart_6ul.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2019 Variscite Ltd. + * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com> + */ + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc.h> +#include <linux/bitops.h> +#include <miiphy.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#ifdef CONFIG_NAND_MXS +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + clrbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* + * config gpmi and bch clock to 100 MHz + * bch/gpmi select PLL2 PFD2 400M + * 100M = 400M / 4 + */ + clrbits_le32(&mxc_ccm->cscmr1, + MXC_CCM_CSCMR1_BCH_CLK_SEL | + MXC_CCM_CSCMR1_GPMI_CLK_SEL); + clrsetbits_le32(&mxc_ccm->cscdr1, + MXC_CCM_CSCDR1_BCH_PODF_MASK | + MXC_CCM_CSCDR1_GPMI_PODF_MASK, + (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_FEC_MXC +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_FAST) +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_ODE) +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) + imx_iomux_v3_setup_multiple_pads(fec1_pads, + ARRAY_SIZE(fec1_pads)); + else + imx_iomux_v3_setup_multiple_pads(fec2_pads, + ARRAY_SIZE(fec2_pads)); +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + +#if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER) + /* USB Ethernet Gadget */ + usb_eth_initialize(bis); +#endif + return ret; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + if (fec_id == 0) { + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select + * 50 MHz RMII clock mode. + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif /* CONFIG_FEC_MXC */ + +int board_early_init_f(void) +{ + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: Variscite DART-6UL Evaluation Kit\n"); + + return 0; +} diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c new file mode 100644 index 0000000000..f7e6ab6325 --- /dev/null +++ b/board/variscite/dart_6ul/spl.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2019 Variscite Ltd. + * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com> + */ + +#include <common.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/crm_regs.h> +#include <fsl_esdhc.h> + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000008, + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x414C0158, + .p0_mprddlctl = 0x40403A3A, + .p0_mpwrdlctl = 0x40405A56, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); + /* Enable Audio Clock for SOM codec */ + writel(0x01130100, (long *)CCM_CCOSR); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, + }, +#ifndef CONFIG_NAND_MXS + { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 8, + }, +#endif +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#ifndef CONFIG_NAND_MXS + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; +#endif + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* setup GP timer */ + timer_init(); + + setup_iomux_uart(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 2882dc9870..134a6c99d7 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -14,7 +14,6 @@ #include <asm/io.h> #include <common.h> #include <asm/arch/crm_regs.h> -#include <usb.h> #include <netdev.h> #include <power/pmic.h> #include <power/pfuze3000_pmic.h> @@ -128,11 +127,6 @@ int checkboard(void) return 0; } -int board_usb_phy_mode(int port) -{ - return USB_INIT_DEVICE; -} - int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; |