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-rw-r--r--board/freescale/ls1012ardb/Kconfig2
-rw-r--r--board/freescale/ls1043aqds/ls1043aqds.c98
-rw-r--r--board/freescale/ls1046afrwy/ls1046afrwy.c17
-rw-r--r--board/freescale/ls1046aqds/ls1046aqds.c25
-rw-r--r--board/freescale/lx2160a/lx2160a.c48
5 files changed, 172 insertions, 18 deletions
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index 639353a94b..5a2fa91f6b 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -35,7 +35,7 @@ config SYS_LS_PFE_FW_ADDR
config SYS_LS_PFE_ESBC_ADDR
hex "PFE Firmware HDR Addr"
- default 0x40700000
+ default 0x40640000
config DDR_PFE_PHYS_BASEADDR
hex "PFE DDR physical base address"
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 8c96b962b7..2d4b18cdbc 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
*/
#include <common.h>
@@ -271,11 +272,24 @@ unsigned long get_board_ddr_clk(void)
return 66666666;
}
-int select_i2c_ch_pca9547(u8 ch)
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+ 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ bus_num);
+ return ret;
+ }
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@@ -290,8 +304,10 @@ int dram_init(void)
* When resuming from deep sleep, the I2C channel may not be
* in the default channel. So, switch to the default channel
* before accessing DDR SPD.
+ *
+ * PCA9547 mount on I2C1 bus
*/
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
fsl_initdram();
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
defined(CONFIG_SPL_BUILD)
@@ -304,16 +320,83 @@ int dram_init(void)
int i2c_multiplexer_select_vid_channel(u8 channel)
{
- return select_i2c_ch_pca9547(channel);
+ return select_i2c_ch_pca9547(channel, 0);
}
void board_retimer_init(void)
{
u8 reg;
+ int bus_num = 0;
/* Retimer is connected to I2C1_CH7_CH5 */
- select_i2c_ch_pca9547(I2C_MUX_CH7);
+ select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
reg = I2C_MUX_CH5;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
+ 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ bus_num);
+ return;
+ }
+ dm_i2c_write(dev, 0, &reg, 1);
+
+ /* Access to Control/Shared register */
+ ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
+ 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ bus_num);
+ return;
+ }
+
+ reg = 0x0;
+ dm_i2c_write(dev, 0xff, &reg, 1);
+
+ /* Read device revision and ID */
+ dm_i2c_read(dev, 1, &reg, 1);
+ debug("Retimer version id = 0x%x\n", reg);
+
+ /* Enable Broadcast. All writes target all channel register sets */
+ reg = 0x0c;
+ dm_i2c_write(dev, 0xff, &reg, 1);
+
+ /* Reset Channel Registers */
+ dm_i2c_read(dev, 0, &reg, 1);
+ reg |= 0x4;
+ dm_i2c_write(dev, 0, &reg, 1);
+
+ /* Enable override divider select and Enable Override Output Mux */
+ dm_i2c_read(dev, 9, &reg, 1);
+ reg |= 0x24;
+ dm_i2c_write(dev, 9, &reg, 1);
+
+ /* Select VCO Divider to full rate (000) */
+ dm_i2c_read(dev, 0x18, &reg, 1);
+ reg &= 0x8f;
+ dm_i2c_write(dev, 0x18, &reg, 1);
+
+ /* Selects active PFD MUX Input as Re-timed Data (001) */
+ dm_i2c_read(dev, 0x1e, &reg, 1);
+ reg &= 0x3f;
+ reg |= 0x20;
+ dm_i2c_write(dev, 0x1e, &reg, 1);
+
+ /* Set data rate as 10.3125 Gbps */
+ reg = 0x0;
+ dm_i2c_write(dev, 0x60, &reg, 1);
+ reg = 0xb2;
+ dm_i2c_write(dev, 0x61, &reg, 1);
+ reg = 0x90;
+ dm_i2c_write(dev, 0x62, &reg, 1);
+ reg = 0xb3;
+ dm_i2c_write(dev, 0x63, &reg, 1);
+ reg = 0xcd;
+ dm_i2c_write(dev, 0x64, &reg, 1);
+#else
i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
/* Access to Control/Shared register */
@@ -360,9 +443,10 @@ void board_retimer_init(void)
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
+#endif
/* Return the default channel */
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
}
int board_early_init_f(void)
@@ -375,9 +459,11 @@ int board_early_init_f(void)
u8 uart;
#endif
+#ifdef CONFIG_SYS_I2C
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
+#endif
fsl_lsch2_early_init_f();
#ifdef CONFIG_HAS_FSL_XHCI_USB
@@ -457,7 +543,7 @@ int board_init(void)
erratum_a010315();
#endif
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
board_retimer_init();
#ifdef CONFIG_SYS_FSL_SERDES
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
index db8b3a5b92..8c0abb63a9 100644
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -36,11 +36,24 @@
DECLARE_GLOBAL_DATA_PTR;
-int select_i2c_ch_pca9547(u8 ch)
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+ 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ bus_num);
+ return ret;
+ }
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@@ -149,7 +162,7 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
sec_init();
#endif
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return 0;
}
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index aac5d9aa84..cabd7ee648 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
*/
#include <common.h>
@@ -269,11 +270,23 @@ u32 get_lpuart_clk(void)
}
#endif
-int select_i2c_ch_pca9547(u8 ch)
+int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *dev;
+ ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
+ 1, &dev);
+ if (ret) {
+ printf("%s: Cannot find udev for a bus %d\n", __func__,
+ bus_num);
+ return ret;
+ }
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@@ -288,8 +301,10 @@ int dram_init(void)
* When resuming from deep sleep, the I2C channel may not be
* in the default channel. So, switch to the default channel
* before accessing DDR SPD.
+ *
+ * PCA9547 mount on I2C1 bus
*/
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
fsl_initdram();
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
defined(CONFIG_SPL_BUILD)
@@ -302,7 +317,7 @@ int dram_init(void)
int i2c_multiplexer_select_vid_channel(u8 channel)
{
- return select_i2c_ch_pca9547(channel);
+ return select_i2c_ch_pca9547(channel, 0);
}
int board_early_init_f(void)
@@ -315,9 +330,11 @@ int board_early_init_f(void)
u8 uart;
#endif
+#ifdef CONFIG_SYS_I2C
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
+#endif
fsl_lsch2_early_init_f();
#ifdef CONFIG_HAS_FSL_XHCI_USB
@@ -394,7 +411,7 @@ int misc_init_r(void)
int board_init(void)
{
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
#ifdef CONFIG_SYS_FSL_SERDES
config_serdes_mux();
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 103b0cc659..4b20bb440f 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -29,11 +29,14 @@
#include "../common/vid.h"
#include <fsl_immap.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/gic-v3.h>
+#include <cpu_func.h>
#ifdef CONFIG_EMC2305
#include "../common/emc2305.h"
#endif
+#define GIC_LPI_SIZE 0x200000
#ifdef CONFIG_TARGET_LX2160AQDS
#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
@@ -149,6 +152,7 @@ int board_fix_fdt(void *fdt)
reg_name = reg_names;
remaining_names_len = names_len - (reg_name - reg_names);
+ i = 0;
while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
old_name_len = strlen(reg_names_map[i].old_str);
new_name_len = strlen(reg_names_map[i].new_str);
@@ -274,7 +278,14 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
int init_func_vid(void)
{
- if (adjust_vdd(0) < 0)
+ int set_vid;
+
+ if (IS_SVR_REV(get_svr(), 1, 0))
+ set_vid = adjust_vdd(800);
+ else
+ set_vid = adjust_vdd(0);
+
+ if (set_vid < 0)
printf("core voltage not adjusted\n");
return 0;
@@ -469,10 +480,16 @@ int config_board_mux(void)
reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
QIXIS_WRITE(brdcfg[11], reg11);
} else {
- /* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
+ /*
+ * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
+ * do not change it.
+ * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
+ */
reg11 = QIXIS_READ(brdcfg[11]);
- reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
- QIXIS_WRITE(brdcfg[11], reg11);
+ if ((reg11 & 0x30) != 0x30) {
+ reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
+ QIXIS_WRITE(brdcfg[11], reg11);
+ }
/* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
* {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
@@ -627,8 +644,22 @@ void board_quiesce_devices(void)
}
#endif
-#ifdef CONFIG_OF_BOARD_SETUP
+#ifdef CONFIG_GIC_V3_ITS
+void fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
+{
+ u32 phandle;
+ int err;
+ struct fdt_memory gic_lpi;
+
+ gic_lpi.start = gic_lpi_base;
+ gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
+ err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
+ if (err < 0)
+ debug("failed to add reserved memory: %d\n", err);
+}
+#endif
+#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
@@ -639,6 +670,7 @@ int ft_board_setup(void *blob, bd_t *bd)
u64 mc_memory_base = 0;
u64 mc_memory_size = 0;
u16 total_memory_banks;
+ u64 gic_lpi_base;
ft_cpu_setup(blob, bd);
@@ -658,6 +690,12 @@ int ft_board_setup(void *blob, bd_t *bd)
size[i] = gd->bd->bi_dram[i].size;
}
+#ifdef CONFIG_GIC_V3_ITS
+ gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
+ gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
+ fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
+#endif
+
#ifdef CONFIG_RESV_RAM
/* reduce size if reserved memory is within this bank */
if (gd->arch.resv_ram >= base[0] &&
generated by cgit (git 2.34.1) at 2025-01-21 07:22:18 +0000