diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/intel/bayleybay/bayleybay.c | 6 | ||||
| -rw-r--r-- | board/intel/crownbay/crownbay.c | 6 | ||||
| -rw-r--r-- | board/intel/galileo/galileo.c | 56 | ||||
| -rw-r--r-- | board/siemens/corvus/board.c | 23 | ||||
| -rw-r--r-- | board/siemens/smartweb/smartweb.c | 29 | ||||
| -rw-r--r-- | board/siemens/taurus/taurus.c | 229 |
6 files changed, 318 insertions, 31 deletions
diff --git a/board/intel/bayleybay/bayleybay.c b/board/intel/bayleybay/bayleybay.c index 78447965b9..ccbe860b14 100644 --- a/board/intel/bayleybay/bayleybay.c +++ b/board/intel/bayleybay/bayleybay.c @@ -6,14 +6,8 @@ #include <common.h> #include <asm/gpio.h> -#include <netdev.h> void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { return; } - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c index d6de9fabc0..3a79e69112 100644 --- a/board/intel/crownbay/crownbay.c +++ b/board/intel/crownbay/crownbay.c @@ -7,7 +7,6 @@ #include <common.h> #include <asm/ibmpc.h> #include <asm/pnp_def.h> -#include <netdev.h> #include <smsc_lpc47m.h> int board_early_init_f(void) @@ -24,8 +23,3 @@ void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { return; } - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c index 746ab277cb..c1087acb69 100644 --- a/board/intel/galileo/galileo.c +++ b/board/intel/galileo/galileo.c @@ -5,12 +5,68 @@ */ #include <common.h> +#include <asm/io.h> +#include <asm/arch/device.h> +#include <asm/arch/gpio.h> +#include <asm/arch/quark.h> int board_early_init_f(void) { return 0; } +/* + * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin. + * + * We cannot use any public GPIO APIs in <asm-generic/gpio.h> to control this + * pin, as these APIs will eventually call into gpio_ich6_ofdata_to_platdata() + * in the Intel ICH6 GPIO driver where it calls PCI configuration space access + * APIs which will trigger PCI enumeration process. + * + * Check <asm/arch-quark/quark.h> for more details. + */ +void board_assert_perst(void) +{ + u32 base, port, val; + + /* retrieve the GPIO IO base */ + qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, PCI_CFG_GPIOBASE, &base); + base = (base & 0xffff) & ~0x7f; + + /* enable the pin */ + port = base + 0x20; + val = inl(port); + val |= (1 << 0); + outl(val, port); + + /* configure the pin as output */ + port = base + 0x24; + val = inl(port); + val &= ~(1 << 0); + outl(val, port); + + /* pull it down (assert) */ + port = base + 0x28; + val = inl(port); + val &= ~(1 << 0); + outl(val, port); +} + +void board_deassert_perst(void) +{ + u32 base, port, val; + + /* retrieve the GPIO IO base */ + qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, PCI_CFG_GPIOBASE, &base); + base = (base & 0xffff) & ~0x7f; + + /* pull it up (de-assert) */ + port = base + 0x28; + val = inl(port); + val |= (1 << 0); + outl(val, port); +} + void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) { return; diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index 3294203b71..28985b8b08 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -29,6 +29,10 @@ #include <netdev.h> #include <spi.h> +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +#include <asm/arch/atmel_usba_udc.h> +#endif + DECLARE_GLOBAL_DATA_PTR; static void corvus_nand_hw_init(void) @@ -73,7 +77,7 @@ static void corvus_nand_hw_init(void) #include <spl.h> #include <nand.h> -void at91_spl_board_init(void) +void spl_board_init(void) { /* * For on the sam9m10g45ek board, the chip wm9711 stay in the test @@ -202,6 +206,19 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +/* from ./arch/arm/mach-at91/armv7/sama5d3_devices.c */ +void at91_udp_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable UPLL clock */ + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + /* Enable UDPHS clock */ + at91_periph_clk_enable(ATMEL_ID_UDPHS); +} +#endif + int board_init(void) { /* address of boot parameters */ @@ -222,6 +239,10 @@ int board_init(void) #ifdef CONFIG_CMD_USB taurus_usb_hw_init(); #endif +#ifdef CONFIG_USB_GADGET_ATMEL_USBA + at91_udp_hw_init(); + usba_udc_probe(&pdata); +#endif return 0; } diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index cf8a7f5b06..2d424882a9 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -25,6 +25,7 @@ #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_spi.h> #include <spi.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <watchdog.h> #ifdef CONFIG_MACB @@ -108,6 +109,29 @@ static void smartweb_macb_hw_init(void) } #endif /* CONFIG_MACB */ +#ifdef CONFIG_USB_GADGET_AT91 +#include <linux/usb/at91_udc.h> + +void at91_udp_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + /* Enable PLLB */ + writel(get_pllb_init(), &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) + ; + + /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ + at91_periph_clk_enable(ATMEL_ID_UDP); + + writel(AT91SAM926x_PMC_UDP, &pmc->scer); +} + +struct at91_udc_data board_udc_data = { + .baseaddr = ATMEL_BASE_UDP0, +}; +#endif + int board_early_init_f(void) { /* enable this here, as we have SPL without serial support */ @@ -134,6 +158,11 @@ int board_init(void) at91_set_gpio_output(AT91_PIN_PC10, 0); at91_set_gpio_output(AT91_PIN_PC11, 1); +#ifdef CONFIG_USB_GADGET_AT91 + at91_udp_hw_init(); + at91_udc_probe(&board_udc_data); +#endif + return 0; } diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 013dac2e2f..72c5e6083d 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -12,6 +12,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <command.h> #include <common.h> #include <asm/io.h> #include <asm/arch/at91sam9260_matrix.h> @@ -79,25 +80,57 @@ void matrix_init(void) &mat->scfg[3]); } -void at91_spl_board_init(void) +#if defined(CONFIG_BOARD_AXM) +static int at91_is_recovery(void) +{ + if ((at91_get_gpio_value(AT91_PIN_PA26) == 0) && + (at91_get_gpio_value(AT91_PIN_PA27) == 0)) + return 1; + + return 0; +} +#elif defined(CONFIG_BOARD_TAURUS) +static int at91_is_recovery(void) +{ + if (at91_get_gpio_value(AT91_PIN_PA31) == 0) + return 1; + + return 0; +} +#endif + +void spl_board_init(void) { taurus_nand_hw_init(); at91_spi0_hw_init(TAURUS_SPI_MASK); +#if defined(CONFIG_BOARD_AXM) + /* Configure LED PINs */ + at91_set_gpio_output(AT91_PIN_PA6, 0); + at91_set_gpio_output(AT91_PIN_PA8, 0); + at91_set_gpio_output(AT91_PIN_PA9, 0); + at91_set_gpio_output(AT91_PIN_PA10, 0); + at91_set_gpio_output(AT91_PIN_PA11, 0); + at91_set_gpio_output(AT91_PIN_PA12, 0); + /* Configure recovery button PINs */ + at91_set_gpio_input(AT91_PIN_PA26, 1); + at91_set_gpio_input(AT91_PIN_PA27, 1); +#elif defined(CONFIG_BOARD_TAURUS) at91_set_gpio_input(AT91_PIN_PA31, 1); +#endif - /* check if button is pressed */ - if (at91_get_gpio_value(AT91_PIN_PA31) == 0) { + /* check for recovery mode */ + if (at91_is_recovery() == 1) { struct spi_flash *flash; - debug("Recovery button pressed\n"); + puts("Recovery button pressed\n"); nand_init(); spl_nand_erase_one(0, 0); flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, 0, CONFIG_SF_DEFAULT_SPEED, - SPI_MODE_3); + CONFIG_SF_DEFAULT_MODE); if (!flash) { puts("no flash\n"); } else { @@ -108,35 +141,72 @@ void at91_spl_board_init(void) } } -void mem_init(void) +#define SDRAM_BASE_CONF (AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_3 \ + |AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \ + | AT91_SDRAMC_TWR_VAL(3) | AT91_SDRAMC_TRC_VAL(9) \ + | AT91_SDRAMC_TRP_VAL(3) | AT91_SDRAMC_TRCD_VAL(3) \ + | AT91_SDRAMC_TRAS_VAL(6) | AT91_SDRAMC_TXSR_VAL(10)) + +void sdramc_configure(unsigned int mask) { struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX; struct sdramc_reg setting; at91_sdram_hw_init(); - setting.cr = (AT91_SDRAMC_NC_9 | - AT91_SDRAMC_NR_13 | - AT91_SDRAMC_CAS_3 | - AT91_SDRAMC_NB_4 | - AT91_SDRAMC_DBW_32 | - AT91_SDRAMC_TWR_VAL(3) | - AT91_SDRAMC_TRC_VAL(9) | - AT91_SDRAMC_TRP_VAL(3) | - AT91_SDRAMC_TRCD_VAL(3) | - AT91_SDRAMC_TRAS_VAL(6) | - AT91_SDRAMC_TXSR_VAL(10)); + setting.cr = SDRAM_BASE_CONF | mask; setting.mdr = AT91_SDRAMC_MD_SDRAM; setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; - writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC | AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL, &ma->ebicsa); + sdramc_initialize(ATMEL_BASE_CS1, &setting); } + +void mem_init(void) +{ + unsigned int ram_size = 0; + + /* Configure SDRAM for 128MB */ + sdramc_configure(AT91_SDRAMC_NC_10); + + /* Do memtest for 128MB */ + ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + /* + * If 32MB or 16MB should be supported check also for + * expected mirroring at A16 and A17 + * To find mirror addresses depends how the collumns are connected + * at RAM (internaly or externaly) + * If the collumns are not in inverted order the mirror size effect + * behaves like normal SRAM with A0,A1,A2,etc. connected incremantal + */ + + /* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/ + if (ram_size == 0x800) { + printf("\n\r 64MB"); + sdramc_configure(AT91_SDRAMC_NC_9); + } else { + /* Size already initialized */ + printf("\n\r 128MB"); + } +} #endif #ifdef CONFIG_MACB +static void siemens_phy_reset(void) +{ + /* + * we need to reset PHY for 200us + * because of bug in ATMEL G20 CPU (undefined initial state of GPIO) + */ + if ((readl(AT91_ASM_RSTC_SR) & AT91_RSTC_RSTTYP) == + AT91_RSTC_RSTTYP_GENERAL) + at91_set_gpio_value(AT91_PIN_PA25, 0); /* reset eth switch */ +} + static void taurus_macb_hw_init(void) { /* Enable EMAC clock */ @@ -160,6 +230,8 @@ static void taurus_macb_hw_init(void) at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0); at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0); + siemens_phy_reset(); + at91_phy_reset(); at91_set_gpio_input(AT91_PIN_PA25, 1); /* ERST tri-state */ @@ -213,6 +285,29 @@ void spi_cs_deactivate(struct spi_slave *slave) at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1); } +#ifdef CONFIG_USB_GADGET_AT91 +#include <linux/usb/at91_udc.h> + +void at91_udp_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + /* Enable PLLB */ + writel(get_pllb_init(), &pmc->pllbr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) + ; + + /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */ + at91_periph_clk_enable(ATMEL_ID_UDP); + + writel(AT91SAM926x_PMC_UDP, &pmc->scer); +} + +struct at91_udc_data board_udc_data = { + .baseaddr = ATMEL_BASE_UDP0, +}; +#endif + int board_init(void) { /* adress of boot parameters */ @@ -225,6 +320,10 @@ int board_init(void) taurus_macb_hw_init(); #endif at91_spi0_hw_init(TAURUS_SPI_MASK); +#ifdef CONFIG_USB_GADGET_AT91 + at91_udp_hw_init(); + at91_udc_probe(&board_udc_data); +#endif return 0; } @@ -244,3 +343,97 @@ int board_eth_init(bd_t *bis) #endif return rc; } + +#if !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_BOARD_AXM) +/* + * Booting the Fallback Image. + * + * The function is used to provide and + * boot the image with the fallback + * parameters, incase if the faulty image + * in upgraded over the base firmware. + * + */ +static int upgrade_failure_fallback(void) +{ + char *partitionset_active = NULL; + char *rootfs = NULL; + char *rootfs_fallback = NULL; + char *kern_off; + char *kern_off_fb; + char *kern_size; + char *kern_size_fb; + + partitionset_active = getenv("partitionset_active"); + if (partitionset_active) { + if (partitionset_active[0] == 'A') + setenv("partitionset_active", "B"); + else + setenv("partitionset_active", "A"); + } else { + printf("partitionset_active missing.\n"); + return -ENOENT; + } + + rootfs = getenv("rootfs"); + rootfs_fallback = getenv("rootfs_fallback"); + setenv("rootfs", rootfs_fallback); + setenv("rootfs_fallback", rootfs); + + kern_size = getenv("kernel_size"); + kern_size_fb = getenv("kernel_size_fallback"); + setenv("kernel_size", kern_size_fb); + setenv("kernel_size_fallback", kern_size); + + kern_off = getenv("kernel_Off"); + kern_off_fb = getenv("kernel_Off_fallback"); + setenv("kernel_Off", kern_off_fb); + setenv("kernel_Off_fallback", kern_off); + + setenv("bootargs", '\0'); + setenv("upgrade_available", '\0'); + setenv("boot_retries", '\0'); + saveenv(); + + return 0; +} + +static int do_upgrade_available(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned long upgrade_available = 0; + unsigned long boot_retry = 0; + char boot_buf[10]; + + upgrade_available = simple_strtoul(getenv("upgrade_available"), NULL, + 10); + if (upgrade_available) { + boot_retry = simple_strtoul(getenv("boot_retries"), NULL, 10); + boot_retry++; + sprintf(boot_buf, "%lx", boot_retry); + setenv("boot_retries", boot_buf); + saveenv(); + + /* + * Here the boot_retries count is checked, and if the + * count becomes greater than 2 switch back to the + * fallback, and reset the board. + */ + + if (boot_retry > 2) { + if (upgrade_failure_fallback() == 0) + do_reset(NULL, 0, 0, NULL); + return -1; + } + } + return 0; +} + +U_BOOT_CMD( + upgrade_available, 1, 1, do_upgrade_available, + "check Siemens update", + "no parameters" +); +#endif +#endif |