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-rw-r--r--board/keymile/Kconfig11
-rw-r--r--board/keymile/common/ivm.c19
-rw-r--r--board/keymile/secu1/MAINTAINERS5
-rw-r--r--board/keymile/secu1/Makefile7
-rw-r--r--board/keymile/secu1/qts/iocsr_config.h694
-rw-r--r--board/keymile/secu1/qts/pinmux_config.h218
-rw-r--r--board/keymile/secu1/qts/pll_config.h83
-rw-r--r--board/keymile/secu1/qts/sdram_config.h327
-rw-r--r--board/keymile/secu1/socfpga.c67
-rw-r--r--board/st/stm32mp1/README520
-rw-r--r--board/toradex/apalis-imx8/MAINTAINERS1
-rw-r--r--board/toradex/apalis-imx8/README66
-rw-r--r--board/toradex/colibri-imx8x/MAINTAINERS1
-rw-r--r--board/toradex/colibri-imx8x/README66
-rw-r--r--board/toradex/colibri_imx7/MAINTAINERS1
-rw-r--r--board/toradex/verdin-imx8mm/MAINTAINERS1
-rw-r--r--board/toradex/verdin-imx8mm/README88
-rw-r--r--board/xilinx/zynq/MAINTAINERS1
-rw-r--r--board/xilinx/zynq/Makefile5
-rw-r--r--board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c4
-rw-r--r--board/xilinx/zynqmp/Makefile5
21 files changed, 1445 insertions, 745 deletions
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index 634dbbe097..7f4cad86aa 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -14,6 +14,7 @@ menu "KM Board Setup"
config KM_PNVRAM
hex "Pseudo RAM"
default 0x80000
+ depends on !ARCH_SOCFPGA
help
Start address of the pseudo non-volatile RAM for application.
@@ -21,6 +22,7 @@ config KM_PHRAM
hex "Physical RAM"
default 0x17F000 if ARM
default 0x100000 if PPC
+ depends on !ARCH_SOCFPGA
help
Start address of the physical RAM, which is the mounted /var folder.
@@ -29,6 +31,7 @@ config KM_RESERVED_PRAM
default 0x801000 if KIRKWOOD
default 0x0 if MPC83xx
default 0x1000 if MPC85xx
+ depends on !ARCH_SOCFPGA
help
Reserved physical RAM area at the end of memory for special purposes.
@@ -37,6 +40,7 @@ config KM_CRAMFS_ADDR
default 0x2400000 if KIRKWOOD
default 0xC00000 if MPC83xx
default 0x2000000 if MPC85xx
+ depends on !ARCH_SOCFPGA
help
Start address of the CRAMFS containing the Linux kernel.
@@ -44,13 +48,13 @@ config KM_KERNEL_ADDR
hex "Kernel Load Address"
default 0x2000000 if KIRKWOOD
default 0x400000 if MPC83xx
- default 0x1000000 if MPC85xx
+ default 0x1000000 if MPC85xx || ARCH_SOCFPGA
help
Address where to load Linux kernel in RAM.
config KM_FDT_ADDR
hex "FDT Load Address"
- default 0x23E0000 if KIRKWOOD
+ default 0x23E0000 if KIRKWOOD || ARCH_SOCFPGA
default 0xB80000 if MPC83xx
default 0x1F80000 if MPC85xx
help
@@ -71,7 +75,7 @@ config KM_DEF_NETDEV
config KM_COMMON_ETH_INIT
bool "Common Ethernet Initialization"
default y if KIRKWOOD || MPC83xx
- default n if MPC85xx
+ default n if MPC85xx || ARCH_SOCFPGA
help
Use the Ethernet initialization implemented in common code, which
detects if a Piggy board is present.
@@ -91,6 +95,7 @@ config KM_MVEXTSW_ADDR
config KM_IVM_BUS
int "IVM I2C Bus"
+ default 0 if ARCH_SOCFPGA
default 1 if KIRKWOOD || MPC85xx
default 2 if MPC83xx
help
diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
index fee7f03c8c..60b89fe348 100644
--- a/board/keymile/common/ivm.c
+++ b/board/keymile/common/ivm.c
@@ -328,7 +328,24 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset)
int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset)
{
int ret;
+#ifdef CONFIG_DM_I2C
+ struct udevice *eedev = NULL;
+
+ ret = i2c_get_chip_for_busnum(CONFIG_KM_IVM_BUS,
+ CONFIG_SYS_I2C_EEPROM_ADDR, 1, &eedev);
+ if (ret) {
+ printf("failed to get device for EEPROM at address 0x%02x\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ return 1;
+ }
+ ret = dm_i2c_read(eedev, 0, buf, len);
+ if (ret != 0) {
+ printf("Error: Unable to read from I2C EEPROM at address %02X:%02X\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ return 1;
+ }
+#else
i2c_set_bus_num(CONFIG_KM_IVM_BUS);
/* add deblocking here */
i2c_make_abort();
@@ -338,6 +355,6 @@ int ivm_read_eeprom(unsigned char *buf, int len, int mac_address_offset)
printf("Error reading EEprom\n");
return -2;
}
-
+#endif
return ivm_populate_env(buf, len, mac_address_offset);
}
diff --git a/board/keymile/secu1/MAINTAINERS b/board/keymile/secu1/MAINTAINERS
new file mode 100644
index 0000000000..5dc4aa6a68
--- /dev/null
+++ b/board/keymile/secu1/MAINTAINERS
@@ -0,0 +1,5 @@
+ABB SECU1 BOARD
+M: Holger Brunck <holger.brunck@ch.abb.com>
+S: Maintained
+F: include/configs/socfpga_arria5_secu1.h
+F: configs/socfpga_secu1_defconfig
diff --git a/board/keymile/secu1/Makefile b/board/keymile/secu1/Makefile
new file mode 100644
index 0000000000..4704d59e48
--- /dev/null
+++ b/board/keymile/secu1/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2020 ABB
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := socfpga.o ../common/ivm.o
diff --git a/board/keymile/secu1/qts/iocsr_config.h b/board/keymile/secu1/qts/iocsr_config.h
new file mode 100644
index 0000000000..7640c56db1
--- /dev/null
+++ b/board/keymile/secu1/qts/iocsr_config.h
@@ -0,0 +1,694 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00100000,
+ 0x40000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00040000,
+ 0x00008000,
+ 0x00080000,
+ 0x20000000,
+ 0x00000000,
+ 0x00000080,
+ 0x00020000,
+ 0x00004000,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x00002000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000020,
+ 0x00008000,
+ 0x00001000,
+ 0x00000000,
+ 0x0300C000,
+ 0x0000000C,
+ 0x00000000,
+ 0x00000000,
+ 0x00000800,
+ 0x01806018,
+ 0x00000000,
+ 0x01800000,
+ 0x00001806,
+ 0x00001806,
+ 0x00000400,
+ 0x00C0300C,
+ 0x00C03000,
+ 0x00C00003,
+ 0x00000C03,
+ 0x00300C03,
+ 0x00000200,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x00100000,
+ 0x40000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00040000,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x00000000,
+ 0x00000080,
+ 0x00020000,
+ 0x00004000,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x00002000,
+ 0x00020000,
+ 0x08000000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x00010000,
+ 0x04000000,
+ 0x00000000,
+ 0x00000010,
+ 0x00004000,
+ 0x00000800,
+ 0x00006018,
+ 0x01806000,
+ 0x00000006,
+ 0x00000008,
+ 0x00601806,
+ 0x00000400,
+ 0x0000300C,
+ 0x00C03000,
+ 0x00C00000,
+ 0x00000003,
+ 0x00000C03,
+ 0x00000200,
+ 0x00000000,
+ 0x00601800,
+ 0x80600000,
+ 0x80000001,
+ 0x00000601,
+ 0x00000100,
+ 0x00300C03,
+ 0xC0300C00,
+ 0xC0300000,
+ 0xC0000300,
+ 0x000C0300,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x00100000,
+ 0x40000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00040000,
+ 0x00008000,
+ 0x00080000,
+ 0x20000000,
+ 0x00000000,
+ 0x00000080,
+ 0x00020000,
+ 0x00004000,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000040,
+ 0x00010000,
+ 0x00002000,
+ 0x00018060,
+ 0x08000000,
+ 0x00000000,
+ 0x00000020,
+ 0x00008000,
+ 0x00001000,
+ 0x0300C030,
+ 0x00000000,
+ 0x03000000,
+ 0x0000000C,
+ 0x00C0300C,
+ 0x00000800,
+ 0x01806018,
+ 0x01806000,
+ 0x00000006,
+ 0x00000000,
+ 0x00601806,
+ 0x00000400,
+ 0x00C0300C,
+ 0x00C03000,
+ 0x00C00003,
+ 0x00000C03,
+ 0x00300C03,
+ 0x00000200,
+ 0x00601806,
+ 0x80601800,
+ 0x80600001,
+ 0x80000601,
+ 0x00180601,
+ 0x00000100,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x2CC20D80,
+ 0x082000FF,
+ 0x08028001,
+ 0x00100000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x00000000,
+ 0xC0000010,
+ 0x00C00512,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0xA2580000,
+ 0x60001800,
+ 0x00600289,
+ 0x800A2580,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x512C0000,
+ 0xB0000C00,
+ 0x00300144,
+ 0xC00512C0,
+ 0x144B0000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000050,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xA0680514,
+ 0xC3034028,
+ 0x06181A00,
+ 0x805140D0,
+ 0x34069A06,
+ 0x01A034D0,
+ 0x240D0000,
+ 0x28A06809,
+ 0x00000340,
+ 0xD000001A,
+ 0x06809240,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x80000000,
+ 0x01800A25,
+ 0x00289600,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x44B00000,
+ 0xC0003001,
+ 0x00C00512,
+ 0x00000FF0,
+ 0x512C0000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x581D8000,
+ 0x60001800,
+ 0x00600289,
+ 0x800A2580,
+ 0x16076001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x512C0000,
+ 0xB0000C00,
+ 0x00300144,
+ 0xC00512C0,
+ 0x144B0000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000050,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xA0680514,
+ 0x4D034028,
+ 0x1A681A03,
+ 0x805140D0,
+ 0x34069A06,
+ 0x01A00020,
+ 0x240D0001,
+ 0x49206809,
+ 0x034D0340,
+ 0xD01A681A,
+ 0x06805140,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x80000000,
+ 0x01800A25,
+ 0x00289600,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x44B0090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x1C864000,
+ 0x45147A07,
+ 0xA228A3DA,
+ 0xF491451E,
+ 0x0358D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x028A0680,
+ 0xDA79E47A,
+ 0x1EA228A3,
+ 0xC8F49965,
+ 0x000344B2,
+ 0x00080000,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000020,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x60120800,
+ 0x00600289,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xC228A3DC,
+ 0xF491451E,
+ 0x0344B2C8,
+ 0x821A034D,
+ 0x0000D000,
+ 0x00000680,
+ 0xD469A47A,
+ 0x1E83CF23,
+ 0xC8F71E79,
+ 0x000344B2,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000020,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820008,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010000,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x0C864000,
+ 0x79E47A03,
+ 0x92AAA3D2,
+ 0xF595551E,
+ 0x034CF3C8,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xDA79E47A,
+ 0x1EA32CA3,
+ 0xC8F69965,
+ 0x000354F3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000020,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820008,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020000,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00002000,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x0C864000,
+ 0x59647A03,
+ 0xC3CF23DC,
+ 0xF711451E,
+ 0x0358D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD459647A,
+ 0x1E83CF23,
+ 0x48F51E79,
+ 0x000348D3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000020,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820008,
+ 0x00489800,
+ 0x801A1A1A,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00008000,
+ 0x00010000,
+ 0x40002000,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00020000,
+ 0x00000000,
+ 0x00000010,
+ 0x00000020,
+ 0x00008000,
+ 0x20001000,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x00000001,
+ 0x00010000,
+ 0x04000000,
+ 0x00FF0000,
+ 0x00000000,
+ 0x00004000,
+ 0x00000800,
+ 0xC0000001,
+ 0x00141419,
+ 0x40000000,
+ 0x04000816,
+ 0x000D0000,
+ 0x00006800,
+ 0x00000340,
+ 0xD000001A,
+ 0x06800000,
+ 0x00340000,
+ 0x0001A000,
+ 0x00000D00,
+ 0x40000068,
+ 0x1A000003,
+ 0x00D00000,
+ 0x00068000,
+ 0x00003400,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x80000008,
+ 0x0000007F,
+ 0x20000000,
+ 0x00000000,
+ 0xE0000080,
+ 0x0000001F,
+ 0x00004000,
+};
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/keymile/secu1/qts/pinmux_config.h b/board/keymile/secu1/qts/pinmux_config.h
new file mode 100644
index 0000000000..a9406060ed
--- /dev/null
+++ b/board/keymile/secu1/qts/pinmux_config.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 3, /* EMACIO0 */
+ 3, /* EMACIO1 */
+ 3, /* EMACIO2 */
+ 3, /* EMACIO3 */
+ 3, /* EMACIO4 */
+ 3, /* EMACIO5 */
+ 3, /* EMACIO6 */
+ 3, /* EMACIO7 */
+ 3, /* EMACIO8 */
+ 3, /* EMACIO9 */
+ 3, /* EMACIO10 */
+ 3, /* EMACIO11 */
+ 3, /* EMACIO12 */
+ 3, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 0, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 0, /* FLASHIO2 */
+ 0, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 0, /* FLASHIO9 */
+ 0, /* FLASHIO10 */
+ 0, /* FLASHIO11 */
+ 3, /* GENERALIO0 */
+ 3, /* GENERALIO1 */
+ 3, /* GENERALIO2 */
+ 3, /* GENERALIO3 */
+ 3, /* GENERALIO4 */
+ 3, /* GENERALIO5 */
+ 3, /* GENERALIO6 */
+ 3, /* GENERALIO7 */
+ 3, /* GENERALIO8 */
+ 3, /* GENERALIO9 */
+ 3, /* GENERALIO10 */
+ 3, /* GENERALIO11 */
+ 3, /* GENERALIO12 */
+ 3, /* GENERALIO13 */
+ 3, /* GENERALIO14 */
+ 0, /* GENERALIO15 */
+ 0, /* GENERALIO16 */
+ 0, /* GENERALIO17 */
+ 0, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 3, /* MIXED1IO0 */
+ 3, /* MIXED1IO1 */
+ 3, /* MIXED1IO2 */
+ 3, /* MIXED1IO3 */
+ 3, /* MIXED1IO4 */
+ 3, /* MIXED1IO5 */
+ 3, /* MIXED1IO6 */
+ 3, /* MIXED1IO7 */
+ 3, /* MIXED1IO8 */
+ 3, /* MIXED1IO9 */
+ 3, /* MIXED1IO10 */
+ 3, /* MIXED1IO11 */
+ 3, /* MIXED1IO12 */
+ 3, /* MIXED1IO13 */
+ 3, /* MIXED1IO14 */
+ 0, /* MIXED1IO15 */
+ 0, /* MIXED1IO16 */
+ 0, /* MIXED1IO17 */
+ 0, /* MIXED1IO18 */
+ 0, /* MIXED1IO19 */
+ 0, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 1, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/keymile/secu1/qts/pll_config.h b/board/keymile/secu1/qts/pll_config.h
new file mode 100644
index 0000000000..f0c31860ca
--- /dev/null
+++ b/board/keymile/secu1/qts/pll_config.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 24
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 1
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 14
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 40000000
+#define CONFIG_HPS_CLK_OSC2_HZ 40000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 600000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 1953125
+#define CONFIG_HPS_CLK_USBCLK_HZ 12500000
+#define CONFIG_HPS_CLK_NAND_HZ 31250000
+#define CONFIG_HPS_CLK_SDMMC_HZ 3125000
+#define CONFIG_HPS_CLK_QSPI_HZ 3125000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/keymile/secu1/qts/sdram_config.h b/board/keymile/secu1/qts/sdram_config.h
new file mode 100644
index 0000000000..b0ff86ef38
--- /dev/null
+++ b/board/keymile/secu1/qts/sdram_config.h
@@ -0,0 +1,327 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x11
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x12
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x14
+#define RW_MGR_CLEAR_DQS_ENABLE 0x4B
+#define RW_MGR_EMR 0x09
+#define RW_MGR_EMR2 0x0D
+#define RW_MGR_EMR3 0x0F
+#define RW_MGR_EMR_OCD_ENABLE 0x0B
+#define RW_MGR_GUARANTEED_READ 0x4E
+#define RW_MGR_GUARANTEED_READ_CONT 0x56
+#define RW_MGR_GUARANTEED_WRITE 0x1A
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1D
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x21
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1F
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x77
+#define RW_MGR_IDLE_LOOP2 0x76
+#define RW_MGR_INIT_CKE_0 0x71
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x27
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x26
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x34
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x23
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x3B
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x3A
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x48
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x37
+#define RW_MGR_MR_CALIB 0x05
+#define RW_MGR_MR_DLL_RESET 0x07
+#define RW_MGR_MR_USER 0x03
+#define RW_MGR_NOP 0x01
+#define RW_MGR_PRECHARGE_ALL 0x16
+#define RW_MGR_READ_B2B 0x5B
+#define RW_MGR_READ_B2B_WAIT1 0x63
+#define RW_MGR_READ_B2B_WAIT2 0x6D
+#define RW_MGR_REFRESH 0x18
+
+/* Sequencer defines configuration */
+#define AFI_CLK_FREQ 301
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 6
+#define CALIB_VFIFO_OFFSET 4
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 416
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504bf
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define TINIT_CNTR0_VAL 74
+#define TINIT_CNTR1_VAL 20
+#define TINIT_CNTR2_VAL 20
+#define TRESET_CNTR0_VAL 74
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+ 0x30700000,
+ 0x38700000,
+ 0x30700000,
+ 0x20700000,
+ 0x10000853,
+ 0x10000853,
+ 0x10000953,
+ 0x10010000,
+ 0x10010380,
+ 0x10020000,
+ 0x10030000,
+ 0x10300400,
+ 0x10600000,
+ 0x10620000,
+ 0x10200400,
+ 0x10400000,
+ 0x1c900000,
+ 0x1c920000,
+ 0x1c900008,
+ 0x1c920008,
+ 0x38f00000,
+ 0x3cf00000,
+ 0x38700000,
+ 0x10100000,
+ 0x18900000,
+ 0x13500000,
+ 0x13520000,
+ 0x13500008,
+ 0x13520008,
+ 0x33700000,
+ 0x10500008
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+ 0x80180,
+ 0x100,
+ 0x80000,
+ 0x200,
+ 0x80000,
+ 0x280,
+ 0x80000,
+ 0x300,
+ 0x80000,
+ 0x380,
+ 0x80000,
+ 0x400,
+ 0x80000,
+ 0x480,
+ 0x80000,
+ 0x500,
+ 0x80000,
+ 0x600,
+ 0x8000,
+ 0x680,
+ 0xa000,
+ 0x80000,
+ 0x700,
+ 0x80000,
+ 0x780,
+ 0x80000,
+ 0x968,
+ 0xcae8,
+ 0x8e8,
+ 0x8ae8,
+ 0x988,
+ 0xea88,
+ 0x808,
+ 0xaa88,
+ 0x80000,
+ 0xcc00,
+ 0xcb80,
+ 0xe080,
+ 0xa00,
+ 0x20ae0,
+ 0x20ae0,
+ 0x20ae0,
+ 0x20ae0,
+ 0xb00,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x60c80,
+ 0x60e80,
+ 0x60e80,
+ 0x60e80,
+ 0xa000,
+ 0x8000,
+ 0x80000,
+ 0xcc00,
+ 0xcb80,
+ 0xe080,
+ 0xa00,
+ 0x30ae0,
+ 0x30ae0,
+ 0x30ae0,
+ 0x30ae0,
+ 0xb00,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x70c80,
+ 0x70e80,
+ 0x70e80,
+ 0x70e80,
+ 0xa000,
+ 0x8000,
+ 0x80000,
+ 0xf58,
+ 0x58,
+ 0x80000,
+ 0xf68,
+ 0x168,
+ 0x168,
+ 0x8168,
+ 0x40de8,
+ 0x40ee8,
+ 0x40ee8,
+ 0x40ee8,
+ 0xf68,
+ 0x168,
+ 0x168,
+ 0xa168,
+ 0x80000,
+ 0x40c88,
+ 0x40e88,
+ 0x40e88,
+ 0x40e88,
+ 0x40d68,
+ 0x40ee8,
+ 0x40ee8,
+ 0x40ee8,
+ 0xa000,
+ 0x40de8,
+ 0x40ee8,
+ 0x40ee8,
+ 0x40ee8,
+ 0x40e08,
+ 0x40e88,
+ 0x40e88,
+ 0x40e88,
+ 0xf00,
+ 0xc000,
+ 0x8000,
+ 0xe000,
+ 0x80000,
+ 0x180,
+ 0x8180,
+ 0xa180,
+ 0xc180,
+ 0x80180,
+ 0x8000,
+ 0xa000,
+ 0x80000
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/keymile/secu1/socfpga.c b/board/keymile/secu1/socfpga.c
new file mode 100644
index 0000000000..dc04a21abe
--- /dev/null
+++ b/board/keymile/secu1/socfpga.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2020 ABB
+ */
+#include <common.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+
+#include "../common/common.h"
+
+/*
+ * For FU1, the MAC address associated with the mgmt port should
+ * be the base address (as read from the IVM) + 4, and for FU2 it
+ * is + 10
+ */
+#define MAC_ADDRESS_OFFSET_FU1 4
+#define MAC_ADDRESS_OFFSET_FU2 10
+
+/*
+ * This function reads the state of GPIO40 and returns true (non-zero)
+ * if it is '1' and false(0) otherwise.
+ *
+ * This pin is routed to a pull-up on FU2 and a pull-down on
+ */
+#define GPIO_FU_DETECTION 40
+
+int secu1_is_fu2(void)
+{
+ int value;
+ int ret = gpio_request(GPIO_FU_DETECTION, "secu");
+
+ if (ret) {
+ printf("gpio: failed to request pin for FU detection\n");
+ return 1;
+ }
+ gpio_direction_input(GPIO_FU_DETECTION);
+ value = gpio_get_value(GPIO_FU_DETECTION);
+
+ if (value == 1)
+ printf("FU2 detected\n");
+ else
+ printf("FU1 detected\n");
+
+ return value;
+}
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+ ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+ return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+ if (secu1_is_fu2())
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+ MAC_ADDRESS_OFFSET_FU2);
+ else
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+ MAC_ADDRESS_OFFSET_FU1);
+
+ return 0;
+}
diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README
index 5d7465a8c8..8172d26a66 100644
--- a/board/st/stm32mp1/README
+++ b/board/st/stm32mp1/README
@@ -1,519 +1 @@
-SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-#
-# Copyright (C) 2018 STMicroelectronics - All Rights Reserved
-#
-
-U-Boot on STMicroelectronics STM32MP15x
-=======================================
-
-1. Summary
-==========
-This is a quick instruction for setup stm32mp1 boards.
-
-2. Supported devices
-====================
-U-Boot supports STMP32MP15x SoCs: STM32MP157, STM32MP153 and STM32MP151
-
-The STM32MP15x is a Cortex-A MPU aimed at various applications.
-It features:
-- Dual core Cortex-A7 application core (Single on STM32MP151)
-- 2D/3D image composition with GPU (only on STM32MP157)
-- Standard memories interface support
-- Standard connectivity, widely inherited from the STM32 MCU family
-- Comprehensive security support
-
-Everything is supported in Linux but U-Boot is limited to:
-1. UART
-2. SDCard/MMC controller (SDMMC)
-3. NAND controller (FMC)
-4. NOR controller (QSPI)
-5. USB controller (OTG DWC2)
-6. Ethernet controller
-
-And the necessary drivers
-1. I2C
-2. STPMIC1 (PMIC and regulator)
-3. Clock, Reset, Sysreset
-4. Fuse
-
-Currently the following boards are supported:
-+ stm32mp157a-avenger96.dts
-+ stm32mp157a-dk1.dts
-+ stm32mp157c-dk2.dts
-+ stm32mp157c-ed1.dts
-+ stm32mp157c-ev1.dts
-
-3. Boot Sequences
-=================
-
-BootRom => FSBL in SYSRAM => SSBL in DDR => OS (Linux Kernel)
-
-with FSBL = First Stage Bootloader
- SSBL = Second Stage Bootloader
-
-3 boot configurations are supported:
-
-1) The "Trusted" boot chain (defconfig_file : stm32mp15_trusted_defconfig)
- BootRom => FSBL = Trusted Firmware-A (TF-A) => SSBL = U-Boot
- TF-A performs a full initialization of Secure peripherals and installs a
- secure monitor.
- U-Boot is running in normal world and uses TF-A monitor
- to access to secure resources.
-
-2) The "Trusted" boot chain with OP-TEE
- (defconfig_file : stm32mp15_optee_defconfig)
- BootRom => FSBL = Trusted Firmware-A (TF-A) => SSBL = U-Boot
- TF-A performs a full initialization of Secure peripherals and installs OP-TEE
- from specific partitions (teeh, teed, teex).
- U-Boot is running in normal world and uses OP-TEE monitor to access
- to secure resources.
-
-3) The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig)
- BootRom => FSBL = U-Boot SPL => SSBL = U-Boot
- SPL has limited security initialisation
- U-Boot is running in secure mode and provide a secure monitor to the kernel
- with only PSCI support (Power State Coordination Interface defined by ARM).
-
-All the STM32MP15x boards supported by U-Boot use the same generic board
-stm32mp1 which support all the bootable devices.
-
-Each board is configurated only with the associated device tree.
-
-4. Device Tree Selection
-========================
-
-You need to select the appropriate device tree for your board,
-the supported device trees for stm32mp157 are:
-
-+ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1)
- dts: stm32mp157c-ev1
-
-+ ed1: daughter board with pmic stpmic1
- dts: stm32mp157c-ed1
-
-+ dk1: Discovery board
- dts: stm32mp157a-dk1
-
-+ dk2: Discovery board = dk1 with a BT/WiFI combo and a DSI panel
- dts: stm32mp157c-dk2
-
-+ avenger96: Avenger96 board from Arrow Electronics
- dts: stm32mp157a-avenger96
-
-5. Build Procedure
-==================
-
-1. Install required tools for U-Boot
-
- + install package needed in U-Boot makefile
- (libssl-dev, swig, libpython-dev...)
- + install ARMv7 toolchain for 32bit Cortex-A (from Linaro,
- from SDK for STM32MP15x, or any crosstoolchains from your distribution)
-
-2. Set the cross compiler:
-
- # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi-
- (you can use any gcc cross compiler compatible with U-Boot)
-
-3. Select the output directory (optional)
-
- # export KBUILD_OUTPUT=/path/to/output
-
- for example: use one output directory for each configuration
- # export KBUILD_OUTPUT=stm32mp15_trusted
- # export KBUILD_OUTPUT=stm32mp15_optee
- # export KBUILD_OUTPUT=stm32mp15_basic
-
- you can build outside of code directory:
- # export KBUILD_OUTPUT=../build/stm32mp15_trusted
-
-4. Configure U-Boot:
-
- # make <defconfig_file>
-
- - For trusted boot mode : "stm32mp15_trusted_defconfig"
- - For trusted with OP-TEE boot mode : "stm32mp15_optee_defconfig"
- - For basic boot mode: "stm32mp15_basic_defconfig"
-
-5. Configure the device-tree and build the U-Boot image:
-
- # make DEVICE_TREE=<name> all
-
- example:
- a) trusted boot on ev1
- # export KBUILD_OUTPUT=stm32mp15_trusted
- # make stm32mp15_trusted_defconfig
- # make DEVICE_TREE=stm32mp157c-ev1 all
-
- b) trusted with OP-TEE boot on dk2
- # export KBUILD_OUTPUT=stm32mp15_optee
- # make stm32mp15_optee_defconfig
- # make DEVICE_TREE=stm32mp157c-dk2 all
-
- c) basic boot on ev1
- # export KBUILD_OUTPUT=stm32mp15_basic
- # make stm32mp15_basic_defconfig
- # make DEVICE_TREE=stm32mp157c-ev1 all
-
- d) basic boot on ed1
- # export KBUILD_OUTPUT=stm32mp15_basic
- # make stm32mp15_basic_defconfig
- # make DEVICE_TREE=stm32mp157c-ed1 all
-
- e) basic boot on dk1
- # export KBUILD_OUTPUT=stm32mp15_basic
- # make stm32mp15_basic_defconfig
- # make DEVICE_TREE=stm32mp157a-dk1 all
-
- f) basic boot on avenger96
- # export KBUILD_OUTPUT=stm32mp15_basic
- # make stm32mp15_basic_defconfig
- # make DEVICE_TREE=stm32mp157a-avenger96 all
-
-6. Output files
-
- BootRom and TF-A expect binaries with STM32 image header
- SPL expects file with U-Boot uImage header
-
- So in the output directory (selected by KBUILD_OUTPUT),
- you can found the needed files:
-
- a) For Trusted boot (with or without OP-TEE)
- + FSBL = tf-a.stm32 (provided by TF-A compilation)
- + SSBL = u-boot.stm32
-
- b) For Basic boot
- + FSBL = spl/u-boot-spl.stm32
- + SSBL = u-boot.img
-
-6. Switch Setting for Boot Mode
-===============================
-
-You can select the boot mode, on the board with one switch :
-
-- on the daugther board ed1 with the switch SW1 : BOOT0, BOOT1, BOOT2
-
- -----------------------------------
- Boot Mode BOOT2 BOOT1 BOOT0
- -----------------------------------
- Reserved 0 0 0
- NOR 0 0 1
- SD-Card 1 0 1
- eMMC 0 1 0
- NAND 0 1 1
- Recovery 1 1 0
- Recovery 0 0 0
-
-- on board DK1/DK2 with the switch SW1 : BOOT0, BOOT2
- (BOOT1 forced to 0, NOR not supported)
-
- --------------------------
- Boot Mode BOOT2 BOOT0
- --------------------------
- Reserved 1 0
- SD-Card 1 1
- Recovery 0 0
-
-- Boot mode of Avenger96 can be selected using switch S3
-
- -----------------------------------
- Boot Mode BOOT2 BOOT1 BOOT0
- -----------------------------------
- Recovery 0 0 0
- NOR 0 0 1
- SD-Card 1 0 1
- eMMC 0 1 0
- NAND 0 1 1
- Reserved 1 0 0
- Recovery 1 1 0
- SD-Card 1 1 1
-
-Recovery is a boot from serial link (UART/USB) and it is used with
-STM32CubeProgrammer tool to load executable in RAM and to update the flash
-devices available on the board (NOR/NAND/eMMC/SDCARD).
-The communication between HOST and board is based on
-- for UARTs : the uart protocol used with all MCU STM32
-- for USB : based on USB DFU 1.1 (without the ST extensions used on MCU STM32)
-
-7. Prepare an SDCard
-===================
-
-The minimal requirements for STMP32MP1 boot up to U-Boot are:
-- GPT partitioning (with gdisk or with sgdisk)
-- 2 fsbl partitions, named fsbl1 and fsbl2, size at least 256KiB
-- one ssbl partition for U-Boot
-
-Then the minimal GPT partition is:
- ----- ------- --------- --------------
- | Num | Name | Size | Content |
- ----- ------- -------- ---------------
- | 1 | fsbl1 | 256 KiB | TF-A or SPL |
- | 2 | fsbl2 | 256 KiB | TF-A or SPL |
- | 3 | ssbl | enought | U-Boot |
- | * | - | - | Boot/Rootfs |
- ----- ------- --------- --------------
-
-(*) add bootable partition for extlinux.conf
- following Generic Distribution
- (doc/README.distro for use)
-
- according the used card reader select the block device
- (/dev/sdx or /dev/mmcblk0)
- in the next example I use /dev/mmcblk0
-
-for example: with gpt table with 128 entries
-
- a) remove previous formatting
- # sgdisk -o /dev/<SDCard dev>
-
- b) create minimal image
- # sgdisk --resize-table=128 -a 1 \
- -n 1:34:545 -c 1:fsbl1 \
- -n 2:546:1057 -c 2:fsbl2 \
- -n 3:1058:5153 -c 3:ssbl \
- -p /dev/<SDCard dev>
-
- you can add other partitions for kernel
- one partition rootfs for example:
- -n 4:5154: -c 4:rootfs \
-
- c) copy the FSBL (2 times) and SSBL file on the correct partition.
- in this example in partition 1 to 3
-
- for basic boot mode : <SDCard dev> = /dev/mmcblk0
- # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p1
- # dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2
- # dd if=u-boot.img of=/dev/mmcblk0p3
-
- for trusted boot mode :
- # dd if=tf-a.stm32 of=/dev/mmcblk0p1
- # dd if=tf-a.stm32 of=/dev/mmcblk0p2
- # dd if=u-boot.stm32 of=/dev/mmcblk0p3
-
-To boot from SDCard, select BootPinMode = 1 0 1 and reset.
-
-8. Prepare eMMC
-===============
-You can use U-Boot to copy binary in eMMC.
-
-In the next example, you need to boot from SDCARD and the images (u-boot-spl.stm32, u-boot.img)
-are presents on SDCARD (mmc 0) in ext4 partition 4 (bootfs).
-
-To boot from SDCard, select BootPinMode = 1 0 1 and reset.
-
-Then you update the eMMC with the next U-Boot command :
-
-a) prepare GPT on eMMC,
- example with 2 partitions, bootfs and roots:
-
- # setenv emmc_part "name=ssbl,size=2MiB;name=bootfs,type=linux,bootable,size=64MiB;name=rootfs,type=linux,size=512"
- # gpt write mmc 1 ${emmc_part}
-
-b) copy SPL on eMMC on firts boot partition
- (SPL max size is 256kB, with LBA 512, 0x200)
-
- # ext4load mmc 0:4 0xC0000000 u-boot-spl.stm32
- # mmc dev 1
- # mmc partconf 1 1 1 1
- # mmc write ${fileaddr} 0 200
- # mmc partconf 1 1 1 0
-
-c) copy U-Boot in first GPT partition of eMMC
-
- # ext4load mmc 0:4 0xC0000000 u-boot.img
- # mmc dev 1
- # part start mmc 1 1 partstart
- # mmc write ${fileaddr} ${partstart} ${filesize}
-
-To boot from eMMC, select BootPinMode = 0 1 0 and reset.
-
-9. MAC Address
-==============
-
-Please read doc/README.enetaddr for the implementation guidelines for mac id
-usage. Basically, environment has precedence over board specific storage.
-
-For STMicroelectonics board, it is retrieved in STM32MP15x otp :
-- OTP_57[31:0] = MAC_ADDR[31:0]
-- OTP_58[15:0] = MAC_ADDR[47:32]
-
-To program a MAC address on virgin OTP words above, you can use the fuse command
-on bank 0 to access to internal OTP:
-
- Prerequisite: check if a MAC address isn't yet programmed in OTP
-
- 1- check OTP: their value must be equal to 0
-
- STM32MP> fuse sense 0 57 2
- Sensing bank 0:
- Word 0x00000039: 00000000 00000000
-
- 2- check environment variable
-
- STM32MP> env print ethaddr
- ## Error: "ethaddr" not defined
-
- Example to set mac address "12:34:56:78:9a:bc"
-
- 1- Write OTP
- STM32MP> fuse prog -y 0 57 0x78563412 0x0000bc9a
-
- 2- Read OTP
- STM32MP> fuse sense 0 57 2
- Sensing bank 0:
- Word 0x00000039: 78563412 0000bc9a
-
- 3- next REBOOT :
- ### Setting environment from OTP MAC address = "12:34:56:78:9a:bc"
-
- 4 check env update
- STM32MP> env print ethaddr
- ethaddr=12:34:56:78:9a:bc
-
-warning:: This MAC address provisioning can't be executed twice on the same
- board as the OTP are protected. It is already done for the board
- provided by STMicroelectronics.
-
-10. Coprocessor firmware
-========================
-
-U-Boot can boot the coprocessor before the kernel (coprocessor early boot).
-
-A/ Manuallly by using rproc commands (update the bootcmd)
- Configurations
- # env set name_copro "rproc-m4-fw.elf"
- # env set dev_copro 0
- # env set loadaddr_copro 0xC1000000
-
- Load binary from bootfs partition (number 4) on SDCard (mmc 0)
- # ext4load mmc 0:4 ${loadaddr_copro} ${name_copro}
- => ${filesize} updated with the size of the loaded file
-
- Start M4 firmware with remote proc command
- # rproc init
- # rproc load ${dev_copro} ${loadaddr_copro} ${filesize}
- # rproc start ${dev_copro}
-
-B/ Automatically by using FIT feature and generic DISTRO bootcmd
-
- see examples in this directory :
-
- Generate FIT including kernel + device tree + M4 firmware
- with cfg with M4 boot
- $> mkimage -f fit_copro_kernel_dtb.its fit_copro_kernel_dtb.itb
-
- Then using DISTRO configuration file: see extlinux.conf to select
- the correct configuration
- => stm32mp157c-ev1-m4
- => stm32mp157c-dk2-m4
-
-11. DFU support
-===============
-
-The DFU is supported on ST board.
-The env variable dfu_alt_info is automatically build, and all
-the memory present on the ST boards are exported.
-
-The mode is started by
-
-STM32MP> dfu 0
-
-On EV1 board:
-
-STM32MP> dfu 0 list
-
-DFU alt settings list:
-dev: RAM alt: 0 name: uImage layout: RAM_ADDR
-dev: RAM alt: 1 name: devicetree.dtb layout: RAM_ADDR
-dev: RAM alt: 2 name: uramdisk.image.gz layout: RAM_ADDR
-dev: eMMC alt: 3 name: sdcard_fsbl1 layout: RAW_ADDR
-dev: eMMC alt: 4 name: sdcard_fsbl2 layout: RAW_ADDR
-dev: eMMC alt: 5 name: sdcard_ssbl layout: RAW_ADDR
-dev: eMMC alt: 6 name: sdcard_bootfs layout: RAW_ADDR
-dev: eMMC alt: 7 name: sdcard_vendorfs layout: RAW_ADDR
-dev: eMMC alt: 8 name: sdcard_rootfs layout: RAW_ADDR
-dev: eMMC alt: 9 name: sdcard_userfs layout: RAW_ADDR
-dev: eMMC alt: 10 name: emmc_fsbl1 layout: RAW_ADDR
-dev: eMMC alt: 11 name: emmc_fsbl2 layout: RAW_ADDR
-dev: eMMC alt: 12 name: emmc_ssbl layout: RAW_ADDR
-dev: eMMC alt: 13 name: emmc_bootfs layout: RAW_ADDR
-dev: eMMC alt: 14 name: emmc_vendorfs layout: RAW_ADDR
-dev: eMMC alt: 15 name: emmc_rootfs layout: RAW_ADDR
-dev: eMMC alt: 16 name: emmc_userfs layout: RAW_ADDR
-dev: MTD alt: 17 name: nor_fsbl1 layout: RAW_ADDR
-dev: MTD alt: 18 name: nor_fsbl2 layout: RAW_ADDR
-dev: MTD alt: 19 name: nor_ssbl layout: RAW_ADDR
-dev: MTD alt: 20 name: nor_env layout: RAW_ADDR
-dev: MTD alt: 21 name: nand_fsbl layout: RAW_ADDR
-dev: MTD alt: 22 name: nand_ssbl1 layout: RAW_ADDR
-dev: MTD alt: 23 name: nand_ssbl2 layout: RAW_ADDR
-dev: MTD alt: 24 name: nand_UBI layout: RAW_ADDR
-dev: VIRT alt: 25 name: OTP layout: RAW_ADDR
-dev: VIRT alt: 26 name: PMIC layout: RAW_ADDR
-
-All the supported device are exported for dfu-util tool:
-
-$> dfu-util -l
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=26, name="PMIC", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=25, name="OTP", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=24, name="nand_UBI", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=23, name="nand_ssbl2", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=22, name="nand_ssbl1", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=21, name="nand_fsbl", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=20, name="nor_env", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=19, name="nor_ssbl", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=18, name="nor_fsbl2", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=17, name="nor_fsbl1", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=16, name="emmc_userfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=15, name="emmc_rootfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=14, name="emmc_vendorfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=13, name="emmc_bootfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=12, name="emmc_ssbl", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=11, name="emmc_fsbl2", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=10, name="emmc_fsbl1", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=9, name="sdcard_userfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=8, name="sdcard_rootfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=7, name="sdcard_vendorfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=6, name="sdcard_bootfs", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=5, name="sdcard_ssbl", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=4, name="sdcard_fsbl2", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=3, name="sdcard_fsbl1", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=2, name="uramdisk.image.gz", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=1, name="devicetree.dtb", serial="002700333338511934383330"
-Found DFU: [0483:5720] ver=9999, devnum=99, cfg=1, intf=0, alt=0, name="uImage", serial="002700333338511934383330"
-
-You can update the boot device:
-
-#SDCARD
-$> dfu-util -d 0483:5720 -a 3 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 4 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 5 -D u-boot-stm32mp157c-ev1-trusted.img
-$> dfu-util -d 0483:5720 -a 6 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4
-$> dfu-util -d 0483:5720 -a 7 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4
-$> dfu-util -d 0483:5720 -a 8 -D st-image-weston-openstlinux-weston-stm32mp1.ext4
-$> dfu-util -d 0483:5720 -a 9 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4
-
-#EMMC
-$> dfu-util -d 0483:5720 -a 10 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 11 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 12 -D u-boot-stm32mp157c-ev1-trusted.img
-$> dfu-util -d 0483:5720 -a 13 -D st-image-bootfs-openstlinux-weston-stm32mp1.ext4
-$> dfu-util -d 0483:5720 -a 14 -D st-image-vendorfs-openstlinux-weston-stm32mp1.ext4
-$> dfu-util -d 0483:5720 -a 15 -D st-image-weston-openstlinux-weston-stm32mp1.ext4
-$> dfu-util -d 0483:5720 -a 16 -D st-image-userfs-openstlinux-weston-stm32mp1.ext4
-
-#NOR
-$> dfu-util -d 0483:5720 -a 17 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 18 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 19 -D u-boot-stm32mp157c-ev1-trusted.img
-
-#NAND (UBI partition used for NAND only boot or NOR + NAND boot)
-$> dfu-util -d 0483:5720 -a 21 -D tf-a-stm32mp157c-ev1-trusted.stm32
-$> dfu-util -d 0483:5720 -a 22 -D u-boot-stm32mp157c-ev1-trusted.img
-$> dfu-util -d 0483:5720 -a 23 -D u-boot-stm32mp157c-ev1-trusted.img
-$> dfu-util -d 0483:5720 -a 24 -D st-image-weston-openstlinux-weston-stm32mp1_nand_4_256_multivolume.ubi
-
-And you can also dump the OTP and the PMIC NVM with:
-
-$> dfu-util -d 0483:5720 -a 25 -U otp.bin
-$> dfu-util -d 0483:5720 -a 26 -U pmic.bin
+see doc/board/st/stm32mp1.rst
diff --git a/board/toradex/apalis-imx8/MAINTAINERS b/board/toradex/apalis-imx8/MAINTAINERS
index c9ac58b47b..feacf7eded 100644
--- a/board/toradex/apalis-imx8/MAINTAINERS
+++ b/board/toradex/apalis-imx8/MAINTAINERS
@@ -6,4 +6,5 @@ F: arch/arm/dts/fsl-imx8-apalis.dts
F: arch/arm/dts/fsl-imx8-apalis-u-boot.dtsi
F: board/toradex/apalis-imx8/
F: configs/apalis-imx8qm_defconfig
+F: doc/board/toradex/apalix-imx8.rst
F: include/configs/apalis-imx8.h
diff --git a/board/toradex/apalis-imx8/README b/board/toradex/apalis-imx8/README
deleted file mode 100644
index e6e3dcb367..0000000000
--- a/board/toradex/apalis-imx8/README
+++ /dev/null
@@ -1,66 +0,0 @@
-U-Boot for the Toradex Apalis iMX8QM V1.0B Module
-
-Quick Start
-===========
-
-- Build the ARM trusted firmware binary
-- Get scfw_tcm.bin and ahab-container.img
-- Build U-Boot
-- Load U-Boot binary using uuu
-- Flash U-Boot binary into the eMMC
-- Boot
-
-Get and Build the ARM Trusted Firmware
-======================================
-
-$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
-$ cd imx-atf/
-$ make PLAT=imx8qm bl31
-
-Get scfw_tcm.bin and ahab-container.img
-=======================================
-
-$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qm-apalis-scfw-tcm.bin?raw=true
-$ mv mx8qm-apalis-scfw-tcm.bin\?raw\=true mx8qm-apalis-scfw-tcm.bin
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
-$ chmod +x firmware-imx-8.0.bin
-$ ./firmware-imx-8.0.bin
-
-Copy the following binaries to the U-Boot folder:
-
-$ cp imx-atf/build/imx8qm/release/bl31.bin .
-$ cp u-boot/u-boot.bin .
-
-Copy the following firmware to the U-Boot folder:
-
-$ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
-
-Build U-Boot
-============
-
-$ make apalis-imx8qm_defconfig
-$ make u-boot-dtb.imx
-
-Load the U-Boot Binary Using UUU
-================================
-
-Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
-
-https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
-
-Put the module into USB recovery aka serial downloader mode, connect USB device
-to your host and execute uuu:
-
-sudo ./uuu u-boot/u-boot-dtb.imx
-
-Flash the U-Boot Binary into the eMMC
-=====================================
-
-Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
-
-load mmc 1:1 $loadaddr u-boot-dtb.imx
-setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
-mmc dev 0 1
-mmc write ${loadaddr} 0x0 ${blkcnt}
-
-Boot
diff --git a/board/toradex/colibri-imx8x/MAINTAINERS b/board/toradex/colibri-imx8x/MAINTAINERS
index e91b9975c2..f6853586c8 100644
--- a/board/toradex/colibri-imx8x/MAINTAINERS
+++ b/board/toradex/colibri-imx8x/MAINTAINERS
@@ -6,4 +6,5 @@ F: arch/arm/dts/fsl-imx8x-colibri.dts
F: arch/arm/dts/fsl-imx8x-colibri-u-boot.dtsi
F: board/toradex/colibri-imx8x/
F: configs/colibri-imx8qxp_defconfig
+F: doc/board/toradex/colibri-imx8x.rst
F: include/configs/colibri-imx8x.h
diff --git a/board/toradex/colibri-imx8x/README b/board/toradex/colibri-imx8x/README
deleted file mode 100644
index 708bb3e51c..0000000000
--- a/board/toradex/colibri-imx8x/README
+++ /dev/null
@@ -1,66 +0,0 @@
-U-Boot for the Toradex Colibri iMX8QXP V1.0B Module
-
-Quick Start
-===========
-
-- Build the ARM trusted firmware binary
-- Get scfw_tcm.bin and ahab-container.img
-- Build U-Boot
-- Load U-Boot binary using uuu
-- Flash U-Boot binary into the eMMC
-- Boot
-
-Get and Build the ARM Trusted Firmware
-======================================
-
-$ git clone -b imx_4.14.78_1.0.0_ga https://source.codeaurora.org/external/imx/imx-atf
-$ cd imx-atf/
-$ make PLAT=imx8qxp bl31
-
-Get scfw_tcm.bin and ahab-container.img
-=======================================
-
-$ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-bsp/imx-sc-firmware/files/mx8qx-colibri-scfw-tcm.bin?raw=true
-$ mv mx8qx-colibri-scfw-tcm.bin\?raw\=true mx8qx-colibri-scfw-tcm.bin
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
-$ chmod +x firmware-imx-8.0.bin
-$ ./firmware-imx-8.0.bin
-
-Copy the following binaries to the U-Boot folder:
-
-$ cp imx-atf/build/imx8qxp/release/bl31.bin .
-$ cp u-boot/u-boot.bin .
-
-Copy the following firmware to the U-Boot folder:
-
-$ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
-
-Build U-Boot
-============
-
-$ make colibri-imx8qxp_defconfig
-$ make u-boot-dtb.imx
-
-Load the U-Boot Binary Using UUU
-================================
-
-Get the latest version of the universal update utility (uuu) aka mfgtools 3.0:
-
-https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
-
-Put the module into USB recovery aka serial downloader mode, connect USB device
-to your host and execute uuu:
-
-sudo ./uuu u-boot/u-boot-dtb.imx
-
-Flash the U-Boot Binary into the eMMC
-=====================================
-
-Burn the u-boot-dtb.imx binary to the primary eMMC hardware boot area partition:
-
-load mmc 1:1 $loadaddr u-boot-dtb.imx
-setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
-mmc dev 0 1
-mmc write ${loadaddr} 0x0 ${blkcnt}
-
-Boot
diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS
index 178dece797..82246be160 100644
--- a/board/toradex/colibri_imx7/MAINTAINERS
+++ b/board/toradex/colibri_imx7/MAINTAINERS
@@ -4,6 +4,7 @@ W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
S: Maintained
F: board/toradex/colibri_imx7/
+F: doc/board/toradex/colibri_imx7.rst
F: include/configs/colibri_imx7.h
F: configs/colibri_imx7_defconfig
F: configs/colibri_imx7_emmc_defconfig
diff --git a/board/toradex/verdin-imx8mm/MAINTAINERS b/board/toradex/verdin-imx8mm/MAINTAINERS
index 3b4fae5c66..2495696e9d 100644
--- a/board/toradex/verdin-imx8mm/MAINTAINERS
+++ b/board/toradex/verdin-imx8mm/MAINTAINERS
@@ -6,4 +6,5 @@ F: arch/arm/dts/imx8mm-verdin.dts
F: arch/arm/dts/imx8mm-verdin-u-boot.dtsi
F: board/toradex/verdin-imx8mm/
F: configs/verdin-imx8mm_defconfig
+F: doc/board/toradex/verdin-imx8mm.rst
F: include/configs/verdin-imx8mm.h
diff --git a/board/toradex/verdin-imx8mm/README b/board/toradex/verdin-imx8mm/README
deleted file mode 100644
index 1dac969476..0000000000
--- a/board/toradex/verdin-imx8mm/README
+++ /dev/null
@@ -1,88 +0,0 @@
-U-Boot for the Toradex Verdin iMX8M Mini Module
-
-Quick Start
-===========
-
-- Build the ARM trusted firmware binary
-- Get the DDR firmware
-- Build U-Boot
-- Flash to eMMC
-- Boot
-
-Get and Build the ARM Trusted Firmware (Trusted Firmware A)
-===========================================================
-
-$ echo "Downloading and building TF-A..."
-$ git clone -b imx_4.14.98_2.3.0 https://source.codeaurora.org/external/imx/imx-atf
-$ cd imx-atf
-
-Please edit `plat/imx/imx8mm/include/platform_def.h` so it contains proper
-values for UART configuration and BL31 base address (correct values listed
-below):
-#define BL31_BASE 0x910000
-#define IMX_BOOT_UART_BASE 0x30860000
-#define DEBUG_CONSOLE 1
-
-Then build ATF (TF-A):
-$ make PLAT=imx8mm bl31
-
-Get the DDR Firmware
-====================
-
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.4.1.bin
-$ chmod +x firmware-imx-8.4.1.bin
-$ ./firmware-imx-8.4.1.bin
-$ cp firmware-imx-8.4.1/firmware/ddr/synopsys/lpddr4*.bin ./
-
-Build U-Boot
-============
-
-$ export CROSS_COMPILE=aarch64-linux-gnu-
-$ make verdin-imx8mm_defconfig
-$ make flash.bin
-
-Flash to eMMC
-=============
-
-> tftpboot ${loadaddr} flash.bin
-> setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
-> mmc dev 0 1 && mmc write ${loadaddr} 0x2 ${blkcnt}
-
-As a convenience, instead of the last two commands one may also use the update
-U-Boot wrapper:
-> run update_uboot
-
-Boot
-====
-
-ATF, U-boot proper and u-boot.dtb images are packed into FIT image,
-which is loaded and parsed by SPL.
-
-Boot sequence is:
-SPL ---> ATF (TF-A) ---> U-boot proper
-
-Output:
-U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
-Normal Boot
-Trying to boot from MMC1
-NOTICE: Configuring TZASC380
-NOTICE: RDC off
-NOTICE: BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty
-NOTICE: BL31: Built : 01:11:41, Jan 25 2020
-NOTICE: sip svc init
-
-
-U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
-
-CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz
-Reset cause: POR
-DRAM: 2 GiB
-MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
-Loading Environment from MMC... OK
-In: serial
-Out: serial
-Err: serial
-Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.0A, Serial# 06535149
-Net: eth0: ethernet@30be0000
-Hit any key to stop autoboot: 0
-Verdin iMX8MM #
diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS
index fc6463a8c6..78bcd84d30 100644
--- a/board/xilinx/zynq/MAINTAINERS
+++ b/board/xilinx/zynq/MAINTAINERS
@@ -5,3 +5,4 @@ F: arch/arm/dts/zynq-*
F: board/xilinx/zynq/
F: include/configs/zynq*.h
F: configs/zynq_*_defconfig
+F: configs/xilinx_zynq_*
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index 6a2acee108..096a7aceb9 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -13,6 +13,11 @@ spl/board/xilinx/zynq/ps_init_gpl.o board/xilinx/zynq/ps_init_gpl.o: $(PS_INIT_F
$(CC) $(c_flags) -I $(srctree)/$(src) -c -o $@ $^
endif
+DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
+ifeq ($(DEVICE_TREE),)
+DEVICE_TREE := unset
+endif
+
ifeq ($(init-objs),)
hw-platform-y :=$(shell echo $(DEVICE_TREE))
init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
diff --git a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
index 7c6bc9fa3f..a376ba574e 100644
--- a/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo-z7/ps7_init_gpl.c
@@ -219,8 +219,8 @@ static unsigned long ps7_mio_init_data_3_0[] = {
EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U),
EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
- EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001200U),
- EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001200U),
+ EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
+ EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002F0037U),
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 174f4ed24b..398c6aaa45 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -13,6 +13,11 @@ spl/board/xilinx/zynqmp/ps_init_gpl.o board/xilinx/zynqmp/ps_init_gpl.o: $(PS_IN
$(CC) $(c_flags) -I $(srctree)/$(src) -c -o $@ $^
endif
+DEVICE_TREE ?= $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%)
+ifeq ($(DEVICE_TREE),)
+DEVICE_TREE := unset
+endif
+
ifeq ($(init-objs),)
hw-platform-y :=$(shell echo $(DEVICE_TREE))
init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
generated by cgit (git 2.34.1) at 2025-01-26 07:44:47 +0000