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-rw-r--r--board/coreboot/coreboot/Kconfig28
-rw-r--r--board/coreboot/coreboot/Makefile2
-rw-r--r--board/coreboot/coreboot/coreboot.c17
-rw-r--r--board/coreboot/coreboot/start.S (renamed from board/coreboot/coreboot/coreboot_start.S)0
-rw-r--r--board/davinci/da8xxevm/README.da85019
-rw-r--r--board/freescale/common/ns_access.c167
-rw-r--r--board/freescale/ls1012ardb/ls1012ardb.c85
-rw-r--r--board/freescale/ls1046aqds/ls1046aqds.c3
-rw-r--r--board/freescale/ls1046ardb/ls1046ardb.c3
-rw-r--r--board/qualcomm/dragonboard410c/dragonboard410c.c55
-rw-r--r--board/sandbox/sandbox.c9
-rw-r--r--board/st/stm32f429-discovery/stm32f429-discovery.c2
-rw-r--r--board/st/stm32f429-evaluation/stm32f429-evaluation.c2
-rw-r--r--board/st/stm32f469-discovery/stm32f469-discovery.c2
-rw-r--r--board/st/stm32f746-disco/stm32f746-disco.c35
-rw-r--r--board/st/stm32mp1/stm32mp1.c4
16 files changed, 347 insertions, 86 deletions
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
index cfa1d50ee4..5bd6465d98 100644
--- a/board/coreboot/coreboot/Kconfig
+++ b/board/coreboot/coreboot/Kconfig
@@ -9,35 +9,15 @@ config SYS_VENDOR
config SYS_SOC
default "coreboot"
+config SYS_CONFIG_NAME
+ default "coreboot"
+
config SYS_TEXT_BASE
default 0x01110000
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- imply SPI_FLASH_ATMEL
- imply SPI_FLASH_EON
- imply SPI_FLASH_GIGADEVICE
- imply SPI_FLASH_MACRONIX
- imply SPI_FLASH_SPANSION
- imply SPI_FLASH_STMICRO
- imply SPI_FLASH_SST
- imply SPI_FLASH_WINBOND
-
-comment "coreboot-specific options"
-
-config SYS_CONFIG_NAME
- string "Board configuration file"
- default "qemu-x86"
- help
- This option selects the board configuration file in include/configs/
- directory to be used to build U-Boot for coreboot.
-
-config DEFAULT_DEVICE_TREE
- string "Board Device Tree Source (dts) file"
- default "qemu-x86_i440fx"
- help
- This option selects the board Device Tree Source (dts) file in
- arch/x86/dts/ directory to be used to build U-Boot for coreboot.
+ select BOARD_EARLY_INIT_R
config SYS_CAR_ADDR
hex "Board specific Cache-As-RAM (CAR) address"
diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile
index ea0f3ee1ae..8db7cc62f3 100644
--- a/board/coreboot/coreboot/Makefile
+++ b/board/coreboot/coreboot/Makefile
@@ -10,4 +10,4 @@
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
-obj-y += coreboot_start.o
+obj-y += start.o coreboot.o
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
new file mode 100644
index 0000000000..ed5606d4a4
--- /dev/null
+++ b/board/coreboot/coreboot/coreboot.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+
+int board_early_init_r(void)
+{
+ /*
+ * Make sure PCI bus is enumerated so that peripherals on the PCI bus
+ * can be discovered by their drivers
+ */
+ pci_init();
+
+ return 0;
+}
diff --git a/board/coreboot/coreboot/coreboot_start.S b/board/coreboot/coreboot/start.S
index aa702622d4..aa702622d4 100644
--- a/board/coreboot/coreboot/coreboot_start.S
+++ b/board/coreboot/coreboot/start.S
diff --git a/board/davinci/da8xxevm/README.da850 b/board/davinci/da8xxevm/README.da850
index 519267e2f0..f24e8b5342 100644
--- a/board/davinci/da8xxevm/README.da850
+++ b/board/davinci/da8xxevm/README.da850
@@ -112,6 +112,25 @@ uflash writes the AIS image at offset 117. For compatibility with uflash,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is set to take into account this
offset, and the dd command is adjusted accordingly.
+Flashing the images to NOR
+==========================
+NOR Flash is XIP (execute-in-place), so no AIS (or SPL) is needed. The
+u-boot.bin is directy flashed, but CONFIT_DA850_LOWLEVEL must be set
+to initialize hardware that's normally done by SPL.
+
+For this case, CONFIG_SYS_TEXT_BASE=0x60000000 which is the address to
+which the bootloader jumps when powered on.
+
+Example:
+For the da850evm, there is a defconfig setup to use the NOR flash on
+the UI expander board called da850evm_direct_nor_defconfig.
+
+Flash to NOR directly using
+sudo mono ./sfh_OMAP-L138.exe -p /dev/ttyUSB0 -flash_noubl
+ -flashType NOR u-boot.bin
+
+SW7:5 through SW7:7 should be switched on and all others off.
+
Recovery
========
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
index 79fa6aa2e7..0e6f2135b4 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -9,6 +9,173 @@
#include <asm/arch/ns_access.h>
#include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_ARCH_LS1021A
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_ALL_RW },
+ { CSU_CSLX_GDI, CSU_ALL_RW },
+ { CSU_CSLX_DDI, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+ { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+
+#else
+static struct csu_ns_dev ns_dev[] = {
+ {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
+ {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
+ {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
+ {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
+ {CSU_CSLX_OCRAM, CSU_ALL_RW},
+ {CSU_CSLX_GIC, CSU_ALL_RW},
+ {CSU_CSLX_PCIE1, CSU_ALL_RW},
+ {CSU_CSLX_OCRAM2, CSU_ALL_RW},
+ {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
+ {CSU_CSLX_PCIE2, CSU_ALL_RW},
+ {CSU_CSLX_SATA, CSU_ALL_RW},
+ {CSU_CSLX_USB1, CSU_ALL_RW},
+ {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
+ {CSU_CSLX_PCIE3, CSU_ALL_RW},
+ {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
+ {CSU_CSLX_USB3, CSU_ALL_RW},
+ {CSU_CSLX_USB2, CSU_ALL_RW},
+ {CSU_CSLX_PFE, CSU_ALL_RW},
+ {CSU_CSLX_SERDES, CSU_ALL_RW},
+ {CSU_CSLX_QDMA, CSU_ALL_RW},
+ {CSU_CSLX_LPUART2, CSU_ALL_RW},
+ {CSU_CSLX_LPUART1, CSU_ALL_RW},
+ {CSU_CSLX_LPUART4, CSU_ALL_RW},
+ {CSU_CSLX_LPUART3, CSU_ALL_RW},
+ {CSU_CSLX_LPUART6, CSU_ALL_RW},
+ {CSU_CSLX_LPUART5, CSU_ALL_RW},
+ {CSU_CSLX_DSPI1, CSU_ALL_RW},
+ {CSU_CSLX_QSPI, CSU_ALL_RW},
+ {CSU_CSLX_ESDHC, CSU_ALL_RW},
+ {CSU_CSLX_IFC, CSU_ALL_RW},
+ {CSU_CSLX_I2C1, CSU_ALL_RW},
+ {CSU_CSLX_I2C3, CSU_ALL_RW},
+ {CSU_CSLX_I2C2, CSU_ALL_RW},
+ {CSU_CSLX_DUART2, CSU_ALL_RW},
+ {CSU_CSLX_DUART1, CSU_ALL_RW},
+ {CSU_CSLX_WDT2, CSU_ALL_RW},
+ {CSU_CSLX_WDT1, CSU_ALL_RW},
+ {CSU_CSLX_EDMA, CSU_ALL_RW},
+ {CSU_CSLX_SYS_CNT, CSU_ALL_RW},
+ {CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
+ {CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
+ {CSU_CSLX_DDR, CSU_ALL_RW},
+ {CSU_CSLX_QUICC, CSU_ALL_RW},
+ {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
+ {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
+ {CSU_CSLX_SFP, CSU_ALL_RW},
+ {CSU_CSLX_TMU, CSU_ALL_RW},
+ {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
+ {CSU_CSLX_SCFG, CSU_ALL_RW},
+ {CSU_CSLX_FM, CSU_ALL_RW},
+ {CSU_CSLX_SEC5_5, CSU_ALL_RW},
+ {CSU_CSLX_BM, CSU_ALL_RW},
+ {CSU_CSLX_QM, CSU_ALL_RW},
+ {CSU_CSLX_GPIO2, CSU_ALL_RW},
+ {CSU_CSLX_GPIO1, CSU_ALL_RW},
+ {CSU_CSLX_GPIO4, CSU_ALL_RW},
+ {CSU_CSLX_GPIO3, CSU_ALL_RW},
+ {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
+ {CSU_CSLX_CSU, CSU_ALL_RW},
+ {CSU_CSLX_IIC4, CSU_ALL_RW},
+ {CSU_CSLX_WDT4, CSU_ALL_RW},
+ {CSU_CSLX_WDT3, CSU_ALL_RW},
+ {CSU_CSLX_ESDHC2, CSU_ALL_RW},
+ {CSU_CSLX_WDT5, CSU_ALL_RW},
+ {CSU_CSLX_SAI2, CSU_ALL_RW},
+ {CSU_CSLX_SAI1, CSU_ALL_RW},
+ {CSU_CSLX_SAI4, CSU_ALL_RW},
+ {CSU_CSLX_SAI3, CSU_ALL_RW},
+ {CSU_CSLX_FTM2, CSU_ALL_RW},
+ {CSU_CSLX_FTM1, CSU_ALL_RW},
+ {CSU_CSLX_FTM4, CSU_ALL_RW},
+ {CSU_CSLX_FTM3, CSU_ALL_RW},
+ {CSU_CSLX_FTM6, CSU_ALL_RW},
+ {CSU_CSLX_FTM5, CSU_ALL_RW},
+ {CSU_CSLX_FTM8, CSU_ALL_RW},
+ {CSU_CSLX_FTM7, CSU_ALL_RW},
+ {CSU_CSLX_DSCR, CSU_ALL_RW},
+};
+#endif
+
void set_devices_ns_access(unsigned long index, u16 val)
{
u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index a1668b9728..888f8500d4 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -25,6 +25,9 @@
DECLARE_GLOBAL_DATA_PTR;
+#define BOOT_FROM_UPPER_BANK 0x2
+#define BOOT_FROM_LOWER_BANK 0x1
+
int checkboard(void)
{
#ifdef CONFIG_TARGET_LS1012ARDB
@@ -211,3 +214,85 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
+
+static int switch_to_bank1(void)
+{
+ u8 data;
+ int ret;
+
+ i2c_set_bus_num(0);
+
+ data = 0xf4;
+ ret = i2c_write(0x24, 0x3, 1, &data, 1);
+ if (ret) {
+ printf("i2c write error to chip : %u, addr : %u, data : %u\n",
+ 0x24, 0x3, data);
+ }
+
+ return ret;
+}
+
+static int switch_to_bank2(void)
+{
+ u8 data;
+ int ret;
+
+ i2c_set_bus_num(0);
+
+ data = 0xfc;
+ ret = i2c_write(0x24, 0x7, 1, &data, 1);
+ if (ret) {
+ printf("i2c write error to chip : %u, addr : %u, data : %u\n",
+ 0x24, 0x7, data);
+ goto err;
+ }
+
+ data = 0xf5;
+ ret = i2c_write(0x24, 0x3, 1, &data, 1);
+ if (ret) {
+ printf("i2c write error to chip : %u, addr : %u, data : %u\n",
+ 0x24, 0x3, data);
+ }
+err:
+ return ret;
+}
+
+static int convert_flash_bank(int bank)
+{
+ int ret = 0;
+
+ switch (bank) {
+ case BOOT_FROM_UPPER_BANK:
+ ret = switch_to_bank2();
+ break;
+ case BOOT_FROM_LOWER_BANK:
+ ret = switch_to_bank1();
+ break;
+ default:
+ ret = CMD_RET_USAGE;
+ break;
+ };
+
+ return ret;
+}
+
+static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc != 2)
+ return CMD_RET_USAGE;
+ if (strcmp(argv[1], "1") == 0)
+ convert_flash_bank(BOOT_FROM_LOWER_BANK);
+ else if (strcmp(argv[1], "2") == 0)
+ convert_flash_bank(BOOT_FROM_UPPER_BANK);
+ else
+ return CMD_RET_USAGE;
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ boot_bank, 2, 0, flash_bank_cmd,
+ "Flash bank Selection Control",
+ "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
+);
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index b765f07f85..0da82381af 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -14,6 +14,7 @@
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <ahci.h>
#include <hwconfig.h>
#include <mmc.h>
@@ -309,6 +310,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
+ fdt_fixup_icid(blob);
+
reg = QIXIS_READ(brdcfg[0]);
reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index feb5c2448a..0a73fe859d 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -11,6 +11,7 @@
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ppa.h>
#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <hwconfig.h>
#include <ahci.h>
#include <mmc.h>
@@ -174,6 +175,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
#endif
+ fdt_fixup_icid(blob);
+
return 0;
}
#endif
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
index e7ead57f0d..53e231e55a 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -10,6 +10,9 @@
#include <usb.h>
#include <asm/gpio.h>
#include <fdt_support.h>
+#include <environment.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/misc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -148,38 +151,38 @@ int board_init(void)
return 0;
}
+/* Fixup of DTB for Linux Kernel
+ * 1. Fixup installed DRAM.
+ * 2. Fixup WLAN/BT Mac address:
+ * First, check if MAC addresses for WLAN/BT exists as environemnt
+ * variables wlanaddr,btaddr. if not, generate a unique address.
+ */
+
int ft_board_setup(void *blob, bd_t *bd)
{
- int offset, len, i;
- const char *mac;
- struct {
- const char *compatible;
- const char *property;
- } fix[] = {
- [0] = {
- /* update the kernel's dtb with wlan mac */
- .compatible = "qcom,wcnss-wlan",
- .property = "local-mac-address",
- },
- [1] = {
- /* update the kernel's dtb with bt mac */
- .compatible = "qcom,wcnss-bt",
- .property = "local-bd-address",
- },
+ u8 mac[ARP_HLEN];
+
+ msm_fixup_memory(blob);
+
+ if (!eth_env_get_enetaddr("wlanaddr", mac)) {
+ msm_generate_mac_addr(mac);
};
- for (i = 0; i < sizeof(fix) / sizeof(fix[0]); i++) {
- offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- fix[i].compatible);
- if (offset < 0)
- continue;
+ do_fixup_by_compat(blob, "qcom,wcnss-wlan",
+ "local-mac-address", mac, ARP_HLEN, 1);
- mac = fdt_getprop(gd->fdt_blob, offset, fix[i].property, &len);
- if (mac)
- do_fixup_by_compat(blob, fix[i].compatible,
- fix[i].property, mac, ARP_HLEN, 1);
- }
+ if (!eth_env_get_enetaddr("btaddr", mac)) {
+ msm_generate_mac_addr(mac);
+
+/* The BD address is same as WLAN MAC address but with
+ * least significant bit flipped.
+ */
+ mac[0] ^= 0x01;
+ };
+
+ do_fixup_by_compat(blob, "qcom,wcnss-bt",
+ "local-bd-address", mac, ARP_HLEN, 1);
return 0;
}
diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c
index 195f620834..0e87674826 100644
--- a/board/sandbox/sandbox.c
+++ b/board/sandbox/sandbox.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <cros_ec.h>
#include <dm.h>
+#include <led.h>
#include <os.h>
#include <asm/test.h>
#include <asm/u-boot-sandbox.h>
@@ -47,6 +48,14 @@ int dram_init(void)
return 0;
}
+int board_init(void)
+{
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ return 0;
+}
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c
index e800d70f76..500dc5fe3a 100644
--- a/board/st/stm32f429-discovery/stm32f429-discovery.c
+++ b/board/st/stm32f429-discovery/stm32f429-discovery.c
@@ -54,7 +54,7 @@ int board_early_init_f(void)
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}
diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c
index fd2109b27c..8ab2fa5d59 100644
--- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c
+++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c
@@ -48,7 +48,7 @@ int board_early_init_f(void)
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}
diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c
index a457f90952..70d23d90f4 100644
--- a/board/st/stm32f469-discovery/stm32f469-discovery.c
+++ b/board/st/stm32f469-discovery/stm32f469-discovery.c
@@ -48,7 +48,7 @@ int board_early_init_f(void)
int board_init(void)
{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index e21cfc6e49..7c9b1ad82a 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -21,25 +21,10 @@
DECLARE_GLOBAL_DATA_PTR;
-int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size)
-{
- int mr_node;
-
- mr_node = fdt_path_offset(gd->fdt_blob, "/memory");
- if (mr_node < 0)
- return mr_node;
- *mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node,
- "reg", 0, mr_size, false);
- debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size);
-
- return 0;
-}
int dram_init(void)
{
- int rv;
- fdt_addr_t mr_base, mr_size;
-
#ifndef CONFIG_SUPPORT_SPL
+ int rv;
struct udevice *dev;
rv = uclass_get_device(UCLASS_RAM, 0, &dev);
if (rv) {
@@ -48,26 +33,12 @@ int dram_init(void)
}
#endif
- rv = get_memory_base_size(&mr_base, &mr_size);
- if (rv)
- return rv;
- gd->ram_size = mr_size;
- gd->ram_top = mr_base;
-
- return rv;
+ return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
- fdt_addr_t mr_base, mr_size;
- get_memory_base_size(&mr_base, &mr_size);
- /*
- * Fill in global info with description of SRAM configuration
- */
- gd->bd->bi_dram[0].start = mr_base;
- gd->bd->bi_dram[0].size = mr_size;
-
- return 0;
+ return fdtdec_setup_memory_banksize();
}
int board_early_init_f(void)
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index cc39fa6df9..bfc8ab64d3 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -4,6 +4,7 @@
*/
#include <config.h>
#include <common.h>
+#include <led.h>
#include <asm/arch/stm32.h>
/*
@@ -22,5 +23,8 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
+ if (IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
return 0;
}
generated by cgit (git 2.34.1) at 2025-01-01 13:24:00 +0000