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-rw-r--r--board/BuR/kwb/board.c27
-rw-r--r--board/gdsys/405ep/dlvision-10g.c67
-rw-r--r--board/gdsys/405ep/iocon.c8
-rw-r--r--board/gdsys/common/Makefile9
-rw-r--r--board/gdsys/common/adv7611.c177
-rw-r--r--board/gdsys/common/adv7611.h13
-rw-r--r--board/gdsys/common/ch7301.c64
-rw-r--r--board/gdsys/common/ch7301.h13
-rw-r--r--board/gdsys/common/dp501.c27
-rw-r--r--board/gdsys/common/fanctrl.c32
-rw-r--r--board/gdsys/common/fanctrl.h13
-rw-r--r--board/gdsys/common/ioep-fpga.c232
-rw-r--r--board/gdsys/common/ioep-fpga.h14
-rw-r--r--board/gdsys/common/osd.c194
-rw-r--r--board/gdsys/common/osd.h1
-rw-r--r--board/gdsys/mpc8308/Kconfig13
-rw-r--r--board/gdsys/mpc8308/MAINTAINERS4
-rw-r--r--board/gdsys/mpc8308/Makefile1
-rw-r--r--board/gdsys/mpc8308/hrcon.c293
-rw-r--r--board/gdsys/mpc8308/strider.c479
-rw-r--r--board/gdsys/p1022/controlcenterd.c5
-rw-r--r--board/silica/pengwyn/board.c6
-rw-r--r--board/ti/am335x/mux.c2
23 files changed, 1323 insertions, 371 deletions
diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c
index 039ec207c2..ad74ff299c 100644
--- a/board/BuR/kwb/board.c
+++ b/board/BuR/kwb/board.c
@@ -47,10 +47,6 @@
#define RSTCTRL_FORCE_PWR_NEN 0x0404
#define RSTCTRL_CAN_STB 0x4040
-#define VXWORKS_BOOTLINE 0x80001100
-#define DEFAULT_BOOTLINE "cpsw(0,0):pme/vxWorks"
-#define VXWORKS_USER "u=vxWorksFTP pw=vxWorks tn=vxtarget"
-
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPL_BUILD)
@@ -281,20 +277,15 @@ int board_late_init(void)
} else {
puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
}
- /* setup vxworks bootline */
- char *vxworksbootline = (char *)VXWORKS_BOOTLINE;
- sprintf(vxworksbootline,
- "%s h=%s e=%s:%s g=%s %s o=0x%08x;0x%08x;0x%08x;0x%08x",
- DEFAULT_BOOTLINE,
- getenv("serverip"),
- getenv("ipaddr"), getenv("netmask"),
- getenv("gatewayip"),
- VXWORKS_USER,
- (unsigned int) gd->fb_base-0x20,
- (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20),
- (u32)getenv_ulong("vx_romfsbase", 16, 0),
- (u32)getenv_ulong("vx_romfssize", 16, 0));
-
+ /* setup othbootargs for bootvx-command (vxWorks bootline) */
+ char othbootargs[128];
+ snprintf(othbootargs, sizeof(othbootargs),
+ "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
+ (unsigned int) gd->fb_base-0x20,
+ (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20),
+ (u32)getenv_ulong("vx_romfsbase", 16, 0),
+ (u32)getenv_ulong("vx_romfssize", 16, 0));
+ setenv("othbootargs", othbootargs);
/*
* reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
* expect that vectors are there, original u-boot moves them to _start
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index 35dfbbc577..54c7eb3a12 100644
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -25,17 +25,19 @@
#define LATCH2_MC2_PRESENT_N 0x0080
enum {
- UNITTYPE_VIDEO_USER = 0,
- UNITTYPE_MAIN_USER = 1,
- UNITTYPE_VIDEO_SERVER = 2,
- UNITTYPE_MAIN_SERVER = 3,
+ UNITTYPE_MAIN = 1<<0,
+ UNITTYPE_SERVER = 1<<1,
+ UNITTYPE_DISPLAYPORT = 1<<2,
};
enum {
HWVER_101 = 0,
HWVER_110 = 1,
- HWVER_120 = 2,
- HWVER_130 = 3,
+ HWVER_130 = 2,
+ HWVER_140 = 3,
+ HWVER_150 = 4,
+ HWVER_160 = 5,
+ HWVER_170 = 6,
};
enum {
@@ -121,43 +123,48 @@ static void print_fpga_info(unsigned dev)
feature_carriers = (fpga_features >> 2) & 0x0003;
feature_video_channels = fpga_features & 0x0003;
- switch (unit_type) {
- case UNITTYPE_VIDEO_USER:
- printf("Videochannel Userside");
- break;
+ if (unit_type & UNITTYPE_MAIN)
+ printf("Mainchannel ");
+ else
+ printf("Videochannel ");
- case UNITTYPE_MAIN_USER:
- printf("Mainchannel Userside");
- break;
+ if (unit_type & UNITTYPE_SERVER)
+ printf("Serverside ");
+ else
+ printf("Userside ");
+
+ if (unit_type & UNITTYPE_DISPLAYPORT)
+ printf("DisplayPort");
+ else
+ printf("DVI-DL");
- case UNITTYPE_VIDEO_SERVER:
- printf("Videochannel Serverside");
+ switch (hardware_version) {
+ case HWVER_101:
+ printf(" HW-Ver 1.01\n");
break;
- case UNITTYPE_MAIN_SERVER:
- printf("Mainchannel Serverside");
+ case HWVER_110:
+ printf(" HW-Ver 1.10-1.20\n");
break;
- default:
- printf("UnitType %d(not supported)", unit_type);
+ case HWVER_130:
+ printf(" HW-Ver 1.30\n");
break;
- }
- switch (hardware_version) {
- case HWVER_101:
- printf(" HW-Ver 1.01\n");
+ case HWVER_140:
+ printf(" HW-Ver 1.40-1.43\n");
break;
- case HWVER_110:
- printf(" HW-Ver 1.10-1.12\n");
+ case HWVER_150:
+ printf(" HW-Ver 1.50\n");
break;
- case HWVER_120:
- printf(" HW-Ver 1.20\n");
+ case HWVER_160:
+ printf(" HW-Ver 1.60-1.61\n");
break;
- case HWVER_130:
- printf(" HW-Ver 1.30\n");
+ case HWVER_170:
+ printf(" HW-Ver 1.70\n");
break;
default:
@@ -260,7 +267,7 @@ int last_stage_init(void)
if (get_mc2_present())
print_fpga_info(1);
- if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
+ if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER)
return 0;
if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 3a51d864cd..7484624d13 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -381,7 +381,7 @@ int last_stage_init(void)
ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
}
- /* wait for FPGA done */
+ /* wait for FPGA done; then reset FPGA */
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
unsigned int ctr = 0;
@@ -396,6 +396,12 @@ int last_stage_init(void)
break;
}
}
+
+ pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
+ pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
+ udelay(10);
+ pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
+ MCFPGA_RESET_N);
}
if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index 49579434df..ce230455c8 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -9,7 +9,10 @@ obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
obj-$(CONFIG_IO) += miiphybb.o
obj-$(CONFIG_IO64) += miiphybb.o
-obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o
-obj-$(CONFIG_DLVISION_10G) += osd.o
+obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o
+obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
-obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o
+obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
+obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
+obj-$(CONFIG_STRIDER) += fanctrl.o
+obj-$(CONFIG_STRIDER_CON) += osd.o
diff --git a/board/gdsys/common/adv7611.c b/board/gdsys/common/adv7611.c
new file mode 100644
index 0000000000..b728274cce
--- /dev/null
+++ b/board/gdsys/common/adv7611.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#define ADV7611_I2C_ADDR 0x4c
+#define ADV7611_RDINFO 0x2051
+
+/*
+ * ADV7611 I2C Addresses in u-boot notation
+ */
+enum {
+ CP_I2C_ADDR = 0x22,
+ DPLL_I2C_ADDR = 0x26,
+ KSV_I2C_ADDR = 0x32,
+ HDMI_I2C_ADDR = 0x34,
+ EDID_I2C_ADDR = 0x36,
+ INFOFRAME_I2C_ADDR = 0x3e,
+ CEC_I2C_ADDR = 0x40,
+ IO_I2C_ADDR = ADV7611_I2C_ADDR,
+};
+
+/*
+ * Global Control Registers
+ */
+enum {
+ IO_RD_INFO_MSB = 0xea,
+ IO_RD_INFO_LSB = 0xeb,
+ IO_CEC_ADDR = 0xf4,
+ IO_INFOFRAME_ADDR = 0xf5,
+ IO_DPLL_ADDR = 0xf8,
+ IO_KSV_ADDR = 0xf9,
+ IO_EDID_ADDR = 0xfa,
+ IO_HDMI_ADDR = 0xfb,
+ IO_CP_ADDR = 0xfd,
+};
+
+int adv7611_i2c[] = CONFIG_SYS_ADV7611_I2C;
+
+int adv7611_probe(unsigned int screen)
+{
+ int old_bus = i2c_get_bus_num();
+ unsigned int rd_info;
+ int res = 0;
+
+ i2c_set_bus_num(adv7611_i2c[screen]);
+
+ rd_info = (i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_MSB) << 8)
+ | i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_LSB);
+
+ if (rd_info != ADV7611_RDINFO) {
+ res = -1;
+ goto out;
+ }
+
+ /*
+ * set I2C addresses to default values
+ */
+ i2c_reg_write(IO_I2C_ADDR, IO_CEC_ADDR, CEC_I2C_ADDR << 1);
+ i2c_reg_write(IO_I2C_ADDR, IO_INFOFRAME_ADDR, INFOFRAME_I2C_ADDR << 1);
+ i2c_reg_write(IO_I2C_ADDR, IO_DPLL_ADDR, DPLL_I2C_ADDR << 1);
+ i2c_reg_write(IO_I2C_ADDR, IO_KSV_ADDR, KSV_I2C_ADDR << 1);
+ i2c_reg_write(IO_I2C_ADDR, IO_EDID_ADDR, EDID_I2C_ADDR << 1);
+ i2c_reg_write(IO_I2C_ADDR, IO_HDMI_ADDR, HDMI_I2C_ADDR << 1);
+ i2c_reg_write(IO_I2C_ADDR, IO_CP_ADDR, CP_I2C_ADDR << 1);
+
+ /*
+ * do magic initialization sequence from
+ * "ADV7611 Register Settings Recommendations Revision 1.5"
+ * with most registers undocumented
+ */
+ i2c_reg_write(CP_I2C_ADDR, 0x6c, 0x00);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x9b, 0x03);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x6f, 0x08);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x85, 0x1f);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x87, 0x70);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x57, 0xda);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x58, 0x01);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x03, 0x98);
+ i2c_reg_write(HDMI_I2C_ADDR, 0x4c, 0x44);
+
+ /*
+ * IO_REG_02, default 0xf0
+ *
+ * INP_COLOR_SPACE (IO, Address 0x02[7:4])
+ * default: 0b1111 auto
+ * set to : 0b0001 force RGB (range 0 to 255) input
+ *
+ * RGB_OUT (IO, Address 0x02[1])
+ * default: 0 YPbPr color space output
+ * set to : 1 RGB color space output
+ */
+ i2c_reg_write(IO_I2C_ADDR, 0x02, 0x12);
+
+ /*
+ * IO_REG_03, default 0x00
+ *
+ * OP_FORMAT_SEL (IO, Address 0x03[7:0])
+ * default: 0x00 8-bit SDR ITU-656 mode
+ * set to : 0x40 24-bit 4:4:4 SDR mode
+ */
+ i2c_reg_write(IO_I2C_ADDR, 0x03, 0x40);
+
+ /*
+ * IO_REG_05, default 0x2c
+ *
+ * AVCODE_INSERT_EN (IO, Address 0x05[2])
+ * default: 1 insert AV codes into data stream
+ * set to : 0 do not insert AV codes into data stream
+ */
+ i2c_reg_write(IO_I2C_ADDR, 0x05, 0x28);
+
+ /*
+ * IO_REG_0C, default 0x62
+ *
+ * POWER_DOWN (IO, Address 0x0C[5])
+ * default: 1 chip is powered down
+ * set to : 0 chip is operational
+ */
+ i2c_reg_write(IO_I2C_ADDR, 0x0c, 0x42);
+
+ /*
+ * IO_REG_15, default 0xbe
+ *
+ * TRI_SYNCS (IO, Address 0x15[3)
+ * TRI_LLC (IO, Address 0x15[2])
+ * TRI_PIX (IO, Address 0x15[1])
+ * default: 1 video output pins are tristate
+ * set to : 0 video output pins are active
+ */
+ i2c_reg_write(IO_I2C_ADDR, 0x15, 0xb0);
+
+ /*
+ * HDMI_REGISTER_02H, default 0xff
+ *
+ * CLOCK_TERMA_DISABLE (HDMI, Address 0x83[0])
+ * default: 1 disable termination
+ * set to : 0 enable termination
+ * Future options are:
+ * - use the chips automatic termination control
+ * - set this manually on cable detect
+ * but at the moment this seems a safe default.
+ */
+ i2c_reg_write(HDMI_I2C_ADDR, 0x83, 0xfe);
+
+ /*
+ * HDMI_CP_CNTRL_1, default 0x01
+ *
+ * HDMI_FRUN_EN (CP, Address 0xBA[0])
+ * default: 1 Enable the free run feature in HDMI mode
+ * set to : 0 Disable the free run feature in HDMI mode
+ */
+ i2c_reg_write(CP_I2C_ADDR, 0xba, 0x00);
+
+ /*
+ * INT1_CONFIGURATION, default 0x20
+ *
+ * INTRQ_DUR_SEL[1:0] (IO, Address 0x40[7:6])
+ * default: 00 Interrupt signal is active for 4 Xtal periods
+ * set to : 11 Active until cleared
+ *
+ * INTRQ_OP_SEL[1:0] (IO, Address 0x40[1:0])
+ * default: 00 Open drain
+ * set to : 10 Drives high when active
+ */
+ i2c_reg_write(IO_I2C_ADDR, 0x40, 0xc2);
+
+out:
+ i2c_set_bus_num(old_bus);
+
+ return res;
+}
diff --git a/board/gdsys/common/adv7611.h b/board/gdsys/common/adv7611.h
new file mode 100644
index 0000000000..25a8367db6
--- /dev/null
+++ b/board/gdsys/common/adv7611.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ADV7611_H_
+#define _ADV7611_H_
+
+int adv7611_probe(unsigned int screen);
+
+#endif
diff --git a/board/gdsys/common/ch7301.c b/board/gdsys/common/ch7301.c
new file mode 100644
index 0000000000..c054e55cf7
--- /dev/null
+++ b/board/gdsys/common/ch7301.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Chrontel CH7301C DVI Transmitter */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+
+#define CH7301_I2C_ADDR 0x75
+
+enum {
+ CH7301_CM = 0x1c, /* Clock Mode Register */
+ CH7301_IC = 0x1d, /* Input Clock Register */
+ CH7301_GPIO = 0x1e, /* GPIO Control Register */
+ CH7301_IDF = 0x1f, /* Input Data Format Register */
+ CH7301_CD = 0x20, /* Connection Detect Register */
+ CH7301_DC = 0x21, /* DAC Control Register */
+ CH7301_HPD = 0x23, /* Hot Plug Detection Register */
+ CH7301_TCTL = 0x31, /* DVI Control Input Register */
+ CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
+ CH7301_TPD = 0x34, /* DVI PLL Divide Register */
+ CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
+ CH7301_TPF = 0x36, /* DVI PLL Filter Register */
+ CH7301_TCT = 0x37, /* DVI Clock Test Register */
+ CH7301_TSTP = 0x48, /* Test Pattern Register */
+ CH7301_PM = 0x49, /* Power Management register */
+ CH7301_VID = 0x4a, /* Version ID Register */
+ CH7301_DID = 0x4b, /* Device ID Register */
+ CH7301_DSP = 0x56, /* DVI Sync polarity Register */
+};
+
+int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
+
+int ch7301_probe(unsigned screen, bool power)
+{
+ u8 value;
+
+ i2c_set_bus_num(ch7301_i2c[screen]);
+ if (i2c_probe(CH7301_I2C_ADDR))
+ return -1;
+
+ value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+ if (value != 0x17)
+ return -1;
+
+ if (power) {
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+ } else {
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x00);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0x01);
+ }
+
+ return 0;
+}
diff --git a/board/gdsys/common/ch7301.h b/board/gdsys/common/ch7301.h
new file mode 100644
index 0000000000..8383719808
--- /dev/null
+++ b/board/gdsys/common/ch7301.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CH7301_H_
+#define _CH7301_H_
+
+int ch7301_probe(unsigned screen, bool power);
+
+#endif
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index 7eb15ed0ba..d35aee0879 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -40,11 +40,29 @@ static int dp501_detect_cable_adapter(u8 addr)
static void dp501_link_training(u8 addr)
{
u8 val;
+ u8 link_bw;
+ u8 max_lane_cnt;
+ u8 lane_cnt;
val = i2c_reg_read(addr, 0x51);
- i2c_reg_write(addr, 0x5d, val); /* set link_bw */
+ if (val >= 0x0a)
+ link_bw = 0x0a;
+ else
+ link_bw = 0x06;
+ if (link_bw != val)
+ printf("DP sink supports %d Mbps link rate, set to %d Mbps\n",
+ val * 270, link_bw * 270);
+ i2c_reg_write(addr, 0x5d, link_bw); /* set link_bw */
val = i2c_reg_read(addr, 0x52);
- i2c_reg_write(addr, 0x5e, val); /* set lane_cnt */
+ max_lane_cnt = val & 0x1f;
+ if (max_lane_cnt >= 4)
+ lane_cnt = 4;
+ else
+ lane_cnt = max_lane_cnt;
+ if (lane_cnt != max_lane_cnt)
+ printf("DP sink supports %d lanes, set to %d lanes\n",
+ max_lane_cnt, lane_cnt);
+ i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */
val = i2c_reg_read(addr, 0x53);
i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */
@@ -77,6 +95,8 @@ void dp501_powerup(u8 addr)
i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
#endif
+ i2c_reg_write(addr + 2, 0x1a, 0x04); /* SPDIF input method TTL */
+
i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
@@ -86,7 +106,8 @@ void dp501_powerup(u8 addr)
dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
- i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
+ i2c_reg_write(addr, 0x87, 0x7f); /* set retry counter as 7
+ retry interval 400us */
if (dp501_detect_cable_adapter(addr)) {
printf("DVI/HDMI cable adapter detected\n");
diff --git a/board/gdsys/common/fanctrl.c b/board/gdsys/common/fanctrl.c
new file mode 100644
index 0000000000..44569bb1ab
--- /dev/null
+++ b/board/gdsys/common/fanctrl.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+enum {
+ FAN_CONFIG = 0x03,
+ FAN_TACHLIM_LSB = 0x48,
+ FAN_TACHLIM_MSB = 0x49,
+ FAN_PWM_FREQ = 0x4D,
+};
+
+void init_fan_controller(u8 addr)
+{
+ int val;
+
+ /* set PWM Frequency to 2.5% resolution */
+ i2c_reg_write(addr, FAN_PWM_FREQ, 20);
+
+ /* set Tachometer Limit */
+ i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10);
+ i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a);
+
+ /* enable Tach input */
+ val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
+ i2c_reg_write(addr, FAN_CONFIG, val);
+}
diff --git a/board/gdsys/common/fanctrl.h b/board/gdsys/common/fanctrl.h
new file mode 100644
index 0000000000..12bc850f85
--- /dev/null
+++ b/board/gdsys/common/fanctrl.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FANCTRL_H_
+#define _FANCTRL_H_
+
+void init_fan_controller(u8 addr);
+
+#endif
diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c
new file mode 100644
index 0000000000..96f02d68ed
--- /dev/null
+++ b/board/gdsys/common/ioep-fpga.c
@@ -0,0 +1,232 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <gdsys_fpga.h>
+
+enum {
+ UNITTYPE_MAIN_SERVER = 0,
+ UNITTYPE_MAIN_USER = 1,
+ UNITTYPE_VIDEO_SERVER = 2,
+ UNITTYPE_VIDEO_USER = 3,
+};
+
+enum {
+ UNITTYPEPCB_DVI = 0,
+ UNITTYPEPCB_DP_165 = 1,
+ UNITTYPEPCB_DP_300 = 2,
+ UNITTYPEPCB_HDMI = 3,
+};
+
+enum {
+ COMPRESSION_NONE = 0,
+ COMPRESSION_TYPE1_DELTA = 1,
+ COMPRESSION_TYPE1_TYPE2_DELTA = 3,
+};
+
+enum {
+ AUDIO_NONE = 0,
+ AUDIO_TX = 1,
+ AUDIO_RX = 2,
+ AUDIO_RXTX = 3,
+};
+
+enum {
+ SYSCLK_147456 = 0,
+};
+
+enum {
+ RAM_DDR2_32 = 0,
+ RAM_DDR3_32 = 1,
+ RAM_DDR3_48 = 2,
+};
+
+enum {
+ CARRIER_SPEED_1G = 0,
+ CARRIER_SPEED_2_5G = 1,
+};
+
+bool ioep_fpga_has_osd(unsigned int fpga)
+{
+ u16 fpga_features;
+ unsigned feature_osd;
+
+ FPGA_GET_REG(0, fpga_features, &fpga_features);
+ feature_osd = fpga_features & (1<<11);
+
+ return feature_osd;
+}
+
+void ioep_fpga_print_info(unsigned int fpga)
+{
+ u16 versions;
+ u16 fpga_version;
+ u16 fpga_features;
+ unsigned unit_type;
+ unsigned unit_type_pcb_video;
+ unsigned feature_compression;
+ unsigned feature_osd;
+ unsigned feature_audio;
+ unsigned feature_sysclock;
+ unsigned feature_ramconfig;
+ unsigned feature_carrier_speed;
+ unsigned feature_carriers;
+ unsigned feature_video_channels;
+
+ FPGA_GET_REG(fpga, versions, &versions);
+ FPGA_GET_REG(fpga, fpga_version, &fpga_version);
+ FPGA_GET_REG(fpga, fpga_features, &fpga_features);
+
+ unit_type = (versions & 0xf000) >> 12;
+ unit_type_pcb_video = (versions & 0x01c0) >> 6;
+ feature_compression = (fpga_features & 0xe000) >> 13;
+ feature_osd = fpga_features & (1<<11);
+ feature_audio = (fpga_features & 0x0600) >> 9;
+ feature_sysclock = (fpga_features & 0x0180) >> 7;
+ feature_ramconfig = (fpga_features & 0x0060) >> 5;
+ feature_carrier_speed = fpga_features & (1<<4);
+ feature_carriers = (fpga_features & 0x000c) >> 2;
+ feature_video_channels = fpga_features & 0x0003;
+
+ switch (unit_type) {
+ case UNITTYPE_MAIN_SERVER:
+ case UNITTYPE_MAIN_USER:
+ printf("Mainchannel");
+ break;
+
+ case UNITTYPE_VIDEO_SERVER:
+ case UNITTYPE_VIDEO_USER:
+ printf("Videochannel");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (unit_type) {
+ case UNITTYPE_MAIN_SERVER:
+ case UNITTYPE_VIDEO_SERVER:
+ printf(" Server");
+ if (versions & (1<<4))
+ printf(" UC");
+ break;
+
+ case UNITTYPE_MAIN_USER:
+ case UNITTYPE_VIDEO_USER:
+ printf(" User");
+ break;
+
+ default:
+ break;
+ }
+
+ if (versions & (1<<5))
+ printf(" Fiber");
+ else
+ printf(" CAT");
+
+ switch (unit_type_pcb_video) {
+ case UNITTYPEPCB_DVI:
+ printf(" DVI,");
+ break;
+
+ case UNITTYPEPCB_DP_165:
+ printf(" DP 165MPix/s,");
+ break;
+
+ case UNITTYPEPCB_DP_300:
+ printf(" DP 300MPix/s,");
+ break;
+
+ case UNITTYPEPCB_HDMI:
+ printf(" HDMI,");
+ break;
+ }
+
+ printf(" FPGA V %d.%02d\n features:",
+ fpga_version / 100, fpga_version % 100);
+
+
+ switch (feature_compression) {
+ case COMPRESSION_NONE:
+ printf(" no compression");
+ break;
+
+ case COMPRESSION_TYPE1_DELTA:
+ printf(" type1-deltacompression");
+ break;
+
+ case COMPRESSION_TYPE1_TYPE2_DELTA:
+ printf(" type1-deltacompression, type2-inlinecompression");
+ break;
+
+ default:
+ printf(" compression %d(not supported)", feature_compression);
+ break;
+ }
+
+ printf(", %sosd", feature_osd ? "" : "no ");
+
+ switch (feature_audio) {
+ case AUDIO_NONE:
+ printf(", no audio");
+ break;
+
+ case AUDIO_TX:
+ printf(", audio tx");
+ break;
+
+ case AUDIO_RX:
+ printf(", audio rx");
+ break;
+
+ case AUDIO_RXTX:
+ printf(", audio rx+tx");
+ break;
+
+ default:
+ printf(", audio %d(not supported)", feature_audio);
+ break;
+ }
+
+ puts(",\n ");
+
+ switch (feature_sysclock) {
+ case SYSCLK_147456:
+ printf("clock 147.456 MHz");
+ break;
+
+ default:
+ printf("clock %d(not supported)", feature_sysclock);
+ break;
+ }
+
+ switch (feature_ramconfig) {
+ case RAM_DDR2_32:
+ printf(", RAM 32 bit DDR2");
+ break;
+
+ case RAM_DDR3_32:
+ printf(", RAM 32 bit DDR3");
+ break;
+
+ case RAM_DDR3_48:
+ printf(", RAM 48 bit DDR3");
+ break;
+
+ default:
+ printf(", RAM %d(not supported)", feature_ramconfig);
+ break;
+ }
+
+ printf(", %d carrier(s) %s", feature_carriers,
+ feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
+
+ printf(", %d video channel(s)\n", feature_video_channels);
+}
diff --git a/board/gdsys/common/ioep-fpga.h b/board/gdsys/common/ioep-fpga.h
new file mode 100644
index 0000000000..44f71399e7
--- /dev/null
+++ b/board/gdsys/common/ioep-fpga.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _IOEP_FPGA_H_
+#define _IOEP_FPGA_H_
+
+void ioep_fpga_print_info(unsigned int fpga);
+bool ioep_fpga_has_osd(unsigned int fpga);
+
+#endif
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 55ecdf1012..7444bee129 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -9,11 +9,10 @@
#include <i2c.h>
#include <malloc.h>
+#include "ch7301.h"
#include "dp501.h"
#include <gdsys_fpga.h>
-#define CH7301_I2C_ADDR 0x75
-
#define ICS8N3QV01_I2C_ADDR 0x6E
#define ICS8N3QV01_FREF 114285000
#define ICS8N3QV01_FREF_LL 114285000LL
@@ -28,43 +27,53 @@
#define DP501_I2C_ADDR 0x08
#define PIXCLK_640_480_60 25180000
+#define MAX_X_CHARS 53
+#define MAX_Y_CHARS 26
+
+#ifdef CONFIG_SYS_OSD_DH
+#define MAX_OSD_SCREEN 8
+#define OSD_DH_BASE 4
+#else
+#define MAX_OSD_SCREEN 4
+#endif
+
+#ifdef CONFIG_SYS_OSD_DH
+#define OSD_SET_REG(screen, fld, val) \
+ do { \
+ if (screen >= OSD_DH_BASE) \
+ FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
+ else \
+ FPGA_SET_REG(screen, osd0.fld, val); \
+ } while (0)
+#else
+#define OSD_SET_REG(screen, fld, val) \
+ FPGA_SET_REG(screen, osd0.fld, val)
+#endif
-enum {
- CH7301_CM = 0x1c, /* Clock Mode Register */
- CH7301_IC = 0x1d, /* Input Clock Register */
- CH7301_GPIO = 0x1e, /* GPIO Control Register */
- CH7301_IDF = 0x1f, /* Input Data Format Register */
- CH7301_CD = 0x20, /* Connection Detect Register */
- CH7301_DC = 0x21, /* DAC Control Register */
- CH7301_HPD = 0x23, /* Hot Plug Detection Register */
- CH7301_TCTL = 0x31, /* DVI Control Input Register */
- CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
- CH7301_TPD = 0x34, /* DVI PLL Divide Register */
- CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
- CH7301_TPF = 0x36, /* DVI PLL Filter Register */
- CH7301_TCT = 0x37, /* DVI Clock Test Register */
- CH7301_TSTP = 0x48, /* Test Pattern Register */
- CH7301_PM = 0x49, /* Power Management register */
- CH7301_VID = 0x4a, /* Version ID Register */
- CH7301_DID = 0x4b, /* Device ID Register */
- CH7301_DSP = 0x56, /* DVI Sync polarity Register */
-};
+#ifdef CONFIG_SYS_OSD_DH
+#define OSD_GET_REG(screen, fld, val) \
+ do { \
+ if (screen >= OSD_DH_BASE) \
+ FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
+ else \
+ FPGA_GET_REG(screen, osd0.fld, val); \
+ } while (0)
+#else
+#define OSD_GET_REG(screen, fld, val) \
+ FPGA_GET_REG(screen, osd0.fld, val)
+#endif
unsigned int base_width;
unsigned int base_height;
size_t bufsize;
u16 *buf;
-unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
+unsigned int osd_screen_mask = 0;
#ifdef CONFIG_SYS_ICS8N3QV01_I2C
int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
#endif
-#ifdef CONFIG_SYS_CH7301_I2C
-int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
-#endif
-
#ifdef CONFIG_SYS_SIL1178_I2C
int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
#endif
@@ -73,6 +82,9 @@ int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
#endif
+#ifdef CONFIG_SYS_DP501_BASE
+int dp501_base[] = CONFIG_SYS_DP501_BASE;
+#endif
#ifdef CONFIG_SYS_MPC92469AC
static void mpc92469ac_calc_parameters(unsigned int fout,
@@ -242,7 +254,15 @@ static int osd_write_videomem(unsigned screen, unsigned offset,
for (k = 0; k < charcount; ++k) {
if (offset + k >= bufsize)
return -1;
- FPGA_SET_REG(screen, videomem[offset + k], data[k]);
+#ifdef CONFIG_SYS_OSD_DH
+ if (screen >= OSD_DH_BASE)
+ FPGA_SET_REG(screen - OSD_DH_BASE,
+ videomem1[offset + k], data[k]);
+ else
+ FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
+#else
+ FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
+#endif
}
return charcount;
@@ -252,7 +272,12 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned screen;
- for (screen = 0; screen <= max_osd_screen; ++screen) {
+ if (argc < 5) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
unsigned x;
unsigned y;
unsigned charcount;
@@ -262,10 +287,8 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
char *text;
int res;
- if (argc < 5) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (!(osd_screen_mask & (1 << screen)))
+ continue;
x = simple_strtoul(argv[1], NULL, 16);
y = simple_strtoul(argv[2], NULL, 16);
@@ -280,6 +303,8 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
res = osd_write_videomem(screen, y * base_width + x, buf, len);
if (res < 0)
return res;
+
+ OSD_SET_REG(screen, control, 0x0049);
}
return 0;
@@ -292,9 +317,16 @@ int osd_probe(unsigned screen)
int old_bus = i2c_get_bus_num();
bool pixclock_present = false;
bool output_driver_present = false;
+#ifdef CONFIG_SYS_DP501_I2C
+#ifdef CONFIG_SYS_DP501_BASE
+ uint8_t dp501_addr = dp501_base[screen];
+#else
+ uint8_t dp501_addr = DP501_I2C_ADDR;
+#endif
+#endif
- FPGA_GET_REG(0, osd.version, &version);
- FPGA_GET_REG(0, osd.features, &features);
+ OSD_GET_REG(0, version, &version);
+ OSD_GET_REG(0, features, &features);
base_width = ((features & 0x3f00) >> 8) + 1;
base_height = (features & 0x001f) + 1;
@@ -303,9 +335,15 @@ int osd_probe(unsigned screen)
if (!buf)
return -1;
+#ifdef CONFIG_SYS_OSD_DH
+ printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+ (screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen,
+ (screen > 3) ? 1 : 0, version/100, version%100, base_width,
+ base_height);
+#else
printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
- screen, version/100, version%100, base_width, base_height);
-
+ screen, version/100, version%100, base_width, base_height);
+#endif
/* setup pixclock */
#ifdef CONFIG_SYS_MPC92469AC
@@ -327,19 +365,8 @@ int osd_probe(unsigned screen)
/* setup output driver */
#ifdef CONFIG_SYS_CH7301_I2C
- i2c_set_bus_num(ch7301_i2c[screen]);
- if (!i2c_probe(CH7301_I2C_ADDR)) {
- u8 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
-
- if (value == 0x17) {
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
- output_driver_present = true;
- }
- }
+ if (!ch7301_probe(screen, true))
+ output_driver_present = true;
#endif
#ifdef CONFIG_SYS_SIL1178_I2C
@@ -367,8 +394,8 @@ int osd_probe(unsigned screen)
#ifdef CONFIG_SYS_DP501_I2C
i2c_set_bus_num(dp501_i2c[screen]);
- if (!i2c_probe(DP501_I2C_ADDR)) {
- dp501_powerup(DP501_I2C_ADDR);
+ if (!i2c_probe(dp501_addr)) {
+ dp501_powerup(dp501_addr);
output_driver_present = true;
}
#endif
@@ -376,14 +403,12 @@ int osd_probe(unsigned screen)
if (!output_driver_present)
printf(" no output driver found\n");
- FPGA_SET_REG(screen, osd.control, 0x0049);
-
- FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
- FPGA_SET_REG(screen, osd.x_pos, 0x007f);
- FPGA_SET_REG(screen, osd.y_pos, 0x005f);
+ OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1));
+ OSD_SET_REG(screen, x_pos, 0x007f);
+ OSD_SET_REG(screen, y_pos, 0x005f);
- if (screen > max_osd_screen)
- max_osd_screen = screen;
+ if (pixclock_present && output_driver_present)
+ osd_screen_mask |= 1 << screen;
i2c_set_bus_num(old_bus);
@@ -394,7 +419,12 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned screen;
- for (screen = 0; screen <= max_osd_screen; ++screen) {
+ if ((argc < 4) || (strlen(argv[3]) % 4)) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
unsigned x;
unsigned y;
unsigned k;
@@ -404,10 +434,8 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
unsigned count = (argc > 4) ?
simple_strtoul(argv[4], NULL, 16) : 1;
- if ((argc < 4) || (strlen(argv[3]) % 4)) {
- cmd_usage(cmdtp);
- return 1;
- }
+ if (!(osd_screen_mask & (1 << screen)))
+ continue;
x = simple_strtoul(argv[1], NULL, 16);
y = simple_strtoul(argv[2], NULL, 16);
@@ -433,6 +461,37 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
osd_write_videomem(screen, offset, buffer,
wp - buffer);
}
+
+ OSD_SET_REG(screen, control, 0x0049);
+ }
+
+ return 0;
+}
+
+int osd_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned screen;
+ unsigned x;
+ unsigned y;
+
+ if (argc < 3) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+
+ if (!x || (x > 64) || (x > MAX_X_CHARS) ||
+ !y || (y > 32) || (y > MAX_Y_CHARS)) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
+ OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1));
+ OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
+ OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
}
return 0;
@@ -449,3 +508,10 @@ U_BOOT_CMD(
"write ASCII buffer to osd memory",
"pos_x pos_y color text\n"
);
+
+U_BOOT_CMD(
+ osdsize, 3, 0, osd_size,
+ "set OSD XY size in characters",
+ "size_x(max. " __stringify(MAX_X_CHARS)
+ ") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
+);
diff --git a/board/gdsys/common/osd.h b/board/gdsys/common/osd.h
index 440b276a0b..5b3f14bf05 100644
--- a/board/gdsys/common/osd.h
+++ b/board/gdsys/common/osd.h
@@ -8,6 +8,7 @@
#ifndef _OSD_H_
#define _OSD_H_
+int ch7301_probe(unsigned screen, bool power);
int osd_probe(unsigned screen);
#endif
diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig
index 43e1663d19..9a1a3a2f28 100644
--- a/board/gdsys/mpc8308/Kconfig
+++ b/board/gdsys/mpc8308/Kconfig
@@ -10,3 +10,16 @@ config SYS_CONFIG_NAME
default "hrcon"
endif
+
+if TARGET_STRIDER
+
+config SYS_BOARD
+ default "mpc8308"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "strider"
+
+endif
diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS
index a7853a59df..3895b01732 100644
--- a/board/gdsys/mpc8308/MAINTAINERS
+++ b/board/gdsys/mpc8308/MAINTAINERS
@@ -4,3 +4,7 @@ S: Maintained
F: board/gdsys/mpc8308/
F: include/configs/hrcon.h
F: configs/hrcon_defconfig
+F: configs/hrcon_dh_defconfig
+F: include/configs/strider.h
+F: configs/strider_cpu_defconfig
+F: configs/strider_con_defconfig
diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile
index b5dfdbb190..42702fb967 100644
--- a/board/gdsys/mpc8308/Makefile
+++ b/board/gdsys/mpc8308/Makefile
@@ -7,3 +7,4 @@
obj-y := mpc8308.o sdram.o
obj-$(CONFIG_HRCON) += hrcon.o
+obj-$(CONFIG_STRIDER) += strider.o
diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c
index e4434b3b6b..880b6387de 100644
--- a/board/gdsys/mpc8308/hrcon.c
+++ b/board/gdsys/mpc8308/hrcon.c
@@ -22,9 +22,11 @@
#include <gdsys_fpga.h>
+#include "../common/ioep-fpga.h"
#include "../common/osd.h"
#include "../common/mclink.h"
#include "../common/phy.h"
+#include "../common/fanctrl.h"
#include <pca953x.h>
#include <pca9698.h>
@@ -36,57 +38,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define MAX_MUX_CHANNELS 2
enum {
- UNITTYPE_MAIN_SERVER = 0,
- UNITTYPE_MAIN_USER = 1,
- UNITTYPE_VIDEO_SERVER = 2,
- UNITTYPE_VIDEO_USER = 3,
-};
-
-enum {
- UNITTYPEPCB_DVI = 0,
- UNITTYPEPCB_DP_165 = 1,
- UNITTYPEPCB_DP_300 = 2,
- UNITTYPEPCB_HDMI = 3,
-};
-
-enum {
- HWVER_100 = 0,
- HWVER_110 = 1,
-};
-
-enum {
- FPGA_HWVER_200 = 0,
- FPGA_HWVER_210 = 1,
-};
-
-enum {
- COMPRESSION_NONE = 0,
- COMPRESSION_TYPE1_DELTA = 1,
- COMPRESSION_TYPE1_TYPE2_DELTA = 3,
-};
-
-enum {
- AUDIO_NONE = 0,
- AUDIO_TX = 1,
- AUDIO_RX = 2,
- AUDIO_RXTX = 3,
-};
-
-enum {
- SYSCLK_147456 = 0,
-};
-
-enum {
- RAM_DDR2_32 = 0,
- RAM_DDR3_32 = 1,
-};
-
-enum {
- CARRIER_SPEED_1G = 0,
- CARRIER_SPEED_2_5G = 1,
-};
-
-enum {
MCFPGA_DONE = 1 << 0,
MCFPGA_INIT_N = 1 << 1,
MCFPGA_PROGRAM_N = 1 << 2,
@@ -102,6 +53,11 @@ enum {
unsigned int mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+struct {
+ u8 bus;
+ u8 addr;
+} hrcon_fans[] = CONFIG_HRCON_FANS;
+
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
{
int res;
@@ -164,197 +120,12 @@ int checkboard(void)
return 0;
}
-static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
-{
- u16 versions;
- u16 fpga_version;
- u16 fpga_features;
- unsigned unit_type;
- unsigned unit_type_pcb_video;
- unsigned hardware_version;
- unsigned feature_compression;
- unsigned feature_osd;
- unsigned feature_audio;
- unsigned feature_sysclock;
- unsigned feature_ramconfig;
- unsigned feature_carrier_speed;
- unsigned feature_carriers;
- unsigned feature_video_channels;
-
- FPGA_GET_REG(fpga, versions, &versions);
- FPGA_GET_REG(fpga, fpga_version, &fpga_version);
- FPGA_GET_REG(fpga, fpga_features, &fpga_features);
-
- unit_type = (versions & 0xf000) >> 12;
- unit_type_pcb_video = (versions & 0x01c0) >> 6;
- feature_compression = (fpga_features & 0xe000) >> 13;
- feature_osd = fpga_features & (1<<11);
- feature_audio = (fpga_features & 0x0600) >> 9;
- feature_sysclock = (fpga_features & 0x0180) >> 7;
- feature_ramconfig = (fpga_features & 0x0060) >> 5;
- feature_carrier_speed = fpga_features & (1<<4);
- feature_carriers = (fpga_features & 0x000c) >> 2;
- feature_video_channels = fpga_features & 0x0003;
-
- switch (unit_type) {
- case UNITTYPE_MAIN_USER:
- printf("Mainchannel");
- break;
-
- case UNITTYPE_VIDEO_USER:
- printf("Videochannel");
- break;
-
- default:
- printf("UnitType %d(not supported)", unit_type);
- break;
- }
-
- if (unit_type == UNITTYPE_MAIN_USER) {
- hardware_version =
- (!!pca9698_get_value(0x20, 24) << 0)
- | (!!pca9698_get_value(0x20, 25) << 1)
- | (!!pca9698_get_value(0x20, 26) << 2)
- | (!!pca9698_get_value(0x20, 27) << 3)
- | (!!pca9698_get_value(0x20, 28) << 4);
- switch (hardware_version) {
- case HWVER_100:
- printf(" HW-Ver 1.00,");
- break;
-
- case HWVER_110:
- printf(" HW-Ver 1.10,");
- break;
-
- default:
- printf(" HW-Ver %d(not supported),",
- hardware_version);
- break;
- }
- if (rgmii2_present)
- printf(" RGMII2,");
- }
-
- if (unit_type == UNITTYPE_VIDEO_USER) {
- hardware_version = versions & 0x000f;
- switch (hardware_version) {
- case FPGA_HWVER_200:
- printf(" HW-Ver 2.00,");
- break;
-
- case FPGA_HWVER_210:
- printf(" HW-Ver 2.10,");
- break;
-
- default:
- printf(" HW-Ver %d(not supported),",
- hardware_version);
- break;
- }
- }
-
- switch (unit_type_pcb_video) {
- case UNITTYPEPCB_DVI:
- printf(" DVI,");
- break;
-
- case UNITTYPEPCB_DP_165:
- printf(" DP 165MPix/s,");
- break;
-
- case UNITTYPEPCB_DP_300:
- printf(" DP 300MPix/s,");
- break;
-
- case UNITTYPEPCB_HDMI:
- printf(" HDMI,");
- break;
- }
-
- printf(" FPGA V %d.%02d\n features:",
- fpga_version / 100, fpga_version % 100);
-
-
- switch (feature_compression) {
- case COMPRESSION_NONE:
- printf(" no compression");
- break;
-
- case COMPRESSION_TYPE1_DELTA:
- printf(" type1-deltacompression");
- break;
-
- case COMPRESSION_TYPE1_TYPE2_DELTA:
- printf(" type1-deltacompression, type2-inlinecompression");
- break;
-
- default:
- printf(" compression %d(not supported)", feature_compression);
- break;
- }
-
- printf(", %sosd", feature_osd ? "" : "no ");
-
- switch (feature_audio) {
- case AUDIO_NONE:
- printf(", no audio");
- break;
-
- case AUDIO_TX:
- printf(", audio tx");
- break;
-
- case AUDIO_RX:
- printf(", audio rx");
- break;
-
- case AUDIO_RXTX:
- printf(", audio rx+tx");
- break;
-
- default:
- printf(", audio %d(not supported)", feature_audio);
- break;
- }
-
- puts(",\n ");
-
- switch (feature_sysclock) {
- case SYSCLK_147456:
- printf("clock 147.456 MHz");
- break;
-
- default:
- printf("clock %d(not supported)", feature_sysclock);
- break;
- }
-
- switch (feature_ramconfig) {
- case RAM_DDR2_32:
- printf(", RAM 32 bit DDR2");
- break;
-
- case RAM_DDR3_32:
- printf(", RAM 32 bit DDR3");
- break;
-
- default:
- printf(", RAM %d(not supported)", feature_ramconfig);
- break;
- }
-
- printf(", %d carrier(s) %s", feature_carriers,
- feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
-
- printf(", %d video channel(s)\n", feature_video_channels);
-}
-
int last_stage_init(void)
{
int slaves;
unsigned int k;
unsigned int mux_ch;
- unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
+ unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
u16 fpga_features;
bool hw_type_cat = pca9698_get_value(0x20, 20);
bool ch0_rgmii2_present = false;
@@ -363,10 +134,11 @@ int last_stage_init(void)
/* Turn on Parade DP501 */
pca9698_direction_output(0x20, 10, 1);
+ pca9698_direction_output(0x20, 11, 1);
ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
- /* wait for FPGA done */
+ /* wait for FPGA done, then reset FPGA */
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
unsigned int ctr = 0;
@@ -381,6 +153,12 @@ int last_stage_init(void)
break;
}
}
+
+ pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
+ pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
+ udelay(10);
+ pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
+ MCFPGA_RESET_N);
}
if (hw_type_cat) {
@@ -401,8 +179,11 @@ int last_stage_init(void)
slaves = mclink_probe();
mclink_fpgacount = 0;
- print_fpga_info(0, ch0_rgmii2_present);
+ ioep_fpga_print_info(0);
osd_probe(0);
+#ifdef CONFIG_SYS_OSD_DH
+ osd_probe(4);
+#endif
if (slaves <= 0)
return 0;
@@ -412,8 +193,11 @@ int last_stage_init(void)
for (k = 1; k <= slaves; ++k) {
FPGA_GET_REG(k, fpga_features, &fpga_features);
- print_fpga_info(k, false);
+ ioep_fpga_print_info(k);
osd_probe(k);
+#ifdef CONFIG_SYS_OSD_DH
+ osd_probe(k + 4);
+#endif
if (hw_type_cat) {
miiphy_register(bb_miiphy_buses[k].name,
bb_miiphy_read, bb_miiphy_write);
@@ -421,32 +205,53 @@ int last_stage_init(void)
}
}
+ for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {
+ i2c_set_bus_num(hrcon_fans[k].bus);
+ init_fan_controller(hrcon_fans[k].addr);
+ }
+
return 0;
}
/*
- * provide access to fpga gpios (for I2C bitbang)
+ * provide access to fpga gpios and controls (for I2C bitbang)
* (these may look all too simple but make iocon.h much more readable)
*/
void fpga_gpio_set(unsigned int bus, int pin)
{
- FPGA_SET_REG(bus, gpio.set, pin);
+ FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
}
void fpga_gpio_clear(unsigned int bus, int pin)
{
- FPGA_SET_REG(bus, gpio.clear, pin);
+ FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
}
int fpga_gpio_get(unsigned int bus, int pin)
{
u16 val;
- FPGA_GET_REG(bus, gpio.read, &val);
+ FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val);
return val & pin;
}
+void fpga_control_set(unsigned int bus, int pin)
+{
+ u16 val;
+
+ FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
+ FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
+}
+
+void fpga_control_clear(unsigned int bus, int pin)
+{
+ u16 val;
+
+ FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
+ FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
+}
+
void mpc8308_init(void)
{
pca9698_direction_output(0x20, 4, 1);
diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c
new file mode 100644
index 0000000000..ef5b6c03f8
--- /dev/null
+++ b/board/gdsys/mpc8308/strider.c
@@ -0,0 +1,479 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <spi.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+#include "mpc8308.h"
+
+#include <gdsys_fpga.h>
+
+#include "../common/adv7611.h"
+#include "../common/ch7301.h"
+#include "../common/ioep-fpga.h"
+#include "../common/mclink.h"
+#include "../common/osd.h"
+#include "../common/phy.h"
+#include "../common/fanctrl.h"
+
+#include <pca953x.h>
+#include <pca9698.h>
+
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_MUX_CHANNELS 2
+
+enum {
+ MCFPGA_DONE = 1 << 0,
+ MCFPGA_INIT_N = 1 << 1,
+ MCFPGA_PROGRAM_N = 1 << 2,
+ MCFPGA_UPDATE_ENABLE_N = 1 << 3,
+ MCFPGA_RESET_N = 1 << 4,
+};
+
+enum {
+ GPIO_MDC = 1 << 14,
+ GPIO_MDIO = 1 << 15,
+};
+
+unsigned int mclink_fpgacount;
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+struct {
+ u8 bus;
+ u8 addr;
+} strider_fans[] = CONFIG_STRIDER_FANS;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+ int res;
+
+ switch (fpga) {
+ case 0:
+ out_le16(reg, data);
+ break;
+ default:
+ res = mclink_send(fpga - 1, regoff, data);
+ if (res < 0) {
+ printf("mclink_send reg %02lx data %04x returned %d\n",
+ regoff, data, res);
+ return res;
+ }
+ break;
+ }
+
+ return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+ int res;
+
+ switch (fpga) {
+ case 0:
+ *data = in_le16(reg);
+ break;
+ default:
+ if (fpga > mclink_fpgacount)
+ return -EINVAL;
+ res = mclink_receive(fpga - 1, regoff, data);
+ if (res < 0) {
+ printf("mclink_receive reg %02lx returned %d\n",
+ regoff, res);
+ return res;
+ }
+ }
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+ bool hw_type_cat = pca9698_get_value(0x20, 18);
+
+ puts("Board: ");
+
+ printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ int slaves;
+ unsigned int k;
+ unsigned int mux_ch;
+ unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
+ bool hw_type_cat = pca9698_get_value(0x20, 18);
+ bool ch0_sgmii2_present = false;
+
+ /* Turn on Analog Devices ADV7611 */
+ pca9698_direction_output(0x20, 8, 0);
+
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 9, 1);
+
+ ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
+
+ /* wait for FPGA done, then reset FPGA */
+ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
+ unsigned int ctr = 0;
+
+ if (i2c_probe(mclink_controllers[k]))
+ continue;
+
+ while (!(pca953x_get_val(mclink_controllers[k])
+ & MCFPGA_DONE)) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ printf("no done for mclink_controller %d\n", k);
+ break;
+ }
+ }
+
+ pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
+ pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
+ udelay(10);
+ pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
+ MCFPGA_RESET_N);
+ }
+
+ if (hw_type_cat) {
+ miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
+ bb_miiphy_write);
+ for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
+ if ((mux_ch == 1) && !ch0_sgmii2_present)
+ continue;
+
+ setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
+ }
+ }
+
+ /* give slave-PLLs and Parade DP501 some time to be up and running */
+ udelay(500000);
+
+ mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
+ slaves = mclink_probe();
+ mclink_fpgacount = 0;
+
+ ioep_fpga_print_info(0);
+
+ if (!adv7611_probe(0))
+ printf(" Advantiv ADV7611 HDMI Receiver\n");
+
+#ifdef CONFIG_STRIDER_CON
+ if (ioep_fpga_has_osd(0))
+ osd_probe(0);
+#endif
+
+#ifdef CONFIG_STRIDER_CPU
+ ch7301_probe(0, false);
+#endif
+
+ if (slaves <= 0)
+ return 0;
+
+ mclink_fpgacount = slaves;
+
+ for (k = 1; k <= slaves; ++k) {
+ ioep_fpga_print_info(k);
+#ifdef CONFIG_STRIDER_CON
+ if (ioep_fpga_has_osd(k))
+ osd_probe(k);
+#endif
+#ifdef CONFIG_STRIDER_CPU
+ FPGA_SET_REG(k, extended_control, 0); /* enable video in*/
+ if (!adv7611_probe(k))
+ printf(" Advantiv ADV7611 HDMI Receiver\n");
+ ch7301_probe(k, false);
+#endif
+ if (hw_type_cat) {
+ miiphy_register(bb_miiphy_buses[k].name,
+ bb_miiphy_read, bb_miiphy_write);
+ setup_88e1514(bb_miiphy_buses[k].name, 0);
+ }
+ }
+
+ for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
+ i2c_set_bus_num(strider_fans[k].bus);
+ init_fan_controller(strider_fans[k].addr);
+ }
+
+ return 0;
+}
+
+/*
+ * provide access to fpga gpios (for I2C bitbang)
+ * (these may look all too simple but make iocon.h much more readable)
+ */
+void fpga_gpio_set(unsigned int bus, int pin)
+{
+ FPGA_SET_REG(bus, gpio.set, pin);
+}
+
+void fpga_gpio_clear(unsigned int bus, int pin)
+{
+ FPGA_SET_REG(bus, gpio.clear, pin);
+}
+
+int fpga_gpio_get(unsigned int bus, int pin)
+{
+ u16 val;
+
+ FPGA_GET_REG(bus, gpio.read, &val);
+
+ return val & pin;
+}
+
+void mpc8308_init(void)
+{
+ pca9698_direction_output(0x20, 26, 1);
+}
+
+void mpc8308_set_fpga_reset(unsigned state)
+{
+ pca9698_set_value(0x20, 26, state ? 0 : 1);
+}
+
+void mpc8308_setup_hw(void)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /*
+ * set "startup-finished"-gpios
+ */
+ setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
+ setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
+}
+
+int mpc8308_get_fpga_done(unsigned fpga)
+{
+ return pca9698_get_value(0x20, 20);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+
+ /* Enable cache snooping in eSDHC system configuration register */
+ out_be32(&sysconf->sdhccr, 0x02000000);
+
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
+static struct pci_region pcie_regions_0[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+void pci_init_board(void)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+ law83xx_t *pcie_law = sysconf->pcielaw;
+ struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+ /* Deassert the resets in the control register */
+ out_be32(&sysconf->pecr1, 0xE0008000);
+ udelay(2000);
+
+ /* Configure PCI Express Local Access Windows */
+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ mpc83xx_pcie_init(1, pcie_reg);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
+
+ return 0;
+}
+#endif
+
+/*
+ * FPGA MII bitbang implementation
+ */
+
+struct fpga_mii {
+ unsigned fpga;
+ int mdio;
+} fpga_mii[] = {
+ { 0, 1},
+ { 1, 1},
+ { 2, 1},
+ { 3, 1},
+};
+
+static int mii_dummy_init(struct bb_miiphy_bus *bus)
+{
+ return 0;
+}
+
+static int mii_mdio_active(struct bb_miiphy_bus *bus)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (fpga_mii->mdio)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+ return 0;
+}
+
+static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+
+ return 0;
+}
+
+static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (v)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+ fpga_mii->mdio = v;
+
+ return 0;
+}
+
+static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ u16 gpio;
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
+
+ *v = ((gpio & GPIO_MDIO) != 0);
+
+ return 0;
+}
+
+static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (v)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
+
+ return 0;
+}
+
+static int mii_delay(struct bb_miiphy_bus *bus)
+{
+ udelay(1);
+
+ return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+ {
+ .name = "board0",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[0],
+ },
+ {
+ .name = "board1",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[1],
+ },
+ {
+ .name = "board2",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[2],
+ },
+ {
+ .name = "board3",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[3],
+ },
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+ sizeof(bb_miiphy_buses[0]);
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index 64d90dd3fd..2f98e4757f 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -57,6 +57,8 @@ struct ihs_fpga {
u32 versions; /* 0x0004 */
u32 fpga_version; /* 0x0008 */
u32 fpga_features; /* 0x000c */
+ u32 reserved[4]; /* 0x0010 */
+ u32 control; /* 0x0020 */
};
#ifndef CONFIG_TRAILBLAZER
@@ -384,6 +386,9 @@ static void hydra_initialize(void)
fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
PCI_REGION_MEM);
+ /* disable sideband clocks */
+ writel(1, &fpga->control);
+
versions = readl(&fpga->versions);
fpga_version = readl(&fpga->fpga_version);
fpga_features = readl(&fpga->fpga_features);
diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c
index 815c9a7d15..1f5a5868cb 100644
--- a/board/silica/pengwyn/board.c
+++ b/board/silica/pengwyn/board.c
@@ -141,12 +141,6 @@ static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
- .phy_if = PHY_INTERFACE_MODE_MII,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
.phy_addr = 1,
.phy_if = PHY_INTERFACE_MODE_MII,
},
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 28c29a2f9c..79ed02f68f 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -317,7 +317,6 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
/* Do board-specific muxes. */
if (board_is_bone(header)) {
/* Beaglebone pinmux */
- configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
#if defined(CONFIG_NAND)
@@ -356,7 +355,6 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
configure_module_pin_mux(mmc0_pin_mux_sk_evm);
} else if (board_is_bone_lt(header)) {
/* Beaglebone LT pinmux */
- configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
generated by cgit (git 2.34.1) at 2025-01-14 22:22:49 +0000