diff options
Diffstat (limited to 'board')
29 files changed, 2010 insertions, 493 deletions
diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c index 1704627112..106be9b761 100644 --- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -42,12 +42,12 @@ void pinmux_init(void) void gpio_early_init(void) { /* Turn on the alive signal */ - gpio_request(GPIO_PV2, "ALIVE"); - gpio_direction_output(GPIO_PV2, 1); + gpio_request(TEGRA_GPIO(V, 2), "ALIVE"); + gpio_direction_output(TEGRA_GPIO(V, 2), 1); /* Remove the reset on the external periph */ - gpio_request(GPIO_PI4, "nRST_PERIPH"); - gpio_direction_output(GPIO_PI4, 1); + gpio_request(TEGRA_GPIO(I, 4), "nRST_PERIPH"); + gpio_direction_output(TEGRA_GPIO(I, 4), 1); } void pmu_write(uchar reg, uchar data) @@ -73,8 +73,8 @@ void board_sdmmc_voltage_init(void) pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300)); /* Switch the power on */ - gpio_request(GPIO_PJ2, "EN_3V3_EMMC"); - gpio_direction_output(GPIO_PJ2, 1); + gpio_request(TEGRA_GPIO(J, 2), "EN_3V3_EMMC"); + gpio_direction_output(TEGRA_GPIO(J, 2), 1); } /* diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 9c8677943a..4fb36a2cf8 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -23,8 +23,8 @@ #ifdef CONFIG_BOARD_EARLY_INIT_F void gpio_early_init(void) { - gpio_request(GPIO_PI4, NULL); - gpio_direction_output(GPIO_PI4, 1); + gpio_request(TEGRA_GPIO(I, 4), NULL); + gpio_direction_output(TEGRA_GPIO(I, 4), 1); } #endif diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index ba15e2e6cf..f04f843c31 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -110,11 +110,11 @@ int tegra_pcie_board_init(void) } /* GPIO: PEX = 3.3V */ - err = gpio_request(GPIO_PL7, "PEX"); + err = gpio_request(TEGRA_GPIO(L, 7), "PEX"); if (err < 0) return err; - gpio_direction_output(GPIO_PL7, 1); + gpio_direction_output(TEGRA_GPIO(L, 7), 1); /* TPS659110: LDO2_REG = 1.05V, ACTIVE */ data[0] = 0x15; diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h index 7eb1e6c1b3..7955ca5cdf 100644 --- a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h +++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h @@ -15,71 +15,71 @@ #ifndef _PINMUX_CONFIG_E2220_1170_H_ #define _PINMUX_CONFIG_E2220_1170_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config e2220_1170_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A5, IN), - GPIO_INIT(A6, IN), - GPIO_INIT(B4, IN), - GPIO_INIT(E6, IN), - GPIO_INIT(G2, OUT0), - GPIO_INIT(G3, OUT0), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H1, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(H6, OUT0), - GPIO_INIT(H7, OUT0), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I3, OUT0), - GPIO_INIT(K0, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, OUT0), - GPIO_INIT(K3, OUT0), - GPIO_INIT(K4, IN), - GPIO_INIT(K5, OUT0), - GPIO_INIT(K6, IN), - GPIO_INIT(K7, OUT0), - GPIO_INIT(L0, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, OUT0), - GPIO_INIT(S6, OUT0), - GPIO_INIT(S7, OUT0), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V2, OUT0), - GPIO_INIT(V3, IN), - GPIO_INIT(V5, OUT0), - GPIO_INIT(V6, OUT0), - GPIO_INIT(X0, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X2, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y0, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z4, OUT0), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(BB3, OUT0), - GPIO_INIT(BB4, IN), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC5, OUT0), - GPIO_INIT(CC6, IN), - GPIO_INIT(CC7, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 5, IN), + GPIO_INIT(A, 6, IN), + GPIO_INIT(B, 4, IN), + GPIO_INIT(E, 6, IN), + GPIO_INIT(G, 2, OUT0), + GPIO_INIT(G, 3, OUT0), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 1, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(H, 6, OUT0), + GPIO_INIT(H, 7, OUT0), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(I, 3, OUT0), + GPIO_INIT(K, 0, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, OUT0), + GPIO_INIT(K, 3, OUT0), + GPIO_INIT(K, 4, IN), + GPIO_INIT(K, 5, OUT0), + GPIO_INIT(K, 6, IN), + GPIO_INIT(K, 7, OUT0), + GPIO_INIT(L, 0, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 5, OUT0), + GPIO_INIT(S, 6, OUT0), + GPIO_INIT(S, 7, OUT0), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, OUT0), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 2, OUT0), + GPIO_INIT(V, 3, IN), + GPIO_INIT(V, 5, OUT0), + GPIO_INIT(V, 6, OUT0), + GPIO_INIT(X, 0, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 2, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 5, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 0, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 4, OUT0), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(BB, 3, OUT0), + GPIO_INIT(BB, 4, IN), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 5, OUT0), + GPIO_INIT(CC, 6, IN), + GPIO_INIT(CC, 7, OUT0), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h index 00e0cdc4b8..01237dbc29 100644 --- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -15,63 +15,63 @@ #ifndef _PINMUX_CONFIG_JETSON_TK1_H_ #define _PINMUX_CONFIG_JETSON_TK1_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(G0, IN), - GPIO_INIT(G1, IN), - GPIO_INIT(G2, IN), - GPIO_INIT(G3, IN), - GPIO_INIT(G4, IN), - GPIO_INIT(H2, OUT0), - GPIO_INIT(H4, IN), - GPIO_INIT(H7, IN), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I6, IN), - GPIO_INIT(J0, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, IN), - GPIO_INIT(K4, OUT0), - GPIO_INIT(K6, OUT0), - GPIO_INIT(N7, IN), - GPIO_INIT(O1, IN), - GPIO_INIT(O4, IN), - GPIO_INIT(P2, OUT0), - GPIO_INIT(Q0, IN), - GPIO_INIT(Q3, IN), - GPIO_INIT(Q5, IN), - GPIO_INIT(R0, OUT0), - GPIO_INIT(R2, OUT0), - GPIO_INIT(R4, IN), - GPIO_INIT(R7, IN), - GPIO_INIT(S7, IN), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, IN), - GPIO_INIT(U0, IN), - GPIO_INIT(U1, IN), - GPIO_INIT(U2, IN), - GPIO_INIT(U3, IN), - GPIO_INIT(U4, IN), - GPIO_INIT(U5, IN), - GPIO_INIT(U6, IN), - GPIO_INIT(V0, IN), - GPIO_INIT(V1, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X7, OUT0), - GPIO_INIT(BB3, OUT0), - GPIO_INIT(BB5, OUT0), - GPIO_INIT(BB6, OUT0), - GPIO_INIT(BB7, OUT0), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC2, IN), - GPIO_INIT(EE2, OUT1), + /* port, pin, init_val */ + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 1, IN), + GPIO_INIT(G, 2, IN), + GPIO_INIT(G, 3, IN), + GPIO_INIT(G, 4, IN), + GPIO_INIT(H, 2, OUT0), + GPIO_INIT(H, 4, IN), + GPIO_INIT(H, 7, IN), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 6, IN), + GPIO_INIT(J, 0, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, IN), + GPIO_INIT(K, 4, OUT0), + GPIO_INIT(K, 6, OUT0), + GPIO_INIT(N, 7, IN), + GPIO_INIT(O, 1, IN), + GPIO_INIT(O, 4, IN), + GPIO_INIT(P, 2, OUT0), + GPIO_INIT(Q, 0, IN), + GPIO_INIT(Q, 3, IN), + GPIO_INIT(Q, 5, IN), + GPIO_INIT(R, 0, OUT0), + GPIO_INIT(R, 2, OUT0), + GPIO_INIT(R, 4, IN), + GPIO_INIT(R, 7, IN), + GPIO_INIT(S, 7, IN), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, IN), + GPIO_INIT(U, 0, IN), + GPIO_INIT(U, 1, IN), + GPIO_INIT(U, 2, IN), + GPIO_INIT(U, 3, IN), + GPIO_INIT(U, 4, IN), + GPIO_INIT(U, 5, IN), + GPIO_INIT(U, 6, IN), + GPIO_INIT(V, 0, IN), + GPIO_INIT(V, 1, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 7, OUT0), + GPIO_INIT(BB, 3, OUT0), + GPIO_INIT(BB, 5, OUT0), + GPIO_INIT(BB, 6, OUT0), + GPIO_INIT(BB, 7, OUT0), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 2, IN), + GPIO_INIT(EE, 2, OUT1), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index ba96401890..8f68ae9fbe 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -36,8 +36,9 @@ void pinmux_init(void) int tegra_board_id(void) { - static const int vector[] = {GPIO_PQ3, GPIO_PT1, GPIO_PX1, - GPIO_PX4, -1}; + static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1), + TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4), + -1}; gpio_claim_vector(vector, "board_id%d"); return gpio_get_values_as_int(vector); diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h index dca0171f26..fd7f1d17f4 100644 --- a/board/nvidia/nyan-big/pinmux-config-nyan-big.h +++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h @@ -15,59 +15,59 @@ #ifndef _PINMUX_CONFIG_NYAN_BIG_H_ #define _PINMUX_CONFIG_NYAN_BIG_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config nyan_big_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A0, IN), - GPIO_INIT(C7, IN), - GPIO_INIT(G0, IN), - GPIO_INIT(G1, IN), - GPIO_INIT(G2, IN), - GPIO_INIT(G3, IN), - GPIO_INIT(H2, IN), - GPIO_INIT(H4, IN), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, OUT1), - GPIO_INIT(I0, IN), - GPIO_INIT(I1, IN), - GPIO_INIT(I5, OUT1), - GPIO_INIT(I6, IN), - GPIO_INIT(I7, IN), - GPIO_INIT(J0, IN), - GPIO_INIT(J7, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, IN), - GPIO_INIT(K4, OUT0), - GPIO_INIT(K6, OUT0), - GPIO_INIT(K7, IN), - GPIO_INIT(N7, IN), - GPIO_INIT(P2, OUT0), - GPIO_INIT(Q0, IN), - GPIO_INIT(Q2, IN), - GPIO_INIT(Q3, IN), - GPIO_INIT(Q6, IN), - GPIO_INIT(Q7, IN), - GPIO_INIT(R0, OUT0), - GPIO_INIT(R1, IN), - GPIO_INIT(R4, IN), - GPIO_INIT(R7, IN), - GPIO_INIT(S3, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S7, IN), - GPIO_INIT(T1, IN), - GPIO_INIT(U4, IN), - GPIO_INIT(U5, IN), - GPIO_INIT(U6, IN), - GPIO_INIT(V0, IN), - GPIO_INIT(W3, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X7, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 0, IN), + GPIO_INIT(C, 7, IN), + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 1, IN), + GPIO_INIT(G, 2, IN), + GPIO_INIT(G, 3, IN), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 4, IN), + GPIO_INIT(H, 6, IN), + GPIO_INIT(H, 7, OUT1), + GPIO_INIT(I, 0, IN), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 5, OUT1), + GPIO_INIT(I, 6, IN), + GPIO_INIT(I, 7, IN), + GPIO_INIT(J, 0, IN), + GPIO_INIT(J, 7, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, IN), + GPIO_INIT(K, 4, OUT0), + GPIO_INIT(K, 6, OUT0), + GPIO_INIT(K, 7, IN), + GPIO_INIT(N, 7, IN), + GPIO_INIT(P, 2, OUT0), + GPIO_INIT(Q, 0, IN), + GPIO_INIT(Q, 2, IN), + GPIO_INIT(Q, 3, IN), + GPIO_INIT(Q, 6, IN), + GPIO_INIT(Q, 7, IN), + GPIO_INIT(R, 0, OUT0), + GPIO_INIT(R, 1, IN), + GPIO_INIT(R, 4, IN), + GPIO_INIT(R, 7, IN), + GPIO_INIT(S, 3, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 7, IN), + GPIO_INIT(T, 1, IN), + GPIO_INIT(U, 4, IN), + GPIO_INIT(U, 5, IN), + GPIO_INIT(U, 6, IN), + GPIO_INIT(V, 0, IN), + GPIO_INIT(W, 3, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 7, OUT0), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h index 35706b4745..24acbccd97 100644 --- a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h +++ b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h @@ -15,62 +15,62 @@ #ifndef _PINMUX_CONFIG_P2371_0000_H_ #define _PINMUX_CONFIG_P2371_0000_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config p2371_0000_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A5, IN), - GPIO_INIT(E4, OUT0), - GPIO_INIT(E6, IN), - GPIO_INIT(G0, IN), - GPIO_INIT(G3, OUT0), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(H6, OUT0), - GPIO_INIT(H7, OUT0), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I3, OUT0), - GPIO_INIT(K4, IN), - GPIO_INIT(K5, OUT0), - GPIO_INIT(K6, IN), - GPIO_INIT(K7, OUT0), - GPIO_INIT(L0, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, OUT0), - GPIO_INIT(S6, OUT0), - GPIO_INIT(S7, OUT0), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V2, OUT0), - GPIO_INIT(V5, OUT0), - GPIO_INIT(V6, OUT0), - GPIO_INIT(V7, OUT1), - GPIO_INIT(X0, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X2, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z4, OUT0), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(BB3, OUT0), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC6, IN), - GPIO_INIT(CC7, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 5, IN), + GPIO_INIT(E, 4, OUT0), + GPIO_INIT(E, 6, IN), + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 3, OUT0), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(H, 6, OUT0), + GPIO_INIT(H, 7, OUT0), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(I, 3, OUT0), + GPIO_INIT(K, 4, IN), + GPIO_INIT(K, 5, OUT0), + GPIO_INIT(K, 6, IN), + GPIO_INIT(K, 7, OUT0), + GPIO_INIT(L, 0, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 5, OUT0), + GPIO_INIT(S, 6, OUT0), + GPIO_INIT(S, 7, OUT0), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, OUT0), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 2, OUT0), + GPIO_INIT(V, 5, OUT0), + GPIO_INIT(V, 6, OUT0), + GPIO_INIT(V, 7, OUT1), + GPIO_INIT(X, 0, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 2, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 5, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 4, OUT0), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(BB, 3, OUT0), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 6, IN), + GPIO_INIT(CC, 7, OUT0), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h index d5be6ecda9..601728e469 100644 --- a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h +++ b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h @@ -15,73 +15,73 @@ #ifndef _PINMUX_CONFIG_P2371_2180_H_ #define _PINMUX_CONFIG_P2371_2180_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config p2371_2180_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A5, IN), - GPIO_INIT(B0, IN), - GPIO_INIT(B1, IN), - GPIO_INIT(B2, IN), - GPIO_INIT(B3, IN), - GPIO_INIT(C0, IN), - GPIO_INIT(C1, IN), - GPIO_INIT(C2, IN), - GPIO_INIT(C3, IN), - GPIO_INIT(C4, IN), - GPIO_INIT(E4, IN), - GPIO_INIT(E5, IN), - GPIO_INIT(E6, IN), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H1, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, IN), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(K4, IN), - GPIO_INIT(K5, OUT0), - GPIO_INIT(K6, IN), - GPIO_INIT(K7, IN), - GPIO_INIT(L1, IN), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, OUT0), - GPIO_INIT(S6, OUT0), - GPIO_INIT(S7, OUT0), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(U2, IN), - GPIO_INIT(U3, IN), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V2, OUT0), - GPIO_INIT(V3, IN), - GPIO_INIT(V5, OUT0), - GPIO_INIT(V6, OUT0), - GPIO_INIT(X0, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X2, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y0, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z2, IN), - GPIO_INIT(Z3, OUT0), - GPIO_INIT(BB0, IN), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(BB3, IN), - GPIO_INIT(CC1, IN), + /* port, pin, init_val */ + GPIO_INIT(A, 5, IN), + GPIO_INIT(B, 0, IN), + GPIO_INIT(B, 1, IN), + GPIO_INIT(B, 2, IN), + GPIO_INIT(B, 3, IN), + GPIO_INIT(C, 0, IN), + GPIO_INIT(C, 1, IN), + GPIO_INIT(C, 2, IN), + GPIO_INIT(C, 3, IN), + GPIO_INIT(C, 4, IN), + GPIO_INIT(E, 4, IN), + GPIO_INIT(E, 5, IN), + GPIO_INIT(E, 6, IN), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 1, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(H, 6, IN), + GPIO_INIT(H, 7, IN), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(K, 4, IN), + GPIO_INIT(K, 5, OUT0), + GPIO_INIT(K, 6, IN), + GPIO_INIT(K, 7, IN), + GPIO_INIT(L, 1, IN), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 5, OUT0), + GPIO_INIT(S, 6, OUT0), + GPIO_INIT(S, 7, OUT0), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, OUT0), + GPIO_INIT(U, 2, IN), + GPIO_INIT(U, 3, IN), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 2, OUT0), + GPIO_INIT(V, 3, IN), + GPIO_INIT(V, 5, OUT0), + GPIO_INIT(V, 6, OUT0), + GPIO_INIT(X, 0, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 2, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 5, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 0, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 2, IN), + GPIO_INIT(Z, 3, OUT0), + GPIO_INIT(BB, 0, IN), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(BB, 3, IN), + GPIO_INIT(CC, 1, IN), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index d80a7d0d3e..7ce656f51a 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -58,6 +58,6 @@ void pinmux_init(void) void start_cpu_fan(void) { /* GPIO_PE4 is PS_VDD_FAN_ENABLE */ - gpio_request(GPIO_PE4, "FAN_VDD"); - gpio_direction_output(GPIO_PE4, 1); + gpio_request(TEGRA_GPIO(E, 4), "FAN_VDD"); + gpio_direction_output(TEGRA_GPIO(E, 4), 1); } diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h index d3233016b5..dd4228f671 100644 --- a/board/nvidia/p2571/pinmux-config-p2571.h +++ b/board/nvidia/p2571/pinmux-config-p2571.h @@ -15,37 +15,37 @@ #ifndef _PINMUX_CONFIG_P2571_H_ #define _PINMUX_CONFIG_P2571_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config p2571_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A0, IN), - GPIO_INIT(A5, IN), - GPIO_INIT(D4, IN), - GPIO_INIT(E4, OUT0), - GPIO_INIT(G0, IN), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V6, OUT1), - GPIO_INIT(X4, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z4, OUT0), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC3, IN), + /* port, pin, init_val */ + GPIO_INIT(A, 0, IN), + GPIO_INIT(A, 5, IN), + GPIO_INIT(D, 4, IN), + GPIO_INIT(E, 4, OUT0), + GPIO_INIT(G, 0, IN), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 6, OUT1), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 4, OUT0), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 3, IN), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig new file mode 100644 index 0000000000..1b1116f020 --- /dev/null +++ b/board/nvidia/p2771-0000/Kconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +if TARGET_P2771_0000 + +config SYS_BOARD + default "p2771-0000" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "p2771-0000" + +endif diff --git a/board/nvidia/p2771-0000/MAINTAINERS b/board/nvidia/p2771-0000/MAINTAINERS new file mode 100644 index 0000000000..4fc4ebd5e0 --- /dev/null +++ b/board/nvidia/p2771-0000/MAINTAINERS @@ -0,0 +1,6 @@ +P2771-0000 BOARD +M: Stephen Warren <swarren@nvidia.com> +S: Maintained +F: board/nvidia/p2771-0000/ +F: include/configs/p2771-0000.h +F: configs/p2771-0000_defconfig diff --git a/board/nvidia/p2771-0000/Makefile b/board/nvidia/p2771-0000/Makefile new file mode 100644 index 0000000000..b28a47d907 --- /dev/null +++ b/board/nvidia/p2771-0000/Makefile @@ -0,0 +1,5 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +obj-y += p2771-0000.o diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c new file mode 100644 index 0000000000..4ba8ebc0dc --- /dev/null +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 2d07001800..fc9c1c9b34 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -20,8 +20,8 @@ void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ - gpio_request(GPIO_PI3, "uart_en"); - gpio_direction_output(GPIO_PI3, 0); + gpio_request(TEGRA_GPIO(I, 3), "uart_en"); + gpio_direction_output(TEGRA_GPIO(I, 3), 0); } #endif diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h index fb444b3b1d..59d53efe44 100644 --- a/board/nvidia/venice2/pinmux-config-venice2.h +++ b/board/nvidia/venice2/pinmux-config-venice2.h @@ -15,70 +15,70 @@ #ifndef _PINMUX_CONFIG_VENICE2_H_ #define _PINMUX_CONFIG_VENICE2_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config venice2_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A0, IN), - GPIO_INIT(C7, IN), - GPIO_INIT(G0, IN), - GPIO_INIT(G1, IN), - GPIO_INIT(G2, IN), - GPIO_INIT(G3, IN), - GPIO_INIT(H2, IN), - GPIO_INIT(H4, IN), - GPIO_INIT(H5, OUT0), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, OUT1), - GPIO_INIT(I0, IN), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I4, OUT0), - GPIO_INIT(I5, OUT1), - GPIO_INIT(I6, IN), - GPIO_INIT(J0, IN), - GPIO_INIT(J7, IN), - GPIO_INIT(K0, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, IN), - GPIO_INIT(K3, IN), - GPIO_INIT(K4, OUT0), - GPIO_INIT(K6, OUT0), - GPIO_INIT(K7, IN), - GPIO_INIT(N7, IN), - GPIO_INIT(O2, IN), - GPIO_INIT(O5, IN), - GPIO_INIT(O6, OUT0), - GPIO_INIT(O7, IN), - GPIO_INIT(P2, OUT0), - GPIO_INIT(Q0, IN), - GPIO_INIT(Q2, IN), - GPIO_INIT(Q3, IN), - GPIO_INIT(Q6, IN), - GPIO_INIT(Q7, IN), - GPIO_INIT(R0, OUT0), - GPIO_INIT(R1, IN), - GPIO_INIT(R4, IN), - GPIO_INIT(S0, IN), - GPIO_INIT(S3, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S7, IN), - GPIO_INIT(T1, IN), - GPIO_INIT(U4, IN), - GPIO_INIT(U5, IN), - GPIO_INIT(U6, IN), - GPIO_INIT(V0, IN), - GPIO_INIT(V1, IN), - GPIO_INIT(W3, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X7, OUT0), - GPIO_INIT(CC5, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 0, IN), + GPIO_INIT(C, 7, IN), + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 1, IN), + GPIO_INIT(G, 2, IN), + GPIO_INIT(G, 3, IN), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 4, IN), + GPIO_INIT(H, 5, OUT0), + GPIO_INIT(H, 6, IN), + GPIO_INIT(H, 7, OUT1), + GPIO_INIT(I, 0, IN), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(I, 4, OUT0), + GPIO_INIT(I, 5, OUT1), + GPIO_INIT(I, 6, IN), + GPIO_INIT(J, 0, IN), + GPIO_INIT(J, 7, IN), + GPIO_INIT(K, 0, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, IN), + GPIO_INIT(K, 3, IN), + GPIO_INIT(K, 4, OUT0), + GPIO_INIT(K, 6, OUT0), + GPIO_INIT(K, 7, IN), + GPIO_INIT(N, 7, IN), + GPIO_INIT(O, 2, IN), + GPIO_INIT(O, 5, IN), + GPIO_INIT(O, 6, OUT0), + GPIO_INIT(O, 7, IN), + GPIO_INIT(P, 2, OUT0), + GPIO_INIT(Q, 0, IN), + GPIO_INIT(Q, 2, IN), + GPIO_INIT(Q, 3, IN), + GPIO_INIT(Q, 6, IN), + GPIO_INIT(Q, 7, IN), + GPIO_INIT(R, 0, OUT0), + GPIO_INIT(R, 1, IN), + GPIO_INIT(R, 4, IN), + GPIO_INIT(S, 0, IN), + GPIO_INIT(S, 3, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 7, IN), + GPIO_INIT(T, 1, IN), + GPIO_INIT(U, 4, IN), + GPIO_INIT(U, 5, IN), + GPIO_INIT(U, 6, IN), + GPIO_INIT(V, 0, IN), + GPIO_INIT(V, 1, IN), + GPIO_INIT(W, 3, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 7, OUT0), + GPIO_INIT(CC, 5, OUT0), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ diff --git a/board/samtec/vining_fpga/MAINTAINERS b/board/samtec/vining_fpga/MAINTAINERS new file mode 100644 index 0000000000..c2002fe3ce --- /dev/null +++ b/board/samtec/vining_fpga/MAINTAINERS @@ -0,0 +1,5 @@ +VINING FPGA BOARD +M: Marek Vasut <marex@denx.de> +S: Maintained +F: include/configs/socfpga_vining_fpga.h +F: configs/socfpga_vining_fpga_defconfig diff --git a/board/samtec/vining_fpga/Makefile b/board/samtec/vining_fpga/Makefile new file mode 100644 index 0000000000..86f9b78cad --- /dev/null +++ b/board/samtec/vining_fpga/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o diff --git a/board/samtec/vining_fpga/qts/iocsr_config.h b/board/samtec/vining_fpga/qts/iocsr_config.h new file mode 100644 index 0000000000..fe5cb61a62 --- /dev/null +++ b/board/samtec/vining_fpga/qts/iocsr_config.h @@ -0,0 +1,660 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00000000, + 0x300C0000, + 0x000000C0, + 0x00000000, + 0x00000000, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00601806, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x300C0300, + 0x300C0000, + 0x0FF00000, + 0x00000000, + 0x000300C0, + 0x00008000, + 0x18060180, + 0x18060000, + 0x00000000, + 0x00000000, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x00000030, + 0x00000000, + 0x0300C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, + 0x0000C030, + 0x00000000, + 0x03000000, + 0x0000000C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680A28, + 0x41034051, + 0x12481A00, + 0x80A280D0, + 0x34051406, + 0x01A02490, + 0x080D0000, + 0x51406802, + 0x02490340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x49034051, + 0x12481A02, + 0x80A280D0, + 0x34030C06, + 0x01A00040, + 0x280D0002, + 0x5140680A, + 0x02490340, + 0xD012481A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8A28A3D5, + 0xF6D1451E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x05140680, + 0xD569A47A, + 0x1E8A28A3, + 0x48F6D145, + 0x00035292, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0x8A28A3D5, + 0xF4D1451E, + 0x034AD348, + 0x821A0186, + 0x0000D000, + 0x00000680, + 0xD569A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x0C864000, + 0x59647A03, + 0xCB2CA3DD, + 0xF6D9651E, + 0x034AD348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDD59647A, + 0x1E8A28A3, + 0x48F6D965, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F16080, + 0x1A041404, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xF228A3D5, + 0xF4D1451E, + 0x03529248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1E8A28A3, + 0x48F6D145, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/qts/pinmux_config.h b/board/samtec/vining_fpga/qts/pinmux_config.h new file mode 100644 index 0000000000..968036587d --- /dev/null +++ b/board/samtec/vining_fpga/qts/pinmux_config.h @@ -0,0 +1,219 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 2, /* FLASHIO0 */ + 2, /* FLASHIO1 */ + 2, /* FLASHIO2 */ + 2, /* FLASHIO3 */ + 2, /* FLASHIO4 */ + 2, /* FLASHIO5 */ + 2, /* FLASHIO6 */ + 2, /* FLASHIO7 */ + 2, /* FLASHIO8 */ + 2, /* FLASHIO9 */ + 2, /* FLASHIO10 */ + 2, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 2, /* GENERALIO15 */ + 2, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 2, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 1, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 1, /* SPIS1USEFPGA */ + 1, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/qts/pll_config.h b/board/samtec/vining_fpga/qts/pll_config.h new file mode 100644 index 0000000000..c8a6e961fd --- /dev/null +++ b/board/samtec/vining_fpga/qts/pll_config.h @@ -0,0 +1,91 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 488281 +#define CONFIG_HPS_CLK_SDMMC_HZ 1953125 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 12500000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/qts/sdram_config.h b/board/samtec/vining_fpga/qts/sdram_config.h new file mode 100644 index 0000000000..74cb405601 --- /dev/null +++ b/board/samtec/vining_fpga/qts/sdram_config.h @@ -0,0 +1,341 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 7 +#define CALIB_VFIFO_OFFSET 5 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080421, + 0x10080520, + 0x10090046, + 0x100a0088, + 0x100b0000, + 0x10380400, + 0x10080441, + 0x100804c0, + 0x100a0026, + 0x10090110, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c new file mode 100644 index 0000000000..f3a92b5e64 --- /dev/null +++ b/board/samtec/vining_fpga/socfpga.c @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ +int board_late_init(void) +{ + const unsigned int phy_nrst_gpio = 0; + const unsigned int usb_nrst_gpio = 35; + int ret; + + status_led_set(1, STATUS_LED_ON); + status_led_set(2, STATUS_LED_ON); + + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio"); + if (!ret) + gpio_direction_output(phy_nrst_gpio, 1); + else + printf("Cannot remove PHY from reset!\n"); + + ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio"); + if (!ret) + gpio_direction_output(usb_nrst_gpio, 1); + else + printf("Cannot remove USB from reset!\n"); + + mdelay(50); + + return 0; +} + +#ifndef CONFIG_SPL_BUILD +int misc_init_r(void) +{ + uchar data[128]; + char str[32]; + u32 serial; + int ret; + + /* EEPROM is at bus 0. */ + ret = i2c_set_bus_num(0); + if (ret) { + puts("Cannot select EEPROM I2C bus.\n"); + return 0; + } + + /* EEPROM is at address 0x50. */ + ret = eeprom_read(0x50, 0, data, sizeof(data)); + if (ret) { + puts("Cannot read I2C EEPROM.\n"); + return 0; + } + + /* Check EEPROM signature. */ + if (!(data[0] == 0xa5 && data[1] == 0x5a)) { + puts("Invalid I2C EEPROM signature.\n"); + setenv("unit_serial", "invalid"); + setenv("unit_ident", "VINing-xxxx-STD"); + setenv("hostname", "vining-invalid"); + return 0; + } + + /* If 'unit_serial' is already set, do nothing. */ + if (!getenv("unit_serial")) { + /* This field is Big Endian ! */ + serial = (data[0x54] << 24) | (data[0x55] << 16) | + (data[0x56] << 8) | (data[0x57] << 0); + memset(str, 0, sizeof(str)); + sprintf(str, "%07i", serial); + setenv("unit_serial", str); + } + + if (!getenv("unit_ident")) { + memset(str, 0, sizeof(str)); + memcpy(str, &data[0x2e], 18); + setenv("unit_ident", str); + } + + /* Set ethernet address from EEPROM. */ + if (!getenv("ethaddr") && is_valid_ethaddr(&data[0x62])) + eth_setenv_enetaddr("ethaddr", &data[0x62]); + + return 0; +} +#endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index b42546a148..bde5ac7c99 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -678,71 +678,71 @@ static struct ti_usb_phy_device usb_phy2_device = { .index = 1, }; +int usb_gadget_handle_interrupts(int index) +{ + u32 status; + + status = dwc3_omap_uboot_interrupt_status(index); + if (status) + dwc3_uboot_handle_interrupt(index); + + return 0; +} +#endif /* CONFIG_USB_DWC3 */ + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) int board_usb_init(int index, enum usb_init_type init) { enable_usb_clocks(index); +#ifdef CONFIG_USB_DWC3 switch (index) { case 0: if (init == USB_INIT_DEVICE) { usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; - } else { - usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; - usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; + dwc3_omap_uboot_init(&usb_otg_ss1_glue); + ti_usb_phy_uboot_init(&usb_phy1_device); + dwc3_uboot_init(&usb_otg_ss1); } - - dwc3_omap_uboot_init(&usb_otg_ss1_glue); - ti_usb_phy_uboot_init(&usb_phy1_device); - dwc3_uboot_init(&usb_otg_ss1); break; case 1: if (init == USB_INIT_DEVICE) { usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; - } else { - usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; - usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; + ti_usb_phy_uboot_init(&usb_phy2_device); + dwc3_omap_uboot_init(&usb_otg_ss2_glue); + dwc3_uboot_init(&usb_otg_ss2); } - - ti_usb_phy_uboot_init(&usb_phy2_device); - dwc3_omap_uboot_init(&usb_otg_ss2_glue); - dwc3_uboot_init(&usb_otg_ss2); break; default: printf("Invalid Controller Index\n"); } +#endif return 0; } int board_usb_cleanup(int index, enum usb_init_type init) { +#ifdef CONFIG_USB_DWC3 switch (index) { case 0: case 1: - ti_usb_phy_uboot_exit(index); - dwc3_uboot_exit(index); - dwc3_omap_uboot_exit(index); + if (init == USB_INIT_DEVICE) { + ti_usb_phy_uboot_exit(index); + dwc3_uboot_exit(index); + dwc3_omap_uboot_exit(index); + } break; default: printf("Invalid Controller Index\n"); } +#endif disable_usb_clocks(index); return 0; } - -int usb_gadget_handle_interrupts(int index) -{ - u32 status; - - status = dwc3_omap_uboot_interrupt_status(index); - if (status) - dwc3_uboot_handle_interrupt(index); - - return 0; -} -#endif +#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ #ifdef CONFIG_DRIVER_TI_CPSW diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 9904047a07..ccf97b2b13 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -63,28 +63,28 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) } static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { - .sdram_config_init = 0x61851b32, - .sdram_config = 0x61851b32, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x000040F1, - .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xcccf36ab, - .sdram_tim2 = 0x308f7fda, - .sdram_tim3 = 0x409f88a8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x5007190b, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400b, - .emif_ddr_phy_ctlr_1 = 0x0e24400b, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00910091, - .emif_ddr_ext_phy_ctrl_3 = 0x00950095, - .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, - .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 + .sdram_config_init = 0x61851b32, + .sdram_config = 0x61851b32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xcccf36ab, + .sdram_tim2 = 0x308f7fda, + .sdram_tim3 = 0x409f88a8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, + .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 }; /* Ext phy ctrl regs 1-35 */ @@ -127,28 +127,28 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { }; static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { - .sdram_config_init = 0x61851b32, - .sdram_config = 0x61851b32, - .sdram_config2 = 0x08000000, - .ref_ctrl = 0x000040F1, - .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xcccf36b3, - .sdram_tim2 = 0x308f7fda, - .sdram_tim3 = 0x407f88a8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x5007190b, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400b, - .emif_ddr_phy_ctlr_1 = 0x0e24400b, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00910091, - .emif_ddr_ext_phy_ctrl_3 = 0x00950095, - .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, - .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 + .sdram_config_init = 0x61851b32, + .sdram_config = 0x61851b32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xcccf36b3, + .sdram_tim2 = 0x308f7fda, + .sdram_tim3 = 0x407f88a8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009b009b, + .emif_ddr_ext_phy_ctrl_5 = 0x009e009e, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 }; static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { @@ -216,41 +216,77 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) } struct vcores_data beagle_x15_volts = { - .mpu.value = VDD_MPU_DRA752, - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.value = VDD_MPU_DRA7, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS659038_REG_ADDR_SMPS12, .mpu.pmic = &tps659038, - .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, - .eve.value = VDD_EVE_DRA752, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.value = VDD_EVE_DRA7, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS659038_REG_ADDR_SMPS45, .eve.pmic = &tps659038, .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, - .gpu.value = VDD_GPU_DRA752, - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.value = VDD_GPU_DRA7, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS659038_REG_ADDR_SMPS45, .gpu.pmic = &tps659038, .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, - .core.value = VDD_CORE_DRA752, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.value = VDD_CORE_DRA7, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, .core.addr = TPS659038_REG_ADDR_SMPS6, .core.pmic = &tps659038, - .iva.value = VDD_IVA_DRA752, - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.value = VDD_IVA_DRA7, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS659038_REG_ADDR_SMPS45, .iva.pmic = &tps659038, .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, }; +struct vcores_data am572x_idk_volts = { + .mpu.value = VDD_MPU_DRA7, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, + .mpu.pmic = &tps659038, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + + .eve.value = VDD_EVE_DRA7, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45, + .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, + + .gpu.value = VDD_GPU_DRA7, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS6, + .gpu.pmic = &tps659038, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, + + .core.value = VDD_CORE_DRA7, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS7, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA7, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS8, + .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, +}; + #ifdef CONFIG_SPL_BUILD /* No env to setup for SPL */ static inline void setup_board_eeprom_env(void) { } @@ -315,11 +351,18 @@ invalid_eeprom: #endif /* CONFIG_SPL_BUILD */ +void vcores_init(void) +{ + if (board_is_am572x_idk()) + *omap_vcores = &am572x_idk_volts; + else + *omap_vcores = &beagle_x15_volts; +} + void hw_data_init(void) { *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; - *omap_vcores = &beagle_x15_volts; *ctrl = &dra7xx_ctrl; } @@ -439,6 +482,19 @@ static struct ti_usb_phy_device usb_phy2_device = { .index = 1, }; +int usb_gadget_handle_interrupts(int index) +{ + u32 status; + + status = dwc3_omap_uboot_interrupt_status(index); + if (status) + dwc3_uboot_handle_interrupt(index); + + return 0; +} +#endif /* CONFIG_USB_DWC3 */ + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) int board_usb_init(int index, enum usb_init_type init) { enable_usb_clocks(index); @@ -448,31 +504,23 @@ int board_usb_init(int index, enum usb_init_type init) printf("port %d can't be used as device\n", index); disable_usb_clocks(index); return -EINVAL; - } else { - usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; - usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; - setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, - OTG_SS_CLKCTRL_MODULEMODE_HW | - OPTFCLKEN_REFCLK960M); } - - ti_usb_phy_uboot_init(&usb_phy1_device); - dwc3_omap_uboot_init(&usb_otg_ss1_glue); - dwc3_uboot_init(&usb_otg_ss1); break; case 1: if (init == USB_INIT_DEVICE) { +#ifdef CONFIG_USB_DWC3 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; + ti_usb_phy_uboot_init(&usb_phy2_device); + dwc3_omap_uboot_init(&usb_otg_ss2_glue); + dwc3_uboot_init(&usb_otg_ss2); +#endif } else { printf("port %d can't be used as host\n", index); disable_usb_clocks(index); return -EINVAL; } - ti_usb_phy_uboot_init(&usb_phy2_device); - dwc3_omap_uboot_init(&usb_otg_ss2_glue); - dwc3_uboot_init(&usb_otg_ss2); break; default: printf("Invalid Controller Index\n"); @@ -483,31 +531,24 @@ int board_usb_init(int index, enum usb_init_type init) int board_usb_cleanup(int index, enum usb_init_type init) { +#ifdef CONFIG_USB_DWC3 switch (index) { case 0: case 1: - ti_usb_phy_uboot_exit(index); - dwc3_uboot_exit(index); - dwc3_omap_uboot_exit(index); + if (init == USB_INIT_DEVICE) { + ti_usb_phy_uboot_exit(index); + dwc3_uboot_exit(index); + dwc3_omap_uboot_exit(index); + } break; default: printf("Invalid Controller Index\n"); } +#endif disable_usb_clocks(index); return 0; } - -int usb_gadget_handle_interrupts(int index) -{ - u32 status; - - status = dwc3_omap_uboot_interrupt_status(index); - if (status) - dwc3_uboot_handle_interrupt(index); - - return 0; -} -#endif +#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ #ifdef CONFIG_DRIVER_TI_CPSW diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index b62c412250..8f16845d8e 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -117,12 +117,28 @@ int board_mmc_init(bd_t *bis) #endif #ifdef CONFIG_BOARD_EARLY_INIT_F + +static void k2g_reset_mux_config(void) +{ + /* Unlock the reset mux register */ + clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); + + /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */ + clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK, + RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT); + + /* lock the reset mux register to prevent any spurious writes. */ + setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); +} + int board_early_init_f(void) { init_plls(); k2g_mux_config(); + k2g_reset_mux_config(); + /* deassert FLASH_HOLD */ clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET, BIT(9)); diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 879f25a538..68fbf49579 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -103,11 +103,11 @@ void pin_mux_usb(void) pinmux_tristate_disable(PMUX_PINGRP_DTE); /* Reset ASIX using LAN_RESET */ - gpio_request(GPIO_PV4, "LAN_RESET"); - gpio_direction_output(GPIO_PV4, 0); + gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET"); + gpio_direction_output(TEGRA_GPIO(V, 4), 0); pinmux_tristate_disable(PMUX_PINGRP_GPV); udelay(5); - gpio_set_value(GPIO_PV4, 1); + gpio_set_value(TEGRA_GPIO(V, 4), 1); /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ pinmux_tristate_disable(PMUX_PINGRP_SPIG); diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 44b5beb928..e32362a93a 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -47,8 +47,8 @@ void pinmux_init(void) void pin_mux_usb(void) { /* Reset ASIX using LAN_RESET */ - gpio_request(GPIO_PDD0, "LAN_RESET"); - gpio_direction_output(GPIO_PDD0, 0); + gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET"); + gpio_direction_output(TEGRA_GPIO(DD, 0), 0); udelay(5); - gpio_set_value(GPIO_PDD0, 1); + gpio_set_value(TEGRA_GPIO(DD, 0), 1); } |