diff options
Diffstat (limited to 'board')
73 files changed, 1085 insertions, 193 deletions
diff --git a/board/advantech/Kconfig b/board/advantech/Kconfig new file mode 100644 index 0000000000..a8d49691f7 --- /dev/null +++ b/board/advantech/Kconfig @@ -0,0 +1,28 @@ +if VENDOR_ADVANTECH + +choice + prompt "Mainboard model" + optional + +config TARGET_SOM_DB5800_SOM_6867 + bool "Advantech SOM-DB5800 & SOM-6867" + help + Advantech SOM-DB5800 COM Express development board with SOM-6867 + installed. + + SOM-6867 is a COM Express Type 6 Compact Module with either an Intel + Atom E3845 or Celeron N2920 processor. + + SOM-DB5800 is a COM Express Development board with: + 10/100/1000 Ethernet + PCIe slots + 4x USB ports + HDMI/DisplayPort/DVI, LVDS, VGA + SATA ports + ALC892 HD Audio Codec + +endchoice + +source "board/advantech/som-db5800-som-6867/Kconfig" + +endif diff --git a/board/advantech/som-db5800-som-6867/.gitignore b/board/advantech/som-db5800-som-6867/.gitignore new file mode 100644 index 0000000000..6eb8a5481a --- /dev/null +++ b/board/advantech/som-db5800-som-6867/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig new file mode 100644 index 0000000000..f6f3748fc3 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/Kconfig @@ -0,0 +1,28 @@ +if TARGET_SOM_DB5800_SOM_6867 + +config SYS_BOARD + default "som-db5800-som-6867" + +config SYS_VENDOR + default "advantech" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "som-db5800-som-6867" + +config SYS_TEXT_BASE + default 0xfff00000 if !EFI_STUB + default 0x01110000 if EFI_STUB + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR if !EFI_STUB + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + +config PCIE_ECAM_BASE + default 0xe0000000 + +endif diff --git a/board/advantech/som-db5800-som-6867/MAINTAINERS b/board/advantech/som-db5800-som-6867/MAINTAINERS new file mode 100644 index 0000000000..92989bfba0 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/MAINTAINERS @@ -0,0 +1,7 @@ +Advantech SOM-DB5800-SOM-6867 +M: George McCollister <george.mccollister@gmail.com> +S: Maintained +F: board/advantech/som-db5800-som-6867 +F: include/configs/som-db5800-som-6867.h +F: configs/som-db5800-som-6867_defconfig +F: arch/x86/dts/baytrail_som-db5800-som-6867.dts diff --git a/board/advantech/som-db5800-som-6867/Makefile b/board/advantech/som-db5800-som-6867/Makefile new file mode 100644 index 0000000000..9837aa0c79 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2015, Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += som-db5800-som-6867.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/advantech/som-db5800-som-6867/acpi/mainboard.asl b/board/advantech/som-db5800-som-6867/acpi/mainboard.asl new file mode 100644 index 0000000000..21785ea73b --- /dev/null +++ b/board/advantech/som-db5800-som-6867/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/board/advantech/som-db5800-som-6867/dsdt.asl b/board/advantech/som-db5800-som-6867/dsdt.asl new file mode 100644 index 0000000000..6042011acf --- /dev/null +++ b/board/advantech/som-db5800-som-6867/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c new file mode 100644 index 0000000000..5bed2c1146 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * Copyright (C) 2016 George McCollister <george.mccollister@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +int board_early_init_f(void) +{ + /* + * The FSP enables the BayTrail internal legacy UART (again). + * Disable it again, so that the one on the EC can be used. + */ + setup_internal_uart(0); + + return 0; +} + +int arch_early_init_r(void) +{ + return 0; +} diff --git a/board/advantech/som-db5800-som-6867/start.S b/board/advantech/som-db5800-som-6867/start.S new file mode 100644 index 0000000000..2c941a4a51 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 973b57969f..e34af6c4d9 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -31,13 +31,15 @@ U_BOOT_DEVICE(vexpress_serials) = { static struct mm_region vexpress64_mem_map[] = { { - .base = 0x0UL, + .virt = 0x0UL, + .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .base = 0x80000000UL, + .virt = 0x80000000UL, + .phys = 0x80000000UL, .size = 0xff80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index 9131a385fd..960ca53b02 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -45,16 +45,19 @@ DECLARE_GLOBAL_DATA_PTR; static struct mm_region thunderx_mem_map[] = { { - .base = 0x000000000000UL, + .virt = 0x000000000000UL, + .phys = 0x000000000000UL, .size = 0x40000000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE, }, { - .base = 0x800000000000UL, + .virt = 0x800000000000UL, + .phys = 0x800000000000UL, .size = 0x40000000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE, }, { - .base = 0x840000000000UL, + .virt = 0x840000000000UL, + .phys = 0x840000000000UL, .size = 0x40000000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE, diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c index 6a946d5758..737e6103f3 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c +++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c @@ -12,6 +12,7 @@ int board_early_init_f(void) { +#ifndef CONFIG_INTERNAL_UART /* * The FSP enables the BayTrail internal legacy UART (again). * Disable it again, so that the Winbond one can be used. @@ -21,6 +22,7 @@ int board_early_init_f(void) /* Enable the legacy UART in the Winbond W83627 Super IO chip */ winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1), UART0_BASE, UART0_IRQ); +#endif return 0; } diff --git a/board/evb-rk3288/evb-rk3288/Kconfig b/board/evb-rk3288/evb-rk3288/Kconfig new file mode 100644 index 0000000000..b201acb983 --- /dev/null +++ b/board/evb-rk3288/evb-rk3288/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3288 + +config SYS_BOARD + default "evb-rk3288" + +config SYS_VENDOR + default "evb-rk3288" + +config SYS_CONFIG_NAME + default "evb-rk3288" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/evb-rk3288/evb-rk3288/MAINTAINERS b/board/evb-rk3288/evb-rk3288/MAINTAINERS new file mode 100644 index 0000000000..222c254c61 --- /dev/null +++ b/board/evb-rk3288/evb-rk3288/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RK3288 +M: Lin Huang <hl@rock-chips.com> +S: Maintained +F: board/evb-rk3288/evb-rk3288 +F: include/configs/evb-rk3288.h +F: configs/evb-rk3288_defconfig diff --git a/board/evb-rk3288/evb-rk3288/Makefile b/board/evb-rk3288/evb-rk3288/Makefile new file mode 100644 index 0000000000..c11b657601 --- /dev/null +++ b/board/evb-rk3288/evb-rk3288/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb-rk3288.o diff --git a/board/evb-rk3288/evb-rk3288/evb-rk3288.c b/board/evb-rk3288/evb-rk3288/evb-rk3288.c new file mode 100644 index 0000000000..a82f0ae283 --- /dev/null +++ b/board/evb-rk3288/evb-rk3288/evb-rk3288.c @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +void board_boot_order(u32 *spl_boot_list) +{ + /* eMMC prior to sdcard. */ + spl_boot_list[0] = BOOT_DEVICE_MMC2; + spl_boot_list[1] = BOOT_DEVICE_MMC1; +} diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index ecfcc8253a..dea231b866 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -6,7 +6,21 @@ #include <common.h> #include <fsl_validate.h> +#include <fsl_secboot_err.h> #include <fsl_sfp.h> +#include <dm/root.h> + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) +#include <spl.h> +#endif + +#ifdef CONFIG_ADDR_MAP +#include <asm/mmu.h> +#endif + +#ifdef CONFIG_FSL_CORENET +#include <asm/fsl_pamu.h> +#endif #ifdef CONFIG_LS102XA #include <asm/arch/immap_ls102xa.h> @@ -52,6 +66,7 @@ int fsl_check_boot_mode_secure(void) return 0; } +#ifndef CONFIG_SPL_BUILD int fsl_setenv_chain_of_trust(void) { /* Check Boot Mode @@ -68,3 +83,76 @@ int fsl_setenv_chain_of_trust(void) setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD); return 0; } +#endif + +#ifdef CONFIG_SPL_BUILD +void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) +{ + int res; + + /* + * Check Boot Mode + * If Boot Mode is Non-Secure, skip validation + */ + if (fsl_check_boot_mode_secure() == 0) + return; + + printf("SPL: Validating U-Boot image\n"); + +#ifdef CONFIG_ADDR_MAP + init_addr_map(); +#endif + +#ifdef CONFIG_FSL_CORENET + if (pamu_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); +#endif + +#ifdef CONFIG_FSL_CAAM + if (sec_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT); +#endif + +/* + * dm_init_and_scan() is called as part of common SPL framework, so no + * need to call it again but in case of powerpc platforms which currently + * do not use common SPL framework, so need to call this function here. + */ +#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK)) + dm_init_and_scan(true); +#endif + res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH, + &img_addr); + + if (res == 0) + printf("SPL: Validation of U-boot successful\n"); +} + +#ifdef CONFIG_SPL_FRAMEWORK +/* Override weak funtion defined in SPL framework to enable validation + * of main u-boot image before jumping to u-boot image. + */ +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + typedef void __noreturn (*image_entry_noargs_t)(void); + uint32_t hdr_addr; + + image_entry_noargs_t image_entry = + (image_entry_noargs_t)(unsigned long)spl_image->entry_point; + + hdr_addr = (spl_image->entry_point + spl_image->size - + CONFIG_U_BOOT_HDR_SIZE); + spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point); + /* + * In case of failure in validation, spl_validate_uboot would + * not return back in case of Production environment with ITS=1. + * Thus U-Boot will not start. + * In Development environment (ITS=0 and SB_EN=1), the function + * may return back in case of non-fatal failures. + */ + + debug("image entry point: 0x%X\n", spl_image->entry_point); + image_entry(); +} +#endif /* ifdef CONFIG_SPL_FRAMEWORK */ +#endif /* ifdef CONFIG_SPL_BUILD */ diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index ab0234412c..f0390c129f 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -8,3 +8,4 @@ obj-y += ls1021aqds.o obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/psci.S b/board/freescale/ls1021aqds/psci.S new file mode 100644 index 0000000000..598168c7b0 --- /dev/null +++ b/board/freescale/ls1021aqds/psci.S @@ -0,0 +1,33 @@ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Wang Dongsheng <dongsheng.wang@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +#include <asm/armv7.h> +#include <asm/psci.h> + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: + @ Get QIXIS base address + movw r1, #(QIXIS_BASE & 0xffff) + movt r1, #(QIXIS_BASE >> 16) + + ldrb r2, [r1, #QIXIS_PWR_CTL] + orr r2, r2, #QIXIS_PWR_CTL_POWEROFF + strb r2, [r1, #QIXIS_PWR_CTL] + +1: wfi + b 1b + + .popsection diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile index 01296c04b2..5238b158d7 100644 --- a/board/freescale/ls1021atwr/Makefile +++ b/board/freescale/ls1021atwr/Makefile @@ -6,3 +6,4 @@ obj-y += ls1021atwr.o obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index c69c9cba42..77482a947b 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -503,6 +503,13 @@ int board_init(void) return 0; } +#if defined(CONFIG_SPL_BUILD) +void spl_board_init(void) +{ + ls102xa_smmu_stream_id_init(); +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { diff --git a/board/freescale/ls1021atwr/psci.S b/board/freescale/ls1021atwr/psci.S new file mode 100644 index 0000000000..bec73568d3 --- /dev/null +++ b/board/freescale/ls1021atwr/psci.S @@ -0,0 +1,25 @@ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Wang Dongsheng <dongsheng.wang@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +#include <asm/armv7.h> +#include <asm/psci.h> + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: +1: wfi + b 1b + + .popsection diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS index 65a0af1930..992c54c95f 100644 --- a/board/freescale/ls1043aqds/MAINTAINERS +++ b/board/freescale/ls1043aqds/MAINTAINERS @@ -9,3 +9,4 @@ F: configs/ls1043aqds_nand_defconfig F: configs/ls1043aqds_sdcard_ifc_defconfig F: configs/ls1043aqds_sdcard_qspi_defconfig F: configs/ls1043aqds_qspi_defconfig +F: configs/ls1043aqds_lpuart_defconfig diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 0fd835d74f..d4540d0a9a 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -128,7 +128,7 @@ phys_size_t initdram(int board_type) void dram_init_banksize(void) { /* - * gd->secure_ram tracks the location of secure memory. + * gd->arch.secure_ram tracks the location of secure memory. * It was set as if the memory starts from 0. * The address needs to add the offset of its bank. */ @@ -139,16 +139,17 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[1].start + - gd->secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } else { gd->bd->bi_dram[0].size = gd->ram_size; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } } diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index b7e9c21727..941dfbc447 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -327,6 +327,7 @@ int ft_board_setup(void *blob, bd_t *bd) { u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; + u8 reg; /* fixup DT for the two DDR banks */ base[0] = gd->bd->bi_dram[0].start; @@ -341,6 +342,15 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif + + reg = QIXIS_READ(brdcfg[0]); + reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + /* Disable IFC if QSPI is enabled */ + if (reg == 0xF) + do_fixup_by_compat(blob, "fsl,ifc", + "status", "disabled", 8 + 1, 1); + return 0; } #endif diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 1e2fd2ed0c..61b1cc4f30 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -189,7 +189,7 @@ phys_size_t initdram(int board_type) void dram_init_banksize(void) { /* - * gd->secure_ram tracks the location of secure memory. + * gd->arch.secure_ram tracks the location of secure memory. * It was set as if the memory starts from 0. * The address needs to add the offset of its bank. */ @@ -200,16 +200,17 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[1].start + - gd->secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } else { gd->bd->bi_dram[0].size = gd->ram_size; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } } diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 14365207da..d3e37b4996 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -24,7 +24,9 @@ #ifdef CONFIG_U_QE #include <fsl_qe.h> #endif - +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -92,6 +94,10 @@ int board_init(void) enable_layerscape_ns_access(); #endif +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + #ifdef CONFIG_U_QE u_qe_init(); #endif diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c index 1827ddca69..e6130ec709 100644 --- a/board/freescale/ls2080a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -177,7 +177,7 @@ void dram_init_banksize(void) #endif /* - * gd->secure_ram tracks the location of secure memory. + * gd->arch.secure_ram tracks the location of secure memory. * It was set as if the memory starts from 0. * The address needs to add the offset of its bank. */ @@ -188,16 +188,17 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[1].start + - gd->secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } else { gd->bd->bi_dram[0].size = gd->ram_size; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index 076532622f..8f78b67baa 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -6,6 +6,7 @@ F: board/freescale/ls2080a/ls2080aqds.c F: include/configs/ls2080aqds.h F: configs/ls2080aqds_defconfig F: configs/ls2080aqds_nand_defconfig +F: configs/ls2080aqds_qspi_defconfig LS2080A_SECURE_BOOT BOARD M: Saksham Jain <saksham.jain@nxp.freescale.com> diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index fcb03665bf..9c6f477c7f 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -177,7 +177,7 @@ void dram_init_banksize(void) #endif /* - * gd->secure_ram tracks the location of secure memory. + * gd->arch.secure_ram tracks the location of secure memory. * It was set as if the memory starts from 0. * The address needs to add the offset of its bank. */ @@ -188,16 +188,17 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[1].start + - gd->secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } else { gd->bd->bi_dram[0].size = gd->ram_size; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index a04d21be13..ecd1e71ad8 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -177,7 +177,7 @@ void dram_init_banksize(void) #endif /* - * gd->secure_ram tracks the location of secure memory. + * gd->arch.secure_ram tracks the location of secure memory. * It was set as if the memory starts from 0. * The address needs to add the offset of its bank. */ @@ -188,16 +188,17 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[1].start + - gd->secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } else { gd->bd->bi_dram[0].size = gd->ram_size; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } diff --git a/board/freescale/t104xrdb/t104x_pbi_sb.cfg b/board/freescale/t104xrdb/t104x_pbi_sb.cfg new file mode 100644 index 0000000000..98dc8e4c24 --- /dev/null +++ b/board/freescale/t104xrdb/t104x_pbi_sb.cfg @@ -0,0 +1,38 @@ +#PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 bffc0007 +09010f00 081e000d +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 bffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 bf000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF +090e0200 bffd0000 +091380c0 000FFFFF diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 95c15aa596..7c0511e268 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -28,7 +28,8 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + !defined(CONFIG_SECURE_BOOT) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the * SRAM is at 0xfffc0000, it covered the 0xfffff000. @@ -36,6 +37,18 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), + +#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot + * the physical address of the SRAM is at 0xbffc0000, + * and virtual address is 0xfffc0000 + */ + + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR, + CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), #else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c index 426dc05c7d..35fa06a2ee 100644 --- a/board/gdsys/405ep/405ep.c +++ b/board/gdsys/405ep/405ep.c @@ -31,14 +31,6 @@ int get_fpga_state(unsigned dev) return gd->arch.fpga_state[dev]; } -void print_fpga_state(unsigned dev) -{ - if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED) - puts(" Waiting for FPGA-DONE timed out.\n"); - if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) - puts(" FPGA reflection test failed.\n"); -} - int board_early_init_f(void) { unsigned k; diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index 54c7eb3a12..e400d1945a 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -109,7 +109,10 @@ static void print_fpga_info(unsigned dev) && !((hardware_version == HWVER_101) && (fpga_state == FPGA_STATE_DONE_FAILED))) { puts("not available\n"); - print_fpga_state(dev); + if (fpga_state & FPGA_STATE_DONE_FAILED) + puts(" Waiting for FPGA-DONE timed out.\n"); + if (fpga_state & FPGA_STATE_REFLECTION_FAILED) + puts(" FPGA reflection test failed.\n"); return; } diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c index c1a583ffbe..9e1c57f808 100644 --- a/board/gdsys/405ex/405ex.c +++ b/board/gdsys/405ex/405ex.c @@ -24,14 +24,6 @@ int get_fpga_state(unsigned dev) return gd->arch.fpga_state[dev]; } -void print_fpga_state(unsigned dev) -{ - if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED) - puts(" Waiting for FPGA-DONE timed out.\n"); - if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) - puts(" FPGA reflection test failed.\n"); -} - int board_early_init_f(void) { u32 val; diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index 4338a33126..1b8e035b4b 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -31,14 +31,6 @@ int get_fpga_state(unsigned dev) return gd->arch.fpga_state[dev]; } -void print_fpga_state(unsigned dev) -{ - if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED) - puts(" Waiting for FPGA-DONE timed out.\n"); - if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) - puts(" FPGA reflection test failed.\n"); -} - int board_early_init_f(void) { unsigned k; diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c index 9671c5aa54..3786842d36 100644 --- a/board/gumstix/duovero/duovero.c +++ b/board/gumstix/duovero/duovero.c @@ -128,7 +128,7 @@ void board_mmc_power_init(void) #define GPMC_BASEADDR_MASK 0x3F #define GPMC_CS_ENABLE 0x1 -static void enable_gpmc_net_config(const u32 *gpmc_config, struct gpmc_cs *cs, +static void enable_gpmc_net_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base, u32 size) { writel(0, &cs->config7); diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 7abc67874a..72d6334b5f 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -93,12 +93,14 @@ U_BOOT_DEVICE(hikey_seriala) = { static struct mm_region hikey_mem_map[] = { { - .base = 0x0UL, + .virt = 0x0UL, + .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .base = 0x80000000UL, + .virt = 0x80000000UL, + .phys = 0x80000000UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index d1a6a6f56f..808955e69e 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -10,6 +10,7 @@ #include <ns16550.h> #include <twl4030.h> #include <netdev.h> +#include <spl.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/mem.h> @@ -17,21 +18,32 @@ #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> #include <asm/mach-types.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/onenand.h> +#include <jffs2/load_kernel.h> #include "igep00x0.h" DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CMD_NET) -/* GPMC definitions for LAN9221 chips */ -static const u32 gpmc_lan_config[] = { - NET_LAN9221_GPMC_CONFIG1, - NET_LAN9221_GPMC_CONFIG2, - NET_LAN9221_GPMC_CONFIG3, - NET_LAN9221_GPMC_CONFIG4, - NET_LAN9221_GPMC_CONFIG5, - NET_LAN9221_GPMC_CONFIG6, -}; +const omap3_sysinfo sysinfo = { + DDR_STACKED, +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) + "IGEPv2", +#endif +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) + "IGEP COM MODULE/ELECTRON", +#endif +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) + "IGEP COM PROTON", +#endif +#if defined(CONFIG_ENV_IS_IN_ONENAND) + "ONENAND", +#else + "NAND", #endif +}; static const struct ns16550_platdata igep_serial = { .base = OMAP34XX_UART3, @@ -50,7 +62,25 @@ U_BOOT_DEVICE(igep_uart) = { */ int board_init(void) { - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + int loops = 100; + + /* find out flash memory type, assume NAND first */ + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + gpmc_init(); + + /* Issue a RESET and then READID */ + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { + udelay(1); + if (--loops == 0) { + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; + gpmc_init(); /* reinitialize for OneNAND */ + break; + } + } + /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); @@ -63,45 +93,60 @@ int board_init(void) #ifdef CONFIG_SPL_BUILD /* - * Routine: omap_rev_string - * Description: For SPL builds output board rev - */ -void omap_rev_string(void) -{ -} - -/* * Routine: get_board_mem_timings * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ void get_board_mem_timings(struct board_sdrc_timings *timings) { - timings->mr = MICRON_V_MR_165; -#ifdef CONFIG_BOOT_NAND - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; -#else - if (get_cpu_family() == CPU_OMAP34XX) { - timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_165; - timings->ctrlb = NUMONYX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + int mfr, id, err = identify_nand_chip(&mfr, &id); - } else { - timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_200; - timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->mr = MICRON_V_MR_165; + if (!err && mfr == NAND_MFR_MICRON) { + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + } else { + if (get_cpu_family() == CPU_OMAP34XX) { + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } else { + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; } -#endif +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; } #endif +#endif -#if defined(CONFIG_CMD_NET) +int onenand_board_init(struct mtd_info *mtd) +{ + if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) { + struct onenand_chip *this = mtd->priv; + this->base = (void *)CONFIG_SYS_ONENAND_BASE; + return 0; + } + return 1; +} +#if defined(CONFIG_CMD_NET) static void reset_net_chip(int gpio) { if (!gpio_request(gpio, "eth nrst")) { @@ -122,6 +167,14 @@ static void reset_net_chip(int gpio) static void setup_net_chip(void) { struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + static const u32 gpmc_lan_config[] = { + NET_LAN9221_GPMC_CONFIG1, + NET_LAN9221_GPMC_CONFIG2, + NET_LAN9221_GPMC_CONFIG3, + NET_LAN9221_GPMC_CONFIG4, + NET_LAN9221_GPMC_CONFIG5, + NET_LAN9221_GPMC_CONFIG6, + }; enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], CONFIG_SMC911X_BASE, GPMC_SIZE_16M); @@ -136,6 +189,15 @@ static void setup_net_chip(void) reset_net_chip(64); } + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SMC911X + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +#else + return 0; +#endif +} #else static inline void setup_net_chip(void) {} #endif @@ -183,6 +245,23 @@ int misc_init_r(void) return 0; } +void board_mtdparts_default(const char **mtdids, const char **mtdparts) +{ + struct mtd_info *mtd = get_mtd_device(NULL, 0); + if (mtd) { + static char ids[24]; + static char parts[48]; + const char *linux_name = "omap2-nand"; + if (strncmp(mtd->name, "onenand0", 8) == 0) + linux_name = "omap2-onenand"; + snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name); + snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)", + linux_name, 4 * mtd->erasesize >> 10); + *mtdids = ids; + *mtdparts = parts; + } +} + /* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the @@ -201,14 +280,3 @@ void set_muxconf_regs(void) MUX_IGEP0030(); #endif } - -#if defined(CONFIG_CMD_NET) -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SMC911X - return smc911x_initialize(0, CONFIG_SMC911X_BASE); -#else - return 0; -#endif -} -#endif diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h index 3c7ff9b148..5698efab5d 100644 --- a/board/isee/igep00x0/igep00x0.h +++ b/board/isee/igep00x0/igep00x0.h @@ -7,26 +7,6 @@ #ifndef _IGEP00X0_H_ #define _IGEP00X0_H_ -const omap3_sysinfo sysinfo = { - DDR_STACKED, -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) - "IGEPv2", -#endif -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) - "IGEP COM MODULE/ELECTRON", -#endif -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) - "IGEP COM PROTON", -#endif -#if defined(CONFIG_ENV_IS_IN_ONENAND) - "ONENAND", -#else - "NAND", -#endif -}; - -static void setup_net_chip(void); - /* * IEN - Input Enable * IDIS - Input Disable diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index a42f3eca33..0829b7fa06 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -53,7 +53,7 @@ int set_km_env(void) sprintf((char *)buf, "0x%x", pnvramaddr); setenv("pnvramaddr", (char *)buf); - /* try to read rootfssize (ram image) from envrionment */ + /* try to read rootfssize (ram image) from environment */ p = getenv("rootfssize"); if (p != NULL) strict_strtoul(p, 16, &rootfssize); diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c index 34ac6979bd..77af184c82 100644 --- a/board/keymile/kmp204x/ddr.c +++ b/board/keymile/kmp204x/ddr.c @@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* we have only one module, half str should be OK */ popts->half_strength_driver_enable = 1; - /* wrlvl values overriden as recommended by ddr init func */ + /* wrlvl values overridden as recommended by ddr init func */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; popts->wrlvl_start = 0x6; diff --git a/board/kylin/kylin_rk3036/MAINTAINERS b/board/kylin/kylin_rk3036/MAINTAINERS deleted file mode 100644 index e69de29bb2..0000000000 --- a/board/kylin/kylin_rk3036/MAINTAINERS +++ /dev/null diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 982619cd7b..2821ee2267 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -19,6 +19,7 @@ #include <ns16550.h> #include <netdev.h> #include <twl4030.h> +#include <linux/mtd/omap_gpmc.h> #include <asm/io.h> #include <asm/arch/mem.h> #include <asm/arch/mmc_host_def.h> @@ -29,10 +30,10 @@ DECLARE_GLOBAL_DATA_PTR; -/* gpmc_cfg is initialized by gpmc_init and we use it here */ -extern struct gpmc *gpmc_cfg; - -/* GPMC definitions for Ethenet Controller LAN9211 */ +/* + * gpmc_cfg is initialized by gpmc_init and we use it here. + * GPMC definitions for Ethenet Controller LAN9211 + */ static const u32 gpmc_lab_enet[] = { ZOOM1_ENET_GPMC_CONF1, ZOOM1_ENET_GPMC_CONF2, diff --git a/board/micronas/vct/ebi_onenand.c b/board/micronas/vct/ebi_onenand.c index 62eb6489be..ef892cae15 100644 --- a/board/micronas/vct/ebi_onenand.c +++ b/board/micronas/vct/ebi_onenand.c @@ -169,7 +169,7 @@ static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area, return 0; } -void onenand_board_init(struct mtd_info *mtd) +int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *chip = mtd->priv; @@ -181,4 +181,6 @@ void onenand_board_init(struct mtd_info *mtd) chip->read_bufferram = ebi_read_bufferram; chip->write_bufferram = ebi_write_bufferram; + + return 0; } diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 0f587eaaa7..dbdc1b65e6 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -30,6 +30,28 @@ void pin_mux_mmc(void) ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); + + /* Disable LDO4 discharge */ + ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) { + printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret); + } else { + val &= ~BIT(1); /* ADE */ + ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret); + } + + /* Set MBLPD */ + ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) { + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } else { + val |= BIT(6); /* MBLPD */ + ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } } /* diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h index 92c3719112..39e550149a 100644 --- a/board/nvidia/p2571/max77620_init.h +++ b/board/nvidia/p2571/max77620_init.h @@ -13,6 +13,8 @@ #define MAX77620_I2C_ADDR 0x78 #define MAX77620_I2C_ADDR_7BIT 0x3C +#define MAX77620_CNFGGLBL1_REG 0x00 + #define MAX77620_SD0_REG 0x16 #define MAX77620_SD1_REG 0x17 #define MAX77620_SD2_REG 0x18 diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index c45ddb14aa..fbfbf6cbbc 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -234,12 +234,14 @@ static const struct rpi_model *model; #ifdef CONFIG_ARM64 static struct mm_region bcm2837_mem_map[] = { { - .base = 0x00000000UL, + .virt = 0x00000000UL, + .phys = 0x00000000UL, .size = 0x3f000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .base = 0x3f000000UL, + .virt = 0x3f000000UL, + .phys = 0x3f000000UL, .size = 0x01000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | diff --git a/board/evb_rk3036/evb_rk3036/Kconfig b/board/rockchip/evb_rk3036/Kconfig index ae2a9ebe47..ef45f62925 100644 --- a/board/evb_rk3036/evb_rk3036/Kconfig +++ b/board/rockchip/evb_rk3036/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "evb_rk3036" config SYS_VENDOR - default "evb_rk3036" + default "rockchip" config SYS_CONFIG_NAME default "evb_rk3036" diff --git a/board/rockchip/evb_rk3036/MAINTAINERS b/board/rockchip/evb_rk3036/MAINTAINERS new file mode 100644 index 0000000000..152d31ce50 --- /dev/null +++ b/board/rockchip/evb_rk3036/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RK3036 +M: huang lin <hl@rock-chips.com> +S: Maintained +F: board/evb/evb-rk3036 +F: include/configs/evb-rk3036.h +F: configs/evb-rk3036_defconfig diff --git a/board/evb_rk3036/evb_rk3036/Makefile b/board/rockchip/evb_rk3036/Makefile index 0403836e13..0403836e13 100644 --- a/board/evb_rk3036/evb_rk3036/Makefile +++ b/board/rockchip/evb_rk3036/Makefile diff --git a/board/evb_rk3036/evb_rk3036/evb_rk3036.c b/board/rockchip/evb_rk3036/evb_rk3036.c index f5758b1e9a..f5758b1e9a 100644 --- a/board/evb_rk3036/evb_rk3036/evb_rk3036.c +++ b/board/rockchip/evb_rk3036/evb_rk3036.c diff --git a/board/rockchip/evb_rk3399/Kconfig b/board/rockchip/evb_rk3399/Kconfig new file mode 100644 index 0000000000..412b81cbee --- /dev/null +++ b/board/rockchip/evb_rk3399/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3399 + +config SYS_BOARD + default "evb_rk3399" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rk3399" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/evb_rk3036/evb_rk3036/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index e69de29bb2..e69de29bb2 100644 --- a/board/evb_rk3036/evb_rk3036/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS diff --git a/board/rockchip/evb_rk3399/Makefile b/board/rockchip/evb_rk3399/Makefile new file mode 100644 index 0000000000..aaa51c212e --- /dev/null +++ b/board/rockchip/evb_rk3399/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb-rk3399.o diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README new file mode 100644 index 0000000000..fb8bb19763 --- /dev/null +++ b/board/rockchip/evb_rk3399/README @@ -0,0 +1,73 @@ +Introduction +============ + +RK3399 key features we might use in U-Boot: +* CPU: ARMv8 64bit Big-Little architecture, +* Big: dual-core Cortex-A72 +* Little: quad-core Cortex-A53 +* IRAM: 200KB +* DRAM: 4GB-128MB dual-channel +* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50 +* SD/MMC: support SD 3.0, MMC 4.51 +* USB: USB3.0 typc-C port *2 with dwc3 controller +* USB2.0 EHCI host port *2 +* Display: RGB/HDMI/DP/MIPI/EDP + +evb key features: +* regulator: pwm regulator for CPU B/L +* PMIC: rk808 +* debug console: UART2 + +In order to support Arm Trust Firmware(ATF), we need to use the +miniloader from rockchip which: +* do DRAM init +* load and verify ATF image +* load and verify U-Boot image + +Here is the step-by-step to boot to U-Boot on rk3399. + +Get the Source and prebuild binary +================================== + + > mkdir ~/evb_rk3399 + > cd ~/evb_rk3399 + > git clone https://github.com/ARM-software/arm-trusted-firmware.git + > git clone https://github.com/rockchip-linux/rkbin + > git clone https://github.com/rockchip-linux/rkflashtool + +Compile the ATF +=============== + + > cd arm-trusted-firmware + > make realclean + > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 + +Compile the U-Boot +================== + + > cd ../u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3399_defconfig all + +Compile the rkflashtool +======================= + + > cd ../rkflashtool + > make + +Package the image for miniloader +================================ + > cd .. + > cp arm-trusted-firmware/build/rk3399/release/bl31.bin rkbin/rk33 + > ./rkbin/tools/trust_merger rkbin/tools/RK3399TRUST.ini + > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img + > mkdir image + > mv trust.img ./image/ + > mv uboot.img ./image/rk3399evb-uboot.bin + +Flash the image +=============== +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + + > ./rkflashtool/rkflashloader rk3399evb + +You should be able to get U-Boot log message in console/UART2 now. diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c new file mode 100644 index 0000000000..dffacd0a84 --- /dev/null +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/armv8/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x80000000; + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = 0x80000000; +} diff --git a/board/kylin/kylin_rk3036/Kconfig b/board/rockchip/kylin_rk3036/Kconfig index 5d75c1fc0f..8d35b4e62b 100644 --- a/board/kylin/kylin_rk3036/Kconfig +++ b/board/rockchip/kylin_rk3036/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "kylin_rk3036" config SYS_VENDOR - default "kylin" + default "rockchip" config SYS_CONFIG_NAME default "kylin_rk3036" diff --git a/board/rockchip/kylin_rk3036/MAINTAINERS b/board/rockchip/kylin_rk3036/MAINTAINERS new file mode 100644 index 0000000000..f8ee834377 --- /dev/null +++ b/board/rockchip/kylin_rk3036/MAINTAINERS @@ -0,0 +1,6 @@ +KYLIN-RK3036 +M: huang lin <hl@rock-chips.com> +S: Maintained +F: board/kylin/kylin-rk3036 +F: include/configs/kylin-rk3036.h +F: configs/kylin-rk3036_defconfig diff --git a/board/kylin/kylin_rk3036/Makefile b/board/rockchip/kylin_rk3036/Makefile index 0663270506..0663270506 100644 --- a/board/kylin/kylin_rk3036/Makefile +++ b/board/rockchip/kylin_rk3036/Makefile diff --git a/board/kylin/kylin_rk3036/kylin_rk3036.c b/board/rockchip/kylin_rk3036/kylin_rk3036.c index 2a258710ac..2a258710ac 100644 --- a/board/kylin/kylin_rk3036/kylin_rk3036.c +++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c index b74d8e8ac9..cbe1d12fda 100644 --- a/board/samsung/goni/onenand.c +++ b/board/samsung/goni/onenand.c @@ -11,11 +11,13 @@ #include <linux/mtd/samsung_onenand.h> #include <onenand_uboot.h> -void onenand_board_init(struct mtd_info *mtd) +int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; this->base = (void *)CONFIG_SYS_ONENAND_BASE; this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; this->chip_probe = s5pc110_chip_probe; + + return 0; } diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c index 577c1a546f..994d91d999 100644 --- a/board/samsung/smdkc100/onenand.c +++ b/board/samsung/smdkc100/onenand.c @@ -16,7 +16,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> -void onenand_board_init(struct mtd_info *mtd) +int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; struct s5pc100_clock *clk = @@ -65,4 +65,6 @@ void onenand_board_init(struct mtd_info *mtd) writel(value, &onenand->int_err_mask); s3c_onenand_init(mtd); + + return 0; } diff --git a/board/samsung/universal_c210/onenand.c b/board/samsung/universal_c210/onenand.c index 28bc8114f4..147a95e290 100644 --- a/board/samsung/universal_c210/onenand.c +++ b/board/samsung/universal_c210/onenand.c @@ -10,11 +10,13 @@ #include <linux/mtd/onenand.h> #include <linux/mtd/samsung_onenand.h> -void onenand_board_init(struct mtd_info *mtd) +int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; this->base = (void *)CONFIG_SYS_ONENAND_BASE; this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; this->chip_probe = s5pc210_chip_probe; + + return 0; } diff --git a/board/sandbox/MAINTAINERS b/board/sandbox/MAINTAINERS index f5db773a47..4dcbf4ba03 100644 --- a/board/sandbox/MAINTAINERS +++ b/board/sandbox/MAINTAINERS @@ -11,3 +11,10 @@ S: Maintained F: board/sandbox/ F: include/configs/sandbox.h F: configs/sandbox_noblk_defconfig + +SANDBOX SPL BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/sandbox/ +F: include/configs/sandbox_spl.h +F: configs/sandbox_spl_defconfig diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox index 9fe3bf171a..ed820d338e 100644 --- a/board/sandbox/README.sandbox +++ b/board/sandbox/README.sandbox @@ -44,6 +44,9 @@ Note: make sandbox_defconfig all NO_SDL=1 ./u-boot + If you are building on a 32-bit machine you may get errors from __ffs.h + about shifting more than the machine word size. Edit the config file + include/configs/sandbox.h and change CONFIG_SANDBOX_BITS_PER_LONG to 32. U-Boot will start on your computer, showing a sandbox emulation of the serial console: diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 0e04d14148..404fdfa2a7 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -10,6 +10,8 @@ #include <asm/armv7m.h> #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> +#include <asm/arch/rcc.h> +#include <asm/arch/fmc.h> #include <dm/platdata.h> #include <dm/platform_data/serial_stm32x7.h> #include <asm/arch/stm32_periph.h> @@ -33,6 +35,221 @@ const struct stm32_gpio_ctl gpio_ctl_usart = { .af = STM32_GPIO_AF7 }; +const struct stm32_gpio_ctl gpio_ctl_fmc = { + .mode = STM32_GPIO_MODE_AF, + .otype = STM32_GPIO_OTYPE_PP, + .speed = STM32_GPIO_SPEED_100M, + .pupd = STM32_GPIO_PUPD_NO, + .af = STM32_GPIO_AF12 +}; + +static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { + /* Chip is LQFP144, see DM00077036.pdf for details */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ + + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ + + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ + + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ + + {STM32_GPIO_PORT_H, STM32_GPIO_PIN_3}, /* 136, SDRAM_NE */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ + {STM32_GPIO_PORT_H, STM32_GPIO_PIN_5}, /* 26, SDRAM_NWE */ + {STM32_GPIO_PORT_C, STM32_GPIO_PIN_3}, /* 135, SDRAM_CKE */ + + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ +}; + +static int fmc_setup_gpio(void) +{ + int rv = 0; + int i; + + clock_setup(GPIO_B_CLOCK_CFG); + clock_setup(GPIO_C_CLOCK_CFG); + clock_setup(GPIO_D_CLOCK_CFG); + clock_setup(GPIO_E_CLOCK_CFG); + clock_setup(GPIO_F_CLOCK_CFG); + clock_setup(GPIO_G_CLOCK_CFG); + clock_setup(GPIO_H_CLOCK_CFG); + + for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { + rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], + &gpio_ctl_fmc); + if (rv) + goto out; + } + +out: + return rv; +} + +/* + * STM32 RCC FMC specific definitions + */ +#define RCC_ENR_FMC (1 << 0) /* FMC module clock */ + +static inline u32 _ns2clk(u32 ns, u32 freq) +{ + u32 tmp = freq/1000000; + return (tmp * ns) / 1000; +} + +#define NS2CLK(ns) (_ns2clk(ns, freq)) + +/* + * Following are timings for IS42S16400J, from corresponding datasheet + */ +#define SDRAM_CAS 3 /* 3 cycles */ +#define SDRAM_NB 1 /* Number of banks */ +#define SDRAM_MWID 1 /* 16 bit memory */ + +#define SDRAM_NR 0x1 /* 12-bit row */ +#define SDRAM_NC 0x0 /* 8-bit col */ +#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ +#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ + +#define SDRAM_TRRD NS2CLK(12) +#define SDRAM_TRCD NS2CLK(18) +#define SDRAM_TRP NS2CLK(18) +#define SDRAM_TRAS NS2CLK(42) +#define SDRAM_TRC NS2CLK(60) +#define SDRAM_TRFC NS2CLK(60) +#define SDRAM_TCDL (1 - 1) +#define SDRAM_TRDL NS2CLK(12) +#define SDRAM_TBDL (1 - 1) +#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) +#define SDRAM_TCCD (1 - 1) + +#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */ +#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */ + + +/* Last data in to row precharge, need also comply ineq on page 1648 */ +#define SDRAM_TWR max(\ + (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \ + (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\ +) + + +#define SDRAM_MODE_BL_SHIFT 0 +#define SDRAM_MODE_CAS_SHIFT 4 +#define SDRAM_MODE_BL 0 +#define SDRAM_MODE_CAS SDRAM_CAS + +int dram_init(void) +{ + u32 freq; + int rv; + + rv = fmc_setup_gpio(); + if (rv) + return rv; + + setbits_le32(RCC_BASE + RCC_AHB3ENR, RCC_ENR_FMC); + + /* + * Get frequency for NS2CLK calculation. + */ + freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; + + writel( + CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT + | SDRAM_CAS << FMC_SDCR_CAS_SHIFT + | SDRAM_NB << FMC_SDCR_NB_SHIFT + | SDRAM_MWID << FMC_SDCR_MWID_SHIFT + | SDRAM_NR << FMC_SDCR_NR_SHIFT + | SDRAM_NC << FMC_SDCR_NC_SHIFT + | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT + | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, + &STM32_SDRAM_FMC->sdcr1); + + writel( + SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT + | SDRAM_TRP << FMC_SDTR_TRP_SHIFT + | SDRAM_TWR << FMC_SDTR_TWR_SHIFT + | SDRAM_TRC << FMC_SDTR_TRC_SHIFT + | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT + | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT + | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, + &STM32_SDRAM_FMC->sdtr1); + + writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, + &STM32_SDRAM_FMC->sdcmr); + + udelay(200); /* 200 us delay, page 10, "Power-Up" */ + FMC_BUSY_WAIT(); + + writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, + &STM32_SDRAM_FMC->sdcmr); + + udelay(100); + FMC_BUSY_WAIT(); + + writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH + | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); + + udelay(100); + FMC_BUSY_WAIT(); + + writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT + | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) + << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, + &STM32_SDRAM_FMC->sdcmr); + + udelay(100); + + FMC_BUSY_WAIT(); + + writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, + &STM32_SDRAM_FMC->sdcmr); + + FMC_BUSY_WAIT(); + + /* Refresh timer */ + writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); + + /* + * Fill in global info with description of SRAM configuration + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; + gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; + + gd->ram_size = CONFIG_SYS_RAM_SIZE; + + return rv; +} + static const struct stm32_gpio_dsc usart_gpio[] = { {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */ {STM32_GPIO_PORT_B, STM32_GPIO_PIN_7}, /* RX */ @@ -88,12 +305,3 @@ int board_init(void) return 0; } - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; - gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; - - gd->ram_size = CONFIG_SYS_RAM_SIZE; - return 0; -} diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index d2dfebef46..de719cd1f9 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -56,8 +56,10 @@ F: configs/ga10h_v1_1_defconfig F: configs/gt90h_v4_defconfig F: configs/inet86dz_defconfig F: configs/orangepi_2_defconfig +F: configs/orangepi_lite_defconfig F: configs/orangepi_one_defconfig F: configs/orangepi_pc_defconfig +F: configs/orangepi_pc_plus_defconfig F: configs/orangepi_plus_defconfig F: configs/polaroid_mid2407pxe03_defconfig F: configs/polaroid_mid2809pxe04_defconfig diff --git a/board/sunxi/board.c b/board/sunxi/board.c index c8bf3169d1..36cf96381c 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -20,12 +20,15 @@ #include <asm/arch/dram.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <asm/arch/spl.h> #include <asm/arch/usb_phy.h> #ifndef CONFIG_ARM64 #include <asm/armv7.h> #endif #include <asm/gpio.h> #include <asm/io.h> +#include <environment.h> +#include <libfdt.h> #include <nand.h> #include <net.h> #include <sy8106a.h> @@ -133,7 +136,7 @@ int dram_init(void) return 0; } -#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_NAND_SUNXI) static void nand_pinmux_setup(void) { unsigned int pin; @@ -170,6 +173,9 @@ void board_nand_init(void) { nand_pinmux_setup(); nand_clock_setup(); +#ifndef CONFIG_SPL_BUILD + sunxi_nand_init(); +#endif } #endif @@ -366,8 +372,7 @@ int board_mmc_init(bd_t *bis) * are searched there first. Note we only do this for u-boot proper, * not for the SPL, see spl_boot_device(). */ - if (!sunxi_mmc_has_egon_boot_signature(mmc0) && - sunxi_mmc_has_egon_boot_signature(mmc1)) { + if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) { /* Booting from emmc / mmc2, swap */ mmc0->block_dev.devnum = 1; mmc1->block_dev.devnum = 0; @@ -571,9 +576,6 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif -#if !defined(CONFIG_SPL_BUILD) -#include <asm/arch/spl.h> - /* * Check the SPL header for the "sunxi" variant. If found: parse values * that might have been passed by the loader ("fel" utility), and update @@ -582,50 +584,67 @@ void get_board_serial(struct tag_serialnr *serialnr) static void parse_spl_header(const uint32_t spl_addr) { struct boot_file_head *spl = (void *)(ulong)spl_addr; - if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) { - uint8_t spl_header_version = spl->spl_signature[3]; - if (spl_header_version == SPL_HEADER_VERSION) { - if (spl->fel_script_address) - setenv_hex("fel_scriptaddr", - spl->fel_script_address); - return; - } + if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0) + return; /* signature mismatch, no usable header */ + + uint8_t spl_header_version = spl->spl_signature[3]; + if (spl_header_version != SPL_HEADER_VERSION) { printf("sunxi SPL version mismatch: expected %u, got %u\n", SPL_HEADER_VERSION, spl_header_version); + return; } + if (!spl->fel_script_address) + return; + + if (spl->fel_uEnv_length != 0) { + /* + * data is expected in uEnv.txt compatible format, so "env + * import -t" the string(s) at fel_script_address right away. + */ + himport_r(&env_htab, (char *)spl->fel_script_address, + spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL); + return; + } + /* otherwise assume .scr format (mkimage-type script) */ + setenv_hex("fel_scriptaddr", spl->fel_script_address); } -#endif -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) +/* + * Note this function gets called multiple times. + * It must not make any changes to env variables which already exist. + */ +static void setup_environment(const void *fdt) { char serial_string[17] = { 0 }; unsigned int sid[4]; uint8_t mac_addr[6]; - int ret; - -#if !defined(CONFIG_SPL_BUILD) - setenv("fel_booted", NULL); - setenv("fel_scriptaddr", NULL); - /* determine if we are running in FEL mode */ - if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ - setenv("fel_booted", "1"); - parse_spl_header(SPL_ADDR); - } -#endif + char ethaddr[16]; + int i, ret; ret = sunxi_get_sid(sid); if (ret == 0 && sid[0] != 0 && sid[3] != 0) { - if (!getenv("ethaddr")) { + for (i = 0; i < 4; i++) { + sprintf(ethaddr, "ethernet%d", i); + if (!fdt_get_alias(fdt, ethaddr)) + continue; + + if (i == 0) + strcpy(ethaddr, "ethaddr"); + else + sprintf(ethaddr, "eth%daddr", i); + + if (getenv(ethaddr)) + continue; + /* Non OUI / registered MAC address */ - mac_addr[0] = 0x02; + mac_addr[0] = (i << 4) | 0x02; mac_addr[1] = (sid[0] >> 0) & 0xff; mac_addr[2] = (sid[3] >> 24) & 0xff; mac_addr[3] = (sid[3] >> 16) & 0xff; mac_addr[4] = (sid[3] >> 8) & 0xff; mac_addr[5] = (sid[3] >> 0) & 0xff; - eth_setenv_enetaddr("ethaddr", mac_addr); + eth_setenv_enetaddr(ethaddr, mac_addr); } if (!getenv("serial#")) { @@ -635,6 +654,21 @@ int misc_init_r(void) setenv("serial#", serial_string); } } +} + +int misc_init_r(void) +{ + __maybe_unused int ret; + + setenv("fel_booted", NULL); + setenv("fel_scriptaddr", NULL); + /* determine if we are running in FEL mode */ + if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ + setenv("fel_booted", "1"); + parse_spl_header(SPL_ADDR); + } + + setup_environment(gd->fdt_blob); #ifndef CONFIG_MACH_SUN9I ret = sunxi_usb_phy_probe(); @@ -645,12 +679,17 @@ int misc_init_r(void) return 0; } -#endif int ft_board_setup(void *blob, bd_t *bd) { int __maybe_unused r; + /* + * Call setup_environment again in case the boot fdt has + * ethernet aliases the u-boot copy does not have. + */ + setup_environment(blob); + #ifdef CONFIG_VIDEO_DT_SIMPLEFB r = sunxi_simplefb_setup(blob); if (r) diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index f005762eda..27c311ee9d 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -13,6 +13,7 @@ #include <asm/errno.h> #include <spl.h> #include <usb.h> +#include <asm/omap_sec_common.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mux.h> @@ -862,3 +863,10 @@ int board_fit_config_name_match(const char *name) return -1; } #endif + +#ifdef CONFIG_TI_SECURE_DEVICE +void board_fit_image_post_process(void **p_image, size_t *p_size) +{ + secure_boot_verify_image(p_image, p_size); +} +#endif diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 08cf14d5e7..927d1364fe 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -13,6 +13,7 @@ #include <sata.h> #include <usb.h> #include <asm/omap_common.h> +#include <asm/omap_sec_common.h> #include <asm/emif.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> @@ -750,3 +751,10 @@ int board_fit_config_name_match(const char *name) return -1; } #endif + +#ifdef CONFIG_TI_SECURE_DEVICE +void board_fit_image_post_process(void **p_image, size_t *p_size) +{ + secure_boot_verify_image(p_image, p_size); +} +#endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 6a4d02769e..99e82542f7 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -17,6 +17,8 @@ #include <asm/gpio.h> #include <usb.h> #include <linux/usb/gadget.h> +#include <asm/omap_common.h> +#include <asm/omap_sec_common.h> #include <asm/arch/gpio.h> #include <asm/arch/dra7xx_iodelay.h> #include <asm/emif.h> @@ -834,3 +836,10 @@ int board_fit_config_name_match(const char *name) return -1; } #endif + +#ifdef CONFIG_TI_SECURE_DEVICE +void board_fit_image_post_process(void **p_image, size_t *p_size) +{ + secure_boot_verify_image(p_image, p_size); +} +#endif |