diff options
Diffstat (limited to 'board')
56 files changed, 403 insertions, 480 deletions
diff --git a/board/avnet/fx12mm/Kconfig b/board/avnet/fx12mm/Kconfig deleted file mode 100644 index 0b67ebde93..0000000000 --- a/board/avnet/fx12mm/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_FX12MM - -config SYS_BOARD - default "fx12mm" - -config SYS_VENDOR - default "avnet" - -config SYS_CONFIG_NAME - default "fx12mm" - -endif diff --git a/board/avnet/fx12mm/MAINTAINERS b/board/avnet/fx12mm/MAINTAINERS deleted file mode 100644 index c92e258df9..0000000000 --- a/board/avnet/fx12mm/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -FX12MM BOARD -M: Georg Schardt <schardt@team-ctech.de> -S: Maintained -F: board/avnet/fx12mm/ -F: include/configs/fx12mm.h -F: configs/fx12mm_defconfig -F: configs/fx12mm_flash_defconfig diff --git a/board/avnet/fx12mm/Makefile b/board/avnet/fx12mm/Makefile deleted file mode 100644 index 618b42f891..0000000000 --- a/board/avnet/fx12mm/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2008 -# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es -# This work has been supported by: Qtechnology http://qtec.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += fx12mm.o - -include $(srctree)/board/xilinx/ppc405-generic/Makefile diff --git a/board/avnet/fx12mm/fx12mm.c b/board/avnet/fx12mm/fx12mm.c deleted file mode 100644 index 92e1cfb75f..0000000000 --- a/board/avnet/fx12mm/fx12mm.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2008 - * - * Author: Xilinx Inc. - * - * Modified by: - * Georg Schardt <schardt@team-ctech.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <common.h> -#include <asm/processor.h> - -int checkboard(void) -{ - char buf[64]; - int i; - int l = getenv_f("serial#", buf, sizeof(buf)); - - if (l < 0) { - printf("Avnet Virtex4 FX12 with no serial #"); - } else { - printf("Avnet Virtex4 FX12 Minimodul # "); - for (i = 0; i < l; ++i) { - if (buf[i] == ' ') - break; - putc(buf[i]); - } - } - putc('\n'); - return 0; -} diff --git a/board/avnet/fx12mm/xparameters.h b/board/avnet/fx12mm/xparameters.h deleted file mode 100644 index 94f682f8ec..0000000000 --- a/board/avnet/fx12mm/xparameters.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2008 - * - * Georg Schardt <schardt@team-ctech.de> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * CAUTION: This file is based on the xparameters.h automatically - * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5 - */ - -#ifndef __XPARAMETER_H__ -#define __XPARAMETER_H__ - -/* RS232 */ -#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 -#define XPAR_UARTNS550_0_BASEADDR 0x83E00000 - - -/* INT_C */ -#define XPAR_XPS_INTC_0_DEVICE_ID 0 -#define XPAR_XPS_INTC_0_BASEADDR 0x81800000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2 - -/* CPU core clock */ -#define XPAR_CORE_CLOCK_FREQ_HZ 300000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 - -/* RAM */ -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 - -/* FLASH */ -#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000 - -#endif diff --git a/board/avnet/v5fx30teval/Kconfig b/board/avnet/v5fx30teval/Kconfig deleted file mode 100644 index 079387b707..0000000000 --- a/board/avnet/v5fx30teval/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_V5FX30TEVAL - -config SYS_BOARD - default "v5fx30teval" - -config SYS_VENDOR - default "avnet" - -config SYS_CONFIG_NAME - default "v5fx30teval" - -endif diff --git a/board/avnet/v5fx30teval/MAINTAINERS b/board/avnet/v5fx30teval/MAINTAINERS deleted file mode 100644 index 91dde7a5c8..0000000000 --- a/board/avnet/v5fx30teval/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -V5FX30TEVAL BOARD -M: Ricardo Ribalda <ricardo.ribalda@uam.es> -S: Maintained -F: board/avnet/v5fx30teval/ -F: include/configs/v5fx30teval.h -F: configs/v5fx30teval_defconfig -F: configs/v5fx30teval_flash_defconfig diff --git a/board/avnet/v5fx30teval/Makefile b/board/avnet/v5fx30teval/Makefile deleted file mode 100644 index 8c41af02d4..0000000000 --- a/board/avnet/v5fx30teval/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2008 -# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es -# This work has been supported by: Qtechnology http://qtec.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += v5fx30teval.o - -include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/avnet/v5fx30teval/v5fx30teval.c b/board/avnet/v5fx30teval/v5fx30teval.c deleted file mode 100644 index 68b0eb959d..0000000000 --- a/board/avnet/v5fx30teval/v5fx30teval.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <config.h> -#include <common.h> -#include <asm/processor.h> - - -int checkboard(void) -{ - puts("Avnet Virtex 5 FX30 Evaluation Board\n"); - return 0; -} diff --git a/board/avnet/v5fx30teval/xparameters.h b/board/avnet/v5fx30teval/xparameters.h deleted file mode 100644 index 95b8c285ad..0000000000 --- a/board/avnet/v5fx30teval/xparameters.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * based on xparameters.h by Xilinx - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef XPARAMETER_H -#define XPARAMETER_H - -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 - -#endif diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index 6a8fca61a0..e582abbaef 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -16,7 +16,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include <hwconfig.h> @@ -1023,10 +1022,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif /* * Adjust core voltage according to voltage ID * This function changes I2C mux to channel 2. diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index f1bed51d30..1bd65a8e55 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -42,7 +42,7 @@ int __weak board_vdd_drop_compensation(void) * The IR chip can show up under the following addresses: * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA) * 0x09 (Verified on T1040RDB-PA) - * 0x38 (Verified on T2080QDS, T2081QDS) + * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB) */ static int find_ir_chip_on_i2c(void) { @@ -292,7 +292,7 @@ int adjust_vdd(ulong vdd_override) (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif u32 fusesr; - u8 vid; + u8 vid, buf; int vdd_target, vdd_current, vdd_last; int ret, i2caddress; unsigned long vdd_string_override; @@ -346,6 +346,21 @@ int adjust_vdd(ulong vdd_override) debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); } + /* check IR chip work on Intel mode*/ + ret = i2c_read(i2caddress, + IR36021_INTEL_MODE_OOFSET, + 1, (void *)&buf, 1); + if (ret) { + printf("VID: failed to read IR chip mode.\n"); + ret = -1; + goto exit; + } + if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { + printf("VID: IR Chip is not used in Intel mode.\n"); + ret = -1; + goto exit; + } + /* get the voltage ID from fuse status register */ fusesr = in_be32(&gur->dcfg_fusesr); /* diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h index a9c7bb4790..9182c20bc9 100644 --- a/board/freescale/common/vid.h +++ b/board/freescale/common/vid.h @@ -11,6 +11,10 @@ #define IR36021_LOOP1_VOUT_OFFSET 0x9A #define IR36021_MFR_ID_OFFSET 0x92 #define IR36021_MFR_ID 0x43 +#define IR36021_INTEL_MODE_OOFSET 0x14 +#define IR36021_MODE_MASK 0x20 +#define IR36021_INTEL_MODE 0x00 +#define IR36021_AMD_MODE 0x20 /* step the IR regulator in 5mV increments */ #define IR_VDD_STEP_DOWN 5 diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 6f0fea1a35..f41985d2f6 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -125,11 +124,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - return 0; } diff --git a/board/freescale/mx25pdk/Makefile b/board/freescale/mx25pdk/Makefile index 0b288f2588..02085b6b7e 100644 --- a/board/freescale/mx25pdk/Makefile +++ b/board/freescale/mx25pdk/Makefile @@ -7,4 +7,3 @@ # obj-y := mx25pdk.o -obj-y += lowlevel_init.o diff --git a/board/freescale/mx25pdk/lowlevel_init.S b/board/freescale/mx25pdk/lowlevel_init.S deleted file mode 100644 index 8c581b50c6..0000000000 --- a/board/freescale/mx25pdk/lowlevel_init.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2011 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.globl lowlevel_init -lowlevel_init: - - mov pc, lr diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c index 01dac72e85..788d3c3e35 100644 --- a/board/freescale/mx25pdk/mx25pdk.c +++ b/board/freescale/mx25pdk/mx25pdk.c @@ -186,3 +186,6 @@ int checkboard(void) return 0; } + +/* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */ +void lowlevel_init(void) {} diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index f8ae9733fc..bbcc5bb0c6 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -47,6 +47,9 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_PAD_CTRL \ (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1 for PMIC */ @@ -196,6 +199,38 @@ static void iox74lv_init(void) gpio_direction_output(IOX_STCP, 1); }; +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + /* NAND_USDHC_BUS_CLK is set in rom */ + set_clk_nand(); +} +#endif + #ifdef CONFIG_VIDEO_MXS static iomux_v3_cfg_t const lcd_pads[] = { MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), @@ -503,6 +538,10 @@ int board_init(void) setup_fec(); #endif +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + #ifdef CONFIG_VIDEO_MXS setup_lcd(); #endif diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index e600bdbc2a..c6a724217f 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -140,8 +139,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); - setup_portals(); board_config_lanes_mux(); return 0; diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c index 708afcaebf..76793a1186 100644 --- a/board/freescale/t102xqds/t102xqds.c +++ b/board/freescale/t102xqds/t102xqds.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include <hwconfig.h> @@ -280,10 +279,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); board_mux_lane_to_slot(); board_retimer_ds125df111_init(); diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index fddd240f98..01dbf381bd 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "t102xrdb.h" @@ -151,10 +150,6 @@ int board_early_init_r(void) 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif #ifdef CONFIG_T1024RDB board_mux_lane(); #endif diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index eaca57fc5d..d7d56b47c8 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include <hwconfig.h> @@ -153,10 +152,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); return 0; diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 322765288b..ec97677df8 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -16,7 +16,6 @@ #include <asm/fsl_fdt.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "../common/sleep.h" @@ -84,11 +83,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - return 0; } diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 7c89cd5ee9..bfea3a1556 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -356,11 +355,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - /* Disable remote I2C connection to qixis fpga */ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 0c2c1c565b..0cb05aa03f 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -14,7 +14,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "t208xrdb.h" @@ -81,11 +80,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - /* * Adjust core voltage according to voltage ID * This function changes I2C mux to channel 2. diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c index 54410943f2..f1393f25f9 100644 --- a/board/freescale/t4qds/t4240emu.c +++ b/board/freescale/t4qds/t4240emu.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,11 +55,6 @@ int board_early_init_r(void) MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - return 0; } diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index 4f2cccd709..d6df144730 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -15,7 +15,6 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> @@ -552,11 +551,6 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif - /* Disable remote I2C connection to qixis fpga */ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index fac442bfc8..406fb132ae 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -15,12 +15,12 @@ #include <asm/immap_85xx.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> #include "t4rdb.h" #include "cpld.h" +#include "../common/vid.h" DECLARE_GLOBAL_DATA_PTR; @@ -75,10 +75,12 @@ int board_early_init_r(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); - set_liodns(); -#ifdef CONFIG_SYS_DPAA_QBMAN - setup_portals(); -#endif + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); return 0; } diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 1b97a8fea8..d12d74202c 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -14,14 +14,6 @@ int arch_early_init_r(void) { - struct udevice *dev; - int ret; - - /* Make sure the platform controller hub is up and running */ - ret = uclass_get_device(UCLASS_PCH, 0, &dev); - if (ret) - return ret; - return 0; } diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c index 9f6494561c..52a1906c7f 100644 --- a/board/renesas/sh7753evb/sh7753evb.c +++ b/board/renesas/sh7753evb/sh7753evb.c @@ -113,6 +113,7 @@ static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) writel(val, ðer->malr); } +#if defined(CONFIG_SH_32BIT) /***************************************************************** * This PMB must be set on this timing. The lowlevel_init is run on * Area 0(phys 0x00000000), so we have to map it. @@ -154,13 +155,16 @@ static void set_pmb_on_board_init(void) writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); } +#endif int board_init(void) { struct gether_control_regs *gether = GETHER_CONTROL_BASE; init_gpio(); +#if defined(CONFIG_SH_32BIT) set_pmb_on_board_init(); +#endif /* Sets TXnDLY to B'010 */ writel(0x00000202, &gether->gbecont); diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 7c69be918f..a334aa336d 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -71,8 +71,11 @@ config MACH_SUN8I_A33 config MACH_SUN8I_H3 bool "sun8i (Allwinner H3)" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUNXI_GEN_SUN6I select SUPPORT_SPL + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" @@ -92,6 +95,12 @@ config MACH_SUN8I bool default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T +config DRAM_TYPE + int "sunxi dram type" + depends on MACH_SUN8I_A83T + default 3 + ---help--- + Set the dram type, 3: DDR3, 7: LPDDR3 config DRAM_CLK int "sunxi dram clock speed" diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 131c3415aa..739b6fdc88 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -183,6 +183,11 @@ S: Maintained F: configs/Sinlinx_SinA33_defconfig W: http://linux-sunxi.org/Sinlinx_SinA33 +SINOVOIP BPI M3 A83T BOARD +M: VishnuPatekar <vishnupatekar0510@gmail.com> +S: Maintained +F: configs/Sinovoip_BPI_M3_defconfig + WEXLER-TAB7200 BOARD M: Aleksei Mamlin <mamlinav@gmail.com> S: Maintained diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 1cc39e4d18..420481a9fb 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -452,24 +452,22 @@ void sunxi_board_init(void) power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); #endif -#ifdef CONFIG_AXP221_POWER +#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); #endif -#ifndef CONFIG_AXP818_POWER power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); -#endif -#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP818_POWER) +#if !defined(CONFIG_AXP152_POWER) power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); #endif #ifdef CONFIG_AXP209_POWER power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); #endif -#ifdef CONFIG_AXP221_POWER - power_failed |= axp_set_dldo1(CONFIG_AXP_DLDO1_VOLT); - power_failed |= axp_set_dldo2(CONFIG_AXP_DLDO2_VOLT); - power_failed |= axp_set_dldo3(CONFIG_AXP_DLDO3_VOLT); - power_failed |= axp_set_dldo4(CONFIG_AXP_DLDO4_VOLT); +#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER) + power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); + power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); + power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); + power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); diff --git a/board/theadorable/MAINTAINERS b/board/theadorable/MAINTAINERS new file mode 100644 index 0000000000..5ae6b6487c --- /dev/null +++ b/board/theadorable/MAINTAINERS @@ -0,0 +1,7 @@ +THEADORABLE BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/theadorable/ +F: include/configs/theadorable.h +F: configs/theadorable_debug_defconfig +F: configs/theadorable_defconfig diff --git a/board/theadorable/Makefile b/board/theadorable/Makefile new file mode 100644 index 0000000000..9d5b39e696 --- /dev/null +++ b/board/theadorable/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := theadorable.o diff --git a/board/theadorable/kwbimage.cfg b/board/theadorable/kwbimage.cfg new file mode 100644 index 0000000000..4f3b7b23f3 --- /dev/null +++ b/board/theadorable/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c new file mode 100644 index 0000000000..0e232656fc --- /dev/null +++ b/board/theadorable/theadorable.c @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#ifdef CONFIG_NET +#include <netdev.h> +#endif + +#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" +#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780 +#define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0 +#define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0)) + +#define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f +#define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c +#define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000 + +/* DDR3 static configuration */ +static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = { + {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */ + {0x00001404, 0x30000800}, /* Dunit Control Low Register */ + {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */ + {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */ + {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */ + {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */ + {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */ + {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */ + {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */ + + {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */ + {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */ + {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */ + {0x000014A8, 0x00000101}, /* AXI Control Register */ + + /* + * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the + * training sequence + */ + {0x000200e8, 0x3fff0e01}, + {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */ + + {0x0001504, 0x7fffffe1}, /* CS0 Size */ + {0x000150C, 0x00000000}, /* CS1 Size */ + {0x0001514, 0x00000000}, /* CS2 Size */ + {0x000151C, 0x00000000}, /* CS3 Size */ + + {0x00020220, 0x00000007}, /* Reserved */ + + {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */ + {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */ + + {0x000015D0, 0x00000650}, /* MR0 */ + {0x000015D4, 0x00000044}, /* MR1 */ + {0x000015D8, 0x00000010}, /* MR2 */ + {0x000015DC, 0x00000000}, /* MR3 */ + {0x000015E0, 0x00000001}, + {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */ + {0x000015EC, 0xf800a225}, /* DDR PHY */ + + /* Recommended Settings from Marvell for 4 x 16 bit devices: */ + {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/ + {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */ + + {0x0, 0x0} +}; + +static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = { + {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL}, +}; + +extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; + +/* + * Lane0 - PCIE0.0 X1 (to WIFI Module) + * Lane5 - SATA0 + * Lane6 - SATA1 + * Lane7 - SGMII0 (to Ethernet Phy) + * Lane8-11 - PCIE2.0 X4 (to PEX Switch) + * all other lanes are disabled + */ +MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = { + { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111, + { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, + PEX_BUS_DISABLED }, + 0x0060, serdes_change_m_phy + }, +}; + +MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) +{ + /* Only one mode supported for this board */ + return &board_ddr_modes[0]; +} + +MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +{ + return &theadorable_serdes_cfg[0]; +} + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00000000, MVEBU_MPP_BASE + 0x00); + writel(0x03300000, MVEBU_MPP_BASE + 0x04); + writel(0x00000033, MVEBU_MPP_BASE + 0x08); + writel(0x00000000, MVEBU_MPP_BASE + 0x0c); + writel(0x11110000, MVEBU_MPP_BASE + 0x10); + writel(0x00221100, MVEBU_MPP_BASE + 0x14); + writel(0x00000000, MVEBU_MPP_BASE + 0x18); + writel(0x00000000, MVEBU_MPP_BASE + 0x1c); + writel(0x00000000, MVEBU_MPP_BASE + 0x20); + + /* Configure GPIO */ + writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); + writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: theadorable\n"); + + return 0; +} + +#ifdef CONFIG_NET +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in controller(s) come first */ + return pci_eth_init(bis); +} +#endif + +int board_video_init(void) +{ + struct mvebu_lcd_info lcd_info; + + /* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */ + lcd_info.fb_base = gd->ram_size; + lcd_info.x_res = 240; + lcd_info.x_fp = 1; + lcd_info.x_bp = 45; + lcd_info.y_res = 320; + lcd_info.y_fp = 1; + lcd_info.y_bp = 3; + + return mvebu_lcd_register_init(&lcd_info); +} diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index d891a3844c..eca218c9cf 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -43,7 +43,7 @@ ulong flash_get_size (ulong base, int banknum); /* Local functions */ static int detect_num_flash_banks(void); static long int get_ddr_bank_size(short cs, long *base); -static void set_cs_bounds(short cs, long base, long size); +static void set_cs_bounds(short cs, ulong base, ulong size); static void set_cs_config(short cs, long config); static void set_ddr_config(void); @@ -314,7 +314,7 @@ static long int get_ddr_bank_size(short cs, long *base) /************************************************************************** * Sets DDR bank CS bounds. */ -static void set_cs_bounds(short cs, long base, long size) +static void set_cs_bounds(short cs, ulong base, ulong size) { debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs); if(size == 0){ diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index dfa6293222..ccd4ec955b 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -12,7 +12,6 @@ #include <common.h> #include <config.h> #include <fdtdec.h> -#include <netdev.h> #include <asm/processor.h> #include <asm/microblaze_intc.h> #include <asm/asm.h> @@ -24,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; static int reset_pin = -1; #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) ulong ram_base; void dram_init_banksize(void) @@ -58,14 +56,6 @@ int dram_init(void) return 0; }; -#else -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - - return 0; -} -#endif int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -86,7 +76,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -int gpio_init (void) +static int gpio_init(void) { #ifdef CONFIG_XILINX_GPIO reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1); @@ -96,32 +86,9 @@ int gpio_init (void) return 0; } -void board_init(void) +int board_late_init(void) { gpio_init(); -} -int board_eth_init(bd_t *bis) -{ - int ret = 0; - -#ifdef CONFIG_XILINX_AXIEMAC - ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, - XILINX_AXIDMA_BASEADDR); -#endif - -#if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR) - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); -#endif - - return ret; + return 0; } diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index 8ba146cb88..ccb528ed92 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -28,15 +28,6 @@ #define XILINX_TIMER_BASEADDR 0x41c00000 #define XILINX_TIMER_IRQ 0 -/* Uart pheriphery is RS232_Uart */ -#define XILINX_UARTLITE_BASEADDR 0x40600000 -#define XILINX_UARTLITE_BAUDRATE 115200 - -/* IIC pheriphery is IIC_EEPROM */ -#define XILINX_IIC_0_BASEADDR 0x40800000 -#define XILINX_IIC_0_FREQ 100000 -#define XILINX_IIC_0_BIT 0 - /* GPIO is LEDs_4Bit*/ #define XILINX_GPIO_BASEADDR 0x40000000 @@ -44,18 +35,6 @@ #define XILINX_FLASH_START 0x2c000000 #define XILINX_FLASH_SIZE 0x00800000 -/* Main Memory is DDR_SDRAM_64Mx32 */ -#define XILINX_RAM_START 0x28000000 -#define XILINX_RAM_SIZE 0x04000000 - -/* Sysace Controller is SysACE_CompactFlash */ -#define XILINX_SYSACE_BASEADDR 0x41800000 -#define XILINX_SYSACE_HIGHADDR 0x4180ffff -#define XILINX_SYSACE_MEM_WIDTH 16 - -/* Ethernet controller is Ethernet_MAC */ -#define XILINX_EMACLITE_BASEADDR 0x40C00000 - /* Watchdog IP is wxi_timebase_wdt_0 */ #define XILINX_WATCHDOG_BASEADDR 0x50000000 #define XILINX_WATCHDOG_IRQ 1 diff --git a/board/xilinx/ml507/Kconfig b/board/xilinx/ml507/Kconfig deleted file mode 100644 index d580a7beaf..0000000000 --- a/board/xilinx/ml507/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ML507 - -config SYS_BOARD - default "ml507" - -config SYS_VENDOR - default "xilinx" - -config SYS_CONFIG_NAME - default "ml507" - -endif diff --git a/board/xilinx/ml507/MAINTAINERS b/board/xilinx/ml507/MAINTAINERS deleted file mode 100644 index 8b40f44500..0000000000 --- a/board/xilinx/ml507/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -ML507 BOARD -M: Ricardo Ribalda <ricardo.ribalda@uam.es> -S: Maintained -F: board/xilinx/ml507/ -F: include/configs/ml507.h -F: configs/ml507_defconfig -F: configs/ml507_flash_defconfig diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile deleted file mode 100644 index 9a3809f3c0..0000000000 --- a/board/xilinx/ml507/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2008 -# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es -# This work has been supported by: Qtechnology http://qtec.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += ml507.o - -include $(srctree)/board/xilinx/ppc440-generic/Makefile diff --git a/board/xilinx/ml507/ml507.c b/board/xilinx/ml507/ml507.c deleted file mode 100644 index 83b764b733..0000000000 --- a/board/xilinx/ml507/ml507.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <config.h> -#include <common.h> -#include <asm/processor.h> - - -int checkboard(void) -{ - puts("Xilinx ML507 Board\n"); - return 0; -} diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h deleted file mode 100644 index e30e592bbe..0000000000 --- a/board/xilinx/ml507/xparameters.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * based on xparameters-ml507.h by Xilinx - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef XPARAMETER_H -#define XPARAMETER_H - -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 -#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 - -#endif diff --git a/board/xilinx/ppc405-generic/MAINTAINERS b/board/xilinx/ppc405-generic/MAINTAINERS index 2b0c98dc8b..ba48f50c29 100644 --- a/board/xilinx/ppc405-generic/MAINTAINERS +++ b/board/xilinx/ppc405-generic/MAINTAINERS @@ -1,5 +1,5 @@ PPC405-GENERIC BOARD -M: Ricardo Ribalda <ricardo.ribalda@uam.es> +M: Ricardo Ribalda <ricardo.ribalda@gmail.com> S: Maintained F: board/xilinx/ppc405-generic/ F: include/configs/xilinx-ppc405-generic.h diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile index c9da870657..2800f68626 100644 --- a/board/xilinx/ppc405-generic/Makefile +++ b/board/xilinx/ppc405-generic/Makefile @@ -3,10 +3,10 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com # Work supported by Qtechnology http://www.qtec.com # # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o +obj-y += xilinx_ppc405_generic.o diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c index e3dd468f1e..3729f07624 100644 --- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c +++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * SPDX-License-Identifier: GPL-2.0+ @@ -10,39 +10,32 @@ #include <common.h> #include <asm/processor.h> -ulong __get_PCI_freq(void) +ulong get_PCI_freq(void) { return 0; } -ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq"))); - -int __board_pre_init(void) -{ - return 0; -} -int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); - -int __checkboard(void) +int checkboard(void) { puts("Xilinx PPC405 Generic Board\n"); return 0; } -int checkboard(void) __attribute__((weak, alias("__checkboard"))); -phys_size_t __initdram(int board_type) +phys_size_t initdram(int board_type) { return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); } -phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); -void __get_sys_info(sys_info_t *sysInfo) +void get_sys_info(sys_info_t *sys_info) { - sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; - sysInfo->freqPCI = 0; + sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sys_info->freqPCI = 0; return; } -void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); + +int get_serial_clock(void){ + return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; +} diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h index f0ff78fca5..c3df9e5109 100644 --- a/board/xilinx/ppc405-generic/xparameters.h +++ b/board/xilinx/ppc405-generic/xparameters.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * based on xparameters-ml507.h by Xilinx * @@ -14,12 +14,11 @@ #define XPAR_IIC_EEPROM_BASEADDR 0x81600000 #define XPAR_INTC_0_BASEADDR 0x81800000 #define XPAR_SPI_0_BASEADDR 0x83400000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 #define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 #define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 #define XPAR_SPI_0_NUM_TRANSFER_BITS 8 +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 #endif diff --git a/board/xilinx/ppc440-generic/MAINTAINERS b/board/xilinx/ppc440-generic/MAINTAINERS index 2d0b11af91..0258c8204a 100644 --- a/board/xilinx/ppc440-generic/MAINTAINERS +++ b/board/xilinx/ppc440-generic/MAINTAINERS @@ -1,5 +1,5 @@ PPC440-GENERIC BOARD -M: Ricardo Ribalda <ricardo.ribalda@uam.es> +M: Ricardo Ribalda <ricardo.ribalda@gmail.com> S: Maintained F: board/xilinx/ppc440-generic/ F: include/configs/xilinx-ppc440-generic.h diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile index 0acd95d6e4..4d5f41029a 100644 --- a/board/xilinx/ppc440-generic/Makefile +++ b/board/xilinx/ppc440-generic/Makefile @@ -3,11 +3,11 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com # Work supported by Qtechnology http://www.qtec.com # # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o -extra-y += ../../xilinx/ppc440-generic/init.o +obj-y += xilinx_ppc440_generic.o +extra-y += init.o diff --git a/board/xilinx/ppc440-generic/init.S b/board/xilinx/ppc440-generic/init.S index 4598a37684..f9ff35f51b 100644 --- a/board/xilinx/ppc440-generic/init.S +++ b/board/xilinx/ppc440-generic/init.S @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * SPDX-License-Identifier: GPL-2.0+ diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c index 74df2f4ff7..d823352930 100644 --- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c +++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * * SPDX-License-Identifier: GPL-2.0+ @@ -8,34 +8,51 @@ #include <config.h> #include <common.h> +#include <netdev.h> #include <asm/processor.h> -int __board_pre_init(void) -{ - return 0; -} -int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); - -int __checkboard(void) +int checkboard(void) { puts("Xilinx PPC440 Generic Board\n"); return 0; } -int checkboard(void) __attribute__((weak, alias("__checkboard"))); -phys_size_t __initdram(int board_type) +phys_size_t initdram(int board_type) { return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); } -phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); -void __get_sys_info(sys_info_t *sysInfo) +void get_sys_info(sys_info_t *sys_info) { - sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; - sysInfo->freqPCI = 0; + sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sys_info->freqPCI = 0; return; } -void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); + +int get_serial_clock(void){ + return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + + puts("Init xilinx temac\n"); +#ifdef XPAR_LLTEMAC_0_BASEADDR + ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB, + XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR); + +#endif + +#ifdef XPAR_LLTEMAC_1_BASEADDR + ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR, + XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB, + XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR); +#endif + + return ret; +} diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h index e30e592bbe..b45a6a1d76 100644 --- a/board/xilinx/ppc440-generic/xparameters.h +++ b/board/xilinx/ppc440-generic/xparameters.h @@ -1,6 +1,6 @@ /* * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com * This work has been supported by: QTechnology http://qtec.com/ * based on xparameters-ml507.h by Xilinx * @@ -12,12 +12,15 @@ #define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 #define XPAR_IIC_EEPROM_BASEADDR 0x81600000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_INTC_0_BASEADDR 0x87000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xF0000000 #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 #define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 -#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 +#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80 +#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98 +#define XPAR_LLTEMAC_0_BASEADDR 0x83000000 +#define XPAR_LLTEMAC_1_BASEADDR 0x83000040 #endif diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 414f5302a0..01bae5d67e 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -8,7 +8,6 @@ #include <fdtdec.h> #include <fpga.h> #include <mmc.h> -#include <netdev.h> #include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -94,34 +93,11 @@ int board_late_init(void) #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { - puts("Board:\tXilinx Zynq\n"); + puts("Board: Xilinx Zynq\n"); return 0; } #endif -int board_eth_init(bd_t *bis) -{ - u32 ret = 0; - -#ifdef CONFIG_XILINX_AXIEMAC - ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, - XILINX_AXIDMA_BASEADDR); -#endif -#ifdef CONFIG_XILINX_EMACLITE - u32 txpp = 0; - u32 rxpp = 0; -# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG - txpp = 1; -# endif -# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG - rxpp = 1; -# endif - ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, - txpp, rxpp); -#endif - return ret; -} - int dram_init(void) { #if CONFIG_IS_ENABLED(OF_CONTROL) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 2cf47125d4..44d347ed3b 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -9,6 +9,7 @@ #include <netdev.h> #include <ahci.h> #include <scsi.h> +#include <asm/arch/clk.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> @@ -28,10 +29,18 @@ int board_early_init_r(void) { u32 val; - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - + if (current_el() == 3) { + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + /* Program freq register in System counter */ + writel(zynqmp_get_system_timer_freq(), + &iou_scntr_secure->base_frequency_id_register); + /* And enable system counter */ + writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, + &iou_scntr_secure->counter_control_register); + } /* Program freq register in System counter and enable system counter */ writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | @@ -48,11 +57,6 @@ int dram_init(void) return 0; } -int timer_init(void) -{ - return 0; -} - void reset_cpu(ulong addr) { } @@ -73,11 +77,36 @@ int board_late_init(void) reg = readl(&crlapb_base->boot_mode); bootmode = reg & BOOT_MODES_MASK; + puts("Bootmode: "); switch (bootmode) { - case SD_MODE: + case JTAG_MODE: + puts("JTAG_MODE\n"); + setenv("modeboot", "jtagboot"); + break; + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + setenv("modeboot", "qspiboot"); + puts("QSPI_MODE\n"); + break; case EMMC_MODE: + puts("EMMC_MODE\n"); + setenv("modeboot", "sdboot"); + break; + case SD_MODE: + puts("SD_MODE\n"); setenv("modeboot", "sdboot"); break; + case SD_MODE1: + puts("SD_MODE1\n"); +#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1) + setenv("sdbootdev", "1"); +#endif + setenv("modeboot", "sdboot"); + break; + case NAND_MODE: + puts("NAND_MODE\n"); + setenv("modeboot", "nandboot"); + break; default: printf("Invalid Boot Mode:0x%x\n", bootmode); break; @@ -88,7 +117,7 @@ int board_late_init(void) int checkboard(void) { - puts("Board:\tXilinx ZynqMP\n"); + puts("Board: Xilinx ZynqMP\n"); return 0; } |