diff options
Diffstat (limited to 'board')
21 files changed, 461 insertions, 259 deletions
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 441465c005..ce4acc13e0 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -12,7 +12,6 @@ #include <version.h> #include <common.h> #include <errno.h> -#include <spl.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> #include <asm/arch/omap.h> @@ -640,8 +639,7 @@ static struct cpsw_platform_data cpsw_data = { }; #endif /* CONFIG_DRIVER_TI_CPSW, ... */ -#if defined(CONFIG_DRIVER_TI_CPSW) - +#if defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) int board_eth_init(bd_t *bis) { int rv = 0; @@ -658,8 +656,6 @@ int board_eth_init(bd_t *bis) mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; -#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_FDT) printf("<ethaddr> not set. trying DTB ... "); @@ -685,10 +681,9 @@ int board_eth_init(bd_t *bis) printf("Error %d registering CPSW switch\n", rv); return 0; } -#endif /* CONFIG_DRIVER_TI_CPSW, ... */ return rv; } -#endif /* CONFIG_DRIVER_TI_CPSW */ +#endif /* defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) */ #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { diff --git a/board/compulab/cm_t43/Makefile b/board/compulab/cm_t43/Makefile index 399368920d..c749659b26 100644 --- a/board/compulab/cm_t43/Makefile +++ b/board/compulab/cm_t43/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += board.o mux.o +ifdef CONFIG_SPL_BUILD +obj-y += spl.o mux.o +else +obj-y += cm_t43.o mux.o +endif diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c new file mode 100644 index 0000000000..0d5da6f5e9 --- /dev/null +++ b/board/compulab/cm_t43/cm_t43.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2015 Compulab, Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <asm/gpio.h> +#include <asm/arch/sys_proto.h> +#include <asm/emif.h> +#include <power/pmic.h> +#include <power/tps65218.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + uchar tps_status = 0; + + power_tps65218_init(I2C_PMIC); + p = pmic_get("TPS65218_PMIC"); + if (p && !pmic_probe(p)) { + puts("PMIC: TPS65218\n"); + /* We don't care if fseal is locked, but we do need it set */ + tps65218_lock_fseal(); + tps65218_reg_read(TPS65218_STATUS, &tps_status); + if (!(tps_status & TPS65218_FSEAL)) + printf("WARNING: RTC not backed by battery!\n"); + } + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + set_i2c_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_probe(TPS65218_CHIP_PM); + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW + +static void cpsw_control(int enabled) +{ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#define GPIO_PHY1_RST 170 +#define GPIO_PHY2_RST 168 + +int board_phy_config(struct phy_device *phydev) +{ + unsigned short val; + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} + +static void board_phy_init(void) +{ + set_mdio_pin_mux(); + writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */ + writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */ + writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */ + + /* For revision A */ + writel(0x2000009, 0x44df2e6c); + writel(0x38a, 0x44df2e70); + + mdelay(10); + + gpio_request(GPIO_PHY1_RST, "phy1_rst"); + gpio_request(GPIO_PHY2_RST, "phy2_rst"); + gpio_direction_output(GPIO_PHY1_RST, 0); + gpio_direction_output(GPIO_PHY2_RST, 0); + mdelay(2); + + gpio_set_value(GPIO_PHY1_RST, 1); + gpio_set_value(GPIO_PHY2_RST, 1); + mdelay(2); +} + +int board_eth_init(bd_t *bis) +{ + int rv; + + set_rgmii_pin_mux(); + writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); + board_phy_init(); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + + return rv; +} +#endif diff --git a/board/compulab/cm_t43/board.c b/board/compulab/cm_t43/spl.c index 4272c45feb..b7d118eb9c 100644 --- a/board/compulab/cm_t43/board.c +++ b/board/compulab/cm_t43/spl.c @@ -1,31 +1,21 @@ /* - * Copyright (C) 2015 Compulab, Ltd. + * Copyright (C) 2016 Compulab, Ltd. * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <i2c.h> -#include <miiphy.h> -#include <cpsw.h> #include <spl.h> +#include <i2c.h> #include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mux.h> #include <asm/arch/ddr_defs.h> -#include <asm/errno.h> #include <asm/gpio.h> -#include <asm/emif.h> #include <power/pmic.h> #include <power/tps65218.h> #include "board.h" DECLARE_GLOBAL_DATA_PTR; -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 }; const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 }; const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 }; @@ -114,22 +104,21 @@ const struct dpll_params *get_dpll_per_params(void) return &dpll_per; } -static void enable_vtt_regulator(void) +void scale_vcores(void) { - u32 temp; + set_i2c_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + if (i2c_probe(TPS65218_CHIP_PM)) + return; - writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); - writel(GPIO_SETDATAOUT(7), AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); - temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); - temp = temp & ~(GPIO_OE_ENABLE(7)); - writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); + tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV); + tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV); } void sdram_init(void) { unsigned long ram_size; - enable_vtt_regulator(); config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (ram_size == 0x80000000 || @@ -145,128 +134,4 @@ void sdram_init(void) hang(); } -#endif - -/* setup board specific PMIC */ -int power_init_board(void) -{ - struct pmic *p; - - power_tps65218_init(I2C_PMIC); - p = pmic_get("TPS65218_PMIC"); - if (p && !pmic_probe(p)) - puts("PMIC: TPS65218\n"); - - return 0; -} -int board_init(void) -{ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - gpmc_init(); - set_i2c_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - i2c_probe(TPS65218_CHIP_PM); - - return 0; -} - -#ifdef CONFIG_DRIVER_TI_CPSW - -static void cpsw_control(int enabled) -{ - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, - { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, - .phy_addr = 1, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 2, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -#define GPIO_PHY1_RST 170 -#define GPIO_PHY2_RST 168 - -int board_phy_config(struct phy_device *phydev) -{ - unsigned short val; - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} - -static void board_phy_init(void) -{ - set_mdio_pin_mux(); - writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */ - writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */ - writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */ - - /* For revision A */ - writel(0x2000009, 0x44df2e6c); - writel(0x38a, 0x44df2e70); - - mdelay(10); - - gpio_request(GPIO_PHY1_RST, "phy1_rst"); - gpio_request(GPIO_PHY2_RST, "phy2_rst"); - gpio_direction_output(GPIO_PHY1_RST, 0); - gpio_direction_output(GPIO_PHY2_RST, 0); - mdelay(2); - - gpio_set_value(GPIO_PHY1_RST, 1); - gpio_set_value(GPIO_PHY2_RST, 1); - mdelay(2); -} - -int board_eth_init(bd_t *bis) -{ - int rv; - - set_rgmii_pin_mux(); - writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); - board_phy_init(); - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - - return rv; -} -#endif diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index a498c65f04..71ed15e6a6 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -19,7 +19,7 @@ #include "sleep.h" #ifdef CONFIG_U_QE -#include "../../../drivers/qe/qe.h" +#include <fsl_qe.h> #endif DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c index e9cbd515a1..498d770991 100644 --- a/board/freescale/common/mpc85xx_sleep.c +++ b/board/freescale/common/mpc85xx_sleep.c @@ -8,7 +8,7 @@ #include <asm/immap_85xx.h> #include "sleep.h" #ifdef CONFIG_U_QE -#include "../../../drivers/qe/qe.h" +#include <fsl_qe.h> #endif DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS index 820d3223c2..c37ab993ee 100644 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -8,6 +8,7 @@ F: configs/ls1021aqds_ddr4_nor_defconfig F: configs/ls1021aqds_ddr4_nor_lpuart_defconfig F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig F: configs/ls1021aqds_nor_lpuart_defconfig -F: configs/ls1021aqds_sdcard_defconfig +F: configs/ls1021aqds_sdcard_ifc_defconfig +F: configs/ls1021aqds_sdcard_qspi_defconfig F: configs/ls1021aqds_qspi_defconfig F: configs/ls1021aqds_nand_defconfig diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 5f4ec9d878..dbea0bff26 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -10,7 +10,6 @@ #include <asm/arch/immap_ls102xa.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> -#include <asm/arch/ls102xa_stream_id.h> #include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_devdis.h> #include <asm/arch/ls102xa_sata.h> @@ -28,7 +27,7 @@ #include "../common/qixis.h" #include "ls1021aqds_qixis.h" #ifdef CONFIG_U_QE -#include "../../../drivers/qe/qe.h" +#include <fsl_qe.h> #endif #define PIN_MUX_SEL_CAN 0x03 @@ -61,7 +60,7 @@ enum { int checkboard(void) { -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) char buf[64]; #endif #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) @@ -90,7 +89,7 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); @@ -426,42 +425,6 @@ int misc_init_r(void) return 0; } -struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), - SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), - SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), - SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), - SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), -}; - -struct smmu_stream_id dev_stream_id[] = { - { 0x100, 0x01, "ETSEC MAC1" }, - { 0x104, 0x02, "ETSEC MAC2" }, - { 0x108, 0x03, "ETSEC MAC3" }, - { 0x10c, 0x04, "PEX1" }, - { 0x110, 0x05, "PEX2" }, - { 0x114, 0x06, "qDMA" }, - { 0x118, 0x07, "SATA" }, - { 0x11c, 0x08, "USB3" }, - { 0x120, 0x09, "QE" }, - { 0x124, 0x0a, "eSDHC" }, - { 0x128, 0x0b, "eMA" }, - { 0x14c, 0x0c, "2D-ACE" }, - { 0x150, 0x0d, "USB2" }, - { 0x18c, 0x0e, "DEBUG" }, -}; - int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -481,10 +444,7 @@ int board_init(void) config_serdes_mux(); #endif - ls1021x_config_caam_stream_id(sec_liodn_tbl, - ARRAY_SIZE(sec_liodn_tbl)); - ls102xa_config_smmu_stream_id(dev_stream_id, - ARRAY_SIZE(dev_stream_id)); + ls102xa_smmu_stream_id_init(); #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg index 9d99bd862d..9d99bd862d 100644 --- a/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg +++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg new file mode 100644 index 0000000000..2bd398cc53 --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +#0608000a 00000000 00000000 00000000 +#60000000 00407900 60040a00 21046000 +#00000000 00000000 00000000 00038000 +#00000000 001b7200 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +0608000a 00000000 00000000 00000000 +60000000 00407900 60040a00 21046000 +00000000 00000000 00000000 00038000 +20024800 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 616e0bfd39..c69c9cba42 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -10,7 +10,6 @@ #include <asm/arch/immap_ls102xa.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> -#include <asm/arch/ls102xa_stream_id.h> #include <asm/arch/ls102xa_devdis.h> #include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_sata.h> @@ -28,7 +27,7 @@ #include <spl.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE -#include "../../../drivers/qe/qe.h" +#include <fsl_qe.h> #endif #include <fsl_validate.h> @@ -448,43 +447,6 @@ void board_init_f(ulong dummy) } #endif - -struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), - SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), - SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), - SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), - SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), -}; - -struct smmu_stream_id dev_stream_id[] = { - { 0x100, 0x01, "ETSEC MAC1" }, - { 0x104, 0x02, "ETSEC MAC2" }, - { 0x108, 0x03, "ETSEC MAC3" }, - { 0x10c, 0x04, "PEX1" }, - { 0x110, 0x05, "PEX2" }, - { 0x114, 0x06, "qDMA" }, - { 0x118, 0x07, "SATA" }, - { 0x11c, 0x08, "USB3" }, - { 0x120, 0x09, "QE" }, - { 0x124, 0x0a, "eSDHC" }, - { 0x128, 0x0b, "eMA" }, - { 0x14c, 0x0c, "2D-ACE" }, - { 0x150, 0x0d, "USB2" }, - { 0x18c, 0x0e, "DEBUG" }, -}; - #ifdef CONFIG_DEEP_SLEEP /* program the regulator (MC34VR500) to support deep sleep */ void ls1twr_program_regulator(void) @@ -525,10 +487,7 @@ int board_init(void) #endif #endif - ls1021x_config_caam_stream_id(sec_liodn_tbl, - ARRAY_SIZE(sec_liodn_tbl)); - ls102xa_config_smmu_stream_id(dev_stream_id, - ARRAY_SIZE(dev_stream_id)); + ls102xa_smmu_stream_id_init(); #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 01db078222..a72fe52ea0 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -223,10 +223,25 @@ void board_retimer_init(void) int board_early_init_f(void) { +#ifdef CONFIG_HAS_FSL_XHCI_USB + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; +#endif #ifdef CONFIG_LPUART u8 uart; #endif fsl_lsch2_early_init_f(); + +#ifdef CONFIG_HAS_FSL_XHCI_USB + out_be32(&scfg->rcwpmuxcr0, 0x3333); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#endif + #ifdef CONFIG_LPUART /* We use lpuart0 as system console */ uart = QIXIS_READ(brdcfg[14]); diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index c8f723a108..66d974a40b 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -21,6 +21,10 @@ #include <environment.h> #include <fsl_sec.h> #include "cpld.h" +#ifdef CONFIG_U_QE +#include <fsl_qe.h> +#endif + DECLARE_GLOBAL_DATA_PTR; @@ -71,23 +75,8 @@ int dram_init(void) int board_early_init_f(void) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - u32 usb_pwrfault; - fsl_lsch2_early_init_f(); -#ifdef CONFIG_HAS_FSL_XHCI_USB - out_be32(&scfg->rcwpmuxcr0, 0x3333); - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); - usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB2_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << - SCFG_USBPWRFAULT_USB1_SHIFT); - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); -#endif - return 0; } @@ -113,11 +102,36 @@ int board_init(void) enable_layerscape_ns_access(); #endif +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + return 0; } int config_board_mux(void) { + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + + if (hwconfig("qe-hdlc")) { + out_be32(&scfg->rcwpmuxcr0, + (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600); + printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n", + in_be32(&scfg->rcwpmuxcr0)); + } else { +#ifdef CONFIG_HAS_FSL_XHCI_USB + out_be32(&scfg->rcwpmuxcr0, 0x3333); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#endif + } return 0; } @@ -144,6 +158,16 @@ int misc_init_r(void) } #endif +void fdt_del_qe(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,qe")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + int ft_board_setup(void *blob, bd_t *bd) { u64 base[CONFIG_NR_DRAM_BANKS]; @@ -161,6 +185,23 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); #endif + + /* + * qe-hdlc and usb multi-use the pins, + * when set hwconfig to qe-hdlc, delete usb node. + */ + if (hwconfig("qe-hdlc")) +#ifdef CONFIG_HAS_FSL_XHCI_USB + fdt_del_node_and_alias(blob, "usb1"); +#endif + /* + * qe just support qe-uart and qe-hdlc, + * if qe-uart and qe-hdlc are not set in hwconfig, + * delete qe node. + */ + if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc")) + fdt_del_qe(blob); + return 0; } diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index b5c44f915b..668f68476e 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -228,6 +228,30 @@ int board_init(void) return 0; } +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + switch (gd->bd->bi_arch_number) { + case MACH_TYPE_DM3730_TORPEDO: + setenv("fdtimage", "logicpd-torpedo-37xx-devkit.dtb"); + break; + case MACH_TYPE_DM3730_SOM_LV: + setenv("fdtimage", "logicpd-som-lv-37xx-devkit.dtb"); + break; + case MACH_TYPE_OMAP3_TORPEDO: + setenv("fdtimage", "logicpd-torpedo-35xx-devkit.dtb"); + break; + case MACH_TYPE_OMAP3530_LV_SOM: + setenv("fdtimage", "logicpd-som-lv-35xx-devkit.dtb"); + break; + default: + /* unknown machine type */ + break; + } + return 0; +} +#endif + #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 7f4fe64385..1d3a4e09cf 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <inttypes.h> #include <config.h> #include <dm.h> #include <fdt_support.h> @@ -56,6 +57,12 @@ struct msg_get_board_rev { u32 end_tag; }; +struct msg_get_board_serial { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_board_serial get_board_serial; + u32 end_tag; +}; + struct msg_get_mac_address { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_get_mac_address get_mac_address; @@ -281,6 +288,30 @@ static void set_board_info(void) } #endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */ +static void set_serial_number(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_serial, msg, 1); + int ret; + char serial_string[17] = { 0 }; + + if (getenv("serial#")) + return; + + BCM2835_MBOX_INIT_HDR(msg); + BCM2835_MBOX_INIT_TAG_NO_REQ(&msg->get_board_serial, GET_BOARD_SERIAL); + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); + if (ret) { + printf("bcm2835: Could not query board serial\n"); + /* Ignore error; not critical */ + return; + } + + snprintf(serial_string, sizeof(serial_string), "%016" PRIx64, + msg->get_board_serial.body.resp.serial); + setenv("serial#", serial_string); +} + int misc_init_r(void) { set_fdtfile(); @@ -288,6 +319,8 @@ int misc_init_r(void) #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG set_board_info(); #endif + set_serial_number(); + return 0; } diff --git a/board/samsung/origen/tools/mkorigenspl.c b/board/samsung/origen/tools/mkorigenspl.c index 8b0c3ac4bd..7b5d93b9ef 100644 --- a/board/samsung/origen/tools/mkorigenspl.c +++ b/board/samsung/origen/tools/mkorigenspl.c @@ -83,8 +83,8 @@ int main(int argc, char **argv) for (i = 0; i < IMG_SIZE - SPL_HEADER_SIZE; i++) checksum += buffer[i+16]; - *(ulong *)buffer ^= 0x1f; - *(ulong *)(buffer+4) ^= checksum; + *(unsigned long *)buffer ^= 0x1f; + *(unsigned long *)(buffer+4) ^= checksum; for (i = 1; i < SPL_HEADER_SIZE; i++) buffer[i] ^= buffer[i-1]; diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index fb8475f65f..d16d73fc97 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -50,6 +50,7 @@ int uart_setup_gpio(void) int i; int rv = 0; + clock_setup(GPIO_A_CLOCK_CFG); for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); if (rv) @@ -115,6 +116,13 @@ static int fmc_setup_gpio(void) int rv = 0; int i; + clock_setup(GPIO_B_CLOCK_CFG); + clock_setup(GPIO_C_CLOCK_CFG); + clock_setup(GPIO_D_CLOCK_CFG); + clock_setup(GPIO_E_CLOCK_CFG); + clock_setup(GPIO_F_CLOCK_CFG); + clock_setup(GPIO_G_CLOCK_CFG); + for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], &gpio_ctl_fmc); diff --git a/board/st/stm32f746-disco/Kconfig b/board/st/stm32f746-disco/Kconfig new file mode 100644 index 0000000000..09289d2323 --- /dev/null +++ b/board/st/stm32f746-disco/Kconfig @@ -0,0 +1,19 @@ +if TARGET_STM32F746_DISCO + +config SYS_BOARD + string + default "stm32f746-disco" + +config SYS_VENDOR + string + default "st" + +config SYS_SOC + string + default "stm32f7" + +config SYS_CONFIG_NAME + string + default "stm32f746-disco" + +endif diff --git a/board/st/stm32f746-disco/MAINTAINERS b/board/st/stm32f746-disco/MAINTAINERS new file mode 100644 index 0000000000..2df0a65ac2 --- /dev/null +++ b/board/st/stm32f746-disco/MAINTAINERS @@ -0,0 +1,6 @@ +STM32F746 DISCOVERY BOARD +M: Vikas Manocha <vikas.manocha@st.com> +S: Maintained +F: board/st/stm32f746-disco +F: include/configs/stm32f746-disco.h +F: configs/stm32f746-disco_defconfig diff --git a/board/st/stm32f746-disco/Makefile b/board/st/stm32f746-disco/Makefile new file mode 100644 index 0000000000..db8a0a4dcf --- /dev/null +++ b/board/st/stm32f746-disco/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2016 +# Vikas Manocha <vikas.manocha@st.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := stm32f746-disco.o diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c new file mode 100644 index 0000000000..0e04d14148 --- /dev/null +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/armv7m.h> +#include <asm/arch/stm32.h> +#include <asm/arch/gpio.h> +#include <dm/platdata.h> +#include <dm/platform_data/serial_stm32x7.h> +#include <asm/arch/stm32_periph.h> +#include <asm/arch/stm32_defs.h> + +DECLARE_GLOBAL_DATA_PTR; + +const struct stm32_gpio_ctl gpio_ctl_gpout = { + .mode = STM32_GPIO_MODE_OUT, + .otype = STM32_GPIO_OTYPE_PP, + .speed = STM32_GPIO_SPEED_50M, + .pupd = STM32_GPIO_PUPD_NO, + .af = STM32_GPIO_AF0 +}; + +const struct stm32_gpio_ctl gpio_ctl_usart = { + .mode = STM32_GPIO_MODE_AF, + .otype = STM32_GPIO_OTYPE_PP, + .speed = STM32_GPIO_SPEED_50M, + .pupd = STM32_GPIO_PUPD_UP, + .af = STM32_GPIO_AF7 +}; + +static const struct stm32_gpio_dsc usart_gpio[] = { + {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */ + {STM32_GPIO_PORT_B, STM32_GPIO_PIN_7}, /* RX */ +}; + +int uart_setup_gpio(void) +{ + int i; + int rv = 0; + + clock_setup(GPIO_A_CLOCK_CFG); + clock_setup(GPIO_B_CLOCK_CFG); + for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { + rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); + if (rv) + goto out; + } + +out: + return rv; +} + +static const struct stm32x7_serial_platdata serial_platdata = { + .base = (struct stm32_usart *)USART1_BASE, + .clock = CONFIG_SYS_CLK_FREQ, +}; + +U_BOOT_DEVICE(stm32x7_serials) = { + .name = "serial_stm32x7", + .platdata = &serial_platdata, +}; + +u32 get_board_rev(void) +{ + return 0; +} + +int board_early_init_f(void) +{ + int res; + + res = uart_setup_gpio(); + clock_setup(USART1_CLOCK_CFG); + if (res) + return res; + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; + gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; + + gd->ram_size = CONFIG_SYS_RAM_SIZE; + return 0; +} |