diff options
Diffstat (limited to 'board')
30 files changed, 0 insertions, 1522 deletions
diff --git a/board/mpr2/Kconfig b/board/mpr2/Kconfig deleted file mode 100644 index 54176e8f6f..0000000000 --- a/board/mpr2/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MPR2 - -config SYS_BOARD - default "mpr2" - -config SYS_CONFIG_NAME - default "mpr2" - -endif diff --git a/board/mpr2/MAINTAINERS b/board/mpr2/MAINTAINERS deleted file mode 100644 index beedf8dda6..0000000000 --- a/board/mpr2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MPR2 BOARD -M: Mark Jonas <mark.jonas@de.bosch.com> -S: Maintained -F: board/mpr2/ -F: include/configs/mpr2.h -F: configs/mpr2_defconfig diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile deleted file mode 100644 index 6a71803ac7..0000000000 --- a/board/mpr2/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007 -# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> -# -# Copyright (C) 2007 -# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -# -# Copyright (C) 2007 -# Kenati Technologies, Inc. -# -# (C) Copyright 2008 -# Mark Jonas <mark.jonas@de.bosch.com> -# -# board/mpr2/Makefile -# - -obj-y := mpr2.o -extra-y += lowlevel_init.o diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S deleted file mode 100644 index e34a7a9a17..0000000000 --- a/board/mpr2/lowlevel_init.S +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 - * Mark Jonas <mark.jonas@de.bosch.com> - * - * (C) Copyright 2007 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * board/mpr2/lowlevel_init.S - */ -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - -/* - * Set frequency multipliers and dividers in FRQCR. - */ - write16 WTCSR_A, WTCSR_D - - write16 WTCNT_A, WTCNT_D - - write16 FRQCR_A, FRQCR_D - -/* - * Setup CS0 (Flash). - */ - write32 CS0BCR_A, CS0BCR_D - - write32 CS0WCR_A, CS0WCR_D - -/* - * Setup CS3 (SDRAM). - */ - write32 CS3BCR_A, CS3BCR_D - - write32 CS3WCR_A, CS3WCR_D - - write32 SDCR_A, SDCR_D1 - - write32 RTCSR_A, RTCSR_D - - write32 RTCNT_A, RTCNT_D - - write32 RTCOR_A, RTCOR_D - - write32 SDCR_A, SDCR_D2 - - mov.l SDMR3_A, r1 - mov.l SDMR3_D, r0 - add r0, r1 - mov #0, r0 - mov.w r0, @r1 - - rts - nop - - .align 4 - -/* - * Configuration for MPR2 A.3 through A.7 - */ - -/* - * PLL Settings - */ -FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ -WTCNT_D: .word 0x5A00 /* start counting at zero */ -WTCSR_D: .word 0xA507 /* divide by 4096 */ -.align 2 -/* - * Spansion S29GL256N11 @ 48 MHz - */ -/* 1 idle cycle inserted, normal space, 16 bit */ -CS0BCR_D: .long 0x12490400 -/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ -CS0WCR_D: .long 0x00000340 - -/* - * Samsung K4S511632B-UL75 @ 48 MHz - * Micron MT48LC32M16A2-75 @ 48 MHz - */ -/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ -CS3BCR_D: .long 0x10004400 -/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ -CS3WCR_D: .long 0x00000091 -/* no refresh, 13 rows, 10 cols, NO bank active mode */ -SDCR_D1: .long 0x00000012 -SDCR_D2: .long 0x00000812 /* refresh */ -RTCSR_D: .long 0xA55A0008 /* 1/4, once */ -RTCNT_D: .long 0xA55A005D /* count 93 */ -RTCOR_D: .long 0xa55a005d /* count 93 */ -/* mode register CL2, burst read and SINGLE WRITE */ -SDMR3_D: .long 0x440 - -/* - * Registers - */ - -FRQCR_A: .long 0xA415FF80 -WTCNT_A: .long 0xA415FF84 -WTCSR_A: .long 0xA415FF86 - -#define BSC_BASE 0xA4FD0000 -CS0BCR_A: .long BSC_BASE + 0x04 -CS3BCR_A: .long BSC_BASE + 0x0C -CS0WCR_A: .long BSC_BASE + 0x24 -CS3WCR_A: .long BSC_BASE + 0x2C -SDCR_A: .long BSC_BASE + 0x44 -RTCSR_A: .long BSC_BASE + 0x48 -RTCNT_A: .long BSC_BASE + 0x4C -RTCOR_A: .long BSC_BASE + 0x50 -SDMR3_A: .long BSC_BASE + 0x5000 diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c deleted file mode 100644 index 9eb04907a4..0000000000 --- a/board/mpr2/mpr2.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 - * Mark Jonas <mark.jonas@de.bosch.com> - * - * board/mpr2/mpr2.c - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> - -int checkboard(void) -{ - puts("BOARD: MPR2\n"); - return 0; -} - -int board_init(void) -{ - /* - * For MPR2 A.3 through A.7 - */ - - /* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */ - __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */ - __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */ - - /* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */ - __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */ - __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - - /* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */ - __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */ - __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - - /* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */ - __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */ - __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - - /* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */ - __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */ - __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ - - /* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */ - __raw_writew(0xAABC, PSELA); /* 10 10 10 10 10 11 11 00 */ - - /* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */ - __raw_writew(0x3C00, PSELB); /* 0 0 11 11 0 0 00000000 */ - - /* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */ - __raw_writew(0x0000, PSELC); /* 00 00 00 00 00000000 */ - - /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */ - __raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */ - - /* OTH: (00) Other fuction - * GPO: (01) General Purpose Output - * GPI: (11) General Purpose Input - * GPI+: (10) General Purpose Input with internal pull-up - *------------------------------------------------------- - * A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); - * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); */ - __raw_writew(0x5555, PACR); /* 01 01 01 01 01 01 01 01 */ - - /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); - * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); */ - __raw_writew(0x5555, PBCR); /* 01 01 01 01 01 01 01 01 */ - - /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); - * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; */ - __raw_writew(0x5500, PCCR); /* 01 01 01 01 00 00 00 00 */ - - /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); - * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); */ - __raw_writew(0x5555, PDCR); /* 01 01 01 01 01 01 01 01 */ - - /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; - * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; */ - __raw_writew(0x2800, PECR); /* 00 10 10 00 00 00 00 00 */ - - /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; - * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); */ - __raw_writew(0x0002, PFCR); /* 00 00 00 00 00 00 00 10 */ - - /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2); - * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); */ - __raw_writew(0x03D5, PGCR); /* 00 00 00 11 11 01 01 01 */ - - /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); - * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; */ - __raw_writew(0x0050, PHCR); /* 00 00 00 00 01 01 00 00 */ - - /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; - * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; */ - __raw_writew(0x0000, PJCR); /* 00 00 00 00 00 00 00 00 */ - - /* K7 (x); K6 (x); K5 (x); K4 (x) - * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nc); K0 PINT4(FLASH_READY); */ - __raw_writew(0x00FB, PKCR); /* 00 00 00 00 11 11 10 11 */ - - /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; - * L3 TCK; L2 (x); L1 (x); L0 (x); */ - __raw_writew(0x0000, PLCR); /* 00 00 00 00 00 00 00 00 */ - - /* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); M4 GPO(LAN_RESET); - * M3 GPO(BUZZER); M2 GPO(LCD_BL); M1 CS5B(CAN3_CS); M0 GPI+(nc); */ - __raw_writew(0x5552, PMCR); /* 01 01 01 01 01 01 00 10 */ - __raw_writeb(0xF0, PMDR); /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */ - - /* P7 (x); P6 (x); P5 (x); P4 GPO(on pullup); - * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ); */ - __raw_writew(0x0100, PPCR); /* 00 00 00 01 00 00 00 00 */ - __raw_writeb(0x10, PPDR); /* no current flow through pullup */ - - /* R7 A25; R6 A24; R5 A23; R4 A22; - * R3 A21; R2 A20; R1 A19; R0 A0; */ - __raw_writew(0x0000, PRCR); /* 00 00 00 00 00 00 00 00 */ - - /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); - * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; */ - __raw_writew(0x0140, PSCR); /* 00 00 00 01 01 00 00 00 */ - - /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; - * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG); */ - __raw_writew(0x0001, PTCR); /* 00 00 00 00 00 00 00 01 */ - - /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); - * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; */ - __raw_writew(0x0240, PUCR); /* 00 00 00 10 01 00 00 00 */ - - /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); - * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); */ - __raw_writew(0x0142, PVCR); /* 00 00 00 01 01 00 00 10 */ - - return 0; -} diff --git a/board/ms7720se/Kconfig b/board/ms7720se/Kconfig deleted file mode 100644 index 83313279b3..0000000000 --- a/board/ms7720se/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MS7720SE - -config SYS_BOARD - default "ms7720se" - -config SYS_CONFIG_NAME - default "ms7720se" - -endif diff --git a/board/ms7720se/MAINTAINERS b/board/ms7720se/MAINTAINERS deleted file mode 100644 index 96a80f4e31..0000000000 --- a/board/ms7720se/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MS7720SE BOARD -M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> -S: Maintained -F: board/ms7720se/ -F: include/configs/ms7720se.h -F: configs/ms7720se_defconfig diff --git a/board/ms7720se/Makefile b/board/ms7720se/Makefile deleted file mode 100644 index d3a8e19d0b..0000000000 --- a/board/ms7720se/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007 -# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> -# -# Copyright (C) 2007 -# Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -# -# Copyright (C) 2007 -# Kenati Technologies, Inc. -# -# board/ms7720se/Makefile -# - -obj-y := ms7720se.o -extra-y += lowlevel_init.o diff --git a/board/ms7720se/lowlevel_init.S b/board/ms7720se/lowlevel_init.S deleted file mode 100644 index 871d6a81d5..0000000000 --- a/board/ms7720se/lowlevel_init.S +++ /dev/null @@ -1,184 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - */ - -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - write16 WTCSR_A, WTCSR_D - - write16 WTCNT_A, WTCNT_D - - write16 FRQCR_A, FRQCR_D - - write16 UCLKCR_A, UCLKCR_D - - write32 CMNCR_A, CMNCR_D - - write32 CMNCR_A, CMNCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS2BCR_A, CS2BCR_D - - write32 CS3BCR_A, CS3BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5ABCR_A, CS5ABCR_D - - write32 CS5BBCR_A, CS5BBCR_D - - write32 CS6ABCR_A, CS6ABCR_D - - write32 CS6BBCR_A, CS6BBCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS2WCR_A, CS2WCR_D - - write32 CS3WCR_A, CS3WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5AWCR_A, CS5AWCR_D - - write32 CS5BWCR_A, CS5BWCR_D - - write32 CS6AWCR_A, CS6AWCR_D - - write32 CS6BWCR_A, CS6BWCR_D - - write32 SDCR_A, SDCR_D1 - - write32 RTCSR_A, RTCSR_D - - write32 RTCNT_A RTCNT_D - - write32 RTCOR_A, RTCOR_D - - write32 SDCR_A, SDCR_D2 - - write16 SDMR3_A, SDMR3_D - - write16 PCCR_A, PCCR_D - - write16 PDCR_A, PDCR_D - - write16 PECR_A, PECR_D - - write16 PGCR_A, PGCR_D - - write16 PHCR_A, PHCR_D - - write16 PPCR_A, PPCR_D - - write16 PTCR_A, PTCR_D - - write16 PVCR_A, PVCR_D - - write16 PSELA_A, PSELA_D - - write32 CCR_A, CCR_D - - write8 LED_A, LED_D - - rts - nop - - .align 4 - -FRQCR_A: .long 0xA415FF80 /* FRQCR Address */ -WTCNT_A: .long 0xA415FF84 -WTCSR_A: .long 0xA415FF86 -UCLKCR_A: .long 0xA40A0008 -FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ -WTCNT_D: .word 0x5A00 -WTCSR_D: .word 0xA506 -UCLKCR_D: .word 0xA5C0 - -#define BSC_BASE 0xA4FD0000 -CMNCR_A: .long BSC_BASE -CS0BCR_A: .long BSC_BASE + 0x04 -CS2BCR_A: .long BSC_BASE + 0x08 -CS3BCR_A: .long BSC_BASE + 0x0C -CS4BCR_A: .long BSC_BASE + 0x10 -CS5ABCR_A: .long BSC_BASE + 0x14 -CS5BBCR_A: .long BSC_BASE + 0x18 -CS6ABCR_A: .long BSC_BASE + 0x1C -CS6BBCR_A: .long BSC_BASE + 0x20 -CS0WCR_A: .long BSC_BASE + 0x24 -CS2WCR_A: .long BSC_BASE + 0x28 -CS3WCR_A: .long BSC_BASE + 0x2C -CS4WCR_A: .long BSC_BASE + 0x30 -CS5AWCR_A: .long BSC_BASE + 0x34 -CS5BWCR_A: .long BSC_BASE + 0x38 -CS6AWCR_A: .long BSC_BASE + 0x3C -CS6BWCR_A: .long BSC_BASE + 0x40 -SDCR_A: .long BSC_BASE + 0x44 -RTCSR_A: .long BSC_BASE + 0x48 -RTCNT_A: .long BSC_BASE + 0x4C -RTCOR_A: .long BSC_BASE + 0x50 -SDMR3_A: .long BSC_BASE + 0x58C0 - -CMNCR_D: .long 0x00000010 -CS0BCR_D: .long 0x36DB0400 -CS2BCR_D: .long 0x36DB0400 -CS3BCR_D: .long 0x36DB4600 -CS4BCR_D: .long 0x36DB0400 -CS5ABCR_D: .long 0x36DB0400 -CS5BBCR_D: .long 0x36DB0200 -CS6ABCR_D: .long 0x36DB0400 -CS6BBCR_D: .long 0x36DB0400 -CS0WCR_D: .long 0x00000B01 -CS2WCR_D: .long 0x00000500 -CS3WCR_D: .long 0x00006D1B -CS4WCR_D: .long 0x00000500 -CS5AWCR_D: .long 0x00000500 -CS5BWCR_D: .long 0x00000500 -CS6AWCR_D: .long 0x00000500 -CS6BWCR_D: .long 0x00000500 -SDCR_D1: .long 0x00000011 -RTCSR_D: .long 0xA55A0010 -RTCNT_D: .long 0xA55A001F -RTCOR_D: .long 0xA55A001F -SDMR3_D: .word 0x0000 -.align 2 -SDCR_D2: .long 0x00000811 - -#define PFC_BASE 0xA4050100 -PCCR_A: .long PFC_BASE + 0x04 -PDCR_A: .long PFC_BASE + 0x06 -PECR_A: .long PFC_BASE + 0x08 -PGCR_A: .long PFC_BASE + 0x0C -PHCR_A: .long PFC_BASE + 0x0E -PPCR_A: .long PFC_BASE + 0x18 -PTCR_A: .long PFC_BASE + 0x1E -PVCR_A: .long PFC_BASE + 0x22 -PSELA_A: .long PFC_BASE + 0x24 - -PCCR_D: .word 0x0000 -PDCR_D: .word 0x0000 -PECR_D: .word 0x0000 -PGCR_D: .word 0x0000 -PHCR_D: .word 0x0000 -PPCR_D: .word 0x00AA -PTCR_D: .word 0x0280 -PVCR_D: .word 0x0000 -PSELA_D: .word 0x0000 -.align 2 - -CCR_A: .long 0xFFFFFFEC -!CCR_D: .long 0x0000000D -CCR_D: .long 0x0000000B - -LED_A: .long 0xB6800000 -LED_D: .long 0xFF diff --git a/board/ms7720se/ms7720se.c b/board/ms7720se/ms7720se.c deleted file mode 100644 index a35f72e83b..0000000000 --- a/board/ms7720se/ms7720se.c +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * Copyright (C) 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * Copyright (C) 2007 - * Kenati Technologies, Inc. - * - * board/ms7720se/ms7720se.c - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> - -#define LED_BASE 0xB0800000 - -int checkboard(void) -{ - puts("BOARD: Hitachi UL MS7720SE\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -void led_set_state(unsigned short value) -{ - outw(value & 0xFF, LED_BASE); -} diff --git a/board/renesas/rsk7203/Kconfig b/board/renesas/rsk7203/Kconfig deleted file mode 100644 index 10b8786411..0000000000 --- a/board/renesas/rsk7203/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_RSK7203 - -config SYS_BOARD - default "rsk7203" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "rsk7203" - -endif diff --git a/board/renesas/rsk7203/MAINTAINERS b/board/renesas/rsk7203/MAINTAINERS deleted file mode 100644 index 18d36634cf..0000000000 --- a/board/renesas/rsk7203/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -RSK7203 BOARD -M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> -M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -S: Maintained -F: board/renesas/rsk7203/ -F: include/configs/rsk7203.h -F: configs/rsk7203_defconfig diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile deleted file mode 100644 index 545079e99e..0000000000 --- a/board/renesas/rsk7203/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007,2008 Nobuhiro Iwamatsu -# Copyright (C) 2008 Renesas Solutions Corp. -# -# u-boot/board/rsk7203/Makefile -# - -obj-y := rsk7203.o -extra-y += lowlevel_init.o diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S deleted file mode 100644 index f82dd7dc05..0000000000 --- a/board/renesas/rsk7203/lowlevel_init.S +++ /dev/null @@ -1,199 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - */ -#include <config.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* Cache setting */ - write32 CCR1_A ,CCR1_D - - /* ConfigurePortPins */ - write16 PECRL3_A, PECRL3_D - - write16 PCCRL4_A, PCCRL4_D0 - - write16 PECRL4_A, PECRL4_D0 - - write16 PEIORL_A, PEIORL_D0 - - write16 PCIORL_A, PCIORL_D - - write16 PFCRH2_A, PFCRH2_D - - write16 PFCRH3_A, PFCRH3_D - - write16 PFCRH1_A, PFCRH1_D - - write16 PFIORH_A, PFIORH_D - - write16 PECRL1_A, PECRL1_D0 - - write16 PEIORL_A, PEIORL_D1 - - /* Configure Operating Frequency */ - write16 WTCSR_A, WTCSR_D0 - - write16 WTCSR_A, WTCSR_D1 - - write16 WTCNT_A, WTCNT_D - - /* Set clock mode*/ - write16 FRQCR_A, FRQCR_D - - /* Configure Bus And Memory */ -init_bsc_cs0: - write16 PCCRL4_A, PCCRL4_D1 - - write16 PECRL1_A, PECRL1_D1 - - write32 CMNCR_A, CMNCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS0WCR_A, CS0WCR_D - -init_bsc_cs1: - write16 PECRL4_A, PECRL4_D1 - - write32 CS1WCR_A, CS1WCR_D - -init_sdram: - write16 PCCRL2_A, PCCRL2_D - - write16 PCCRL4_A, PCCRL4_D2 - - write16 PCCRL1_A, PCCRL1_D - - write16 PCCRL3_A, PCCRL3_D - - write32 CS3BCR_A, CS3BCR_D - - write32 CS3WCR_A, CS3WCR_D - - write32 SDCR_A, SDCR_D - - write32 RTCOR_A, RTCOR_D - - write32 RTCSR_A, RTCSR_D - - /* wait 200us */ - mov.l REPEAT_D, r3 - mov #0, r2 -repeat0: - add #1, r2 - cmp/hs r3, r2 - bf repeat0 - nop - - mov.l SDRAM_MODE, r1 - mov #0, r0 - mov.l r0, @r1 - - nop - rts - - .align 4 - -CCR1_A: .long CCR1 -CCR1_D: .long 0x0000090B -PCCRL4_A: .long 0xFFFE3910 -PCCRL4_D0: .word 0x0000 -.align 2 -PECRL4_A: .long 0xFFFE3A10 -PECRL4_D0: .word 0x0000 -.align 2 -PECRL3_A: .long 0xFFFE3A12 -PECRL3_D: .word 0x0000 -.align 2 -PEIORL_A: .long 0xFFFE3A06 -PEIORL_D0: .word 0x1C00 -PEIORL_D1: .word 0x1C02 -PCIORL_A: .long 0xFFFE3906 -PCIORL_D: .word 0x4000 -.align 2 -PFCRH2_A: .long 0xFFFE3A8C -PFCRH2_D: .word 0x0000 -.align 2 -PFCRH3_A: .long 0xFFFE3A8A -PFCRH3_D: .word 0x0000 -.align 2 -PFCRH1_A: .long 0xFFFE3A8E -PFCRH1_D: .word 0x0000 -.align 2 -PFIORH_A: .long 0xFFFE3A84 -PFIORH_D: .word 0x0729 -.align 2 -PECRL1_A: .long 0xFFFE3A16 -PECRL1_D0: .word 0x0033 -.align 2 - - -WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .word 0xA518 -WTCSR_D1: .word 0xA51D -WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .word 0x5A84 -.align 2 -FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .word 0x0104 -.align 2 - -PCCRL4_D1: .word 0x0010 -PECRL1_D1: .word 0x0133 - -CMNCR_A: .long 0xFFFC0000 -CMNCR_D: .long 0x00001810 -CS0BCR_A: .long 0xFFFC0004 -CS0BCR_D: .long 0x10000400 -CS0WCR_A: .long 0xFFFC0028 -CS0WCR_D: .long 0x00000B41 -PECRL4_D1: .word 0x0100 -.align 2 -CS1WCR_A: .long 0xFFFC002C -CS1WCR_D: .long 0x00000B01 -PCCRL4_D2: .word 0x0011 -.align 2 -PCCRL3_A: .long 0xFFFE3912 -PCCRL3_D: .word 0x0011 -.align 2 -PCCRL2_A: .long 0xFFFE3914 -PCCRL2_D: .word 0x1111 -.align 2 -PCCRL1_A: .long 0xFFFE3916 -PCCRL1_D: .word 0x1010 -.align 2 -PDCRL4_A: .long 0xFFFE3990 -PDCRL4_D: .word 0x0011 -.align 2 -PDCRL3_A: .long 0xFFFE3992 -PDCRL3_D: .word 0x00011 -.align 2 -PDCRL2_A: .long 0xFFFE3994 -PDCRL2_D: .word 0x1111 -.align 2 -PDCRL1_A: .long 0xFFFE3996 -PDCRL1_D: .word 0x1000 -.align 2 -CS3BCR_A: .long 0xFFFC0010 -CS3BCR_D: .long 0x00004400 -CS3WCR_A: .long 0xFFFC0034 -CS3WCR_D: .long 0x00002892 -SDCR_A: .long 0xFFFC004C -SDCR_D: .long 0x00000809 -RTCOR_A: .long 0xFFFC0058 -RTCOR_D: .long 0xA55A0041 -RTCSR_A: .long 0xFFFC0050 -RTCSR_D: .long 0xa55a0010 - -SDRAM_MODE: .long 0xFFFC5040 -REPEAT_D: .long 0x00009C40 diff --git a/board/renesas/rsk7203/rsk7203.c b/board/renesas/rsk7203/rsk7203.c deleted file mode 100644 index 780c1866be..0000000000 --- a/board/renesas/rsk7203/rsk7203.c +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * u-boot/board/rsk7203/rsk7203.c - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -int checkboard(void) -{ - puts("BOARD: Renesas Technology RSK7203\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -/* - * The RSK board has the SMSC9118 wired up 'incorrectly'. - * Byte-swapping is necessary, and so poor performance is inevitable. - * This problem cannot evade by the swap function of CHIP, this can - * evade by software Byte-swapping. - * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push - * functions necessary to solve this problem. - */ -u32 pkt_data_pull(struct eth_device *dev, u32 addr) -{ - volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); - return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ - | swab16(*(addr_16 + 1)); -} - -void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) -{ - addr += dev->iobase; - *(volatile u16 *)(addr + 2) = swab16((u16)val); - *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/renesas/rsk7264/Kconfig b/board/renesas/rsk7264/Kconfig deleted file mode 100644 index 755d2896fb..0000000000 --- a/board/renesas/rsk7264/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_RSK7264 - -config SYS_BOARD - default "rsk7264" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "rsk7264" - -endif diff --git a/board/renesas/rsk7264/MAINTAINERS b/board/renesas/rsk7264/MAINTAINERS deleted file mode 100644 index f6202b70d9..0000000000 --- a/board/renesas/rsk7264/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -RSK7264 BOARD -M: Phil Edworthy <phil.edworthy@renesas.com> -S: Maintained -F: board/renesas/rsk7264/ -F: include/configs/rsk7264.h -F: configs/rsk7264_defconfig diff --git a/board/renesas/rsk7264/Makefile b/board/renesas/rsk7264/Makefile deleted file mode 100644 index 4efcf5cba9..0000000000 --- a/board/renesas/rsk7264/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Renesas Electronics Europe Ltd. -# - -obj-y := rsk7264.o -extra-y += lowlevel_init.o diff --git a/board/renesas/rsk7264/lowlevel_init.S b/board/renesas/rsk7264/lowlevel_init.S deleted file mode 100644 index 75c251b716..0000000000 --- a/board/renesas/rsk7264/lowlevel_init.S +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Renesas Electronics Europe Ltd. - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * Based on board/renesas/rsk7203/lowlevel_init.S - */ -#include <config.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* Cache setting */ - write32 CCR1_A ,CCR1_D - - /* io_set_cpg */ - write8 STBCR3_A, STBCR3_D - write8 STBCR4_A, STBCR4_D - write8 STBCR5_A, STBCR5_D - write8 STBCR6_A, STBCR6_D - write8 STBCR7_A, STBCR7_D - write8 STBCR8_A, STBCR8_D - - /* ConfigurePortPins */ - - /* Leaving LED1 ON for sanity test */ - write16 PJCR1_A, PJCR1_D1 - write16 PJCR2_A, PJCR2_D - write16 PJIOR0_A, PJIOR0_D1 - write16 PJDR0_A, PJDR0_D - write16 PJPR0_A, PJPR0_D - - /* Configure EN_PIN & RS_PIN */ - write16 PGCR2_A, PGCR2_D - write16 PGIOR0_A, PGIOR0_D - - /* Configure the port pins connected to UART */ - write16 PJCR1_A, PJCR1_D2 - write16 PJIOR0_A, PJIOR0_D2 - - /* Configure Operating Frequency */ - write16 WTCSR_A, WTCSR_D0 - write16 WTCSR_A, WTCSR_D1 - write16 WTCNT_A, WTCNT_D - - /* Control of RESBANK */ - write16 IBNR_A, IBNR_D - /* Enable SCIF3 module */ - write16 STBCR4_A, STBCR4_D - - /* Set clock mode*/ - write16 FRQCR_A, FRQCR_D - - /* Configure Bus And Memory */ -init_bsc_cs0: - -pfc_settings: - write16 PCCR2_A, PCCR2_D - write16 PCCR1_A, PCCR1_D - write16 PCCR0_A, PCCR0_D - - write16 PBCR0_A, PBCR0_D - write16 PBCR1_A, PBCR1_D - write16 PBCR2_A, PBCR2_D - write16 PBCR3_A, PBCR3_D - write16 PBCR4_A, PBCR4_D - write16 PBCR5_A, PBCR5_D - - write16 PDCR0_A, PDCR0_D - write16 PDCR1_A, PDCR1_D - write16 PDCR2_A, PDCR2_D - write16 PDCR3_A, PDCR3_D - - write32 CS0WCR_A, CS0WCR_D - write32 CS0BCR_A, CS0BCR_D - -init_bsc_cs2: - write16 PJCR0_A, PJCR0_D - write32 CS2WCR_A, CS2WCR_D - -init_sdram: - write32 CS3BCR_A, CS3BCR_D - write32 CS3WCR_A, CS3WCR_D - write32 SDCR_A, SDCR_D - write32 RTCOR_A, RTCOR_D - write32 RTCSR_A, RTCSR_D - - /* wait 200us */ - mov.l REPEAT_D, r3 - mov #0, r2 -repeat0: - add #1, r2 - cmp/hs r3, r2 - bf repeat0 - nop - - mov.l SDRAM_MODE, r1 - mov #0, r0 - mov.l r0, @r1 - - nop - rts - - .align 4 - -CCR1_A: .long CCR1 -CCR1_D: .long 0x0000090B -FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .word 0x1003 -.align 2 -STBCR3_A: .long 0xFFFE0408 -STBCR3_D: .long 0x00000002 -STBCR4_A: .long 0xFFFE040C -STBCR4_D: .word 0x0000 -.align 2 -STBCR5_A: .long 0xFFFE0410 -STBCR5_D: .long 0x00000010 -STBCR6_A: .long 0xFFFE0414 -STBCR6_D: .long 0x00000002 -STBCR7_A: .long 0xFFFE0418 -STBCR7_D: .long 0x0000002A -STBCR8_A: .long 0xFFFE041C -STBCR8_D: .long 0x0000007E -PJCR1_A: .long 0xFFFE390C -PJCR1_D1: .word 0x0000 -PJCR1_D2: .word 0x0022 -PJCR2_A: .long 0xFFFE390A -PJCR2_D: .word 0x0000 -.align 2 -PJIOR0_A: .long 0xFFFE3912 -PJIOR0_D1: .word 0x0FC0 -PJIOR0_D2: .word 0x0FE0 -PJDR0_A: .long 0xFFFE3916 -PJDR0_D: .word 0x0FBF -.align 2 -PJPR0_A: .long 0xFFFE391A -PJPR0_D: .long 0x00000FBF -PGCR2_A: .long 0xFFFE38CA -PGCR2_D: .word 0x0000 -.align 2 -PGIOR0_A: .long 0xFFFE38D2 -PGIOR0_D: .word 0x03F0 -.align 2 -WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .word 0x0000 -WTCSR_D1: .word 0x0000 -WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .word 0x0000 -.align 2 -PCCR0_A: .long 0xFFFE384E -PDCR0_A: .long 0xFFFE386E -PDCR1_A: .long 0xFFFE386C -PDCR2_A: .long 0xFFFE386A -PDCR3_A: .long 0xFFFE3868 -PBCR0_A: .long 0xFFFE382E -PBCR1_A: .long 0xFFFE382C -PBCR2_A: .long 0xFFFE382A -PBCR3_A: .long 0xFFFE3828 -PBCR4_A: .long 0xFFFE3826 -PBCR5_A: .long 0xFFFE3824 -PCCR0_D: .word 0x1111 -PDCR0_D: .word 0x1111 -PDCR1_D: .word 0x1111 -PDCR2_D: .word 0x1111 -PDCR3_D: .word 0x1111 -PBCR0_D: .word 0x1110 -PBCR1_D: .word 0x1111 -PBCR2_D: .word 0x1111 -PBCR3_D: .word 0x1111 -PBCR4_D: .word 0x1111 -PBCR5_D: .word 0x0111 -.align 2 -CS0WCR_A: .long 0xFFFC0028 -CS0WCR_D: .long 0x00000B41 -CS0BCR_A: .long 0xFFFC0004 -CS0BCR_D: .long 0x10000400 -PJCR0_A: .long 0xFFFE390E -PJCR0_D: .word 0x3300 -.align 2 -CS2WCR_A: .long 0xFFFC0030 -CS2WCR_D: .long 0x00000B01 -PCCR2_A: .long 0xFFFE384A -PCCR2_D: .word 0x0001 -.align 2 -PCCR1_A: .long 0xFFFE384C -PCCR1_D: .word 0x1111 -.align 2 -CS3BCR_A: .long 0xFFFC0010 -CS3BCR_D: .long 0x00004400 -CS3WCR_A: .long 0xFFFC0034 -CS3WCR_D: .long 0x0000288A -SDCR_A: .long 0xFFFC004C -SDCR_D: .long 0x00000812 -RTCOR_A: .long 0xFFFC0058 -RTCOR_D: .long 0xA55A0046 -RTCSR_A: .long 0xFFFC0050 -RTCSR_D: .long 0xA55A0010 -IBNR_A: .long 0xFFFE080E -IBNR_D: .word 0x0000 -.align 2 -SDRAM_MODE: .long 0xFFFC5040 -REPEAT_D: .long 0x00000085 diff --git a/board/renesas/rsk7264/rsk7264.c b/board/renesas/rsk7264/rsk7264.c deleted file mode 100644 index 8f3b157bf7..0000000000 --- a/board/renesas/rsk7264/rsk7264.c +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 Renesas Electronics Europe Ltd. - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * Based on u-boot/board/rsk7264/rsk7203.c - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -int checkboard(void) -{ - puts("BOARD: Renesas Technology RSK7264\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -/* - * The RSK board has the SMSC89218 wired up 'incorrectly'. - * Byte-swapping is necessary, and so poor performance is inevitable. - * This problem cannot evade by the swap function of CHIP, this can - * evade by software Byte-swapping. - * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push - * functions necessary to solve this problem. - */ -u32 pkt_data_pull(struct eth_device *dev, u32 addr) -{ - volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); - return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ - | swab16(*(addr_16 + 1)); -} - -void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) -{ - addr += dev->iobase; - *(volatile u16 *)(addr + 2) = swab16((u16)val); - *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/renesas/rsk7269/Kconfig b/board/renesas/rsk7269/Kconfig deleted file mode 100644 index ab5cd0e38f..0000000000 --- a/board/renesas/rsk7269/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_RSK7269 - -config SYS_BOARD - default "rsk7269" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "rsk7269" - -endif diff --git a/board/renesas/rsk7269/MAINTAINERS b/board/renesas/rsk7269/MAINTAINERS deleted file mode 100644 index 698fbdb1df..0000000000 --- a/board/renesas/rsk7269/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -RSK7269 BOARD -#M: - -S: Maintained -F: board/renesas/rsk7269/ -F: include/configs/rsk7269.h -F: configs/rsk7269_defconfig diff --git a/board/renesas/rsk7269/Makefile b/board/renesas/rsk7269/Makefile deleted file mode 100644 index c4371f99fb..0000000000 --- a/board/renesas/rsk7269/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2012 Renesas Electronics Europe Ltd. -# Copyright (C) 2012 Phil Edworthy -# - -obj-y := rsk7269.o -extra-y += lowlevel_init.o diff --git a/board/renesas/rsk7269/lowlevel_init.S b/board/renesas/rsk7269/lowlevel_init.S deleted file mode 100644 index b7ce60b46d..0000000000 --- a/board/renesas/rsk7269/lowlevel_init.S +++ /dev/null @@ -1,179 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Renesas Electronics Europe Ltd. - * Copyright (C) 2012 Phil Edworthy - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * Based on board/renesas/rsk7264/lowlevel_init.S - */ -#include <config.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* Flush and enable caches (data cache in write-through mode) */ - write32 CCR1_A ,CCR1_D - - /* Disable WDT */ - write16 WTCSR_A, WTCSR_D - write16 WTCNT_A, WTCNT_D - - /* Disable Register Bank interrupts */ - write16 IBNR_A, IBNR_D - - /* Set clocks based on 13.225MHz xtal */ - write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */ - - /* Enable all peripherals */ - write8 STBCR3_A, STBCR3_D - write8 STBCR4_A, STBCR4_D - write8 STBCR5_A, STBCR5_D - write8 STBCR6_A, STBCR6_D - write8 STBCR7_A, STBCR7_D - write8 STBCR8_A, STBCR8_D - write8 STBCR9_A, STBCR9_D - write8 STBCR10_A, STBCR10_D - - /* SCIF7 and IIC2 */ - write16 PJCR3_A, PJCR3_D /* TXD7 */ - write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */ - - /* Configure bus (CS0) */ - write16 PFCR3_A, PFCR3_D /* A24 */ - write16 PFCR2_A, PFCR2_D /* A23 and CS1# */ - write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */ - write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */ - write32 CS0WCR_A, CS0WCR_D - write32 CS0BCR_A, CS0BCR_D - - /* Configure SDRAM (CS3) */ - write16 PCCR2_A, PCCR2_D /* CS3# */ - write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */ - write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */ - write32 CS3BCR_A, CS3BCR_D - write32 CS3WCR_A, CS3WCR_D - write32 SDCR_A, SDCR_D - write32 RTCOR_A, RTCOR_D - write32 RTCSR_A, RTCSR_D - - /* Configure ethernet (CS1) */ - write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */ - write16 PHCR0_A, PHCR0_D - write16 PFCR2_A, PFCR2_D /* CS1# */ - write32 CS1BCR_A, CS1BCR_D /* Big endian */ - write32 CS1WCR_A, CS1WCR_D /* 1 cycle */ - write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */ - write16 PJIOR1_A, PJIOR1_D - - /* wait 200us */ - mov.l REPEAT_D, r3 - mov #0, r2 -repeat0: - add #1, r2 - cmp/hs r3, r2 - bf repeat0 - nop - - mov.l SDRAM_MODE, r1 - mov #0, r0 - mov.l r0, @r1 - - nop - rts - - .align 4 - -CCR1_A: .long CCR1 -CCR1_D: .long 0x0000090B - -STBCR3_A: .long 0xFFFE0408 -STBCR4_A: .long 0xFFFE040C -STBCR5_A: .long 0xFFFE0410 -STBCR6_A: .long 0xFFFE0414 -STBCR7_A: .long 0xFFFE0418 -STBCR8_A: .long 0xFFFE041C -STBCR9_A: .long 0xFFFE0440 -STBCR10_A: .long 0xFFFE0444 -STBCR3_D: .long 0x0000001A -STBCR4_D: .long 0x00000000 -STBCR5_D: .long 0x00000000 -STBCR6_D: .long 0x00000000 -STBCR7_D: .long 0x00000012 -STBCR8_D: .long 0x00000009 -STBCR9_D: .long 0x00000000 -STBCR10_D: .long 0x00000010 - -WTCSR_A: .long 0xFFFE0000 -WTCNT_A: .long 0xFFFE0002 -WTCSR_D: .word 0xA518 -WTCNT_D: .word 0x5A00 - -IBNR_A: .long 0xFFFE080E -IBNR_D: .word 0x0000 -.align 2 -FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .word 0x0015 -.align 2 - -PJCR3_A: .long 0xFFFE3908 -PJCR3_D: .word 0x5000 -.align 2 -PECR1_A: .long 0xFFFE388C -PECR1_D: .word 0x2011 -.align 2 - -PFCR3_A: .long 0xFFFE38A8 -PFCR2_A: .long 0xFFFE38AA -PBCR5_A: .long 0xFFFE3824 -PFCR3_D: .word 0x0010 -PFCR2_D: .word 0x0101 -PBCR5_D: .word 0x0111 -.align 2 -CS0WCR_A: .long 0xFFFC0028 -CS0WCR_D: .long 0x00000341 -CS0BCR_A: .long 0xFFFC0004 -CS0BCR_D: .long 0x00000400 - -PCCR2_A: .long 0xFFFE384A -PCCR1_A: .long 0xFFFE384C -PCCR0_A: .long 0xFFFE384E -PCCR2_D: .word 0x0001 -PCCR1_D: .word 0x1111 -PCCR0_D: .word 0x1111 -.align 2 -CS3BCR_A: .long 0xFFFC0010 -CS3BCR_D: .long 0x00004400 -CS3WCR_A: .long 0xFFFC0034 -CS3WCR_D: .long 0x00004912 -SDCR_A: .long 0xFFFC004C -SDCR_D: .long 0x00000811 -RTCOR_A: .long 0xFFFC0058 -RTCOR_D: .long 0xA55A0035 -RTCSR_A: .long 0xFFFC0050 -RTCSR_D: .long 0xA55A0010 -.align 2 -SDRAM_MODE: .long 0xFFFC5460 -REPEAT_D: .long 0x000033F1 - -PHCR1_A: .long 0xFFFE38EC -PHCR0_A: .long 0xFFFE38EE -PHCR1_D: .word 0x2222 -PHCR0_D: .word 0x2222 -.align 2 -CS1BCR_A: .long 0xFFFC0008 -CS1BCR_D: .long 0x00000400 -CS1WCR_A: .long 0xFFFC002C -CS1WCR_D: .long 0x00000080 -PJDR1_A: .long 0xFFFE3914 -PJDR1_D: .word 0x0000 -.align 2 -PJIOR1_A: .long 0xFFFE3910 -PJIOR1_D: .word 0x8000 -.align 2 diff --git a/board/renesas/rsk7269/rsk7269.c b/board/renesas/rsk7269/rsk7269.c deleted file mode 100644 index 223234eb24..0000000000 --- a/board/renesas/rsk7269/rsk7269.c +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Renesas Electronics Europe Ltd. - * Copyright (C) 2012 Phil Edworthy - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * Based on u-boot/board/rsk7264/rsk7264.c - */ - -#include <common.h> -#include <net.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/processor.h> - -int checkboard(void) -{ - puts("BOARD: Renesas RSK7269\n"); - return 0; -} - -int board_init(void) -{ - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -/* - * The RSK board has the SMSC89218 wired up 'incorrectly'. - * Byte-swapping is necessary, and so poor performance is inevitable. - * This problem cannot evade by the swap function of CHIP, this can - * evade by software Byte-swapping. - * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push - * functions necessary to solve this problem. - */ -u32 pkt_data_pull(struct eth_device *dev, u32 addr) -{ - volatile u16 *addr_16 = (u16 *)(dev->iobase + addr); - return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ - | swab16(*(addr_16 + 1)); -} - -void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) -{ - addr += dev->iobase; - *(volatile u16 *)(addr + 2) = swab16((u16)val); - *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/shmin/Kconfig b/board/shmin/Kconfig deleted file mode 100644 index 467580c67b..0000000000 --- a/board/shmin/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_SHMIN - -config SYS_BOARD - default "shmin" - -config SYS_CONFIG_NAME - default "shmin" - -endif diff --git a/board/shmin/MAINTAINERS b/board/shmin/MAINTAINERS deleted file mode 100644 index 5dee37bdf7..0000000000 --- a/board/shmin/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -SHMIN BOARD -M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> -M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -S: Maintained -F: board/shmin/ -F: include/configs/shmin.h -F: configs/shmin_defconfig diff --git a/board/shmin/Makefile b/board/shmin/Makefile deleted file mode 100644 index 697fc20fa4..0000000000 --- a/board/shmin/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2010 Nobuhiro Iwamatsu -# Copyright (C) 2008 Renesas Solutions Corp. -# -# u-boot/board/shmin/Makefile -# - -obj-y := shmin.o -extra-y += lowlevel_init.o diff --git a/board/shmin/lowlevel_init.S b/board/shmin/lowlevel_init.S deleted file mode 100644 index e4b6ae0b13..0000000000 --- a/board/shmin/lowlevel_init.S +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008, 2010 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - */ - -#include <config.h> - -#include <asm/processor.h> -#include <asm/macro.h> - - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - /* Use setting of original bootloader */ - rts - nop - .align 2 diff --git a/board/shmin/shmin.c b/board/shmin/shmin.c deleted file mode 100644 index 91918e9383..0000000000 --- a/board/shmin/shmin.c +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007 - 2010 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * - * board/shmin/shmin.c - * - * Copy board_flash_get_legacy() from board/freescale/m54455evb/m54455evb.c - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <netdev.h> - -int checkboard(void) -{ - puts("BOARD: T-SH7706LAN "); - if(readb(0xb0008006) == 0xab) - puts("v2\n"); - else - puts("v1\n"); - return 0; -} - -int board_init(void) -{ - writew(0x2980, BCR2); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return ne2k_register(); -} - -void led_set_state(unsigned short value) -{ - -} - -#if defined(CONFIG_FLASH_CFI_LEGACY) -#include <flash.h> -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - int sect[] = CONFIG_SYS_ATMEL_SECT; - int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ; - int i, j, k; - - if (base != CONFIG_SYS_ATMEL_BASE) - return 0; - - info->flash_id = 0x01000000; - info->portwidth = 1; - info->chipwidth = 1; - info->buffer_size = 1; - info->erase_blk_tout = 16384; - info->write_tout = 2; - info->buffer_write_tout = 5; - info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */ - info->cmd_reset = 0x00F0; - info->interface = FLASH_CFI_X8; - info->legacy_unlock = 0; - info->manufacturer_id = (u16) ATM_MANUFACT; - info->device_id = ATM_ID_LV040; - info->device_id2 = 0; - info->ext_addr = 0; - info->cfi_version = 0x3133; - info->cfi_offset = 0x0000; - info->addr_unlock1 = 0x00000555; - info->addr_unlock2 = 0x000002AA; - info->name = "CFI conformant"; - info->size = 0; - info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT; - info->start[0] = base; - - for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) { - info->size += sect[i] * sectsz[i]; - for (j = 0; j < sect[i]; j++, k++) { - info->start[k + 1] = info->start[k] + sectsz[i]; - info->protect[k] = 0; - } - } - - return 1; -} -#endif /* CONFIG_FLASH_CFI_LEGACY */ |