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-rw-r--r--board/mpl/vcma9/vcma9.c13
-rw-r--r--board/mpl/vcma9/vcma9.h20
-rw-r--r--board/samsung/smdk2400/smdk2400.c5
-rw-r--r--board/samsung/smdk2410/smdk2410.c5
-rw-r--r--board/samsung/smdkc100/Makefile55
-rw-r--r--board/samsung/smdkc100/config.mk16
-rw-r--r--board/samsung/smdkc100/lowlevel_init.S215
-rw-r--r--board/samsung/smdkc100/mem_setup.S197
-rw-r--r--board/samsung/smdkc100/onenand.c83
-rw-r--r--board/samsung/smdkc100/smdkc100.c51
-rw-r--r--board/sbc2410x/sbc2410x.c7
-rw-r--r--board/trab/cmd_trab.c12
-rw-r--r--board/trab/rs485.c12
-rw-r--r--board/trab/trab.c17
-rw-r--r--board/trab/trab_fkt.c26
-rw-r--r--board/trab/tsc2000.c17
-rw-r--r--board/trab/tsc2000.h4
-rw-r--r--board/trab/vfd.c12
18 files changed, 695 insertions, 72 deletions
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
index 3216d6347d..ed4df17763 100644
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -73,8 +73,9 @@ static inline void delay(unsigned long loops)
int board_init(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
@@ -174,7 +175,7 @@ static inline void NF_Init(void)
void
nand_init(void)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
NF_Init();
#ifdef DEBUG
@@ -190,21 +191,21 @@ nand_init(void)
static u8 Get_PLD_ID(void)
{
- VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+ VCMA9_PLD * const pld = VCMA9_get_base_PLD();
return(pld->ID);
}
static u8 Get_PLD_BOARD(void)
{
- VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+ VCMA9_PLD * const pld = VCMA9_get_base_PLD();
return(pld->BOARD);
}
static u8 Get_PLD_SDRAM(void)
{
- VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+ VCMA9_PLD * const pld = VCMA9_get_base_PLD();
return(pld->SDRAM);
}
diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h
index 220b7053ba..f46e0e4c58 100644
--- a/board/mpl/vcma9/vcma9.h
+++ b/board/mpl/vcma9/vcma9.h
@@ -39,14 +39,14 @@ typedef enum {
static inline void NF_Conf(u16 conf)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
nand->NFCONF = conf;
}
static inline void NF_Cmd(u8 cmd)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
nand->NFCMD = cmd;
}
@@ -59,14 +59,14 @@ static inline void NF_CmdW(u8 cmd)
static inline void NF_Addr(u8 addr)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
nand->NFADDR = addr;
}
static inline void NF_SetCE(NFCE_STATE s)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
switch (s) {
case NFCE_LOW:
@@ -81,35 +81,35 @@ static inline void NF_SetCE(NFCE_STATE s)
static inline void NF_WaitRB(void)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
while (!(nand->NFSTAT & (1<<0)));
}
static inline void NF_Write(u8 data)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
nand->NFDATA = data;
}
static inline u8 NF_Read(void)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
return(nand->NFDATA);
}
static inline void NF_Init_ECC(void)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
nand->NFCONF |= (1<<12);
}
static inline u32 NF_Read_ECC(void)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
return(nand->NFECC);
}
@@ -128,7 +128,7 @@ typedef struct {
} /*__attribute__((__packed__))*/ VCMA9_PLD;
#define VCMA9_PLD_BASE 0x2C000100
-static inline VCMA9_PLD * VCMA9_GetBase_PLD(void)
+static inline VCMA9_PLD *VCMA9_get_base_PLD(void)
{
return (VCMA9_PLD * const)VCMA9_PLD_BASE;
}
diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c
index 2c47063e95..42bf00868d 100644
--- a/board/samsung/smdk2400/smdk2400.c
+++ b/board/samsung/smdk2400/smdk2400.c
@@ -46,8 +46,9 @@ extern int do_mdm_init; /* defined in common/main.c */
int board_init (void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* memory and cpu-speed are setup before relocation */
/* change the clock to be 50 MHz 1:1:1 */
diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c
index 25c38e67e9..fde7730930 100644
--- a/board/samsung/smdk2410/smdk2410.c
+++ b/board/samsung/smdk2410/smdk2410.c
@@ -68,8 +68,9 @@ static inline void delay (unsigned long loops)
int board_init (void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
diff --git a/board/samsung/smdkc100/Makefile b/board/samsung/smdkc100/Makefile
new file mode 100644
index 0000000000..808d0dd0c6
--- /dev/null
+++ b/board/samsung/smdkc100/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := smdkc100.o
+COBJS-$(CONFIG_SAMSUNG_ONENAND) += onenand.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(SOBJS) $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/samsung/smdkc100/config.mk b/board/samsung/smdkc100/config.mk
new file mode 100644
index 0000000000..ebab420815
--- /dev/null
+++ b/board/samsung/smdkc100/config.mk
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2008 # Samsung Elecgtronics
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+
+# On S5PC100 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x38000000 to 0x40000000 (128MiB)
+#
+# On S5PC110 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x40000000 to 0x48000000 (128MiB)
+#
+TEXT_BASE = 0x34800000
diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S
new file mode 100644
index 0000000000..32572c51da
--- /dev/null
+++ b/board/samsung/smdkc100/lowlevel_init.S
@@ -0,0 +1,215 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ */
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+ .globl lowlevel_init
+lowlevel_init:
+ mov r9, lr
+
+ /* r5 has always zero */
+ mov r5, #0
+
+ ldr r8, =S5PC100_GPIO_BASE
+
+ /* Disable Watchdog */
+ ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
+ orr r0, r0, #0x0
+ str r5, [r0]
+
+#ifndef CONFIG_ONENAND_IPL
+ /* setting SRAM */
+ ldr r0, =S5PC100_SROMC_BASE
+ ldr r1, =0x9
+ str r1, [r0]
+#endif
+
+ /* S5PC100 has 3 groups of interrupt sources */
+ ldr r0, =S5PC100_VIC0_BASE @0xE4000000
+ ldr r1, =S5PC100_VIC1_BASE @0xE4000000
+ ldr r2, =S5PC100_VIC2_BASE @0xE4000000
+
+ /* Disable all interrupts (VIC0, VIC1 and VIC2) */
+ mvn r3, #0x0
+ str r3, [r0, #0x14] @INTENCLEAR
+ str r3, [r1, #0x14] @INTENCLEAR
+ str r3, [r2, #0x14] @INTENCLEAR
+
+#ifndef CONFIG_ONENAND_IPL
+ /* Set all interrupts as IRQ */
+ str r5, [r0, #0xc] @INTSELECT
+ str r5, [r1, #0xc] @INTSELECT
+ str r5, [r2, #0xc] @INTSELECT
+
+ /* Pending Interrupt Clear */
+ str r5, [r0, #0xf00] @INTADDRESS
+ str r5, [r1, #0xf00] @INTADDRESS
+ str r5, [r2, #0xf00] @INTADDRESS
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+ /* for UART */
+ bl uart_asm_init
+
+ /* for TZPC */
+ bl tzpc_asm_init
+#endif
+
+#ifdef CONFIG_ONENAND_IPL
+ /* init system clock */
+ bl system_clock_init
+
+ bl mem_ctrl_asm_init
+
+ /* Wakeup support. Don't know if it's going to be used, untested. */
+ ldr r0, =S5PC100_RST_STAT
+ ldr r1, [r0]
+ bic r1, r1, #0xfffffff7
+ cmp r1, #0x8
+ beq wakeup_reset
+#endif
+
+1:
+ mov lr, r9
+ mov pc, lr
+
+#ifdef CONFIG_ONENAND_IPL
+wakeup_reset:
+
+ /* Clear wakeup status register */
+ ldr r0, =S5PC100_WAKEUP_STAT
+ ldr r1, [r0]
+ str r1, [r0]
+
+ /* Load return address and jump to kernel */
+ ldr r0, =S5PC100_INFORM0
+
+ /* r1 = physical address of s5pc100_cpu_resume function */
+ ldr r1, [r0]
+
+ /* Jump to kernel (sleep.S) */
+ mov pc, r1
+ nop
+ nop
+#endif
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+ ldr r8, =S5PC1XX_CLOCK_BASE @ 0xE0100000
+
+ /* Set Clock divider */
+ ldr r1, =0x00011110
+ str r1, [r8, #0x304]
+ ldr r1, =0x1
+ str r1, [r8, #0x308]
+ ldr r1, =0x00011301
+ str r1, [r8, #0x300]
+
+ /* Set Lock Time */
+ ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
+ str r1, [r8, #0x000] @ APLL_LOCK
+ str r1, [r8, #0x004] @ MPLL_LOCK
+ str r1, [r8, #0x008] @ EPLL_LOCK
+ str r1, [r8, #0x00C] @ HPLL_LOCK
+
+ /* APLL_CON */
+ ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
+ str r1, [r8, #0x100]
+ /* MPLL_CON */
+ ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
+ str r1, [r8, #0x104]
+ /* EPLL_CON */
+ ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
+ str r1, [r8, #0x108]
+ /* HPLL_CON */
+ ldr r1, =0x80600603
+ str r1, [r8, #0x10C]
+
+ /* Set Source Clock */
+ ldr r1, =0x1111 @ A, M, E, HPLL Muxing
+ str r1, [r8, #0x200] @ CLK_SRC0
+
+ ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
+ str r1, [r8, #0x204] @ CLK_SRC1
+
+ ldr r1, =0x9000 @ ARMCLK/4
+ str r1, [r8, #0x400] @ CLK_OUT
+
+ /* wait at least 200us to stablize all clock */
+ mov r2, #0x10000
+1: subs r2, r2, #1
+ bne 1b
+
+ mov pc, lr
+
+#ifndef CONFIG_ONENAND_IPL
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+ mov r0, r8
+ ldr r1, =0x22222222
+ str r1, [r0, #0x0] @ GPA0_CON
+ ldr r1, =0x00022222
+ str r1, [r0, #0x20] @ GPA1_CON
+
+ mov pc, lr
+
+/*
+ * tzpc_asm_init: Initialize TZPC
+ */
+tzpc_asm_init:
+ ldr r0, =0xE3800000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x804]
+ str r1, [r0, #0x810]
+
+ ldr r0, =0xE2800000
+ str r1, [r0, #0x804]
+ str r1, [r0, #0x810]
+ str r1, [r0, #0x81C]
+
+ ldr r0, =0xE2900000
+ str r1, [r0, #0x804]
+ str r1, [r0, #0x810]
+
+ mov pc, lr
+#endif
diff --git a/board/samsung/smdkc100/mem_setup.S b/board/samsung/smdkc100/mem_setup.S
new file mode 100644
index 0000000000..94a701d428
--- /dev/null
+++ b/board/samsung/smdkc100/mem_setup.S
@@ -0,0 +1,197 @@
+/*
+ * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
+ *
+ * Copyright (C) 2009 Samsung Electrnoics
+ * Inki Dae <inki.dae@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+ .globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+ ldr r6, =S5PC100_DMC_BASE @ 0xE6000000
+
+ /* DLL parameter setting */
+ ldr r1, =0x50101000
+ str r1, [r6, #0x018] @ PHYCONTROL0
+ ldr r1, =0xf4
+ str r1, [r6, #0x01C] @ PHYCONTROL1
+ ldr r1, =0x0
+ str r1, [r6, #0x020] @ PHYCONTROL2
+
+ /* DLL on */
+ ldr r1, =0x50101002
+ str r1, [r6, #0x018] @ PHYCONTROL0
+
+ /* DLL start */
+ ldr r1, =0x50101003
+ str r1, [r6, #0x018] @ PHYCONTROL0
+
+ /* Force value locking for DLL off */
+ str r1, [r6, #0x018] @ PHYCONTROL0
+
+ /* DLL off */
+ ldr r1, =0x50101001
+ str r1, [r6, #0x018] @ PHYCONTROL0
+
+ /* auto refresh off */
+ ldr r1, =0xff001010
+ str r1, [r6, #0x000] @ CONCONTROL
+
+ /*
+ * Burst Length 4, 2 chips, 32-bit, LPDDR
+ * OFF: dynamic self refresh, force precharge, dynamic power down off
+ */
+ ldr r1, =0x00212100
+ str r1, [r6, #0x004] @ MEMCONTROL
+
+ /*
+ * Note:
+ * If Bank0 has OneDRAM we place it at 0x2800'0000
+ * So finally Bank1 should address start at at 0x2000'0000
+ */
+ mov r4, #0x0
+
+swap_memory:
+ /*
+ * Bank0
+ * 0x30 -> 0x30000000
+ * 0xf8 -> 0x37FFFFFF
+ * [15:12] 0: Linear
+ * [11:8 ] 2: 9 bits
+ * [ 7:4 ] 2: 14 bits
+ * [ 3:0 ] 2: 4 banks
+ */
+ ldr r1, =0x30f80222
+ /* if r4 is 1, swap the bank */
+ cmp r4, #0x1
+ orreq r1, r1, #0x08000000
+ str r1, [r6, #0x008] @ MEMCONFIG0
+
+ /*
+ * Bank1
+ * 0x38 -> 0x38000000
+ * 0xf8 -> 0x3fFFFFFF
+ * [15:12] 0: Linear
+ * [11:8 ] 2: 9 bits
+ * [ 7:4 ] 2: 14 bits
+ * [ 3:0 ] 2: 4 banks
+ */
+ ldr r1, =0x38f80222
+ /* if r4 is 1, swap the bank */
+ cmp r4, #0x1
+ biceq r1, r1, #0x08000000
+ str r1, [r6, #0x00c] @ MEMCONFIG1
+
+ ldr r1, =0x20000000
+ str r1, [r6, #0x014] @ PRECHCONFIG
+
+ /*
+ * FIXME: Please verify these values
+ * 7.8us * 166MHz %LE %LONG1294(0x50E)
+ * 7.8us * 133MHz %LE %LONG1038(0x40E),
+ * 7.8us * 100MHz %LE %LONG780(0x30C),
+ * 7.8us * 20MHz %LE %LONG156(0x9C),
+ * 7.8us * 10MHz %LE %LONG78(0x4E)
+ */
+ ldr r1, =0x0000050e
+ str r1, [r6, #0x030] @ TIMINGAREF
+
+ /* 166 MHz */
+ ldr r1, =0x0c233287
+ str r1, [r6, #0x034] @ TIMINGROW
+
+ /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
+ ldr r1, =0x32330303
+ str r1, [r6, #0x038] @ TIMINGDATA
+
+ /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
+ ldr r1, =0x04141433
+ str r1, [r6, #0x03C] @ TIMINGPOWER
+
+ /* chip0 Deselect */
+ ldr r1, =0x07000000
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip0 PALL */
+ ldr r1, =0x01000000
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip0 REFA */
+ ldr r1, =0x05000000
+ str r1, [r6, #0x010] @ DIRECTCMD
+ /* chip0 REFA */
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+ ldr r1, =0x00000032
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip1 Deselect */
+ ldr r1, =0x07100000
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip1 PALL */
+ ldr r1, =0x01100000
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip1 REFA */
+ ldr r1, =0x05100000
+ str r1, [r6, #0x010] @ DIRECTCMD
+ /* chip1 REFA */
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+ ldr r1, =0x00100032
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* auto refresh on */
+ ldr r1, =0xff002030
+ str r1, [r6, #0x000] @ CONCONTROL
+
+ /* PwrdnConfig */
+ ldr r1, =0x00100002
+ str r1, [r6, #0x028] @ PWRDNCONFIG
+
+ /* BL%LE %LONG */
+ ldr r1, =0xff212100
+ str r1, [r6, #0x004] @ MEMCONTROL
+
+
+ /* Try to test memory area */
+ cmp r4, #0x1
+ beq 1f
+
+ mov r4, #0x1
+ ldr r1, =0x37ffff00
+ str r4, [r1]
+ str r4, [r1, #0x4] @ dummy write
+ ldr r0, [r1]
+ cmp r0, r4
+ bne swap_memory
+
+1:
+ mov pc, lr
+
+ .ltorg
diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c
new file mode 100644
index 0000000000..c25869e5c4
--- /dev/null
+++ b/board/samsung/smdkc100/onenand.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+
+#include <onenand_uboot.h>
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+ struct samsung_onenand *onenand;
+ int value;
+
+ this->base = (void *)S5PC100_ONENAND_BASE;
+ onenand = (struct samsung_onenand *)this->base;
+
+ /* D0 Domain memory clock gating */
+ value = readl(&clk->gate_d01);
+ value &= ~(1 << 2); /* CLK_ONENANDC */
+ value |= (1 << 2);
+ writel(value, &clk->gate_d01);
+
+ value = readl(&clk->src0);
+ value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */
+ value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */
+ writel(value, &clk->src0);
+
+ value = readl(&clk->div1);
+ value &= ~(3 << 16); /* PCLKD1_RATIO */
+ value |= (1 << 16);
+ writel(value, &clk->div1);
+
+ writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
+
+ while (!(readl(&onenand->int_err_stat) & RST_CMP))
+ continue;
+
+ writel(RST_CMP, &onenand->int_err_ack);
+
+ /*
+ * Access_Clock [2:0]
+ * 166 MHz, 134 Mhz : 3
+ * 100 Mhz, 60 Mhz : 2
+ */
+ writel(0x3, &onenand->acc_clock);
+
+ writel(INT_ERR_ALL, &onenand->int_err_mask);
+ writel(1 << 0, &onenand->int_pin_en); /* Enable */
+
+ value = readl(&onenand->int_err_mask);
+ value &= ~RDY_ACT;
+ writel(value, &onenand->int_err_mask);
+
+ s3c_onenand_init(mtd);
+}
diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
new file mode 100644
index 0000000000..15a1a27c36
--- /dev/null
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("Board:\tSMDKC100\n");
+ return 0;
+}
+#endif
diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c
index 62768503ad..7452c1f945 100644
--- a/board/sbc2410x/sbc2410x.c
+++ b/board/sbc2410x/sbc2410x.c
@@ -75,8 +75,9 @@ static inline void delay (unsigned long loops)
int board_init (void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
@@ -170,7 +171,7 @@ static inline void NF_Init(void)
void nand_init(void)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
NF_Init();
#ifdef DEBUG
diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c
index ae6f7c6af8..04a36075b8 100644
--- a/board/trab/cmd_trab.c
+++ b/board/trab/cmd_trab.c
@@ -644,9 +644,9 @@ static int adc_read (unsigned int channel)
{
int j = 1000; /* timeout value for wait loop in us */
int result;
- S3C2400_ADC *padc;
+ struct s3c2400_adc *padc;
- padc = S3C2400_GetBase_ADC();
+ padc = s3c2400_get_base_adc();
channel &= 0x7;
adc_init ();
@@ -686,9 +686,9 @@ static int adc_read (unsigned int channel)
static void adc_init (void)
{
- S3C2400_ADC *padc;
+ struct s3c2400_adc *padc;
- padc = S3C2400_GetBase_ADC();
+ padc = s3c2400_get_base_adc();
padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
@@ -707,7 +707,7 @@ static void adc_init (void)
static void led_set (unsigned int state)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
led_init ();
@@ -740,7 +740,7 @@ static void led_blink (void)
static void led_init (void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure GPA12 as output and set to High -> LED off */
gpio->PACON &= ~(1 << 12);
diff --git a/board/trab/rs485.c b/board/trab/rs485.c
index 97aea91c8e..7d5c0a2c9c 100644
--- a/board/trab/rs485.c
+++ b/board/trab/rs485.c
@@ -42,7 +42,7 @@ static void trab_rs485_disable_rx(void);
static void rs485_setbrg (void)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+ struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
int i;
unsigned int reg = 0;
@@ -67,7 +67,7 @@ static void rs485_setbrg (void)
static void rs485_cfgio (void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
gpio->PFCON &= ~(0x3 << 2);
gpio->PFCON |= (0x2 << 2); /* configure GPF1 as RXD1 */
@@ -101,7 +101,7 @@ int rs485_init (void)
*/
int rs485_getc (void)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+ struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
/* wait for character to arrive */
while (!(uart->UTRSTAT & 0x1));
@@ -114,7 +114,7 @@ int rs485_getc (void)
*/
void rs485_putc (const char c)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+ struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
/* wait for room in the tx FIFO */
while (!(uart->UTRSTAT & 0x2));
@@ -131,7 +131,7 @@ void rs485_putc (const char c)
*/
int rs485_tstc (void)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+ struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
return uart->UTRSTAT & 0x1;
}
@@ -168,7 +168,7 @@ static void set_rs485re(unsigned char rs485re_state)
static void set_rs485de(unsigned char rs485de_state)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* This is on PORT A bit 11 */
if(rs485de_state)
diff --git a/board/trab/trab.c b/board/trab/trab.c
index 2dccd87677..ea782a9137 100644
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -69,8 +69,9 @@ int board_init ()
#if defined(CONFIG_VFD)
extern int vfd_init_clocks(void);
#endif
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* memory and cpu-speed are setup before relocation */
#ifdef CONFIG_TRAB_50MHZ
@@ -338,22 +339,22 @@ static int key_pressed(void)
static inline void SET_CS_TOUCH(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
gpio->PDDAT &= 0x5FF;
}
static inline void CLR_CS_TOUCH(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
gpio->PDDAT |= 0x200;
}
static void spi_init(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
int i;
/* Configure I/O ports. */
@@ -377,7 +378,7 @@ static void spi_init(void)
static void wait_transmit_done(void)
{
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
}
@@ -385,7 +386,7 @@ static void wait_transmit_done(void)
static void tsc2000_write(unsigned int page, unsigned int reg,
unsigned int data)
{
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
unsigned int command;
SET_CS_TOUCH();
diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c
index 74cdbfcbf4..dc2a8d7750 100644
--- a/board/trab/trab_fkt.c
+++ b/board/trab/trab_fkt.c
@@ -406,9 +406,9 @@ static int adc_read (unsigned int channel)
{
int j = 1000; /* timeout value for wait loop in us */
int result;
- S3C2400_ADC *padc;
+ struct s3c2400_adc *padc;
- padc = S3C2400_GetBase_ADC();
+ padc = s3c2400_get_base_adc();
channel &= 0x7;
padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
@@ -446,9 +446,9 @@ static int adc_read (unsigned int channel)
static void adc_init (void)
{
- S3C2400_ADC *padc;
+ struct s3c2400_adc *padc;
- padc = S3C2400_GetBase_ADC();
+ padc = s3c2400_get_base_adc();
padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
@@ -490,7 +490,7 @@ int do_power_switch (void)
{
int result;
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure GPE7 as input */
gpio->PECON &= ~(0x3 << (2 * 7));
@@ -557,7 +557,7 @@ int do_vfd_id (void)
int i;
long int pcup_old, pccon_old;
int vfd_board_id;
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* try to red vfd board id from the value defined by pull-ups */
@@ -589,8 +589,8 @@ int do_buzzer (char **argv)
{
int counter;
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_timers * const timers = s3c24x0_get_base_timers();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* set prescaler for timer 2, 3 and 4 */
timers->TCFG0 &= ~0xFF00;
@@ -637,7 +637,7 @@ int do_buzzer (char **argv)
int do_led (char **argv)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure PC14 and PC15 as output */
gpio->PCCON &= ~(0xF << 28);
@@ -692,7 +692,7 @@ int do_led (char **argv)
int do_full_bridge (char **argv)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure PD5 and PD6 as output */
gpio->PDCON &= ~((0x3 << 5*2) | (0x3 << 6*2));
@@ -801,7 +801,7 @@ int do_motor_contact (void)
int do_motor (char **argv)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* Configure I/O port */
gpio->PGCON &= ~(0x3 << 0);
@@ -827,8 +827,8 @@ static void print_identifier (void)
int do_pwm (char **argv)
{
int counter;
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+ struct s3c24x0_timers * const timers = s3c24x0_get_base_timers();
if (strcmp (argv[2], "on") == 0) {
/* configure pin GPD8 as TOUT3 */
diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c
index 986b6fb079..fc501a8a4b 100644
--- a/board/trab/tsc2000.c
+++ b/board/trab/tsc2000.c
@@ -27,6 +27,7 @@
#include <common.h>
#include <s3c2400.h>
+#include <asm/io.h>
#include <div64.h>
#include "tsc2000.h"
@@ -44,8 +45,8 @@
void tsc2000_spi_init(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
int i;
/* Configure I/O ports. */
@@ -71,7 +72,7 @@ void tsc2000_spi_init(void)
void spi_wait_transmit_done(void)
{
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
}
@@ -79,7 +80,7 @@ void spi_wait_transmit_done(void)
void tsc2000_write(unsigned short reg, unsigned short data)
{
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
unsigned int command;
SET_CS_TOUCH();
@@ -100,7 +101,7 @@ void tsc2000_write(unsigned short reg, unsigned short data)
unsigned short tsc2000_read (unsigned short reg)
{
unsigned short command, data;
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
SET_CS_TOUCH();
command = 0x8000 | reg;
@@ -123,7 +124,7 @@ unsigned short tsc2000_read (unsigned short reg)
void tsc2000_set_mux (unsigned int channel)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
CLR_MUX1_ENABLE; CLR_MUX2_ENABLE;
CLR_MUX3_ENABLE; CLR_MUX4_ENABLE;
@@ -200,7 +201,7 @@ void tsc2000_set_mux (unsigned int channel)
void tsc2000_set_range (unsigned int range)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
switch (range) {
case 1:
@@ -306,7 +307,7 @@ s32 tsc2000_contact_temp (void)
void tsc2000_reg_init (void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
tsc2000_write(TSC2000_REG_ADC, 0x2036);
tsc2000_write(TSC2000_REG_REF, 0x0011);
diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h
index 50c09c295a..0b6253f656 100644
--- a/board/trab/tsc2000.h
+++ b/board/trab/tsc2000.h
@@ -128,7 +128,7 @@ void adc_wait_conversion_done(void);
static inline void SET_CS_TOUCH(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
gpio->PDDAT &= 0x5FF;
}
@@ -136,7 +136,7 @@ static inline void SET_CS_TOUCH(void)
static inline void CLR_CS_TOUCH(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
gpio->PDDAT |= 0x200;
}
diff --git a/board/trab/vfd.c b/board/trab/vfd.c
index e5ca4abe47..d5ad5bbdf5 100644
--- a/board/trab/vfd.c
+++ b/board/trab/vfd.c
@@ -358,9 +358,9 @@ int vfd_init_clocks (void)
{
int i;
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
- S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+ struct s3c24x0_timers * const timers = s3c24x0_get_base_timers();
+ struct s3c24x0_lcd * const lcd = s3c24x0_get_base_lcd();
/* try to determine display type from the value
* defined by pull-ups
@@ -429,8 +429,8 @@ int vfd_init_clocks (void)
*/
int drv_vfd_init(void)
{
- S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_lcd * const lcd = s3c24x0_get_base_lcd();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
char *tmp;
ulong palette;
static int vfd_init_done = 0;
@@ -529,7 +529,7 @@ int drv_vfd_init(void)
*/
void disable_vfd (void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
VFD_DISABLE;
gpio->PDCON &= ~0xC;
generated by cgit (git 2.34.1) at 2025-02-22 03:01:00 +0000