24 files changed, 409 insertions, 21 deletions

diff --git a/board/Marvell/db-88f6820-gp/Kconfig b/board/Marvell/db-88f6820-gp/Kconfig
new file mode 100644
index 0000000000..b2e911512b
--- /dev/null
+++ b/board/Marvell/db-88f6820-gp/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_DB_88F6820_GP
+
+config SYS_BOARD
+	default "db-88f6820-gp"
+
+config SYS_VENDOR
+	default "Marvell"
+
+config SYS_SOC
+	default "mvebu"
+
+config SYS_CONFIG_NAME
+	default "db-88f6820-gp"
+
+endif
diff --git a/board/Marvell/db-88f6820-gp/Makefile b/board/Marvell/db-88f6820-gp/Makefile
new file mode 100644
index 0000000000..58d40dd6cc
--- /dev/null
+++ b/board/Marvell/db-88f6820-gp/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= db-88f6820-gp.o
diff --git a/board/Marvell/db-88f6820-gp/binary.0 b/board/Marvell/db-88f6820-gp/binary.0
new file mode 100644
index 0000000000..57a4cbf330
--- /dev/null
+++ b/board/Marvell/db-88f6820-gp/binary.0
@@ -0,0 +1,16 @@
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
+
+In a few weeks, mainline U-Boot will get support to generate the
+bin_hdr with the DDR training code itself. By implementing this code
+as SPL U-Boot. Then this file will not be needed any more and will
+get removed.
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
new file mode 100644
index 0000000000..51ac495a44
--- /dev/null
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BIT(nr)				(1UL << (nr))
+
+#define ETH_PHY_CTRL_REG		0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT	11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2014_T3.0"
+ */
+#define DB_GP_88F68XX_GPP_OUT_ENA_LOW					\
+	(~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |	\
+	   BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |	\
+	   BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
+#define DB_GP_88F68XX_GPP_OUT_ENA_MID					\
+	(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |	\
+	   BIT(16) | BIT(17) | BIT(18)))
+
+#define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
+#define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x0
+#define DB_GP_88F68XX_GPP_POL_LOW	0x0
+#define DB_GP_88F68XX_GPP_POL_MID	0x0
+
+/* IO expander on Marvell GP board includes e.g. fan enabling */
+struct marvell_io_exp {
+	u8 chip;
+	u8 addr;
+	u8 val;
+};
+
+static struct marvell_io_exp io_exp[] = {
+	{ 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
+	{ 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
+	{ 0x20, 2, 0x1D }, /* Output Data, register#0 */
+	{ 0x20, 3, 0x18 }, /* Output Data, register#1 */
+	{ 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits  */
+	{ 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits  */
+	{ 0x21, 2, 0x08 }, /* Output Data, register#0 */
+	{ 0x21, 3, 0xC0 }  /* Output Data, register#1 */
+};
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+	writel(0x11244011, MVEBU_MPP_BASE + 0x08);
+	writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
+	writel(0x22200002, MVEBU_MPP_BASE + 0x10);
+	writel(0x30042022, MVEBU_MPP_BASE + 0x14);
+	writel(0x55550555, MVEBU_MPP_BASE + 0x18);
+	writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	int i;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/* Init I2C IO expanders */
+	for (i = 0; i < ARRAY_SIZE(io_exp); i++)
+		i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Marvell DB-88F6820-GP\n");
+
+	return 0;
+}
diff --git a/board/Marvell/db-88f6820-gp/kwbimage.cfg b/board/Marvell/db-88f6820-gp/kwbimage.cfg
new file mode 100644
index 0000000000..e81245420f
--- /dev/null
+++ b/board/Marvell/db-88f6820-gp/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/Marvell/db-88f6820-gp/binary.0 0000005b 00000068
diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig
index 98aa10ade0..d0b426e8d9 100644
--- a/board/Marvell/db-mv784mp-gp/Kconfig
+++ b/board/Marvell/db-mv784mp-gp/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
 	default "Marvell"
 
 config SYS_SOC
-	default "armada-xp"
+	default "mvebu"
 
 config SYS_CONFIG_NAME
 	default "db-mv784mp-gp"
diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
index b3dae8910d..00ca878873 100644
--- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
+++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
@@ -86,7 +86,8 @@ int checkboard(void)
 /* Configure and enable MV88E1545 PHY */
 void reset_phy(void)
 {
-	u16 devadr = CONFIG_PHY_BASE_ADDR;
+	u8 phy_addr[] = CONFIG_PHY_ADDR;
+	u16 devadr = phy_addr[0];
 	char *name = "neta0";
 	u16 reg;
 
diff --git a/board/coreboot/Kconfig b/board/coreboot/Kconfig
new file mode 100644
index 0000000000..dc9b70f65d
--- /dev/null
+++ b/board/coreboot/Kconfig
@@ -0,0 +1,26 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+if VENDOR_COREBOOT
+
+choice
+	prompt "Mainboard model"
+
+config TARGET_COREBOOT
+	bool "coreboot"
+	help
+	  This target is used for running U-Boot on top of coreboot. In
+	  this case coreboot does the early inititalisation, and U-Boot
+	  takes over once the RAM, video and CPU are fully running.
+	  U-Boot is loaded as a fallback payload from coreboot, in
+	  coreboot terminology. This method was used for the Chromebook
+	  Pixel when launched.
+
+endchoice
+
+source "board/coreboot/coreboot/Kconfig"
+
+endif
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
index 981de1f071..6a04158f16 100644
--- a/board/coreboot/coreboot/Kconfig
+++ b/board/coreboot/coreboot/Kconfig
@@ -9,6 +9,9 @@ config SYS_VENDOR
 config SYS_SOC
 	default "coreboot"
 
+config SYS_TEXT_BASE
+	default 0x01110000
+
 comment "coreboot-specific options"
 
 config SYS_CONFIG_NAME
diff --git a/board/google/Kconfig b/board/google/Kconfig
new file mode 100644
index 0000000000..302f68e75e
--- /dev/null
+++ b/board/google/Kconfig
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+if VENDOR_GOOGLE
+
+choice
+	prompt "Mainboard model"
+
+config TARGET_CHROMEBOOK_LINK
+	bool "Chromebook link"
+	help
+	  This is the Chromebook Pixel released in 2013. It uses an Intel
+	  i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
+	  SDRAM. It has a Panther Point platform controller hub, PCIe
+	  WiFi and Bluetooth. It also includes a 720p webcam, USB SD
+	  reader, microphone and speakers, display port and 32GB SATA
+	  solid state drive. There is a Chrome OS EC connected on LPC,
+	  and it provides a 2560x1700 high resolution touch-enabled LCD
+	  display.
+
+config TARGET_CHROMEBOX_PANTHER
+	bool "Chromebox panther (not available)"
+	select n
+	help
+	  Note: At present this must be used with coreboot. See README.x86
+	  for instructions.
+
+	  This is the Asus Chromebox CN60 released in 2014. It uses an Intel
+	  Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
+	  Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also
+	  includes a USB SD reader, four USB3 ports, display port and HDMI
+	  video output and a 16GB SATA solid state drive. There is no Chrome
+	  OS EC on this model.
+
+endchoice
+
+source "board/google/chromebook_link/Kconfig"
+source "board/google/chromebox_panther/Kconfig"
+
+endif
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index ea454721c5..9c8d0205a1 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -12,6 +12,9 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "chromebook_link"
 
+config SYS_TEXT_BASE
+	default 0xfff00000
+
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select X86_RESET_VECTOR
diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig
index 11df55a13c..e3604ebe31 100644
--- a/board/google/chromebox_panther/Kconfig
+++ b/board/google/chromebox_panther/Kconfig
@@ -12,6 +12,9 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "chromebox_panther"
 
+config SYS_TEXT_BASE
+	default 0xfff00000
+
 # Panther actually uses haswell, not ivybridge, so this is just a placeholder
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
diff --git a/board/intel/Kconfig b/board/intel/Kconfig
new file mode 100644
index 0000000000..7fe21b983a
--- /dev/null
+++ b/board/intel/Kconfig
@@ -0,0 +1,51 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+if VENDOR_INTEL
+
+choice
+	prompt "Mainboard model"
+
+config TARGET_CROWNBAY
+	bool "Crown Bay"
+	help
+	  This is the Intel Crown Bay Customer Reference Board. It contains
+	  the Intel Atom Processor E6xx populated on the COM Express module
+	  with 1GB DDR2 soldered down memory and a carrier board with the
+	  Intel Platform Controller Hub EG20T, other system components and
+	  peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+
+config TARGET_GALILEO
+	bool "Galileo"
+	help
+	  This is the Intel Galileo board, which is the first in a family of
+	  Arduino-certified development and prototyping boards based on Intel
+	  architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
+	  single-core, single-thread, Intel Pentium processor instrunction set
+	  architecture (ISA) compatible, operating at speeds up to 400Mhz,
+	  along with 256MB DDR3 memory. It supports a wide range of industry
+	  standard I/O interfaces, including a full-sized mini-PCIe slot,
+	  one 100Mb Ethernet port, a microSD card slot, a USB host port and
+	  a USB client port.
+
+config TARGET_MINNOWMAX
+	bool "Minnowboard MAX"
+	help
+	  This is the Intel Minnowboard MAX. It contains an Atom E3800
+	  processor in a small form factor with Ethernet, micro-SD, USB 2,
+	  USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
+	  It requires some binary blobs - see README.x86 for details.
+
+	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+	  by U-Boot matches that value.
+
+endchoice
+
+source "board/intel/crownbay/Kconfig"
+source "board/intel/galileo/Kconfig"
+source "board/intel/minnowmax/Kconfig"
+
+endif
diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig
index 762663a001..b30701afc8 100644
--- a/board/intel/crownbay/Kconfig
+++ b/board/intel/crownbay/Kconfig
@@ -12,6 +12,9 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "crownbay"
 
+config SYS_TEXT_BASE
+	default 0xfff00000
+
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select X86_RESET_VECTOR
diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
index 2a254efe3d..31bb320213 100644
--- a/board/intel/crownbay/crownbay.c
+++ b/board/intel/crownbay/crownbay.c
@@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_early_init_f(void)
 {
-	lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
+	lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ);
 
 	return 0;
 }
diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig
index 85afbbc8c5..6515bacd76 100644
--- a/board/intel/galileo/Kconfig
+++ b/board/intel/galileo/Kconfig
@@ -12,6 +12,9 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "galileo"
 
+config SYS_TEXT_BASE
+	default 0xfff10000
+
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select X86_RESET_VECTOR
diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig
index 43c50a519b..f2a0b71c44 100644
--- a/board/intel/minnowmax/Kconfig
+++ b/board/intel/minnowmax/Kconfig
@@ -12,6 +12,9 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "minnowmax"
 
+config SYS_TEXT_BASE
+	default 0xfff00000
+
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select X86_RESET_VECTOR
diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c
index 6e82b16335..fd2070afb2 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_early_init_f(void)
 {
-	lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
+	lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ);
 
 	return 0;
 }
diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig
index d833ca0e25..e86aa16247 100644
--- a/board/maxbcm/Kconfig
+++ b/board/maxbcm/Kconfig
@@ -4,7 +4,7 @@ config SYS_BOARD
 	default "maxbcm"
 
 config SYS_SOC
-	default "armada-xp"
+	default "mvebu"
 
 config SYS_CONFIG_NAME
 	default "maxbcm"
diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c
index 46b16ac29c..2fbb90cfff 100644
--- a/board/maxbcm/maxbcm.c
+++ b/board/maxbcm/maxbcm.c
@@ -12,7 +12,7 @@
 #include <linux/mbus.h>
 
 #include "../drivers/ddr/mvebu/ddr3_hw_training.h"
-#include "../arch/arm/mvebu-common/serdes/high_speed_env_spec.h"
+#include "../arch/arm/mach-mvebu/serdes/high_speed_env_spec.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 88e335836d..a60d0288fb 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -1,21 +1,40 @@
 if ARCH_SUNXI
 
+# Note only one of these may be selected at a time! But hidden choices are
+# not supported by Kconfig
+config SUNXI_GEN_SUN4I
+	bool
+	---help---
+	Select this for sunxi SoCs which have resets and clocks set up
+	as the original A10 (mach-sun4i).
+
+config SUNXI_GEN_SUN6I
+	bool
+	---help---
+	Select this for sunxi SoCs which have sun6i like periphery, like
+	separate ahb reset control registers, custom pmic bus, new style
+	watchdog, etc.
+
+
 choice
 	prompt "Sunxi SoC Variant"
 
 config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
 	select CPU_V7
+	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 
 config MACH_SUN5I
 	bool "sun5i (Allwinner A13)"
 	select CPU_V7
+	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 
 config MACH_SUN6I
 	bool "sun6i (Allwinner A31)"
 	select CPU_V7
+	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 
 config MACH_SUN7I
@@ -23,16 +42,30 @@ config MACH_SUN7I
 	select CPU_V7
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
+	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
-config MACH_SUN8I
+config MACH_SUN8I_A23
 	bool "sun8i (Allwinner A23)"
 	select CPU_V7
+	select SUNXI_GEN_SUN6I
+	select SUPPORT_SPL
+
+config MACH_SUN8I_A33
+	bool "sun8i (Allwinner A33)"
+	select CPU_V7
+	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 
 endchoice
 
+# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
+config MACH_SUN8I
+	bool
+	default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
+
+
 config DRAM_CLK
 	int "sunxi dram clock speed"
 	default 312 if MACH_SUN6I || MACH_SUN8I
@@ -176,9 +209,6 @@ config UART0_PORT_F
 	at the same time, the system can be only booted in the FEL mode.
 	Only enable this if you really know what you are doing.
 
-config FDTFILE
-	string "Default fdtfile env setting for this board"
-
 config OLD_SUNXI_KERNEL_COMPAT
 	boolean "Enable workarounds for booting old kernels"
 	default n
@@ -307,6 +337,12 @@ config I2C4_ENABLE
 	See I2C0_ENABLE help text.
 endif
 
+config AXP_GPIO
+	boolean "Enable support for gpio-s on axp PMICs"
+	default n
+	---help---
+	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
+
 config VIDEO
 	boolean "Enable graphical uboot console on HDMI, LCD or VGA"
 	default y
@@ -507,4 +543,16 @@ config GMAC_TX_DELAY
 	---help---
 	Set the GMAC Transmit Clock Delay Chain value.
 
+config NET
+	default y
+
+config NETDEVICES
+	default y
+
+config DM_ETH
+	default y
+
+config DM_SERIAL
+	default y
+
 endif
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 75e8b5ab4f..339904b84f 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -38,6 +38,7 @@ F:	configs/qt840a_defconfig
 F:	configs/Wits_Pro_A20_DKT_defconfig
 F:	include/configs/sun8i.h
 F:	configs/Ippo_q8h_v1_2_defconfig
+F:	configs/Ippo_q8h_v1_2_a33_1024x600_defconfig
 
 A20-OLINUXINO-LIME BOARD
 M:	FUKAUMI Naoki <naobsd@gmail.com>
@@ -59,6 +60,11 @@ M:	Paul Kocialkowski <contact@paulk.fr>
 S:	Maintained
 F:	configs/Ampe_A76_defconfig
 
+Astar MID756 BOARD
+M:	VishnuPatekar <vishnupatekar0510@gmail.com>
+S:	Maintained
+F:	configs/Astar_MID756_defconfig
+
 COLOMBUS BOARD
 M:	Maxime Ripard <maxime.ripard@free-electrons.com>
 S:	Maintained
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index dda50b55a5..d9f7691373 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -28,7 +28,8 @@
 #include <asm/arch/dram.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
-#include <asm/arch/usbc.h>
+#include <asm/arch/usb_phy.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include <linux/usb/musb.h>
 #include <net.h>
@@ -37,6 +38,41 @@
 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
 int soft_i2c_gpio_sda;
 int soft_i2c_gpio_scl;
+
+static int soft_i2c_board_init(void)
+{
+	int ret;
+
+	soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
+	if (soft_i2c_gpio_sda < 0) {
+		printf("Error invalid soft i2c sda pin: '%s', err %d\n",
+		       CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
+		return soft_i2c_gpio_sda;
+	}
+	ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
+	if (ret) {
+		printf("Error requesting soft i2c sda pin: '%s', err %d\n",
+		       CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
+		return ret;
+	}
+
+	soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
+	if (soft_i2c_gpio_scl < 0) {
+		printf("Error invalid soft i2c scl pin: '%s', err %d\n",
+		       CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
+		return soft_i2c_gpio_scl;
+	}
+	ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
+	if (ret) {
+		printf("Error requesting soft i2c scl pin: '%s', err %d\n",
+		       CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
+		return ret;
+	}
+
+	return 0;
+}
+#else
+static int soft_i2c_board_init(void) { return 0; }
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -44,7 +80,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* add board specific code here */
 int board_init(void)
 {
-	int id_pfr1;
+	int id_pfr1, ret;
 
 	gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
 
@@ -57,7 +93,12 @@ int board_init(void)
 		asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
 	}
 
-	return 0;
+	ret = axp_gpio_init();
+	if (ret)
+		return ret;
+
+	/* Uses dm gpio code so do this here and not in i2c_init_board() */
+	return soft_i2c_board_init();
 }
 
 int dram_init(void)
@@ -351,11 +392,6 @@ void i2c_init_board(void)
 	clock_twi_onoff(4, 1);
 #endif
 #endif
-
-#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
-	soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
-	soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
-#endif
 }
 
 #ifdef CONFIG_SPL_BUILD
@@ -416,6 +452,8 @@ void sunxi_board_init(void)
 #endif
 
 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
+extern const struct musb_platform_ops sunxi_musb_ops;
+
 static struct musb_hdrc_config musb_config = {
 	.multipoint     = 1,
 	.dyn_fifo       = 1,
@@ -472,6 +510,10 @@ int misc_init_r(void)
 		}
 	}
 
+	ret = sunxi_usb_phy_probe();
+	if (ret)
+		return ret;
+
 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
 	musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
 #endif
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index d90eed48f7..4e222d88c0 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -13,11 +13,11 @@ int sunxi_gmac_initialize(bd_t *bis)
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
 	/* Set up clock gating */
-#ifndef CONFIG_MACH_SUN6I
-	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
-#else
+#ifdef CONFIG_SUNXI_GEN_SUN6I
 	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
+#else
+	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
 #endif
 
 	/* Set MII clock */