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-rw-r--r--board/atmel/common/Makefile1
-rw-r--r--board/atmel/common/mac-spi-nor.c127
-rw-r--r--board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c3
-rw-r--r--board/freescale/imx8qm_mek/imx8qm_mek.c2
-rw-r--r--board/freescale/imx8qxp_mek/imx8qxp_mek.c2
-rw-r--r--board/freescale/ls1028a/ls1028a.c12
-rw-r--r--board/freescale/ls1046afrwy/ls1046afrwy.c11
-rw-r--r--board/gateworks/gw_ventana/Kconfig3
-rw-r--r--board/google/Kconfig15
-rw-r--r--board/google/chromebook_coral/Kconfig43
-rw-r--r--board/google/chromebook_coral/MAINTAINERS6
-rw-r--r--board/google/chromebook_coral/Makefile5
-rw-r--r--board/google/chromebook_coral/coral.c19
-rw-r--r--board/keymile/Kconfig6
-rw-r--r--board/keymile/km83xx/km83xx.c2
-rw-r--r--board/keymile/kmp204x/kmp204x.c2
-rw-r--r--board/toradex/apalis-imx8/apalis-imx8.c2
17 files changed, 253 insertions, 8 deletions
diff --git a/board/atmel/common/Makefile b/board/atmel/common/Makefile
index 4de0912f22..6bc8cabb8d 100644
--- a/board/atmel/common/Makefile
+++ b/board/atmel/common/Makefile
@@ -5,4 +5,5 @@
obj-y += board.o
obj-$(CONFIG_I2C_EEPROM) += mac_eeprom.o
+obj-$(CONFIG_SPI_FLASH_SFDP_SUPPORT) += mac-spi-nor.o
obj-$(CONFIG_DM_VIDEO) += video_display.o
diff --git a/board/atmel/common/mac-spi-nor.c b/board/atmel/common/mac-spi-nor.c
new file mode 100644
index 0000000000..96343678e0
--- /dev/null
+++ b/board/atmel/common/mac-spi-nor.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Tudor Ambarus <tudor.ambarus@microchip.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <linux/mtd/spi-nor.h>
+#include <netdev.h>
+
+#define ETH_ADDR_SIZE 6
+
+#ifdef CONFIG_SPI_FLASH_SST
+#define SFDP_MICROCHIP_MANUF_ID 0xbf
+#define SFDP_MICROCHIP_MEM_TYPE 0x26
+#define SFDP_MICROCHIP_DEV_ID 0x43
+
+#define SFDP_MICROCHIP_EUI_OFFSET 0x60
+#define SFDP_MICROCHIP_EUI48 0x30
+
+struct sst26vf064beui {
+ u8 manufacturer_id;
+ u8 memory_type;
+ u8 device_id;
+ u8 reserved;
+};
+
+/**
+ * sst26vf064beui_check() - Check the validity of the EUI-48 information from
+ * the sst26vf064beui SPI NOR Microchip SFDP table.
+ * @manufacturer_sfdp: pointer to the Microchip manufacturer specific SFDP
+ * table.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int sst26vf064beui_check(const u8 *manufacturer_sfdp)
+{
+ struct sst26vf064beui *sst26vf064beui =
+ (struct sst26vf064beui *)manufacturer_sfdp;
+
+ if (sst26vf064beui->manufacturer_id != SFDP_MICROCHIP_MANUF_ID)
+ return -EINVAL;
+
+ if (sst26vf064beui->memory_type != SFDP_MICROCHIP_MEM_TYPE)
+ return -EINVAL;
+
+ if (sst26vf064beui->device_id != SFDP_MICROCHIP_DEV_ID)
+ return -EINVAL;
+
+ /*
+ * Check if the EUI-48 MAC address is programmed in the next six address
+ * locations.
+ */
+ if (manufacturer_sfdp[SFDP_MICROCHIP_EUI_OFFSET] !=
+ SFDP_MICROCHIP_EUI48)
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * sst26vf064beui_get_ethaddr() - Get the ethernet address from the
+ * sst26vf064beui SPI NOR Microchip SFDP table.
+ * @manufacturer_sfdp: pointer to the Microchip manufacturer specific SFDP
+ * table.
+ * @ethaddr: pointer where to fill the ethernet address
+ * @size: size of the ethernet address.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int sst26vf064beui_get_ethaddr(const u8 *manufacturer_sfdp,
+ u8 *ethaddr, size_t size)
+{
+ u64 eui_table[2];
+ u64 *p = (u64 *)&manufacturer_sfdp[SFDP_MICROCHIP_EUI_OFFSET];
+ int i, ret;
+
+ ret = sst26vf064beui_check(manufacturer_sfdp);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < 2; i++)
+ eui_table[i] = le64_to_cpu(p[i]);
+
+ /* Ethaddr starts at offset one. */
+ memcpy(ethaddr, &((u8 *)eui_table)[1], size);
+
+ return 0;
+}
+#endif
+
+/**
+ * at91_spi_nor_set_ethaddr() - Retrieve and set the ethernet address from the
+ * SPI NOR manufacturer specific SFDP table.
+ */
+void at91_spi_nor_set_ethaddr(void)
+{
+ struct udevice *dev;
+ struct spi_nor *nor;
+ const char *ethaddr_name = "ethaddr";
+ u8 ethaddr[ETH_ADDR_SIZE] = {0};
+
+ if (env_get(ethaddr_name))
+ return;
+
+ if (uclass_first_device_err(UCLASS_SPI_FLASH, &dev))
+ return;
+
+ nor = dev_get_uclass_priv(dev);
+ if (!nor)
+ return;
+
+ if (!nor->manufacturer_sfdp)
+ return;
+
+#ifdef CONFIG_SPI_FLASH_SST
+ if (sst26vf064beui_get_ethaddr(nor->manufacturer_sfdp, ethaddr,
+ ETH_ADDR_SIZE))
+ return;
+#endif
+
+ if (is_valid_ethaddr(ethaddr))
+ eth_env_set_enetaddr(ethaddr_name, ethaddr);
+}
diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
index fda06c824d..fc563ebb71 100644
--- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
+++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
@@ -68,6 +68,9 @@ int board_init(void)
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
+#ifdef CONFIG_SPI_FLASH_SFDP_SUPPORT
+ at91_spi_nor_set_ethaddr();
+#endif
return 0;
}
#endif
diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c
index 68be0fe0cf..667a2743a6 100644
--- a/board/freescale/imx8qm_mek/imx8qm_mek.c
+++ b/board/freescale/imx8qm_mek/imx8qm_mek.c
@@ -50,7 +50,7 @@ int board_early_init_f(void)
return 0;
}
-#if IS_ENABLED(CONFIG_DM_GPIO)
+#if CONFIG_IS_ENABLED(DM_GPIO)
static void board_gpio_init(void)
{
/* TODO */
diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
index 671064fae2..194eb60cd3 100644
--- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c
+++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -54,7 +54,7 @@ int board_early_init_f(void)
return 0;
}
-#if IS_ENABLED(CONFIG_DM_GPIO)
+#if CONFIG_IS_ENABLED(DM_GPIO)
static void board_gpio_init(void)
{
struct gpio_desc desc;
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index a9606b8865..1151e77531 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -86,7 +86,19 @@ int board_init(void)
if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
dm_i2c_write(dev, 0x0b, &val, 1);
#endif
+#endif
+#if defined(CONFIG_TARGET_LS1028ARDB)
+ u8 reg;
+
+ reg = QIXIS_READ(brdcfg[4]);
+ /*
+ * Field | Function
+ * 3 | DisplayPort Power Enable (net DP_PWR_EN):
+ * DPPWR | 0= DP_PWR is enabled.
+ */
+ reg &= ~(DP_PWD_EN_DEFAULT_MASK);
+ QIXIS_WRITE(brdcfg[4], reg);
#endif
return 0;
}
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
index ac2f8ee436..db8b3a5b92 100644
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -24,7 +24,8 @@
#define LS1046A_PORSR1_REG 0x1EE0000
#define BOOT_SRC_SD 0x20000000
#define BOOT_SRC_MASK 0xFF800000
-#define BOARD_REV_GPIO 13
+#define BOARD_REV_GPIO_SHIFT 17
+#define BOARD_REV_MASK 0x03
#define USB2_SEL_MASK 0x00000100
#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
@@ -87,10 +88,14 @@ int board_early_init_f(void)
static inline uint8_t get_board_version(void)
{
- u8 val;
struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
- val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03;
+ /* GPIO 13 and GPIO 14 are used for Board Rev */
+ u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT))
+ & BOARD_REV_MASK;
+
+ /* GPIOs' are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */
+ u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK;
return val;
}
diff --git a/board/gateworks/gw_ventana/Kconfig b/board/gateworks/gw_ventana/Kconfig
index 5d1bae41ac..fee910ca83 100644
--- a/board/gateworks/gw_ventana/Kconfig
+++ b/board/gateworks/gw_ventana/Kconfig
@@ -1,5 +1,8 @@
if TARGET_GW_VENTANA
+config DM_GPIO
+ default y
+
config SYS_BOARD
default "gw_ventana"
diff --git a/board/google/Kconfig b/board/google/Kconfig
index 679a0f1023..22c4be392f 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -8,6 +8,20 @@ choice
prompt "Mainboard model"
optional
+config TARGET_CHROMEBOOK_CORAL
+ bool "Chromebook coral"
+ help
+ This is a range of Intel-based laptops released in 2018. They use an
+ Intel Apollo Lake SoC. The design supports WiFi, 4GB to 16GB of
+ LPDDR4 1600MHz SDRAM, PCIe WiFi and Bluetooth, eMMC (typically 32GB),
+ up two cameras (front-facing 720p and another 5MP option), USB SD
+ reader, microphone and speakers. It also includes two USB 3 Type A and
+ two Type C ports. The latter are used as power input and can also
+ charge external devices as well as a 4K external display. There is a
+ Chrome OS EC connected on LPC, a Cr50 secure chip from Google and
+ various display options. OEMs products include Acer Chromebook 11
+ (e.g. C732, CB11, CP311) and Lenovo Chromebook (100e, 300e, 500e).
+
config TARGET_CHROMEBOOK_LINK
bool "Chromebook link"
help
@@ -62,6 +76,7 @@ config TARGET_CHROMEBOOK_SAMUS_TPL
endchoice
+source "board/google/chromebook_coral/Kconfig"
source "board/google/chromebook_link/Kconfig"
source "board/google/chromebox_panther/Kconfig"
source "board/google/chromebook_samus/Kconfig"
diff --git a/board/google/chromebook_coral/Kconfig b/board/google/chromebook_coral/Kconfig
new file mode 100644
index 0000000000..940bee89b0
--- /dev/null
+++ b/board/google/chromebook_coral/Kconfig
@@ -0,0 +1,43 @@
+if TARGET_CHROMEBOOK_CORAL
+
+config SYS_BOARD
+ default "chromebook_coral"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_SOC
+ default "apollolake"
+
+config SYS_CONFIG_NAME
+ default "chromebook_coral"
+
+config SYS_TEXT_BASE
+ default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select X86_RESET_VECTOR
+ select INTEL_APOLLOLAKE
+ select BOARD_ROMSIZE_KB_16384
+
+config PCIE_ECAM_BASE
+ default 0xf0000000
+
+config EARLY_POST_CROS_EC
+ bool "Enable early post to Chrome OS EC"
+ help
+ Allow post codes to be sent to the Chroem OS EC early during boot,
+ to enable monitoring of the boot and debugging when things go wrong.
+ With this option enabled, the EC console can be used to watch post
+ codes the first part of boot.
+
+config SYS_CAR_ADDR
+ hex
+ default 0xfef00000
+
+config SYS_CAR_SIZE
+ hex
+ default 0xc0000
+
+endif
diff --git a/board/google/chromebook_coral/MAINTAINERS b/board/google/chromebook_coral/MAINTAINERS
new file mode 100644
index 0000000000..904227e2e2
--- /dev/null
+++ b/board/google/chromebook_coral/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOOK_CORAL_BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/chromebook_coral/
+F: include/configs/chromebook_coral.h
+F: configs/chromebook_coral_defconfig
diff --git a/board/google/chromebook_coral/Makefile b/board/google/chromebook_coral/Makefile
new file mode 100644
index 0000000000..6a27ce3da1
--- /dev/null
+++ b/board/google/chromebook_coral/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Google LLC
+
+obj-y += coral.o
diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c
new file mode 100644
index 0000000000..4e34710b97
--- /dev/null
+++ b/board/google/chromebook_coral/coral.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include <common.h>
+
+int arch_misc_init(void)
+{
+ return 0;
+}
+
+/* This function is needed if CONFIG_CMDLINE is not enabled */
+int board_run_command(const char *cmdline)
+{
+ printf("No command line\n");
+
+ return 0;
+}
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index acaa9289f7..5f512d56da 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -62,6 +62,12 @@ config KM_CONSOLE_TTY
help
TTY console to use on board.
+config KM_DEF_NETDEV
+ string "Default Netdevice"
+ default "eth0"
+ help
+ Default netdevice for debug interface
+
config KM_COMMON_ETH_INIT
bool "Common Ethernet Initialization"
default y if KIRKWOOD || MPC83xx
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index abbf985eb2..5969d51395 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -277,7 +277,7 @@ int dram_init(void)
int checkboard(void)
{
- puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
+ puts("Board: ABB " CONFIG_SYS_CONFIG_NAME);
if (piggy_present())
puts(" with PIGGY.");
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index ae9653db78..88914c80e8 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -29,7 +29,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
int checkboard(void)
{
- printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
+ printf("Board: Keymile %s\n", CONFIG_SYS_CONFIG_NAME);
return 0;
}
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c
index 3e5174ef8a..0483041187 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -51,7 +51,7 @@ int board_early_init_f(void)
return 0;
}
-#if IS_ENABLED(CONFIG_DM_GPIO)
+#if CONFIG_IS_ENABLED(DM_GPIO)
static void board_gpio_init(void)
{
/* TODO */
generated by cgit (git 2.34.1) at 2025-01-09 19:16:24 +0000