diff options
Diffstat (limited to 'board')
147 files changed, 1822 insertions, 23431 deletions
diff --git a/board/Marvell/common/ecctest.c b/board/Marvell/common/ecctest.c deleted file mode 100644 index 0a9a2a4c4f..0000000000 --- a/board/Marvell/common/ecctest.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2001 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifdef ECC_TEST -static inline void ecc_off (void) -{ - *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000; -} - -static inline void ecc_on (void) -{ - *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000; -} - -static int putshex (const char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) { - printf ("%02x", buf[i]); - } - return 0; -} - -static int char_memcpy (void *d, const void *s, int len) -{ - int i; - char *cd = d; - const char *cs = s; - - for (i = 0; i < len; i++) { - *(cd++) = *(cs++); - } - return 0; -} - -static int memory_test (char *buf) -{ - const char src[][16] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}, - {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, - 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}, - {0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, - 0x04, 0x04, 0x04, 0x04, 0x04, 0x04}, - {0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, - 0x08, 0x08, 0x08, 0x08, 0x08, 0x08}, - {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, - {0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x20, 0x20, 0x20}, - {0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, - 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}, - {0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80}, - {0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, - 0x55, 0x55, 0x55, 0x55, 0x55, 0x55}, - {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}, - {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }; - const int foo[] = { 0 }; - int i, j, a; - - printf ("\ntest @ %d %p\n", foo[0], buf); - for (i = 0; i < 12; i++) { - for (a = 0; a < 8; a++) { - const char *s = src[i] + a; - int align = (unsigned) (s) & 0x7; - - /* ecc_off(); */ - memcpy (buf, s, 8); - /* ecc_on(); */ - putshex (s, 8); - if (memcmp (buf, s, 8)) { - putc ('\n'); - putshex (buf, 8); - printf (" [FAIL] (%p) align=%d\n", s, align); - for (j = 0; j < 8; j++) { - s[j] == buf[j] ? puts (" ") : - printf ("%02x", - (s[j]) ^ (buf[j])); - } - putc ('\n'); - } else { - printf (" [PASS] (%p) align=%d\n", s, align); - } - /* ecc_off(); */ - char_memcpy (buf, s, 8); - /* ecc_on(); */ - putshex (s, 8); - if (memcmp (buf, s, 8)) { - putc ('\n'); - putshex (buf, 8); - printf (" [FAIL] (%p) align=%d\n", s, align); - for (j = 0; j < 8; j++) { - s[j] == buf[j] ? puts (" ") : - printf ("%02x", - (s[j]) ^ (buf[j])); - } - putc ('\n'); - } else { - printf (" [PASS] (%p) align=%d\n", s, align); - } - } - } - - return 0; -} -#endif diff --git a/board/RPXClassic/Makefile b/board/RPXClassic/Makefile deleted file mode 100644 index 87db754faa..0000000000 --- a/board/RPXClassic/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = RPXClassic.o flash.o eccx.o diff --git a/board/RPXClassic/README b/board/RPXClassic/README deleted file mode 100644 index e03f670d1c..0000000000 --- a/board/RPXClassic/README +++ /dev/null @@ -1,19 +0,0 @@ -# Porting U-Boot onto RPXClassic LF_BW31 board -# Written by Pierre AUBERT -# E-Mail p.aubert@staubli.com -# Stäubli Faverges - <www.staubli.com> -# -# Sept. 20 2001 -# -# Cross compile: Montavista Hardhat ported on HP-UX 10.20 -# - -Flash memories : AM29DL323B (2 banks flash memories) 16 Mb from 0xff000000 -DRAM : 16 Mb from 0 -NVRAM : 512 kb from 0xfa000000 - - -- environment is stored in NVRAM -- Mac address is read from EEPROM -- ethernet on SCC1 or fast ethernet on FEC are running (depending on the - configuration flag CONFIG_FEC_ENET) diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c deleted file mode 100644 index 15b7232fd7..0000000000 --- a/board/RPXClassic/RPXClassic.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * (C) Copyright 2001 - * Stäubli Faverges - <www.staubli.com> - * Pierre AUBERT p.aubert@staubli.com - * U-Boot port on RPXClassic LF (CLLF_BW31) board - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <i2c.h> -#include <config.h> -#include <mpc8xx.h> -#include <net.h> - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static unsigned char aschex_to_byte (unsigned char *cp); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, - 0x0CFFCC00, 0x33FFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXClassic\n"); - return (0); -} - -/*----------------------------------------------------------------------------- - * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM - *----------------------------------------------------------------------------- - */ -static void board_get_enetaddr(uchar *enet) -{ - int i; - char buff[256], *cp; - - /* Initialize I2C */ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - /* Read 256 bytes in EEPROM */ - i2c_read (0x54, 0, 1, (uchar *)buff, 128); - i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128); - - /* Retrieve MAC address in buffer (key EA) */ - for (cp = buff;;) { - if (cp[0] == 'E' && cp[1] == 'A') { - cp += 3; - /* Read MAC address */ - for (i = 0; i < 6; i++, cp += 2) { - enet[i] = aschex_to_byte ((unsigned char *)cp); - } - } - /* Scan to the end of the record */ - while ((*cp != '\n') && (*cp != (char)0xff)) { - cp++; - } - /* If the next character is a \n, 0 or ff, we are done. */ - cp++; - if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff)) - break; - } - -#ifdef CONFIG_FEC_ENET - /* The MAC address is the same as normal ethernet except the 3rd byte */ - /* (See the E.P. Planet Core Overview manual */ - enet[3] |= 0x80; -#endif - - printf("MAC address = %pM\n", enet); -} - -int misc_init_r(void) -{ - uchar enetaddr[6]; - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - return 0; -} - -void rpxclassic_init (void) -{ - /* Enable NVRAM */ - *((uchar *) BCSR0) |= BCSR0_ENNVRAM; - -#ifdef CONFIG_FEC_ENET - - /* Validate the fast ethernet tranceiver */ - *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL; - *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN; - *((volatile uchar *) BCSR2) |= BCSR2_MIIRST; - *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN; -#endif - -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size10; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000000; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 10 column mode - */ - - size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - return (size10); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} -/*----------------------------------------------------------------------------- - * aschex_to_byte -- - *----------------------------------------------------------------------------- - */ -static unsigned char aschex_to_byte (unsigned char *cp) -{ - u_char byte, c; - - c = *cp++; - - if ((c >= 'A') && (c <= 'F')) { - c -= 'A'; - c += 10; - } else if ((c >= 'a') && (c <= 'f')) { - c -= 'a'; - c += 10; - } else { - c -= '0'; - } - - byte = c * 16; - - c = *cp; - - if ((c >= 'A') && (c <= 'F')) { - c -= 'A'; - c += 10; - } else if ((c >= 'a') && (c <= 'f')) { - c -= 'a'; - c += 10; - } else { - c -= '0'; - } - - byte += c; - - return (byte); -} diff --git a/board/RPXClassic/eccx.c b/board/RPXClassic/eccx.c deleted file mode 100644 index 766a19eb1e..0000000000 --- a/board/RPXClassic/eccx.c +++ /dev/null @@ -1,335 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - <www.staubli.com> - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* Video support for the ECCX daughter board */ - - -#include <common.h> -#include <config.h> - -#ifdef CONFIG_VIDEO_SED13806 -#include <sed13806.h> - - -/* Screen configurations: the initialization of the SD13806 depends on - screen and on display mode. We handle only 8bpp and 16 bpp modes */ - -/* ECCX board is supplied with a NEC NL6448BC20 screen */ -#ifdef CONFIG_NEC_NL6448BC20 -#define DISPLAY_WIDTH 640 -#define DISPLAY_HEIGHT 480 - -#ifdef CONFIG_VIDEO_SED13806_8BPP -static const S1D_REGS init_regs [] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0xe5}, /* General IO Pins Control Register 0 */ - {0x0009,0x1f}, /* General IO Pins Control Register 1 */ - {0x0010,0x02}, /* Memory Clock Configuration Register */ - {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x04}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x03}, /* LCD Display Mode Register */ - {0x0041,0x02}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x40}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x01}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x00}, /* TV Output Control Register */ - {0x0060,0x03}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01E4,0x00}, /* Look-Up Table Data Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ - {0, 0} -}; -#endif /* CONFIG_VIDEO_SED13806_8BPP */ - -#ifdef CONFIG_VIDEO_SED13806_16BPP - -static const S1D_REGS init_regs [] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0xe5}, /* General IO Pins Control Register 0 */ - {0x0009,0x1f}, /* General IO Pins Control Register 1 */ - {0x0010,0x02}, /* Memory Clock Configuration Register */ - {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x04}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x05}, /* LCD Display Mode Register */ - {0x0041,0x02}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x00}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x01}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01E4,0x00}, /* Look-Up Table Data Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ - {0, 0} -}; - -#endif /* CONFIG_VIDEO_SED13806_16BPP */ -#endif /* CONFIG_NEC_NL6448BC20 */ - - -#ifdef CONFIG_CONSOLE_EXTRA_INFO - -/*----------------------------------------------------------------------------- - * video_get_info_str -- setup a board string: type, speed, etc. - * line_number= location to place info string beside logo - * info= buffer for info string - *----------------------------------------------------------------------------- - */ -void video_get_info_str (int line_number, char *info) -{ - if (line_number == 1) { - strcpy (info, " RPXClassic board"); - } - else { - info [0] = '\0'; - } - -} -#endif - -/*----------------------------------------------------------------------------- - * board_video_init -- init de l'EPSON, config du CS - *----------------------------------------------------------------------------- - */ -unsigned int board_video_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Program ECCX registers */ - *(ECCX_CSR12) |= ECCX_860; - *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2; - *(ECCX_CSR8) |= ECCX_ENEPSON; - - memctl->memc_or2 = SED13806_OR; - memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES; - - return (SED13806_REG_ADDR); -} - -/*----------------------------------------------------------------------------- - * board_validate_screen -- - *----------------------------------------------------------------------------- - */ -void board_validate_screen (unsigned int base) -{ - /* Activate the panel bias power */ - *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80; -} -/*----------------------------------------------------------------------------- - * board_get_regs -- - *----------------------------------------------------------------------------- - */ -const S1D_REGS *board_get_regs (void) -{ - return (init_regs); -} -/*----------------------------------------------------------------------------- - * board_get_width -- - *----------------------------------------------------------------------------- - */ -int board_get_width (void) -{ - return (DISPLAY_WIDTH); -} - -/*----------------------------------------------------------------------------- - * board_get_height -- - *----------------------------------------------------------------------------- - */ -int board_get_height (void) -{ - return (DISPLAY_HEIGHT); -} - -#endif /* CONFIG_VIDEO_SED13806 */ diff --git a/board/RPXClassic/flash.c b/board/RPXClassic/flash.c deleted file mode 100644 index 97ffa68aa2..0000000000 --- a/board/RPXClassic/flash.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * (C) Copyright 2001 - * Stäubli Faverges - <www.staubli.com> - * Pierre AUBERT p.aubert@staubli.com - * U-Boot port on RPXClassic LF (CLLF_BW31) board - * - * RPXClassic uses Am29DL323B flash memory with 2 banks - * - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL323B: - printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Reset flash componeny */ - addr [0] = 0xf0f0f0f0; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0xAAAAAAAA ; - addr[0x555] = 0x55555555 ; - addr[0xAAA] = 0x90909090 ; - - value = addr[0] ; - - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - - switch (value & 0x00FF00FF) { - case (AMD_ID_DL323B & 0x00FF00FF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; /* 16 Mb */ - - break; - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /* set up sector start address table */ - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x00010000; - info->start[3] = base + 0x00018000; - info->start[4] = base + 0x00020000; - info->start[5] = base + 0x00028000; - info->start[6] = base + 0x00030000; - info->start[7] = base + 0x00038000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i-7) * 0x00040000) ; - } - - /* check for protected sectors */ - for (i = 0; i < 23; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - /* Check for protected sectors in the 2nd bank */ - addr[0x100AAA] = 0xAAAAAAAA ; - addr[0x100555] = 0x55555555 ; - addr[0x100AAA] = 0x90909090 ; - - for (i = 23; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank 1 */ - addr = (volatile unsigned long *)info->start[23]; - - *addr = 0xF0F0F0F0; /* reset bank 2 */ - - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/RPXClassic/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug deleted file mode 100644 index b9c84c77d6..0000000000 --- a/board/RPXClassic/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite/Makefile b/board/RPXlite/Makefile deleted file mode 100644 index c17cbacf32..0000000000 --- a/board/RPXlite/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = RPXlite.o flash.o diff --git a/board/RPXlite/README b/board/RPXlite/README deleted file mode 100644 index 3ca671126d..0000000000 --- a/board/RPXlite/README +++ /dev/null @@ -1,877 +0,0 @@ -# Porting U-Boot onto RPXlite board -# Written by Yoo. Jonghoon -# E-Mail : yooth@ipone.co.kr -# IP ONE Inc. - -# Since 2001. 1. 29 - -# Shell : bash -# Cross-compile tools : Montavista Hardhat -# Debugging tools : Windriver VisionProbe (PowerPC BDM) -# ppcboot ver. : ppcboot-0.8.1 - -############################################################### -# 1. Hardware setting -############################################################### - -1.1. Board, BDM settings - Install board, BDM, connect each other - -1.2. Save Register value - Boot with board-on monitor program and save the - register values with BDM. - -1.3. Configure flash programmer - Check flash memory area in the memory map. - 0xFFC00000 - 0xFFFFFFFF - - Boot monitor program is at - 0xFFF00000 - - You can program on-board flash memory with VisionClick - flash programmer. Set the target flash device as: - - 29DL800B - - (?) The flash memory device in the board *is* 29LV800B, - but I cannot program it with '29LV800B' option. - (in VisionClick flash programming tools) - I don't know why... - -1.4. Save boot monitor program *IMPORTANT* - Upload boot monitor program from board to file. - boot monitor program starts at 0xFFF00000 - -1.5. Test flash memory programming - Try to erase boot program in the flash memory, - and re-write them. - *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE - BEFORE ERASING FLASH - -############################################################### -# 2. U-Boot setting -############################################################### - -2.1. Download U-Boot tarball at - ftp://ftp.denx.de - (The latest version is ppcboot-0.8.1.tar.bz2) - - To extract the archive use the following syntax : - > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf - - -2.2. Add the following lines in '.profile' - export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin - -2.3. Make board specific config, for example: - > cd ppcboot-0.8.1 - > make TQM860L_config - - Now we can build ppcboot bin files. - After make all, you must see these files in your - ppcboot root directory. - - ppcboot - ppcboot.bin - ppcboot.srec - ppcboot.map - -2.4. Make your own board directory into the - ppcboot-0.8.1/board - and make your board-specific files here. - - For exmanple, tqm8xx files are composed of - .depend : Nothing - Makefile : To make config file - config.mk : Sets base address - flash.c : Flash memory control files - ppcboot.lds : linker(ld) script? (I don't know this yet) - tqm8xx.c : DRAM control and board check routines - - And, add your board config lines in the - ppcboot-0.8.1/Makefile - - Finally, add config_(your board).h file in the - ppcboot-0.8.1/include/ - - I've made board/rpxlite directory, and just copied - tqm8xx settings for now. - - Rebuild ppcboot for rpxlite board: - > make rpxlite_config - > make - -############################################################### -# 3. U-Boot porting -############################################################### - -3.1. My RPXlite files are based on tqm8xx board files. - > cd board - > cp -r tqm8xx RPXLITE - > cd RPXLITE - > mv tqm8xx.c RPXLITE.c - > cd ../../include - > cp config_tqm8xx.h config_RPXLITE.h - -3.2. Modified files are: - board/RPXLITE/RPXLITE.c /* DRAM-related routines */ - board/RPXLITE/flash.c /* flash-related routines */ - board/RPXLITE/config.mk /* set text base address */ - arch/powerpc/cpu/mpc8xx/serial.c /* board specific register setting */ - include/config_RPXLITE.h /* board specific registers */ - - See 'reg_config.txt' for register values in detail. - -############################################################### -# 4. Running Linux -############################################################### - - -############################################################### -# Misc Information -############################################################### - -mem_config.txt: -=============== - -Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device -manufacturer id : 01 (AMD) -device id : 5B (AM29LV800B) -size : 4Mbyte -sector # : 19 - -Sector information : - -number start addr. size -00 FFC0_0000 64 -01 FFC1_0000 32 -02 FFC1_8000 32 -03 FFC2_0000 128 -04 FFC4_0000 256 -05 FFC8_0000 256 -06 FFCC_0000 256 -07 FFD0_0000 256 -08 FFD4_0000 256 -09 FFD8_0000 256 -10 FFDC_0000 256 -11 FFE0_0000 256 -12 FFE4_0000 256 -13 FFE8_0000 256 -14 FFEC_0000 256 -15 FFF0_0000 256 -16 FFF4_0000 256 -17 FFF8_0000 256 -18 FFFC_0000 256 - - -reg_config.txt: -=============== - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* SIU (System Interface Unit) */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ - - -/*### IMMR */ -/*### Internal Memory Map Register */ -/*### Chap. 11.4.1 */ - - ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */ - PARTNUM = 0x21 - MASKNUM = 0x00 - - => 0xFA20 2100 - ---------------------------------------------------------------------- - -/*### SIUMCR */ -/*### SIU Module Configuration Register */ -/*### Chap. 11.4.2 */ -/*### Offset : 0x0000 0000 */ - - EARB = 0 - EARP = 0 - DSHW = 0 - DBGC = 0 - DBPC = 0 - FRC = 0 - DLK = 0 - OPAR = 0 - PNCS = 0 - DPC = 0 - MPRE = 0 - MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */ - AEME = 0 - SEME = 0 - BSC = 0 - GB5E = 0 - B2DD = 0 - B3DD = 0 - - => 0x0000 0800 - ---------------------------------------------------------------------- - -/*### SYPCR */ -/*### System Protection Control Register */ -/*### Chap. 11.4.3 */ -/*### Offset : 0x0000 0004 */ - - SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */ - BMT = 0x06 /* BUS monitoring timing */ - BME = 1 /* BUS monitor enable */ - SWF = 1 - SWE = 0 /* SW watchdog disable */ - SWRI = 0 - SWP = 1 - - => 0xFFFF 0689 - ---------------------------------------------------------------------- - -/*### TESR */ -/*### Transfer Error Status Register */ -/*### Chap. 11.4.4 */ -/*### Offset : 0x0000 0020 */ - - IEXT = 0 - ITMT = 0 - IPB = 0000 - DEXT = 0 - DTMT = 0 - DPB = 0000 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIPEND */ -/*### SIU Interrupt Pending Register */ -/*### Chap. 11.5.4.1 */ -/*### Offset : 0x0000 0010 */ - - IRQ0~IRQ7 = 0 - LVL0~LVL7 = 0 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIMASK */ -/*### SIU Interrupt Mask Register */ -/*### Chap. 11.5.4.2 */ -/*### Offset : 0x0000 0014 */ - - IRM0~IRM7 = 0 /* Mask all interrupts */ - LVL0~LVL7 = 0 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIEL */ -/*### SIU Interrupt Edge/Level Register */ -/*### Chap. 11.5.4.3 */ -/*### Offset : 0x0000 0018 */ - - ED0~ED7 = 0 /* Low level triggered */ - WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */ - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIVEC */ -/*### SIU Interrupt Vector Register */ -/*### Chap. 11.5.4.4 */ -/*### Offset : 0x0000 001C */ - - INTC = 3C /* The lowest interrupt is pending..(?) */ - - => 0x3C00 0000 - ---------------------------------------------------------------------- - -/*### SWSR */ -/*### Software Service Register */ -/*### Chap. 11.7.1 */ -/*### Offset : 0x0000 001E */ - - SEQ = 0 - - => 0x0000 - ---------------------------------------------------------------------- - -/*### SDCR */ -/*### SDMA Configuration Register */ -/*### Chap. 20.2.1 */ -/*### Offset : 0x0000 0032 */ - - FRZ = 0 - RAID = 01 /* Priority level 5 (BR5) (normal operation) */ - - => 0x0000 0001 - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* UPMA (User Programmable Machine A) */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ - -/*### Chap. 16.6.4.1 */ -/*### Offset = 0x0000 017c */ - - T0 = CFFF CC24 /* Single Read */ - T1 = 0FFF CC04 - T2 = 0CAF CC04 - T3 = 03AF CC08 - T4 = 3FBF CC27 /* last */ - T5 = FFFF CC25 - T6 = FFFF CC25 - T7 = FFFF CC25 - T8 = CFFF CC24 /* Burst Read */ - T9 = 0FFF CC04 - T10 = 0CAF CC84 - T11 = 03AF CC88 - T12 = 3FBF CC27 /* last */ - T13 = FFFF CC25 - T14 = FFFF CC25 - T15 = FFFF CC25 - T16 = FFFF CC25 - T17 = FFFF CC25 - T18 = FFFF CC25 - T19 = FFFF CC25 - T20 = FFFF CC25 - T21 = FFFF CC25 - T22 = FFFF CC25 - T23 = FFFF CC25 - T24 = CFFF CC24 /* Single Write */ - T25 = 0FFF CC04 - T26 = 0CFF CC04 - T27 = 03FF CC00 - T28 = 3FFF CC27 /* last */ - T29 = FFFF CC25 - T30 = FFFF CC25 - T31 = FFFF CC25 - T32 = CFFF CC24 /* Burst Write */ - T33 = 0FFF CC04 - T34 = 0CFF CC80 - T35 = 03FF CC8C - T36 = 0CFF CC00 - T37 = 33FF CC27 /* last */ - T38 = FFFF CC25 - T39 = FFFF CC25 - T40 = FFFF CC25 - T41 = FFFF CC25 - T42 = FFFF CC25 - T43 = FFFF CC25 - T44 = FFFF CC25 - T45 = FFFF CC25 - T46 = FFFF CC25 - T47 = FFFF CC25 - T48 = C0FF CC24 /* Refresh */ - T49 = 03FF CC24 - T50 = 0FFF CC24 - T51 = 0FFF CC24 - T52 = 3FFF CC27 /* last */ - T53 = FFFF CC25 - T54 = FFFF CC25 - T55 = FFFF CC25 - T56 = FFFF CC25 - T57 = FFFF CC25 - T58 = FFFF CC25 - T59 = FFFF CC25 - T60 = FFFF CC25 /* Exception */ - T61 = FFFF CC25 - T62 = FFFF CC25 - T63 = FFFF CC25 - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* UPMB */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### Chap. 16.6.4.1 */ - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* MEMC */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### BR0 & OR0 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */ -/*### Flash memory */ - - BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFE00 0001 - - AM = 1111 1110 0000 0000 0 /* 32MBytes */ - ATM = 000 - CSNT/SAM = 0 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0100 /* cycle length = 4 */ - SETA = 0 - TRLX = 0 - EHTR = 0 - - => 0xFE00 0140 - -/*### BR1 & OR1 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */ -/*### SDRAM */ - - BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 1 /* UPMA */ - V = 1 /* Valid */ - - => 0x0000 0081 - - AM = 1111 1110 0000 0000 /* 32MBytes */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 11 - BIH = 0 - SCY = 0000 /* cycle length = 0 */ - SETA = 0 - TRLX = 0 - EHTR = 0 - - => 0xFE00 0E00 - -/*### BR2 & OR2 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */ - - BR2 & OR2 = 0x0000 0000 /* Not used */ - -/*### BR3 & OR3 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */ -/*### BCSR */ - - BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFA40 0001 - - AM = 1111 1111 0111 1111 1 /* (?) */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0001 /* cycle length = 1 */ - SETA = 0 - TRLX = 0 - - => 0xFF7F 8910 - -/*### BR4 & OR4 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */ -/*### NVRAM & SRAM */ - - BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */ - AT = 000 - PS = 01 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFA00 0401 - - AM = 1111 1111 1111 1000 0 /* 8MByte */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0111 /* cycle length = 7 */ - SETA = 0 - TRLX = 0 - - => 0xFFF8 0970 - -/*### BR5 & OR5 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */ - - BR5 & OR5 = 0x0000 0000 /* Not used */ - -/*### BR6 & OR6 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */ - - BR6 & OR6 = 0x0000 0000 /* Not used */ - -/*### BR7 & OR7 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */ - - BR7 & OR7 = 0x0000 0000 /* Not used */ - -/*### MAR */ -/*### Memory Address Register */ -/*### Chap. 16.4.7 */ -/*### Offset : 0x0000 0164 */ - - MA = External memory address - -/*### MCR */ -/*### Memory Command Register */ -/*### Chap. 16.4.5 */ -/*### Offset : 0x0000 0168 */ - - OP = xx /* Command op code */ - UM = 1 /* Select UPMA */ - MB = 001 /* Select CS1 */ - MCLF = xxxx /* Loop times */ - MAD = xx xxxx /* Memory array index */ - -/*### MAMR */ -/*### Machine A Mode Register */ -/*### Chap. 16.4.4 */ -/*### Offset : 0x0000 0170 */ - - PTA = 0101 1000 - PTAE = 1 /* Periodic timer A enabled */ - AMA = 010 - DSA = 00 - G0CLA = 000 - GPLA4DIS = 1 - RLFA = 0100 - WLFA = 0011 - TLFA = 0000 - - => 0x58A0 1430 - -/*### MBMR */ -/*### Machine B Mode Register */ -/*### Chap. 16.4.4 */ -/*### Offset : 0x0000 0174 */ - - PTA = 0100 1110 - PTAE = 0 /* Periodic timer B disabled */ - AMA = 000 - DSA = 00 - G0CLA = 000 - GPLA4DIS = 1 - RLFA = 0000 - WLFA = 0000 - TLFA = 0000 - - => 0x4E00 1000 - -/*### MSTAT */ -/*### Memory Status Register */ -/*### Chap. 16.4.3 */ -/*### Offset : 0x0000 0178 */ - - PER0~PER7 = Parity error - WPER = Write protection error - - => 0x0000 - -/*### MPTPR */ -/*### Memory Periodic Timer Prescaler Register */ -/*### Chap. 16.4.8 */ -/*### Offset : 0x0000 017A */ - - PTP = 0000 1000 /* Divide by 8 */ - - => 0x0800 - -/*### MDR */ -/*### Memory Data Register */ -/*### Chap. 16.4.6 */ -/*### Offset : 0x0000 017C */ - - MD = Memory data contains the RAM array word - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* TIMERS */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### TBREFx */ -/*### Timebase Reference Registers */ -/*### Chap. 11.9.2 */ -/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */ -/*### (Locked) */ - - TBREFF0 = 0xFFFF FFFF - TBREFF1 = 0xFFFF FFFF - ---------------------------------------------------------------------- - -/*### TBSCR */ -/*### Timebase Status and Control Registers */ -/*### Chap. 11.9.3 */ -/*### Offset : 0x0000 0200 */ -/*### (Locked) */ - - TBIRQ = 00000000 - REF0 = 0 - REF1 = 0 - REFE0 = 0 /* Reference interrupt disable */ - REFE1 = 0 - TBF = 1 - TBE = 1 /* Timebase enable */ - - => 0x0003 - ---------------------------------------------------------------------- - -/*### RTCSC */ -/*### Real-Time Clock Status and Control Registers */ -/*### Chap. 11.10.1 */ -/*### Offset : 0x0000 0220 */ -/*### (Locked) */ - - RTCIRQ = 00000000 - SEC = 1 - ALR = 0 - 38K = 0 /* PITRTCLK is driven by 32.768KHz */ - SIE = 0 - ALE = 0 - RTF = 0 - RTE = 1 /* Real-Time clock enabled */ - - => 0x0081 - ---------------------------------------------------------------------- - -/*### RTC */ -/*### Real-Time Clock Registers */ -/*### Chap. 11.10.2 */ -/*### Offset : 0x0000 0224 */ -/*### (Locked) */ - - RTC = Real time clock measured in second - ---------------------------------------------------------------------- - -/*### RTCAL */ -/*### Real-Time Clock Alarm Registers */ -/*### Chap. 11.10.3 */ -/*### Offset : 0x0000 022C */ -/*### (Locked) */ - - ALARM = 0xFFFF FFFF - ---------------------------------------------------------------------- - -/*### RTSEC */ -/*### Real-Time Clock Alarm Second Registers */ -/*### Chap. 11.10.4 */ -/*### Offset : 0x0000 0228 */ -/*### (Locked) */ - - COUNTER = Counter bits(fraction of a second) - ---------------------------------------------------------------------- - -/*### PISCR */ -/*### Periodic Interrupt Status and Control Register */ -/*### Chap. 11.11.1 */ -/*### Offset : 0x0000 0240 */ -/*### (Locked) */ - - PIRQ = 0 - PS = 0 /* Write 1 to clear */ - PIE = 0 - PITF = 1 - PTE = 0 /* PIT disabled */ - ---------------------------------------------------------------------- - -/*### PITC */ -/*### PIT Count Register */ -/*### Chap. 11.11.2 */ -/*### Offset : 0x0000 0244 */ -/*### (Locked) */ - - PITC = PIT count - ---------------------------------------------------------------------- - -/*### PITR */ -/*### PIT Register */ -/*### Chap. 11.11.3 */ -/*### Offset : 0x0000 0248 */ -/*### (Locked) */ - - PIT = PIT count /* Read only */ - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* CLOCKS */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - - ---------------------------------------------------------------------- - -/*### SCCR */ -/*### System Clock and Reset Control Register */ -/*### Chap. 15.6.1 */ -/*### Offset : 0x0000 0280 */ -/*### (Locked) */ - - COM = 11 /* Clock output disabled */ - TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */ - RTDIV = 0 /* The clock is divided by 4 */ - RTSEL = 0 /* OSCM(Crystal oscillator) is selected */ - CRQEN = 0 - PRQEN = 0 - EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */ - DFSYNC = 00 /* Divided by 1 (normal operation) */ - DFBRG = 00 /* Divided by 1 (normal operation) */ - DFNL = 000 - DFNH = 000 - - => 0x6200 0000 - ---------------------------------------------------------------------- - -/*### PLPRCR */ -/*### PLL, Low-Power, and Reset Control Register */ -/*### Chap. 15.6.2 */ -/*### Offset : 0x0000 0284 */ -/*### (Locked) */ - - MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */ - SPLSS = 0 - TEXPS = 0 - TMIST = 0 - CSRC = 0 /* The general system clock is generated by the DFNH field */ - LPM = 00 /* Normal high/normal low mode */ - CSR = 0 - LOLRE = 0 - FIOPD = 0 - - => 0x0050 0000 - ---------------------------------------------------------------------- - -/*### RSR */ -/*### Reset Status Register */ -/*### Chap. 12.2 */ -/*### Offset : 0x0000 0288 */ -/*### (Locked) */ - - EHRS = External hard reset - ESRS = External soft reset - LLRS = Loss-of-lock reset - SWRS = Software watchdog reset - CSRS = Check stop reset - DBHRS = Debug port hard reset - DBSRS = Debug port soft reset - JTRS = JTAG reset - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* DMA */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### SDSR */ -/*### SDMA Status Register */ -/*### Chap. 20.2.2 */ -/*### Offset : 0x0000 0908 */ - - SBER = 0 /* SDMA channel bus error */ - DSP2 = 0 /* DSP chain2 (Tx) interrupt */ - DSP1 = 0 /* DSP chain1 (Rx) interrupt */ - - => 0x00 - -/*### SDMR */ -/*### SDMA Mask Register */ -/*### Chap. 20.2.3 */ -/*### Offset : 0x0000 090C */ - - SBER = 0 - DSP2 = 0 - DSP1 = 0 /* All interrupts are masked */ - - => 0x00 - -/*### SDAR */ -/*### SDMA Address Register */ -/*### Chap. 20.2.4 */ -/*### Offset : 0x0000 0904 */ - - AR = 0xxxxx xxxx /* current system address */ - - => 0xFA20 23AC - -/*### IDSRx */ -/*### IDMA Status Register */ -/*### Chap. 20.3.3.2 */ -/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */ - - AD = 0 - DONE = 0 - OB = 0 - - => 0x00 - -/*### IDMRx */ -/*### IDMA Mask Register */ -/*### Chap. 20.3.3.3 */ -/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */ - - AD = 0 - DONE = 0 - OB = 0 diff --git a/board/RPXlite/README.PlanetCore b/board/RPXlite/README.PlanetCore deleted file mode 100644 index b73c5f5a87..0000000000 --- a/board/RPXlite/README.PlanetCore +++ /dev/null @@ -1,163 +0,0 @@ -After several heart-struck failure, I got one workable way to program -each other in FLASH between PlanetCore and U-Boot. - -Hardware Platform : RPXlite DW(EP 823 H1 DW) - -1. From U-Boot to PlanetCore - -Utilities : PlanetCore Boot Loader - PCL200.mot - -[root@sam tftpboot]# ppc_8xx-objcopy -O ppcboot -PCL200.mot pcl200.bin - -[Target Operation] -u-boot>t 100000 pcl200.bin -u-boot>go 0x100000 -## Starting application at 0x00100000 ... - -MPC8xx PlanetCore Flash Burner v2.00 -Copyright 2001 Embedded Planet. All rights reserved. - -Construct Flash Device.....done. - - -Program MPC8xx PlanetCore Boot Loader v2.00 -Built Sep 19, 2001 at 14:34:42 -Image located from FC000000 to FC01B5D1. -(Skipping an image, only loading low boot image) - -Low boot board detected, skipping high boot image. -Erasing, programming and verifying will start in 20 -seconds -Press P to start immediately or ESC to cancel -Press Space or Enter for more options. -.............. - -Erasing -Programming -FLASH programmed successfully! -Press R to induce a hard reset - -MPC8xx PlanetCore Boot Loader v2.00 -Copyright 2001 Embedded Planet. All rights reserved. -DRAM available size = 64 MB -wvCV -DRAM OK -> - -2. From PlanetCore to U-Boot - -Utilities : PlanetCore FLASH Burner - PCB200.mot - -Use Flash Burner to finish the work: - -First, TFTP the U-Boot image file to RAM; For example, -RPXlite_DW.bin to 0x400000 -Second, TFTP FLASH Burner to RAM; For example, -0x100000 -Third, run the FLASH Burner and Program the U-Boot -image into the correct location in FLASH. - -[Target Operation] -MPC8xx PlanetCore Boot Loader v2.00 -Copyright 2001 Embedded Planet. All rights reserved. -DRAM available size = 64 MB -wvCV -DRAM OK ->t -Load using tftp via Ethernet -Enter server IP address <172.16.115.6> : -Enter server filename <PCL200.mot> : RPXlite_DW.bin -Enter (B)inary or (S)record input mode <S> : B -Enter address offset : <00400000 hex> : - -Total bytes = 120096 in 232184 uSecs -Loaded addresses 00400000 through 0041D51F. -Start address = 00400000 ->t -Load using tftp via Ethernet -Enter server IP address <172.16.115.6> : -Enter server filename <RPXlite_DW.bin> : PCB200.mot -Enter (B)inary or (S)record input mode <B> : S -Enter address offset : <00000000 hex> : -.512.1024..2048....4096..... -Total bytes = 326280 in 2570249 uSecs -Loaded addresses 00100000 through 0011BB51. -Start address = 00100000 ->go -[Go 00100000] - -MPC8xx PlanetCore Flash Burner v2.00 -Copyright 2001 Embedded Planet. All rights reserved. - -Construct Flash Device.....done. - -Bad start address -Start = 0xFFFFFFFF, target = 0xFFFFFFFF, length = -0xFFFFFFFF -Forcing Menu Interface - -h[elp] Show commands. -c[ode] Show information on code to be loaded. -di[splay] Display all flash sections. -du[mp] Dump memory. d ? for more info. -e[rase] Erase flash sections. -f[ill] Fill flash sections. -im[age] Toggle load high, low, or both flash -images. -in[fo] Show flash information. -ma[p] Show memory map. -mo[dify] Modify memory. m ? for more info. -p[rogram] Erase, program, and verify now. -reset Restart the loader. -s[how] Show flash sections to erase and program. -t[est] Test flash sections. -q[uit] Quit without programming. -#program 400000 ff000000 1D51F -doProgram( 400000 ff000000 1D51F ) - -Start = 0x00400000, target = 0xFF000000, length = -0x0001D51F -Erasing sector 0xFF000000, length 0x008000. -Erasing sector 0xFF008000, length 0x008000. -Erasing sector 0xFF010000, length 0x008000. -Erasing sector 0xFF018000, length 0x008000. -Programming FF000000 through FF01D51E -FLASH programmed successfully! -Press R to induce a hard reset - -Forcing Hard Reset by MachineCheck and -ResetOnCheckstop... - -U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) - -CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB -D-Cache -Board: RPXlite_DW -DRAM: 64 MB -FLASH: 16 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET -u-boot> - -------------------------------------------------- - -Well, sometimes network function of PlanetCore couldn't work when -switching from U-Boot to PlanetCore. For example, you couldn't -download a file from HOST PC via TFTP. Don't worry, just restart your -HOST PC and everything would work as smooth as clockwork. I don't -know the reason WHY:-) - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Merry Christmas and Happy New Year! - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -===== -Best regards, - -Sam diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c deleted file mode 100644 index 08575a4930..0000000000 --- a/board/RPXlite/RPXlite.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * DRAM related UPMA register values are modified. - * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS - */ - -#include <common.h> -#include <mpc8xx.h> - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = { - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, - 0x0CFFCC00, 0x33FFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXlite\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size10; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000000; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 10 column mode - */ - - size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - return (size10); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} diff --git a/board/RPXlite/flash.c b/board/RPXlite/flash.c deleted file mode 100644 index 21b11d4e90..0000000000 --- a/board/RPXlite/flash.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -/* volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; */ -/* volatile memctl8xx_t *memctl = &immap->im_memctl; */ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ -/* - size_b0 = flash_get_size((vu_long *)FLASH_BASE_DEBUG, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } -*/ - /* Remap FLASH according to real size */ -/*%%% - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; -%%%*/ - /* Re-do sizing to get full correct info */ - - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0x00AA00AA ; - addr[0x555] = 0x00550055 ; - addr[0xAAA] = 0x00900090 ; - - value = addr[0] ; - - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - - switch (value & 0x00FF00FF) { - case (AMD_ID_LV400T & 0x00FF00FF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & 0x00FF00FF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & 0x00FF00FF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & 0x00FF00FF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /*%%% Size doubled by yooth */ - break; /* => 4 MB */ - - case (AMD_ID_LV160T & 0x00FF00FF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & 0x00FF00FF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /*%%% sector start address modified */ - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/RPXlite/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug deleted file mode 100644 index b9c84c77d6..0000000000 --- a/board/RPXlite/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/altera/common/AMDLV065D.c b/board/altera/common/AMDLV065D.c deleted file mode 100644 index eaa6b98025..0000000000 --- a/board/altera/common/AMDLV065D.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#if defined(CONFIG_NIOS) -#include <nios.h> -#else -#include <asm/io.h> -#endif - -#define SECTSZ (64 * 1024) -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------*/ -unsigned long flash_init (void) -{ - int i; - unsigned long addr; - flash_info_t *fli = &flash_info[0]; - - fli->size = CONFIG_SYS_FLASH_SIZE; - fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; - - addr = CONFIG_SYS_FLASH_BASE; - for (i = 0; i < fli->sector_count; ++i) { - fli->start[i] = addr; - addr += SECTSZ; - fli->protect[i] = 1; - } - - return (CONFIG_SYS_FLASH_SIZE); -} -/*--------------------------------------------------------------------*/ -void flash_print_info (flash_info_t * info) -{ - int i, k; - int erased; - unsigned long *addr; - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - - /* Check if whole sector is erased */ - erased = 1; - addr = (unsigned long *) info->start[i]; - for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) { - if ( readl(addr++) != (unsigned long)-1) { - erased = 0; - break; - } - } - - /* Print the info */ - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*-------------------------------------------------------------------*/ - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - unsigned char *addr = (unsigned char *) info->start[0]; - unsigned char *addr2; - int prot, sect; - ulong start; - - /* Some sanity checking */ - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* It's ok to erase multiple sectors provided we don't delay more - * than 50 usec between cmds ... at which point the erase time-out - * occurs. So don't go and put printf() calls in the loop ... it - * won't be very helpful ;-) - */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (unsigned char *) info->start[sect]; - writeb (0xaa, addr); - writeb (0x55, addr); - writeb (0x80, addr); - writeb (0xaa, addr); - writeb (0x55, addr); - writeb (0x30, addr2); - /* Now just wait for 0xff & provide some user - * feedback while we wait. - */ - start = get_timer (0); - while ( readb (addr2) != 0xff) { - udelay (1000 * 1000); - putc ('.'); - if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("timeout\n"); - return 1; - } - } - } - } - printf ("\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - - vu_char *cmd = (vu_char *) info->start[0]; - vu_char *dst = (vu_char *) addr; - unsigned char b; - ulong start; - - while (cnt) { - /* Check for sufficient erase */ - b = *src; - if ((readb (dst) & b) != b) { - printf ("%02x : %02x\n", readb (dst), b); - return (2); - } - - writeb (0xaa, cmd); - writeb (0x55, cmd); - writeb (0xa0, cmd); - writeb (b, dst); - - /* Verify write */ - start = get_timer (0); - while (readb (dst) != b) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return 1; - } - } - dst++; - src++; - cnt--; - } - - return (0); -} diff --git a/board/altera/common/flash.c b/board/altera/common/flash.c deleted file mode 100644 index 8f56a30b48..0000000000 --- a/board/altera/common/flash.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <nios.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*--------------------------------------------------------------------*/ -void flash_print_info (flash_info_t * info) -{ - int i, k; - unsigned long size; - int erased; - volatile unsigned char *flash; - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - - /* Check if whole sector is erased */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned char *) info->start[i]; - for (k = 0; k < size; k++) { - if (*flash++ != 0xff) { - erased = 0; - break; - } - } - - /* Print the info */ - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", info->start[i], erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*-------------------------------------------------------------------*/ - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int prot, sect; - unsigned oldpri; - ulong start; - - /* Some sanity checking */ - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - for (sect = s_first; sect <= s_last; sect++) { - printf("- Erase: Sect: %i @ 0x%08x\n", sect, info->start[sect]); - } -#endif - - /* NOTE: disabling interrupts on Nios can be very bad since it - * also disables the LO_LIMIT exception. It's better here to - * set the interrupt priority to 3 & restore it when we're done. - */ - oldpri = ipri (3); - - /* It's ok to erase multiple sectors provided we don't delay more - * than 50 usec between cmds ... at which point the erase time-out - * occurs. So don't go and put printf() calls in the loop ... it - * won't be very helpful ;-) - */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - *addr = 0xaa; - *addr = 0x55; - *addr = 0x80; - *addr = 0xaa; - *addr = 0x55; - *addr2 = 0x30; - /* Now just wait for 0xff & provide some user - * feedback while we wait. Here we have to grant - * timer interrupts. Otherwise get_timer() can't - * work right. */ - ipri(oldpri); - start = get_timer (0); - while (*addr2 != 0xff) { - udelay (1000 * 1000); - putc ('.'); - if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("timeout\n"); - return 1; - } - } - oldpri = ipri (3); /* disallow non important irqs again */ - } - } - - printf ("\n"); - - /* Restore interrupt priority */ - ipri (oldpri); - - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - - vu_char *cmd = (vu_char *) info->start[0]; - vu_char *dst = (vu_char *) addr; - unsigned char b; - unsigned oldpri; - ulong start; - - while (cnt) { - /* Check for sufficient erase */ - b = *src; - if ((*dst & b) != b) { - printf ("%02x : %02x\n", *dst, b); - return (2); - } - - /* Disable interrupts other than window underflow - * (interrupt priority 2) - */ - oldpri = ipri (3); - *cmd = 0xaa; - *cmd = 0x55; - *cmd = 0xa0; - *dst = b; - - /* Verify write */ - start = get_timer (0); - while (*dst != b) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - ipri (oldpri); - return 1; - } - } - dst++; - src++; - cnt--; - ipri (oldpri); - } - - return (0); -} diff --git a/board/broadcom/bcm28155_ap/Makefile b/board/broadcom/bcm28155_ap/Makefile index b18785a078..4bb9e70823 100644 --- a/board/broadcom/bcm28155_ap/Makefile +++ b/board/broadcom/bcm28155_ap/Makefile @@ -4,4 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += $(BOARD).o +obj-y += bcm28155_ap.o diff --git a/board/compulab/cm_t335/Makefile b/board/compulab/cm_t335/Makefile index 0e6e96e039..b405caaa5c 100644 --- a/board/compulab/cm_t335/Makefile +++ b/board/compulab/cm_t335/Makefile @@ -6,5 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += $(BOARD).o +obj-y += cm_t335.o obj-$(CONFIG_SPL_BUILD) += mux.o spl.o diff --git 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0x85, 0x97, 0xdf, 0x7e, 0x74, -0x47, 0x3b, 0x23, 0x96, 0xf7, 0x17, 0xd5, 0x3f, -0xfe, 0xe9, 0x5b, 0x9f, 0x02, 0x83, 0xe0, 0xfc, -0xc6, 0x7f, 0xbb, 0xa3, 0x9f, 0xfe, 0x29, 0xa1, -0x84, 0x12, 0x4a, 0x28, 0xa1, 0x84, 0x12, 0x4a, -0x28, 0xa1, 0x84, 0x12, 0xca, 0xef, 0xbb, 0xf0, -0xbd, 0x03, 0x0d, 0xf7, 0x0e, 0xa1, 0x84, 0x12, -0x4a, 0x28, 0xa1, 0x84, 0x12, 0x4a, 0x28, 0xa1, -0x84, 0x12, 0x4a, 0x75, 0xe1, 0x7b, 0x87, 0x9a, -0x70, 0xef, 0x10, 0x4a, 0x28, 0xa1, 0x84, 0x12, -0x4a, 0x28, 0xa1, 0x84, 0x12, 0x4a, 0x28, 0xa1, -0x54, 0x17, 0xbe, 0x77, 0xd0, 0xf8, 0xde, 0xe1, -0xff, 0xba, 0x29, 0xa1, 0x84, 0x12, 0x4a, 0x28, -0xa1, 0x84, 0x12, 0x4a, 0x28, 0xa1, 0x84, 0x12, -0xca, 0x17, 0x28, 0x29, 0x16, 0x72, 0x19, 0x5e, -0xf9, 0x20, 0x05, 0x36, 0xf3, 0x62, 0x8a, 0xa4, -0xc0, 0xbc, 0xe8, 0xf3, 0x04, 0xe7, 0x6f, 0xd5, -0x14, 0xe4, 0x89, 0xff, 0xcc, 0xe3, 0x77, 0x15, -0xd7, 0xfb, 0x5f, 0x2b, 0x92, 0xad, 0x46, 0xf1, -0x33, 0x01, 0x00, diff --git a/board/dave/common/fpga.c b/board/dave/common/fpga.c deleted file mode 100644 index 0869ca0718..0000000000 --- a/board/dave/common/fpga.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <command.h> - -/* ------------------------------------------------------------------------- */ - -#ifdef FPGA_DEBUG -#define DBG(x...) printf(x) -#else -#define DBG(x...) -#endif /* DEBUG */ - -#define MAX_ONES 226 - -#ifdef CONFIG_SYS_FPGA_PRG -# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output)*/ -# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */ -# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */ -# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */ -# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */ -#else -# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ -# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#endif - -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ - -#define SET_FPGA(data) out32(GPIO0_OR, data) - -#define FPGA_WRITE_1 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG); /* set data to 0 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#if 0 -static int fpga_boot (unsigned char *fpgadata, int size) -{ - int i, index, len; - int count; - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - int j; -#else - unsigned char b; - int bit; -#endif - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - DBG ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* search for preamble 0xFFFFFFFF */ - while (1) { - if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) - && (fpgadata[index + 2] == 0xff) - && (fpgadata[index + 3] == 0xff)) - break; /* preamble found */ - else - index++; - } -#else - /* search for preamble 0xFF2X */ - for (index = 0; index < size - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x30)) - break; - } - index += 2; -#endif - - DBG ("FPGA: configdata starts at position 0x%x\n", index); - DBG ("FPGA: length of fpga-data %d\n", size - index); - - /* - * Setup port pins for fpga programming - */ - out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */ - out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */ - - DBG ("%s, ", - ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", - ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA (FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA init line low */ - count = 0; - while (in32 (GPIO0_IR) & FPGA_INIT) { - udelay (1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } - } - - DBG ("%s, ", - ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", - ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* deassert PROGRAM* */ - SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA); - - /* Wait for FPGA end of init period . */ - count = 0; - while (!(in32 (GPIO0_IR) & FPGA_INIT)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } - } - - DBG ("%s, ", - ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", - ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - DBG ("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* - * Load uncompressed image into fpga - */ - for (i = index; i < size; i++) { - for (j = 0; j < 8; j++) { - if ((fpgadata[i] & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - fpgadata[i] <<= 1; - } - } -#else /* ! CONFIG_SYS_FPGA_SPARTAN2 */ - /* send 0xff 0x20 */ - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - - /* - ** Bit_DeCompression - ** Code 1 .. maxOnes : n '1's followed by '0' - ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' - ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' - ** 255 : '1' - */ - - for (i = index; i < size; i++) { - b = fpgadata[i]; - if ((b >= 1) && (b <= MAX_ONES)) { - for (bit = 0; bit < b; bit++) { - FPGA_WRITE_1; - } - FPGA_WRITE_0; - } else if (b == (MAX_ONES + 1)) { - for (bit = 1; bit < b; bit++) { - FPGA_WRITE_1; - } - } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { - for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { - FPGA_WRITE_0; - } - FPGA_WRITE_1; - } else if (b == 255) { - FPGA_WRITE_1; - } - } -#endif /* CONFIG_SYS_FPGA_SPARTAN2 */ - - DBG ("%s, ", - ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", - ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); - - /* - * Check if fpga's DONE signal - correctly booted ? - */ - - /* Wait for FPGA end of programming period . */ - count = 0; - while (!(in32 (GPIO0_IR) & FPGA_DONE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } - } - - DBG ("FPGA: Booting successful!\n"); - return 0; -} -#endif /* 0 */ diff --git a/board/dave/common/pci.c b/board/dave/common/pci.c deleted file mode 100644 index 71bc8ac096..0000000000 --- a/board/dave/common/pci.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <pci.h> - - -u_long pci9054_iobase; - - -#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */ -#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */ - - -/*-----------------------------------------------------------------------------+ -| Subroutine: pci9054_read_config_dword -| Description: Read a PCI configuration register -| Inputs: -| hose PCI Controller -| dev PCI Bus+Device+Function number -| offset Configuration register number -| value Address of the configuration register value -| Return value: -| 0 Successful -+-----------------------------------------------------------------------------*/ -int pci9054_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32* value) -{ - unsigned long conAdrVal; - unsigned long val; - - /* generate coded value for CON_ADR register */ - conAdrVal = dev | (offset & 0xfc) | 0x80000000; - - /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */ - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - /* Note: *pResult comes back as -1 if machine check happened */ - val = in32r(PCI_PRIMARY_CDR); - - *value = (unsigned long) val; - - out32r(PCI_PRIMARY_CAR, 0); - - if ((*(unsigned long *)0x50000304) & 0x60000000) - { - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - } - - return 0; -} - -/*-----------------------------------------------------------------------------+ -| Subroutine: pci9054_write_config_dword -| Description: Write a PCI configuration register. -| Inputs: -| hose PCI Controller -| dev PCI Bus+Device+Function number -| offset Configuration register number -| Value Configuration register value -| Return value: -| 0 Successful -| Updated for pass2 errata #6. Need to disable interrupts and clear the -| PCICFGADR reg after writing the PCICFGDATA reg. -+-----------------------------------------------------------------------------*/ -int pci9054_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - unsigned long conAdrVal; - - conAdrVal = dev | (offset & 0xfc) | 0x80000000; - - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - out32r(PCI_PRIMARY_CDR, value); - - out32r(PCI_PRIMARY_CAR, 0); - - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - - return (0); -} - -/*----------------------------------------------------------------------- - */ - -#ifdef CONFIG_DASA_SIM -static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *_) -{ - unsigned int iobase; - unsigned short status = 0; - unsigned char timer; - - /* - * Configure PLX PCI9054 - */ - pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status); - status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; - pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status); - - /* Check the latency timer for values >= 0x60. - */ - pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); - if (timer < 0x60) - { - pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); - } - - /* Set I/O base register. - */ - pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE); - pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); - - pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); - - if (pci9054_iobase == 0xffffffff) - { - printf("Error: Can not set I/O base register.\n"); - return; - } -} -#endif - -static struct pci_config_table pci9054_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN), - pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE, - CONFIG_SYS_ETH_IOBASE, - PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, -#ifdef CONFIG_DASA_SIM - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN), - pci_dasa_sim_config_pci9054 }, -#endif -#endif - { } -}; - -static struct pci_controller pci9054_hose = { - config_table: pci9054_config_table, -}; - -void pci_init(void) -{ - struct pci_controller *hose = &pci9054_hose; - - /* - * Register the hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - 0x00000000, 0x00000000, 0x01000000, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI Memory space */ - pci_set_region(hose->regions + 1, - 0x00000000, 0xc0000000, 0x10000000, - PCI_REGION_MEM); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - pci9054_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - pci9054_write_config_dword); - - hose->region_count = 2; - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); -} diff --git a/board/esd/adciop/Makefile b/board/esd/adciop/Makefile deleted file mode 100644 index d0e264de92..0000000000 --- a/board/esd/adciop/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = adciop.o flash.o ../common/misc.o ../common/pci.o diff --git a/board/esd/adciop/adciop.c b/board/esd/adciop/adciop.c deleted file mode 100644 index b3d637e0a2..0000000000 --- a/board/esd/adciop/adciop.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include "adciop.h" - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -/* ------------------------------------------------------------------------- */ - - -int board_early_init_f (void) -{ - /* - * Set port pin in escc2 to keep living, and configure user led output - */ - *(unsigned char *) 0x2000033e = 0x77; /* ESCC2: PCR bit3=pwr on, bit7=led out */ - *(unsigned char *) 0x2000033c = 0x88; /* ESCC2: PVR pwr on, led off */ - - /* - * Init pci regs - */ - *(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */ - *(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */ - *(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */ - *(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */ - *(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */ - *(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */ - *(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */ - - return 0; -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (!i || strncmp (str, "ADCIOP", 6)) { - puts ("### No HW ID - assuming ADCIOP\n"); - return (1); - } - - puts (str); - - putc ('\n'); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - return (16 * 1024 * 1024); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/esd/adciop/adciop.h b/board/esd/adciop/adciop.h deleted file mode 100644 index 75e7950bcd..0000000000 --- a/board/esd/adciop/adciop.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/adciop/flash.c b/board/esd/adciop/flash.c deleted file mode 100644 index b1db12ecc8..0000000000 --- a/board/esd/adciop/flash.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - if (size_b1 > size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM+size_b0-monitor_flash_len, - FLASH_BASE0_PRELIM+size_b0-1, - &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(FLASH_BASE0_PRELIM + size_b0), - &flash_info[1]); - - flash_get_offsets (FLASH_BASE0_PRELIM + size_b0, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM+size_b0+size_b1-monitor_flash_len, - FLASH_BASE0_PRELIM+size_b0+size_b1-1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - flash_protect(FLAG_PROTECT_CLEAR, - FLASH_BASE0_PRELIM+size_b0-monitor_flash_len, - FLASH_BASE0_PRELIM+size_b0-1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} diff --git a/board/esd/dasa_sim/Makefile b/board/esd/dasa_sim/Makefile deleted file mode 100644 index eb9f5f86d0..0000000000 --- a/board/esd/dasa_sim/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = dasa_sim.o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c deleted file mode 100644 index 91916247d6..0000000000 --- a/board/esd/dasa_sim/cmd_dasa_sim.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <pci.h> -#include <asm/io.h> - -#define OK 0 -#define ERROR (-1) - -extern u_long pci9054_iobase; - - -/*************************************************************************** - * - * Routines for PLX PCI9054 eeprom access - * - */ - -static unsigned int PciEepromReadLongVPD (int offs) -{ - unsigned int value; - unsigned int ret; - int count; - - pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, - (offs << 16) | 0x0003); - count = 0; - - for (;;) { - udelay (10 * 1000); - pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret); - if ((ret & 0x80000000) != 0) { - break; - } else { - count++; - if (count > 10) { - printf ("\nTimeout: ret=%08x - Please try again!\n", ret); - break; - } - } - } - - pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value); - - return value; -} - - -static int PciEepromWriteLongVPD (int offs, unsigned int value) -{ - unsigned int ret; - int count; - - pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value); - pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, - (offs << 16) | 0x80000003); - count = 0; - - for (;;) { - udelay (10 * 1000); - pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret); - if ((ret & 0x80000000) == 0) { - break; - } else { - count++; - if (count > 10) { - printf ("\nTimeout: ret=%08x - Please try again!\n", ret); - break; - } - } - } - - return true; -} - - -static void showPci9054 (void) -{ - int val; - int l, i; - - /* read 9054-values */ - for (l = 0; l < 6; l++) { - printf ("%02x: ", l * 0x10); - for (i = 0; i < 4; i++) { - pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, - l * 16 + i * 4, - (unsigned int *)&val); - printf ("%08x ", val); - } - printf ("\n"); - } - printf ("\n"); - - for (l = 0; l < 7; l++) { - printf ("%02x: ", l * 0x10); - for (i = 0; i < 4; i++) - printf ("%08x ", - PciEepromReadLongVPD ((i + l * 4) * 4)); - printf ("\n"); - } - printf ("\n"); -} - - -static void updatePci9054 (void) -{ - /* - * Set EEPROM write-protect register to 0 - */ - out_be32 ((void *)(pci9054_iobase + 0x0c), - in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff); - - /* Long Serial EEPROM Load Registers... */ - PciEepromWriteLongVPD (0x00, 0x905410b5); - PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */ - PciEepromWriteLongVPD (0x08, 0x28140100); - - PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */ - PciEepromWriteLongVPD (0x10, 0x00000000); - - /* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */ - PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */ - PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */ - - PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */ - PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */ - - PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */ - PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */ - - PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */ - - PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */ - PciEepromWriteLongVPD (0x34, 0x00000000); - PciEepromWriteLongVPD (0x38, 0x00000000); - - PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */ - PciEepromWriteLongVPD (0x40, 0x00000000); - - /* Extra Long Serial EEPROM Load Registers... */ - PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */ - - /* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */ - /* Offset to LAS1: Group 1: 0x00040000 */ - /* Group 2: 0x00080000 */ - /* Group 3: 0x000c0000 */ - PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */ - PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */ - PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */ - - PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */ - - printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n"); -} - - -static void clearPci9054 (void) -{ - /* - * Set EEPROM write-protect register to 0 - */ - out_be32 ((void *)(pci9054_iobase + 0x0c), - in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff); - - /* Long Serial EEPROM Load Registers... */ - PciEepromWriteLongVPD (0x00, 0xffffffff); - PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */ - - printf ("Finished clearing PLX PCI9054 EEPROM!\n"); -} - - -/* ------------------------------------------------------------------------- */ -int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc, - char * const argv[]) -{ - if (strcmp (argv[1], "info") == 0) { - showPci9054 (); - return 0; - } - - if (strcmp (argv[1], "update") == 0) { - updatePci9054 (); - return 0; - } - - if (strcmp (argv[1], "clear") == 0) { - clearPci9054 (); - return 0; - } - - return cmd_usage(cmdtp); -} - -U_BOOT_CMD( - pci9054, 3, 1, do_pci9054, - "PLX PCI9054 EEPROM access", - "pci9054 info - print EEPROM values\n" - "pci9054 update - updates EEPROM with default values" -); - -/* ------------------------------------------------------------------------- */ diff --git a/board/esd/dasa_sim/dasa_sim.c b/board/esd/dasa_sim/dasa_sim.c deleted file mode 100644 index b779a09e82..0000000000 --- a/board/esd/dasa_sim/dasa_sim.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include "dasa_sim.h" - -/* ------------------------------------------------------------------------- */ - -#undef FPGA_DEBUG - -#define _NOT_USED_ 0xFFFFFFFF - -/* ------------------------------------------------------------------------- */ - -/* fpga configuration data - generated by bit2inc */ -static unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -#define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */ -#define LOAD_LONG(a) a - - -/****************************************************************************** - * - * sysFpgaBoot - Load fpga-image into fpga - * - */ -static int fpgaBoot (void) -{ - int i, j, index, len; - unsigned char b; - int imageSize; - - imageSize = sizeof (fpgadata); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - index += len + 3; - } - - /* search for preamble 0xFF2X */ - for (index = 0; index < imageSize - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x20)) - break; - } - - /* enable cs1 instead of user0... */ - *(unsigned long *) 0x50000084 &= ~0x00000002; - -#ifdef FPGA_DEBUG - printf ("%s\n", - ((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ? - "NOT DONE" : "DONE"); -#endif - - /* init fpga by asserting and deasserting PROGRAM* (USER2)... */ - *(unsigned long *) 0x50000084 &= ~0x00000400; - udelay (FPGA_PRG_SLEEP * 1000); - - *(unsigned long *) 0x50000084 |= 0x00000400; - udelay (FPGA_PRG_SLEEP * 1000); - -#ifdef FPGA_DEBUG - printf ("%s\n", - ((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ? - "NOT DONE" : "DONE"); -#endif - - /* cs1: disable burst, disable ready */ - *(unsigned long *) 0x50000114 &= ~0x00000300; - - /* cs1: set write timing */ - *(unsigned long *) 0x50000118 |= 0x00010900; - - /* write configuration-data into fpga... */ - for (i = index; i < imageSize; i++) { - b = fpgadata[i]; - for (j = 0; j < 8; j++) { - *(unsigned long *) 0x30000000 = - ((b & 0x80) == 0x80) - ? LOAD_LONG (0x03030101) - : LOAD_LONG (0x02020000); - b <<= 1; - } - } - -#ifdef FPGA_DEBUG - printf ("%s\n", - ((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ? - "NOT DONE" : "DONE"); -#endif - - /* set cs1 to 32 bit data-width, disable burst, enable ready */ - *(unsigned long *) 0x50000114 |= 0x00000202; - *(unsigned long *) 0x50000114 &= ~0x00000100; - - /* cs1: set iop access to little endian */ - *(unsigned long *) 0x50000114 &= ~0x00000010; - - /* cs1: set read and write timing */ - *(unsigned long *) 0x50000118 = 0x00010000; - *(unsigned long *) 0x5000011c = 0x00010001; - -#ifdef FPGA_DEBUG - printf ("%s\n", - ((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ? - "NOT DONE" : "DONE"); -#endif - - /* wait for 30 ms... */ - udelay (30 * 1000); - /* check if fpga's DONE signal - correctly booted ? */ - if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0) - return -1; - - return 0; -} - - -int board_early_init_f (void) -{ - /* - * Init pci regs - */ - *(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */ - *(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */ - *(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */ - *(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */ - *(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */ - *(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */ - *(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */ - - return 0; -} - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - int index; - int len; - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - int fpga; - unsigned short val; - - puts ("Board: "); - - /* - * Boot onboard FPGA - */ - fpga = fpgaBoot (); - - if (!i || strncmp (str, "DASA_SIM", 8)) { - puts ("### No HW ID - assuming DASA_SIM"); - } - - puts (str); - - if (fpga == 0) { - val = *(unsigned short *) 0x30000202; - printf (" (Id=%d Version=%d Revision=%d)", - (val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1); - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("%s ", &(fpgadata[index + 1])); - index += len + 3; - } - } else { - puts ("\nFPGA: Booting failed!"); - } - - putc ('\n'); - - return 0; -} - -phys_size_t initdram (int board_type) -{ - return (16 * 1024 * 1024); -} diff --git a/board/esd/dasa_sim/dasa_sim.h b/board/esd/dasa_sim/dasa_sim.h deleted file mode 100644 index 75e7950bcd..0000000000 --- a/board/esd/dasa_sim/dasa_sim.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/dasa_sim/eeprom.c b/board/esd/dasa_sim/eeprom.c deleted file mode 100644 index 1fc78decd2..0000000000 --- a/board/esd/dasa_sim/eeprom.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/io.h> - -#define EEPROM_CAP 0x50000358 -#define EEPROM_DATA 0x5000035c - - -unsigned int eepromReadLong(int offs) -{ - unsigned int value; - unsigned short ret; - int count; - - out_be16((void *)EEPROM_CAP, offs); - - count = 0; - - for (;;) - { - count++; - ret = in_be16((void *)EEPROM_CAP); - - if ((ret & 0x8000) != 0) - break; - } - - value = in_be32((void *)EEPROM_DATA); - - return value; -} - - -unsigned char eepromReadByte(int offs) -{ - unsigned int valueLong; - unsigned char *ptr; - - valueLong = eepromReadLong(offs & ~3); - ptr = (unsigned char *)&valueLong; - - return ptr[offs & 3]; -} - - -void eepromWriteLong(int offs, unsigned int value) -{ - unsigned short ret; - int count; - - count = 0; - - out_be32((void *)EEPROM_DATA, value); - out_be16((void *)EEPROM_CAP, 0x8000 + offs); - - for (;;) - { - count++; - ret = in_be16((void *)EEPROM_CAP); - - if ((ret & 0x8000) == 0) - break; - } -} - - -void eepromWriteByte(int offs, unsigned char valueByte) -{ - unsigned int valueLong; - unsigned char *ptr; - - valueLong = eepromReadLong(offs & ~3); - ptr = (unsigned char *)&valueLong; - - ptr[offs & 3] = valueByte; - - eepromWriteLong(offs & ~3, valueLong); -} - - -void i2c_read (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - int len2, ptr; - - /* printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */ - - ptr = *(short *)addr; - - /* - * Read till lword boundary - */ - len2 = 4 - (*(short *)addr & 0x0003); - for (i=0; i<len2; i++) - { - *buffer++ = eepromReadByte(ptr++); - } - - /* - * Read all lwords - */ - len2 = (len - len2) >> 2; - for (i=0; i<len2; i++) - { - *(unsigned int *)buffer = eepromReadLong(ptr); - buffer += 4; - ptr += 4; - } - - /* - * Read last bytes - */ - len2 = (*(short *)addr + len) & 0x0003; - for (i=0; i<len2; i++) - { - *buffer++ = eepromReadByte(ptr++); - } -} - -void i2c_write (uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - int len2, ptr; - - /* printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */ - - ptr = *(short *)addr; - - /* - * Write till lword boundary - */ - len2 = 4 - (*(short *)addr & 0x0003); - for (i=0; i<len2; i++) - { - eepromWriteByte(ptr++, *buffer++); - } - - /* - * Write all lwords - */ - len2 = (len - len2) >> 2; - for (i=0; i<len2; i++) - { - eepromWriteLong(ptr, *(unsigned int *)buffer); - buffer += 4; - ptr += 4; - } - - /* - * Write last bytes - */ - len2 = (*(short *)addr + len) & 0x0003; - for (i=0; i<len2; i++) - { - eepromWriteByte(ptr++, *buffer++); - } -} diff --git a/board/esd/dasa_sim/flash.c b/board/esd/dasa_sim/flash.c deleted file mode 100644 index 05691d0b86..0000000000 --- a/board/esd/dasa_sim/flash.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -monitor_flash_len, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/dasa_sim/fpgadata.c b/board/esd/dasa_sim/fpgadata.c deleted file mode 100644 index f54ef1c35a..0000000000 --- a/board/esd/dasa_sim/fpgadata.c +++ /dev/null @@ -1,3903 +0,0 @@ -0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, -0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d, -0x61, 0x63, 0x6d, 0x30, 0x30, 0x30, 0x35, 0x64, -0x2e, 0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b, -0x73, 0x33, 0x30, 0x78, 0x6c, 0x74, 0x71, 0x31, -0x34, 0x34, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30, -0x30, 0x30, 0x2f, 0x30, 0x37, 0x2f, 0x31, 0x30, -0x00, 0x64, 0x00, 0x09, 0x31, 0x39, 0x3a, 0x32, -0x37, 0x3a, 0x33, 0x38, 0x00, 0x65, 0x00, 0x00, -0x79, 0xaa, 0xff, 0x20, 0x3c, 0xd4, 0x9f, 0x5b, -0xff, 0x7e, 0xde, 0xee, 0xbd, 0xaa, 0xfe, 0xbf, -0x9e, 0xff, 0xfb, 0xfe, 0x5f, 0xbf, 0xed, 0xab, -0xdb, 0xbe, 0xe5, 0xfb, 0xfe, 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0xef, -0xfb, 0xfe, 0xff, 0xbf, 0xef, 0xfb, 0xfe, 0xff, -0xbf, 0xef, 0xfb, 0xfe, 0xcf, 0xff, 0xcf, 0xf3, -0xfc, 0xff, 0xbf, 0xef, 0xfb, 0xfc, 0xff, 0x3f, -0xef, 0xf3, 0xfc, 0xff, 0x3f, 0xb3, 0xfc, 0xff, -0x3f, 0xef, 0xf3, 0xfc, 0xff, 0x3f, 0xef, 0xf3, -0xfe, 0xff, 0x3f, 0xef, 0xff, 0xfd, 0xff, 0xff, -0xbf, 0xef, 0xff, 0xff, 0xef, 0xff, 0xfe, 0xff, -0xff, 0xff, 0xfb, 0xff, 0xfb, 0xff, 0xf7, 0xff, -0xfb, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x3f, -0xfe, 0xfe, 0xbb, 0xaf, 0xeb, 0xfa, 0xff, 0xbf, -0xae, 0xeb, 0xba, 0xfe, 0xfb, 0xee, 0xeb, 0xfb, -0xbb, 0xae, 0xef, 0xbe, 0xff, 0xbb, 0xee, 0xef, -0xbe, 0xff, 0xfb, 0xef, 0xfb, 0xbe, 0xef, 0xff, -0x17, 0xff, 0x75, 0xad, 0xab, 0x4a, 0xba, 0xef, -0xeb, 0xaf, 0x6a, 0xda, 0xae, 0xb5, 0xfb, 0x7a, -0xd2, 0xbd, 0xab, 0x7a, 0x5f, 0xaf, 0xed, 0x7b, -0x7a, 0x5f, 0xaf, 0xe5, 0xfa, 0xfe, 0xdb, 0xbf, -0xe2, 0xd4, 0xff, 0xff, diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds deleted file mode 100644 index b8fb3705df..0000000000 --- a/board/esd/dasa_sim/u-boot.lds +++ /dev/null @@ -1,89 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - .resetvec 0xFFFFFFFC : - { - KEEP(*(.resetvec)) - } = 0xffff - - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/ppc4xx/start.o (.text) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index e86996c55f..062ae67276 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -12,7 +12,6 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> #include <libfdt.h> #include <fdt_support.h> @@ -34,14 +33,14 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; extern void __ft_board_setup(void *blob, bd_t *bd); ulong flash_get_size(ulong base, int banknum); -int pci_is_66mhz(void); +static int pci_is_66mhz(void); int is_monarch(void); -int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt); +static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt); struct serial_device *default_serial_console(void) { @@ -58,23 +57,24 @@ struct serial_device *default_serial_console(void) if (((val & 0xf0000000) >> 29) != 7) return &eserial2_device; - ulong scratchreg = in_be32((void*)GPIO0_ISR3L); + ulong scratchreg = in_be32((void *)GPIO0_ISR3L); if (!(scratchreg & 0x80)) { /* mark scratchreg valid */ scratchreg = (scratchreg & 0xffffff00) | 0x80; + i2c_init_all(); + i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4); if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) { scratchreg |= buf[2]; /* bringup delay for console */ - for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) { + for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++) udelay(1000); - } } else scratchreg |= 0x01; - out_be32((void*)GPIO0_ISR3L, scratchreg); + out_be32((void *)GPIO0_ISR3L, scratchreg); } if (scratchreg & 0x01) @@ -93,10 +93,7 @@ int board_early_init_f(void) mtdcr(EBC0_CFGADDR, EBC0_CFG); mtdcr(EBC0_CFGDATA, 0xf8400000); - /* - * Setup the GPIO pins - * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file - */ + /* Setup the GPIO pins */ out_be32((void *)GPIO0_OR, 0x40000102); out_be32((void *)GPIO0_TCR, 0x4c90011f); out_be32((void *)GPIO0_OSRL, 0x28051400); @@ -259,7 +256,7 @@ int misc_init_r(void) * USB suff... */ if ((act == NULL || strcmp(act, "host") == 0) && - !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){ + !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_USB2D0CR, usb2d0cr); @@ -326,16 +323,16 @@ int misc_init_r(void) mtsdr(SDR0_SRST1, 0x00000000); mtsdr(SDR0_SRST0, 0x00000000); - if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { + if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { /* enable power on USB socket */ - out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); + out_be32((void *)GPIO1_OR, + in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N); } printf("USB: Host\n"); } else if ((strcmp(act, "dev") == 0) || - (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { + (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; @@ -414,30 +411,31 @@ int misc_init_r(void) #endif /* turn off POST LED */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N); + out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N); /* turn on RUN LED */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N); + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N); return 0; } int is_monarch(void) { - if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH) + if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH) return 0; return 1; } -int pci_is_66mhz(void) +static int pci_is_66mhz(void) { - if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN) + if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN) return 1; return 0; } -int board_revision(void) +static int board_revision(void) { - return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4); + return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4); } int checkboard(void) @@ -495,7 +493,7 @@ void pci_target_init(struct pci_controller *hose) out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */ /* and enable region */ @@ -532,7 +530,8 @@ void pci_target_init(struct pci_controller *hose) if (is_monarch()) { /* BAR2: map FPGA registers behind system memory at 1GB */ - pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008); + pci_hose_write_config_dword(hose, 0, + PCI_BASE_ADDRESS_2, 0x40000008); } /* @@ -562,10 +561,10 @@ void pci_target_init(struct pci_controller *hose) CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); /* PCI configuration done: release ERREADY */ - out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY); - out_be32((void*)GPIO1_TCR, - in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY); + out_be32((void *)GPIO1_OR, + in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY); + out_be32((void *)GPIO1_TCR, + in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY); } else { /* Program the board's subsystem id/classcode */ pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, @@ -595,14 +594,14 @@ void pci_master_init(struct pci_controller *hose) static void wait_for_pci_ready(void) { - if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) { + if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) { printf("PCI: Waiting for EREADY (CTRL-C to skip) ... "); while (1) { if (ctrlc()) { puts("abort\n"); break; } - if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) { + if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) { printf("done\n"); break; } @@ -641,34 +640,73 @@ int is_pci_host(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ #ifdef CONFIG_RESET_PHY_R -void reset_phy(void) +static int pmc440_setup_vsc8601(char *devname, int phy_addr, + unsigned short behavior, unsigned short method) { - char *s; - unsigned short val_method, val_behavior; + /* adjust LED behavior */ + if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) { + printf("Phy%d: register write access failed\n", phy_addr); + return -1; + } - /* special LED setup for NGCC/CANDES */ - if ((s = getenv("bd_type")) && - ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) { - val_method = 0x0e0a; - val_behavior = 0x0cf2; - } else { - /* PMC440 standard type */ - val_method = 0x0e10; - val_behavior = 0x0cf0; + miiphy_write(devname, phy_addr, 0x11, 0x0010); + miiphy_write(devname, phy_addr, 0x11, behavior); + miiphy_write(devname, phy_addr, 0x10, method); + miiphy_write(devname, phy_addr, 0x1f, 0x0000); + + return 0; +} + +static int pmc440_setup_ksz9031(char *devname, int phy_addr) +{ + unsigned short id1, id2; + + if (miiphy_read(devname, phy_addr, 2, &id1) || + miiphy_read(devname, phy_addr, 3, &id2)) { + printf("Phy%d: cannot read id\n", phy_addr); + return -1; } - if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) { - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000); + if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) { + printf("Phy%d: unexpected id\n", phy_addr); + return -1; } - if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) { - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000); + /* MMD 2.08: adjust tx_clk pad skew */ + miiphy_write(devname, phy_addr, 0x0d, 2); + miiphy_write(devname, phy_addr, 0x0e, 8); + miiphy_write(devname, phy_addr, 0x0d, 0x4002); + miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5)); + + return 0; +} + +void reset_phy(void) +{ + char *s; + unsigned short val_method, val_behavior; + + if (gd->board_type < 4) { + /* special LED setup for NGCC/CANDES */ + s = getenv("bd_type"); + if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) { + val_method = 0x0e0a; + val_behavior = 0x0cf2; + } else { + /* PMC440 standard type */ + val_method = 0x0e10; + val_behavior = 0x0cf0; + } + + /* boards up to rev. 1.3 use Vitesse VSC8601 phys */ + pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR, + val_method, val_behavior); + pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR, + val_method, val_behavior); + } else { + /* rev. 1.4 uses a Micrel KSZ9031 */ + pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR); + pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR); } } #endif @@ -729,7 +767,6 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, * We must write the address again when changing pages * because the address counter only increments within a page. */ - while (offset < end) { unsigned alen, len; unsigned maxlen; @@ -771,8 +808,8 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, return rcode; } -int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt) +static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt) { unsigned end = offset + cnt; unsigned blk_off; @@ -820,10 +857,10 @@ int board_usb_init(int index, enum usb_init_type init) int i; if ((act == NULL || strcmp(act, "host") == 0) && - !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) + !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) /* enable power on USB socket */ - out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); + out_be32((void *)GPIO1_OR, + in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N); for (i=0; i<1000; i++) udelay(1000); @@ -834,7 +871,7 @@ int board_usb_init(int index, enum usb_init_type init) int usb_board_stop(void) { /* disable power on USB socket */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N); + out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N); return 0; } @@ -858,8 +895,8 @@ void ft_board_setup(void *blob, bd_t *bd) rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status", "disabled", sizeof("disabled"), 1); if (rc) { - printf("Unable to update property status in PCI node, err=%s\n", - fdt_strerror(rc)); + printf("Unable to update property status in PCI node, "); + printf("err=%s\n", fdt_strerror(rc)); } } } diff --git a/board/evb64260/ecctest.c b/board/evb64260/ecctest.c deleted file mode 100644 index 5d3679aa93..0000000000 --- a/board/evb64260/ecctest.c +++ /dev/null @@ -1,111 +0,0 @@ -indent: Standard input:27: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -#ifdef ECC_TEST -static inline void ecc_off (void) -{ - *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000; -} - -static inline void ecc_on (void) -{ - *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000; -} - -static int putshex (const char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) { - printf ("%02x", buf[i]); - } - return 0; -} - -static int char_memcpy (void *d, const void *s, int len) -{ - int i; - char *cd = d; - const char *cs = s; - - for (i = 0; i < len; i++) { - *(cd++) = *(cs++); - } - return 0; -} - -static int memory_test (char *buf) -{ - const char src[][16] = { - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}, - {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, - 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}, - {0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, - 0x04, 0x04, 0x04, 0x04, 0x04, 0x04}, - {0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, - 0x08, 0x08, 0x08, 0x08, 0x08, 0x08}, - {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10}, - {0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x20, 0x20, 0x20}, - {0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, - 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}, - {0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80}, - {0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, - 0x55, 0x55, 0x55, 0x55, 0x55, 0x55}, - {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}, - {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff} - }; - const int foo[] = { 0 }; - int i, j, a; - - printf ("\ntest @ %d %p\n", foo[0], buf); - for (i = 0; i < 12; i++) { - for (a = 0; a < 8; a++) { - const char *s = src[i] + a; - int align = (unsigned) (s) & 0x7; - - /* ecc_off(); */ - memcpy (buf, s, 8); - /* ecc_on(); */ - putshex (s, 8); - if (memcmp (buf, s, 8)) { - putc ('\n'); - putshex (buf, 8); - printf (" [FAIL] (%p) align=%d\n", s, align); - for (j = 0; j < 8; j++) { - s[j] == buf[j] ? puts (" ") : - printf ("%02x", - (s[j]) ^ (buf[j])); - } - putc ('\n'); - } else { - printf (" [PASS] (%p) align=%d\n", s, align); - } - /* ecc_off(); */ - char_memcpy (buf, s, 8); - /* ecc_on(); */ - putshex (s, 8); - if (memcmp (buf, s, 8)) { - putc ('\n'); - putshex (buf, 8); - printf (" [FAIL] (%p) align=%d\n", s, align); - for (j = 0; j < 8; j++) { - s[j] == buf[j] ? puts (" ") : - printf ("%02x", - (s[j]) ^ (buf[j])); - } - putc ('\n'); - } else { - printf (" [PASS] (%p) align=%d\n", s, align); - } - } - } - - return 0; -} -#endif diff --git a/board/fads/fads.c b/board/fads/fads.c index 89dd9efe78..fdb46b1f35 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -210,11 +210,7 @@ static int _draminit (uint base, uint noMbytes, uint edo, uint delay) switch (noMbytes) { case 4: /* 4 Mbyte uses only CS2 */ -#ifdef CONFIG_ADS - memctl->memc_mamr = 0xc0a21114; -#else memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */ -#endif memctl->memc_or2 = 0xffc00800; /* 4M */ break; @@ -226,11 +222,7 @@ static int _draminit (uint base, uint noMbytes, uint edo, uint delay) break; case 16: /* 16 Mbyte uses only CS2 */ -#ifdef CONFIG_ADS /* XXX: why PTA=0x60 only in 16M case? - NTL */ - memctl->memc_mamr = 0x60b21114; /* PTA 0x60 AMA 011 */ -#else memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */ -#endif memctl->memc_or2 = 0xff000800; /* 16M */ break; @@ -674,42 +666,6 @@ int testdram (void) * Check Board Identity: */ -#if defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD) -static void checkdboard(void) -{ - /* get db type from BCSR 3 */ - uint k = (*((uint *)BCSR3) >> 24) & 0x3f; - - puts (" with db "); - - switch(k) { - case 0x03 : - puts ("MPC823"); - break; - case 0x20 : - puts ("MPC801"); - break; - case 0x21 : - puts ("MPC850"); - break; - case 0x22 : - puts ("MPC821, MPC860 / MPC860SAR / MPC860T"); - break; - case 0x23 : - puts ("MPC860SAR"); - break; - case 0x24 : - case 0x2A : - puts ("MPC860T"); - break; - case 0x3F : - puts ("MPC850SAR"); - break; - default : printf("0x%x", k); - } -} -#endif /* defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD) */ - int checkboard (void) { #if defined(CONFIG_MPC86xADS) @@ -732,27 +688,12 @@ int checkboard (void) puts (" rev "); switch (r) { -#if defined(CONFIG_ADS) - case 0x00: - puts ("ENG - this board sucks, check the errata, not supported\n"); - return -1; - case 0x01: - puts ("PILOT - warning, read errata \n"); - break; - case 0x02: - puts ("A - warning, read errata \n"); - break; - case 0x03: - puts ("B\n"); - break; -#else /* FADS */ case 0x00: puts ("ENG\n"); break; case 0x01: puts ("PILOT\n"); break; -#endif /* CONFIG_ADS */ default: printf ("unknown (0x%x)\n", r); return -1; @@ -865,12 +806,6 @@ int pcmcia_init(void) #endif case 5: printf("; using 5V"); -#ifdef CONFIG_ADS - /* - ** Enable 5 volt Vcc. - */ - *((uint *)BCSR1) &= ~BCSR1_PCCVCCON; -#endif #ifdef CONFIG_FADS /* ** Enable 5 volt Vcc. diff --git a/board/fads/fads.h b/board/fads/fads.h index fa49080fb7..1be00b9048 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -66,13 +66,8 @@ * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have * got FEC so FEC is the default. */ -#ifndef CONFIG_ADS #undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */ #define CONFIG_FEC_ENET /* Use FEC ethernet */ -#else /* Old ADS has not got FEC option */ -#define CONFIG_SCC1_ENET /* Use SCC1 ethernet */ -#undef CONFIG_FEC_ENET /* No FEC ethernet */ -#endif /* !CONFIG_ADS */ #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured diff --git a/board/fads/lamp.c b/board/fads/lamp.c index 4e58291c06..ffcc2b3c41 100644 --- a/board/fads/lamp.c +++ b/board/fads/lamp.c @@ -1,7 +1,5 @@ #include <config.h> -#ifndef CONFIG_ADS /* Old ADS has not got any user-controllable LED */ - #include <common.h> void @@ -43,5 +41,3 @@ fast_blink(unsigned int n) signal_delay(0x00100000); } } - -#endif /* !CONFIG_ADS */ diff --git a/board/fads/pcmcia.c b/board/fads/pcmcia.c index 99fe0b4fb9..996f032f64 100644 --- a/board/fads/pcmcia.c +++ b/board/fads/pcmcia.c @@ -14,11 +14,7 @@ #ifdef CONFIG_PCMCIA -#ifdef CONFIG_ADS -#define PCMCIA_BOARD_MSG "ADS" -#else #define PCMCIA_BOARD_MSG "FADS" -#endif int pcmcia_voltage_set(int slot, int vcc, int vpp) { @@ -33,9 +29,6 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) switch(vcc) { case 0: reg = 0; break; -#ifdef CONFIG_ADS - case 50: reg = BCSR1_PCCVCCON; break; -#endif #ifdef CONFIG_FADS case 33: reg = BCSR1_PCCVCC0 | BCSR1_PCCVCC1; break; case 50: reg = BCSR1_PCCVCC1; break; @@ -45,9 +38,6 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) /* first, turn off all power */ -#ifdef CONFIG_ADS - *((uint *)BCSR1) |= BCSR1_PCCVCCON; -#endif #ifdef CONFIG_FADS *((uint *)BCSR1) &= ~(BCSR1_PCCVCC0 | BCSR1_PCCVCC1); #endif @@ -55,9 +45,6 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) /* enable new powersettings */ -#ifdef CONFIG_ADS - *((uint *)BCSR1) &= ~reg; -#endif #ifdef CONFIG_FADS *((uint *)BCSR1) |= reg; #endif diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile index e5cc054a01..0acd2a9aa4 100644 --- a/board/freescale/b4860qds/Makefile +++ b/board/freescale/b4860qds/Makefile @@ -4,9 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-y += b4860qds.o -obj-y += ddr.o obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o -obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_PCI) += pci.o +endif + +obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg index 57b726eead..05377bac5b 100644 --- a/board/freescale/b4860qds/b4_pbi.cfg +++ b/board/freescale/b4860qds/b4_pbi.cfg @@ -22,6 +22,9 @@ 09110024 00100008 09110028 00100008 0911002c 00100008 +#slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 #Flush PBL data 09138000 00000000 091380c0 00000000 diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index 187c3b3ebc..2c17156586 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -179,6 +179,7 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); @@ -186,7 +187,9 @@ phys_size_t initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c new file mode 100644 index 0000000000..3aa5a780f4 --- /dev/null +++ b/board/freescale/b4860qds/spl.c @@ -0,0 +1,114 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/spl.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include "../common/qixis.h" +#include "b4860qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((sysclk_conf & 0x0C) >> 2) { + case QIXIS_CLK_100: + return 100000000; + case QIXIS_CLK_125: + return 125000000; + case QIXIS_CLK_133: + return 133333333; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch (ddrclk_conf & 0x03) { + case QIXIS_CLK_100: + return 100000000; + case QIXIS_CLK_125: + return 125000000; + case QIXIS_CLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); + env_relocate(); +#else + /* relocate environment function pointers etc. */ + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#endif + + i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_boot(); +#endif +} diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c index 00798a1c19..7b55b860d0 100644 --- a/board/freescale/b4860qds/tlb.c +++ b/board/freescale/b4860qds/tlb.c @@ -62,6 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -96,6 +97,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -118,6 +120,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for SRIO2. */ +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_SYS_SRIO1_MEM_PHYS /* *I*G* - SRIO1 */ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, @@ -140,6 +143,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 17, BOOKE_PAGESZ_1M, 1), #endif +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 17, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/mousse/Makefile b/board/freescale/qemu-ppce500/Makefile index e2951d54ad..2d2749205f 100644 --- a/board/mousse/Makefile +++ b/board/freescale/qemu-ppce500/Makefile @@ -1,8 +1,9 @@ # +# Copyright 2007 Freescale Semiconductor, Inc. # (C) Copyright 2001-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # SPDX-License-Identifier: GPL-2.0+ # -obj-y = mousse.o m48t59y.o pci.o flash.o +obj-y += qemu-ppce500.o diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c new file mode 100644 index 0000000000..3dbb0cf43b --- /dev/null +++ b/board/freescale/qemu-ppce500/qemu-ppce500.c @@ -0,0 +1,348 @@ +/* + * Copyright 2007,2009-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/fsl_pci.h> +#include <asm/io.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <netdev.h> +#include <fdtdec.h> +#include <errno.h> +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void *get_fdt_virt(void) +{ + return (void *)CONFIG_SYS_TMPVIRT; +} + +static uint64_t get_fdt_phys(void) +{ + return (uint64_t)(uintptr_t)gd->fdt_blob; +} + +static void map_fdt_as(int esel) +{ + u32 mas0, mas1, mas2, mas3, mas7; + uint64_t fdt_phys = get_fdt_phys(); + unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful; + unsigned long fdt_virt_tlb = (ulong)get_fdt_virt() & ~0xffffful; + + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(esel); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); + mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0); + mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb); + + write_tlb(mas0, mas1, mas2, mas3, mas7); +} + +uint64_t get_phys_ccsrbar_addr_early(void) +{ + void *fdt = get_fdt_virt(); + uint64_t r; + + /* + * To be able to read the FDT we need to create a temporary TLB + * map for it. + */ + map_fdt_as(10); + r = fdt_get_base_address(fdt, fdt_path_offset(fdt, "/soc")); + disable_tlb(10); + + return r; +} + +int board_early_init_f(void) +{ + return 0; +} + +int checkboard(void) +{ + return 0; +} + +static int pci_map_region(void *fdt, int pci_node, int range_id, + phys_size_t *ppaddr, pci_addr_t *pvaddr, + pci_size_t *psize, ulong *pmap_addr) +{ + uint64_t addr; + uint64_t size; + ulong map_addr; + int r; + + r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size); + if (r) + return r; + + if (ppaddr) + *ppaddr = addr; + if (psize) + *psize = size; + + if (!pmap_addr) + return 0; + + map_addr = *pmap_addr; + + /* Align map_addr */ + map_addr += size - 1; + map_addr &= ~(size - 1); + + if (map_addr + size >= CONFIG_SYS_PCI_MAP_END) + return -1; + + /* Map virtual memory for range */ + assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO)); + *pmap_addr = map_addr + size; + + if (pvaddr) + *pvaddr = map_addr; + + return 0; +} + +void pci_init_board(void) +{ + struct pci_controller *pci_hoses; + void *fdt = get_fdt_virt(); + int pci_node = -1; + int pci_num = 0; + int pci_count = 0; + ulong map_addr; + + puts("\n"); + + /* Start MMIO and PIO range maps above RAM */ + map_addr = CONFIG_SYS_PCI_MAP_START; + + /* Count and allocate PCI buses */ + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + while (pci_node != -FDT_ERR_NOTFOUND) { + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + pci_count++; + } + + if (pci_count) { + pci_hoses = malloc(sizeof(struct pci_controller) * pci_count); + } else { + printf("PCI: disabled\n\n"); + return; + } + + /* Spawn PCI buses based on device tree */ + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + while (pci_node != -FDT_ERR_NOTFOUND) { + struct fsl_pci_info pci_info = { }; + const fdt32_t *reg; + int r; + + reg = fdt_getprop(fdt, pci_node, "reg", NULL); + pci_info.regs = fdt_translate_address(fdt, pci_node, reg); + + /* Map MMIO range */ + r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL, + &pci_info.mem_size, &map_addr); + if (r) + break; + + /* Map PIO range */ + r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL, + &pci_info.io_size, &map_addr); + if (r) + break; + + /* + * The PCI framework finds virtual addresses for the buses + * through our address map, so tell it the physical addresses. + */ + pci_info.mem_bus = pci_info.mem_phys; + pci_info.io_bus = pci_info.io_phys; + + /* Instantiate */ + pci_info.pci_num = pci_num + 1; + + fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs); + printf("PCI: base address %lx\n", pci_info.regs); + + fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num); + + /* Jump to next PCI node */ + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + pci_num++; + } + + puts("\n"); +} + +int last_stage_init(void) +{ + void *fdt = get_fdt_virt(); + int len = 0; + const uint64_t *prop; + int chosen; + + chosen = fdt_path_offset(fdt, "/chosen"); + if (chosen < 0) { + printf("Couldn't find /chosen node in fdt\n"); + return -EIO; + } + + /* -kernel boot */ + prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len); + if (prop && (len >= 8)) + setenv_hex("qemu_kernel_addr", *prop); + + /* Give the user a variable for the host fdt */ + setenv_hex("fdt_addr_r", (ulong)fdt); + + return 0; +} + +static uint64_t get_linear_ram_size(void) +{ + void *fdt = get_fdt_virt(); + const void *prop; + int memory; + int len; + + memory = fdt_path_offset(fdt, "/memory"); + prop = fdt_getprop(fdt, memory, "reg", &len); + + if (prop && len >= 16) + return *(uint64_t *)(prop+8); + + panic("Couldn't determine RAM size"); +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} +#endif + +void print_laws(void) +{ + /* We don't emulate LAWs yet */ +} + +phys_size_t fixed_sdram(void) +{ + return get_linear_ram_size(); +} + +phys_size_t fsl_ddr_sdram_size(void) +{ + return get_linear_ram_size(); +} + +void init_tlbs(void) +{ + phys_size_t ram_size; + + /* + * Create a temporary AS=1 map for the fdt + * + * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves + * which was only 4k big. This way we don't have to clear any other maps. + */ + map_fdt_as(0); + + /* Fetch RAM size from the fdt */ + ram_size = get_linear_ram_size(); + + /* And remove our fdt map again */ + disable_tlb(0); + + /* Create an internal map of manually created TLB maps */ + init_used_tlb_cams(); + + /* Create a dynamic AS=0 CCSRBAR mapping */ + assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + 1024 * 1024, TLB_MAP_IO)); + + /* Create a RAM map that spans all accessible RAM */ + setup_ddr_tlbs(ram_size >> 20); + + /* Create a map for the TLB */ + assert(!tlb_map_range((ulong)get_fdt_virt(), get_fdt_phys(), + 1024 * 1024, TLB_MAP_RAM)); +} + +void init_laws(void) +{ + /* We don't emulate LAWs yet */ +} + +static uint32_t get_cpu_freq(void) +{ + void *fdt = get_fdt_virt(); + int cpus_node = fdt_path_offset(fdt, "/cpus"); + int cpu_node = fdt_first_subnode(fdt, cpus_node); + const char *prop = "clock-frequency"; + return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0); +} + +void get_sys_info(sys_info_t *sys_info) +{ + int freq = get_cpu_freq(); + + memset(sys_info, 0, sizeof(sys_info_t)); + sys_info->freq_systembus = freq; + sys_info->freq_ddrbus = freq; + sys_info->freq_processor[0] = freq; +} + +int get_clocks (void) +{ + sys_info_t sys_info; + + get_sys_info(&sys_info); + + gd->cpu_clk = sys_info.freq_processor[0]; + gd->bus_clk = sys_info.freq_systembus; + gd->mem_clk = sys_info.freq_ddrbus; + gd->arch.lbc_clk = sys_info.freq_ddrbus; + + return 0; +} + +unsigned long get_tbclk (void) +{ + void *fdt = get_fdt_virt(); + int cpus_node = fdt_path_offset(fdt, "/cpus"); + int cpu_node = fdt_first_subnode(fdt, cpus_node); + const char *prop = "timebase-frequency"; + return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0); +} + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq (ulong dummy) +{ + sys_info_t sys_info; + get_sys_info(&sys_info); + return sys_info.freq_systembus; +} diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index da89a36b96..43f952f9c0 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -39,14 +39,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (pbsp->n_ranks == pdimm->n_ranks && (pdimm->rank_density >> 30) >= pbsp->rank_gb) { if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -59,13 +55,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, printf("for data rate %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } @@ -81,7 +74,7 @@ found: * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ - popts->half_strength_driver_enable = 0; + popts->half_strength_driver_enable = 1; /* * Write leveling override */ @@ -97,8 +90,14 @@ found: popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif } phys_size_t initdram(int board_type) diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index afa72af26a..a6e1673525 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,9 +14,6 @@ struct board_specific_parameters { u32 wrlvl_start; u32 wrlvl_ctl_2; u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2t; }; /* @@ -28,21 +25,25 @@ struct board_specific_parameters { static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, - {2, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, - {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, - {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, - {1, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, - {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, - {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, + {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, +#else +#error DDR type not defined +#endif {} }; diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 3dec4473e5..0e83d172da 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -18,6 +18,8 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> +#include <hwconfig.h> +#include <asm/mpc85xx_gpio.h> #include "../common/qixis.h" #include "t1040qds.h" @@ -89,6 +91,30 @@ int select_i2c_ch_pca9547(u8 ch) return 0; } +static void qe_board_setup(void) +{ + u8 brdcfg15, brdcfg9; + + if (hwconfig("qe") && hwconfig("tdm")) { + brdcfg15 = QIXIS_READ(brdcfg[15]); + /* + * TDMRiser uses QE-TDM + * Route QE_TDM signals to TDM Riser slot + */ + QIXIS_WRITE(brdcfg[15], brdcfg15 | 7); + } else if (hwconfig("qe") && hwconfig("uart")) { + brdcfg15 = QIXIS_READ(brdcfg[15]); + brdcfg9 = QIXIS_READ(brdcfg[9]); + /* + * Route QE_TDM signals to UCC + * ProfiBus controlled by UCC3 + */ + brdcfg15 &= 0xfc; + QIXIS_WRITE(brdcfg[15], brdcfg15 | 2); + QIXIS_WRITE(brdcfg[9], brdcfg9 | 4); + } +} + int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE @@ -196,6 +222,8 @@ int misc_init_r(void) } } + qe_board_setup(); + return 0; } @@ -245,3 +273,14 @@ int board_need_mem_reset(void) { return 1; } + +#ifdef CONFIG_DEEP_SLEEP +void board_mem_sleep_setup(void) +{ + /* does not provide HW signals for power management */ + QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index e51fb7a7f4..6cd304cce9 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -4,10 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # - +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-y += t104xrdb.o -obj-y += ddr.o +obj-y += cpld.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index 1da52bb0b0..cdbe1fafd9 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -198,3 +198,76 @@ The below commands apply to the board 2.To change from vbank4 to vbank0 => qixis reset (it will boot using vbank0) + +NAND boot with 2 Stage boot loader +---------------------------------- +PBL initialise the internal SRAM and copy SPL(160KB) in SRAM. +SPL further initialise DDR using SPD and environment variables and copy +u-boot(768 KB) from flash to DDR. +Finally SPL transer control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + + Run time view of SPL framework during boot :- + ----------------------------------------------- + Area | Address | +----------------------------------------------- + Secure boot | 0xFFFC0000 (32KB) | + headers | | + ----------------------------------------------- + GD, BD | 0xFFFC8000 (4KB) | + ----------------------------------------------- + ENV | 0xFFFC9000 (8KB) | + ----------------------------------------------- + HEAP | 0xFFFCB000 (30KB) | + ----------------------------------------------- + STACK | 0xFFFD8000 (22KB) | + ----------------------------------------------- + U-boot SPL | 0xFFFD8000 (160KB) | + ----------------------------------------------- + +NAND Flash memory Map on T104xRDB +------------------------------------------ + Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x180000 0x19FFFF u-boot env 128KB +0x280000 0x29FFFF FMAN Ucode 128KB +0x380000 0x39FFFF QE Firmware 128KB + +SD Card memory Map on T104xRDB +------------------------------------------ + Block #blocks Definition Size +0x008 2048 u-boot 1MB +0x800 0024 u-boot env 8KB +0x820 0256 FMAN Ucode 128KB +0x920 0256 QE Firmware 128KB + +SPI Flash memory Map on T104xRDB +------------------------------------------ + Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x12FFFF FMAN Ucode 128KB +0x130000 0x14FFFF QE Firmware 128KB + +Please note QE Firmware is only valid for T1040RDB + + +Switch Settings: (ON is 0, OFF is 1) +=============== +NAND boot SW setting: +SW1: 10001000 +SW2: 00111001 +SW3: 11110001 + +SPI boot SW setting: +SW1: 00100010 +SW2: 10111001 +SW3: 11100001 + +SD boot SW setting: +SW1: 00100000 +SW2: 00111001 +SW3: 11100001 diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c new file mode 100644 index 0000000000..df0e348d4a --- /dev/null +++ b/board/freescale/t104xrdb/cpld.c @@ -0,0 +1,112 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); + printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); + printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); + printf("int_status = 0x%02x\n", CPLD_READ(int_status)); + printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); + printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); + printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); + printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); + printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); + printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); + printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1)); + printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2)); + putc('\n'); +} +#endif + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - hard reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h new file mode 100644 index 0000000000..0da9a0159b --- /dev/null +++ b/board/freescale/t104xrdb/cpld.h @@ -0,0 +1,40 @@ +/** + * Copyright 2013 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl1; /* 0x10 - Reset control Register1 */ + u8 reset_ctl2; /* 0x11 - Reset control Register2 */ + u8 int_status; /* 0x12 - Interrupt status Register */ + u8 flash_ctl_status; /* 0x13 - Flash control and status register */ + u8 fan_ctl_status; /* 0x14 - Fan control and status register */ + u8 led_ctl_status; /* 0x15 - LED control and status register */ + u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ + u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ + u8 boot_override; /* 0x18 - Boot override register */ + u8 boot_config1; /* 0x19 - Boot config override register*/ + u8 boot_config2; /* 0x1A - Boot config override register*/ +} cpld_data_t; + + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value)\ + cpld_write(offsetof(struct cpld_data, reg), value) diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 57d0f9cfd8..34c9224adb 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -113,6 +113,7 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); @@ -120,6 +121,8 @@ phys_size_t initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 0188fd4090..63e5f900da 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -41,6 +41,7 @@ int board_eth_init(bd_t *bis) /* T1040RDB only supports SGMII on DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_SGMII1_PHY_ADDR); + break; #endif case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c new file mode 100644 index 0000000000..c628c95f2d --- /dev/null +++ b/board/freescale/t104xrdb/spl.c @@ -0,0 +1,122 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; +#ifdef CONFIG_SPL_NAND_BOOT + u32 porsr1, pinctl; +#endif + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#ifdef CONFIG_SPL_NAND_BOOT + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t104xrdb/t1040_rcw.cfg b/board/freescale/t104xrdb/t1040_rcw.cfg new file mode 100644 index 0000000000..3300c184a1 --- /dev/null +++ b/board/freescale/t104xrdb/t1040_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 80000002 e8106000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042_rcw.cfg b/board/freescale/t104xrdb/t1042_rcw.cfg new file mode 100644 index 0000000000..a3ea8ada56 --- /dev/null +++ b/board/freescale/t104xrdb/t1042_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +06000002 00400002 e8106000 01000000 +00000000 00000000 00000000 00030810 +00000000 01fe0a06 00000000 00000000 diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg new file mode 100644 index 0000000000..7b9e9b05f7 --- /dev/null +++ b/board/freescale/t104xrdb/t104x_pbi.cfg @@ -0,0 +1,26 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 6e29d64107..fb5b84940e 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -17,16 +17,30 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> +#include <asm/mpc85xx_gpio.h> #include "t104xrdb.h" +#include "cpld.h" DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; + u8 sw; printf("Board: %sRDB\n", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + + sw = CPLD_READ(flash_ctl_status); + sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); + return 0; } @@ -91,3 +105,12 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); #endif } + +#ifdef CONFIG_DEEP_SLEEP +void board_mem_sleep_setup(void) +{ + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 84f97a41e3..95c15aa596 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -53,6 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -82,6 +83,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -102,6 +104,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile index 947b7f7324..6cb72c9fd5 100644 --- a/board/freescale/t208xqds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -4,11 +4,16 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-$(CONFIG_T2080QDS) += t208xqds.o obj-$(CONFIG_T2080QDS) += eth_t208xqds.o obj-$(CONFIG_T2081QDS) += t208xqds.o obj-$(CONFIG_T2081QDS) += eth_t208xqds.o obj-$(CONFIG_PCI) += pci.o +endif + obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index ed1334d985..3348971b01 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -107,13 +107,16 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif - puts(" DDR: "); return dram_size; } diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c new file mode 100644 index 0000000000..a71c617121 --- /dev/null +++ b/board/freescale/t208xqds/spl.c @@ -0,0 +1,137 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> +#include "../common/qixis.h" +#include "t208xqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index 62cd11033a..8d602989b2 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -141,6 +143,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile index 092c9ff0dc..9605f8b606 100644 --- a/board/freescale/t208xrdb/Makefile +++ b/board/freescale/t208xrdb/Makefile @@ -4,10 +4,15 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-$(CONFIG_T2080RDB) += t208xrdb.o obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o obj-$(CONFIG_T2080RDB) += cpld.o obj-$(CONFIG_PCI) += pci.o +endif + obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index 0012c6cb40..24484cd0ff 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -67,7 +67,7 @@ T2080PCIe-RDB board Overview - One PCIe x2 end-point device (C293 Crypto co-processor) - IFC/Local Bus - NOR: 128MB 16-bit NOR Flash - - NAND: 512MB 8-bit NAND flash + - NAND: 1GB 8-bit NAND flash - CPLD: for system controlling with programable header on-board - SATA - Two SATA 2.0 onnectors on-board @@ -120,7 +120,7 @@ Start Address End Address Definition Max size 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB -0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB 0xE8000000 0xE801FFFF RCW (current bank) 128KB @@ -146,7 +146,8 @@ Software configurations and board settings ------------------------------------------ 1. NOR boot: a. build NOR boot image - $ make T2080RDB + $ make T2080RDB_config + $ make b. program u-boot.bin image to NOR flash => tftp 1000000 u-boot.bin => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize @@ -155,18 +156,18 @@ Software configurations and board settings Switching between default bank and alternate bank on NOR flash To change boot source to vbank4: via software: run command 'cpld reset altbank' in u-boot. - via DIP-switch: set SW3[5:7] = '011' + via DIP-switch: set SW3[5:7] = '100' To change boot source to vbank0: via software: run command 'cpld reset' in u-boot. - via DIP-Switch: set SW3[5:7] = '111' + via DIP-Switch: set SW3[5:7] = '000' 2. NAND Boot: a. build PBL image for NAND boot $ make T2080RDB_NAND_config - $ make u-boot.pbl - b. program u-boot.pbl to NAND flash - => tftp 1000000 u-boot.pbl + $ make + b. program u-boot-with-spl-pbl.bin to NAND flash + => tftp 1000000 u-boot-with-spl-pbl.bin => nand erase 0 d0000 => nand write 1000000 0 $filesize set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot @@ -174,9 +175,9 @@ Software configurations and board settings 3. SPI Boot: a. build PBL image for SPI boot $ make T2080RDB_SPIFLASH_config - $ make u-boot.pbl - b. program u-boot.pbl to SPI flash - => tftp 1000000 u-boot.pbl + $ make + b. program u-boot-with-spl-pbl.bin to SPI flash + => tftp 1000000 u-boot-with-spl-pbl.bin => sf probe 0 => sf erase 0 d0000 => sf write 1000000 0 $filesize @@ -185,13 +186,68 @@ Software configurations and board settings 4. SD Boot: a. build PBL image for SD boot $ make T2080RDB_SDCARD_config - $ make u-boot.pbl - b. program u-boot.pbl to TF card - => tftp 1000000 u-boot.pbl - => mmc write 1000000 8 1650 + $ make + b. program u-boot-with-spl-pbl.bin to micro-SD/TF card + => tftp 1000000 u-boot-with-spl-pbl.bin + => mmc write 1000000 8 0x800 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot +2-stage NAND/SPI/SD boot loader +------------------------------- +PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. +SPL further initializes DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (50KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T2080RDB +-------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB (2 blocks) +0x100000 0x17FFFF u-boot env 512KB (1 block) +0x180000 0x1FFFFF FMAN ucode 512KB (1 block) +0x200000 0x27FFFF CS4315 ucode 512KB (1 block) + + +Micro SD Card memory Map on T2080RDB +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0128 FMAN ucode 64KB +0x8a0 0512 CS4315 ucode 256KB + + +SPI Flash memory Map on T2080RDB +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x11FFFF FMAN ucode 64KB +0x120000 0x15FFFF CS4315 ucode 256KB + + How to update the ucode of Cortina CS4315/CS4340 10G PHY -------------------------------------------------------- => tftp 1000000 CS4315-CS4340-PHY-ucode.txt diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h index 4cee4e55cf..3f1533888d 100644 --- a/board/freescale/t208xrdb/cpld.h +++ b/board/freescale/t208xrdb/cpld.h @@ -35,8 +35,8 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_LBMAP_MASK 0x3F #define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_OVERRIDE 0x40 -#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */ -#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */ +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 #define CPLD_BOOT_SEL 0x80 diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c index 01e917398f..8a26276273 100644 --- a/board/freescale/t208xrdb/ddr.c +++ b/board/freescale/t208xrdb/ddr.c @@ -100,13 +100,15 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - - puts(" DDR: "); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c new file mode 100644 index 0000000000..9ae2b1e863 --- /dev/null +++ b/board/freescale/t208xrdb/spl.c @@ -0,0 +1,107 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index f3fec2aa6e..265c1f97dd 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -44,7 +44,7 @@ int checkboard(void) puts("NAND\n"); } else { reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); - printf("NOR vBank%d\n", ~reg & 0x7); + printf("NOR vBank%d\n", reg); } #endif diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index 085d9f5c6a..2ebea36a5c 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -140,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 18, BOOKE_PAGESZ_1M, 1), #endif -#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 19, BOOKE_PAGESZ_2G, 1) diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile index 2b1f7aa301..4e8e5cb8e9 100644 --- a/board/freescale/t4qds/Makefile +++ b/board/freescale/t4qds/Makefile @@ -4,10 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-$(CONFIG_T4240QDS) += t4240qds.o obj-$(CONFIG_T4240EMU) += t4240emu.o -obj-y += ddr.o obj-$(CONFIG_T4240QDS)+= eth.o obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 7586cc3c4b..7abd38def1 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -117,11 +117,15 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c new file mode 100644 index 0000000000..0c6156e7f0 --- /dev/null +++ b/board/freescale/t4qds/spl.c @@ -0,0 +1,141 @@ +/* Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/spl.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include "../common/qixis.h" +#include "t4240qds_qixis.h" + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#ifdef CONFIG_SPL_NAND_BOOT + u32 porsr1, pinctl; +#endif + +#ifdef CONFIG_SPL_NAND_BOOT + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg index c598fb5afd..6126266a96 100644 --- a/board/freescale/t4qds/t4_pbi.cfg +++ b/board/freescale/t4qds/t4_pbi.cfg @@ -13,20 +13,6 @@ 09000d00 00000000 09000d04 fff80000 09000d08 81000012 -#workaround for IFC bus speed -091241c0 f03f3f3f -091241c4 ff003f3f -09124010 00000101 -09124130 0000000c -#workaround for SERDES A-006031 -090ea000 064740e6 -090ea020 064740e6 -090eb000 064740e6 -090eb020 064740e6 -090ec000 064740e6 -090ec020 064740e6 -090ed000 064740e6 -090ed020 064740e6 #Configure alternate space 09000010 00000000 09000014 ff000000 diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg index 74df01a70c..3e56817204 100644 --- a/board/freescale/t4qds/t4_rcw.cfg +++ b/board/freescale/t4qds/t4_rcw.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 010e0100 #serdes protocol 1_28_6_12 -120c0019 0c101915 00000000 00000000 -04383063 30548c00 6c020000 1d000000 +16070019 18101916 00000000 00000000 +04383060 30548c00 ec020000 f5000000 00000000 ee0000ee 00000000 000307fc -00000000 00000000 00000000 00000020 +00000000 00000000 00000000 00000028 diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index b701e75209..1e4d096f5f 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), - +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -105,6 +105,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -136,6 +137,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/genietv/Makefile b/board/genietv/Makefile deleted file mode 100644 index fd11f14b3a..0000000000 --- a/board/genietv/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = genietv.o flash.o diff --git a/board/genietv/flash.c b/board/genietv/flash.c deleted file mode 100644 index 5f57978a33..0000000000 --- a/board/genietv/flash.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * (C) Copyright 2000-2011 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long *addr, flash_info_t *info); -static int write_word(flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets(ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* Detect size */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, - &flash_info[0]); - - /* Setup offsets */ - flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return size_b0; -} - -/*----------------------------------------------------------------------- - * Fix this to support variable sector sizes -*/ -static void flash_get_offsets(ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) { - /* set sector offsets for bottom boot block type */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - puts("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_BM: - printf("BRIGHT MICRO "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - if (info->size >> 20) { - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - } else { - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, - info->sector_count); - } - - puts(" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - puts("\n "); - - printf(" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - putc('\n'); - return; -} -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size(vu_long *addr, flash_info_t *info) -{ - short i; - volatile unsigned char *caddr; - char value; - - caddr = (volatile unsigned char *)addr ; - - /* Write auto select command: read Manufacturer ID */ - - debug("Base address is: %8p\n", caddr); - - caddr[0x0555] = 0xAA; - caddr[0x02AA] = 0x55; - caddr[0x0555] = 0x90; - - value = caddr[0]; - - debug("Manufact ID: %02x\n", value); - - switch (value) { - case 0x1: /* AMD_MANUFACT */ - info->flash_id = FLASH_MAN_AMD; - break; - case 0x4: /* FUJ_MANUFACT */ - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - value = caddr[1]; /* device ID */ - - debug("Device ID: %02x\n", value); - - switch (value) { - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - - default: - info->flash_id = FLASH_UNKNOWN; - return 0; /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, &flash_info[0]); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* - * read sector protection at sector address, - * (A7 .. A0) = 0x02 - * D0 = 1 if protected - */ - caddr = (volatile unsigned char *)(info->start[i]); - info->protect[i] = caddr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - caddr = (volatile unsigned char *)info->start[0]; - *caddr = 0xF0; /* reset bank */ - } - - return info->size; -} - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile unsigned char *addr = - (volatile unsigned char *)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0x80; - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile unsigned char *)(info->start[sect]); - addr[0] = 0x30; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = start; - addr = (volatile unsigned char *)(info->start[l_sect]); - - while ((addr[0] & 0xFF) != 0xFF) { - - now = get_timer(start); - - if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned char *)info->start[0]; - - addr[0] = 0xF0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - l = addr - wp; - - if (l != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - rc = write_word(info, wp, data); - - if (rc != 0) - return rc; - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return 0; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - return write_word(info, wp, data); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - volatile unsigned char *cdest, *cdata; - volatile unsigned char *addr = - (volatile unsigned char *)(info->start[0]); - ulong start; - int flag, count = 4 ; - - cdest = (volatile unsigned char *)dest ; - cdata = (volatile unsigned char *)&data ; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return 2; - - while (count--) { - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; - - *cdest = *cdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((*cdest ^ *cdata) & 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return 1; - } - - cdata++ ; - cdest++ ; - } - return 0; -} diff --git a/board/genietv/genietv.c b/board/genietv/genietv.c deleted file mode 100644 index 0a015ea2de..0000000000 --- a/board/genietv/genietv.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - * genietv/genietv.c - * - * The GENIETV is using the following physical memorymap (copied from - * the FADS configuration): - * - * ff020000 -> ff02ffff : pcmcia - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM - * ff000000 -> ff00ffff : IMAP internal in the cpu - * 02800000 -> 0287ffff : flash connected to CS0 - * 00000000 -> nnnnnnnn : sdram setup by U-Boot - * - * CS pins are connected as follows: - * - * CS0 -512Kb boot flash - * CS1 - SDRAM #1 - * CS2 - SDRAM #2 - * CS3 - Flash #1 - * CS4 - Flash #2 - * CS5 - LON (if present) - * CS6 - PCMCIA #1 - * CS7 - PCMCIA #2 - * - * Ports are configured as follows: - * - * PA7 - SDRAM banks enable - */ - -#include <common.h> -#include <mpc8xx.h> - -#define CONFIG_SYS_PA7 0x0100 - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPMB RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBEEC00, - 0x1FFDDC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMB RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMB RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBEEC00, 0x1FFDDC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMB RAM) - */ - 0x1F2DFC04, 0xEEAFAC00, 0x01BE4C04, 0x1FFDDC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMB RAM) - */ - 0x1F0DFC04, 0xEEAFAC00, 0x10AF5C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BEEC04, 0x1FFDDC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMB RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMB RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity - */ - -int checkboard (void) -{ - puts ("Board: GenieTV\n"); - return 0; -} - -#if 0 -static void PrintState (void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &im->im_memctl; - - printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0, - memctl->memc_or0); - printf ("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1, - memctl->memc_or1); - printf ("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2, - memctl->memc_or2); -} -#endif - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &im->im_memctl; - long int size_b0, size_b1, size8; - - /* Enable SDRAM */ - - /* Configuring PA7 for general purpouse output pin */ - im->im_ioport.iop_papar &= ~CONFIG_SYS_PA7; /* 0 = general purpouse */ - im->im_ioport.iop_padir |= CONFIG_SYS_PA7; /* 1 = output */ - - /* Enable SDRAM - PA7 = 1 */ - im->im_ioport.iop_padat |= CONFIG_SYS_PA7; /* value of PA7 */ - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; - - upmconfig (UPMB, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - - memctl->memc_or1 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = - ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); - - memctl->memc_or2 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); - - /* perform SDRAM initialization sequence */ - memctl->memc_mar = 0x00000088; - - memctl->memc_mcr = 0x80802105; /* SDRAM bank 0 */ - - memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */ - - /* Execute refresh 8 times */ - memctl->memc_mbmr = (CONFIG_SYS_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X; - - memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */ - - memctl->memc_mcr = 0x80804130; /* SDRAM bank 1 - execute twice */ - - /* Execute refresh 4 times */ - memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - -#if 0 - PrintState (); -#endif -/* printf ("\nChecking bank1..."); */ - size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - size_b0 = size8; - -/* printf ("\nChecking bank2..."); */ - size_b1 = - dram_size (memctl->memc_mbmr, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); - - /* - * Final mapping: map bigger bank first - */ - - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) + - (size_b0 & BR_BA_MSK); - } else { - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - /* adjust refresh rate depending on SDRAM type, one bank */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; - } - - /* If no memory detected, disable SDRAM */ - if ((size_b0 + size_b1) == 0) { - printf ("disabling SDRAM!\n"); - /* Disable SDRAM - PA7 = 1 */ - im->im_ioport.iop_padat &= ~CONFIG_SYS_PA7; /* value of PA7 */ - } -/* else */ -/* printf("done! (%08lx)\n", size_b0 + size_b1); */ - -#if 0 - PrintState (); -#endif - return (size_b0 + size_b1); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mbmr_value, long int *base, - long int maxsize) -{ - long size; - - /*memctl->memc_mbmr = mbmr_value; */ - - size = get_ram_size (base, maxsize); - - if (size) { -/* printf("(%08lx)", size); */ - } else { - printf ("(0)"); - } - - return (size); -} - -#if defined(CONFIG_CMD_PCMCIA) - -#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char *) CONFIG_SYS_PCMCIA_MEM_ADDR; -#endif - -int pcmcia_init (void) -{ - volatile pcmconf8xx_t *pcmp; - uint v, slota, slotb; - - /* - ** Enable the PCMCIA for a Flash card. - */ - pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia)); - -#if 0 - pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR; - pcmp->pcmc_por0 = 0xc00ff05d; -#endif - - /* Set all slots to zero by default. */ - pcmp->pcmc_pgcra = 0; - pcmp->pcmc_pgcrb = 0; -#ifdef PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0x40; -#endif -#ifdef PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0x40; -#endif - - /* Check if any PCMCIA card is luged in. */ - slota = (pcmp->pcmc_pipr & 0x18000000) == 0; - slotb = (pcmp->pcmc_pipr & 0x00001800) == 0; - - if (!(slota || slotb)) { - printf ("No card present\n"); -#ifdef PCMCIA_SLOT_A - pcmp->pcmc_pgcra = 0; -#endif -#ifdef PCMCIA_SLOT_B - pcmp->pcmc_pgcrb = 0; -#endif - return -1; - } else - printf ("Unknown card ("); - - v = 0; - - switch ((pcmp->pcmc_pipr >> 14) & 3) { - case 0x00: - printf ("5V"); - v = 5; - break; - case 0x01: - printf ("5V and 3V"); - v = 3; - break; - case 0x03: - printf ("5V, 3V and x.xV"); - v = 3; - break; - } - - switch (v) { - case 3: - printf ("; using 3V"); - /* Enable 3 volt Vcc. */ - - break; - - default: - printf ("; unknown voltage"); - return -1; - } - printf (")\n"); - /* disable pcmcia reset after a while */ - - udelay (20); - - pcmp->pcmc_pgcrb = 0; - - /* If you using a real hd you should give a short - * spin-up time. */ -#ifdef CONFIG_DISK_SPINUP_TIME - udelay (CONFIG_DISK_SPINUP_TIME); -#endif - - return 0; -} -#endif diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds deleted file mode 100644 index 70ab702fd9..0000000000 --- a/board/genietv/u-boot.lds +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - lib/built-in.o (.text*) - net/built-in.o (.text*) - arch/powerpc/cpu/mpc8xx/built-in.o (.text*) - board/genietv/built-in.o (.text*) - arch/powerpc/lib/built-in.o (.text*) - *(.text.do_load_serial*) - *(.text.do_mem_*) - *(.text.do_bootm*) - - . = env_offset; - common/env_embedded.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } - . = ALIGN(4); - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug deleted file mode 100644 index cc8cd3a631..0000000000 --- a/board/genietv/u-boot.lds.debug +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - lib/zlib.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - . = ALIGN(256 * 1024); - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/hidden_dragon/early_init.S b/board/hidden_dragon/early_init.S deleted file mode 100644 index 5a9b924ef9..0000000000 --- a/board/hidden_dragon/early_init.S +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2001 - * Thomas Koeller, tkoeller@gmx.net - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASSEMBLY__ -#define __ASSEMBLY__ 1 -#endif - -#include <asm-offsets.h> -#include <config.h> -#include <asm/processor.h> -#include <mpc824x.h> -#include <ppc_asm.tmpl> - -#if defined(USE_DINK32) - /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ - #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) -#else - #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) -#endif - - .text - - /* Values to program into memory controller registers */ -tbl: .long MCCR1, MCCR1VAL - .long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT - .long MCCR3 - .long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ - (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \ - (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT) - .long MCCR4 - .long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ - (CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \ - (((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ - ((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \ - (CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ - (CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ - ((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) - .long MSAR1 - .long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR1 - .long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MSAR2 - .long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR2 - .long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR1 - .long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR1 - .long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR2 - .long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR2 - .long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long 0 - - - /* - * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This - * must be done in assembly, since we have no stack at this point. - */ - .global early_init_f -early_init_f: - mflr r10 - - /* basic memory controller configuration */ - lis r3, CONFIG_ADDR_HIGH - lis r4, CONFIG_DATA_HIGH - bl lab -lab: mflr r5 - lwzu r0, tbl - lab(r5) -loop: lwz r1, 4(r5) - stwbrx r0, 0, r3 - eieio - stwbrx r1, 0, r4 - eieio - lwzu r0, 8(r5) - cmpli cr0, 0, r0, 0 - bne cr0, loop - - /* set bank enable bits */ - lis r0, MBER@h - ori r0, 0, MBER@l - li r1, CONFIG_SYS_BANK_ENABLE - stwbrx r0, 0, r3 - eieio - stb r1, 0(r4) - eieio - - /* delay loop */ - lis r0, 0x0003 - mtctr r0 -delay: bdnz delay - - /* enable memory controller */ - lis r0, MCCR1@h - ori r0, 0, MCCR1@l - stwbrx r0, 0, r3 - eieio - lwbrx r0, 0, r4 - oris r0, 0, MCCR1_MEMGO@h - stwbrx r0, 0, r4 - eieio - - /* set up stack pointer */ - lis r1, CONFIG_SYS_INIT_SP_OFFSET@h - ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l - - mtlr r10 - blr diff --git a/board/ids8247/Makefile b/board/ids/ids8247/Makefile index 99c47b6697..99c47b6697 100644 --- a/board/ids8247/Makefile +++ b/board/ids/ids8247/Makefile diff --git a/board/ids8247/ids8247.c b/board/ids/ids8247/ids8247.c index 1b2d0e09a9..1b2d0e09a9 100644 --- a/board/ids8247/ids8247.c +++ b/board/ids/ids8247/ids8247.c diff --git a/board/ids/ids8313/Makefile b/board/ids/ids8313/Makefile new file mode 100644 index 0000000000..56cfd403f4 --- /dev/null +++ b/board/ids/ids8313/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2013 +# Heiko Schocher, DENX Software Engineering, <hs@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ids8313.o diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c new file mode 100644 index 0000000000..f742143bb9 --- /dev/null +++ b/board/ids/ids8313/ids8313.c @@ -0,0 +1,208 @@ +/* + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (c) 2011 IDS GmbH, Germany + * ids8313.c - ids8313 board support. + * + * Sergej Stepanov <ste@ids.de> + * Based on board/freescale/mpc8313erdb/mpc8313erdb.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mpc83xx.h> +#include <spi.h> +#include <libfdt.h> + +DECLARE_GLOBAL_DATA_PTR; +/** CPLD contains the info about: + * - board type: *pCpld & 0xF0 + * - hw-revision: *pCpld & 0x0F + * - cpld-revision: *pCpld+1 + */ +int checkboard(void) +{ + char *pcpld = (char *)CONFIG_SYS_CPLD_BASE; + u8 u8Vers = readb(pcpld); + u8 u8Revs = readb(pcpld + 1); + + printf("Board: "); + switch (u8Vers & 0xF0) { + case '\x40': + printf("CU73X"); + break; + case '\x50': + printf("CC73X"); + break; + default: + printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs); + return 0; + } + printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n", + u8Vers & 0x0F, u8Revs & 0xFF); + return 0; +} + +/* + * fixed sdram init + */ +int fixed_sdram(unsigned long config) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE << 20; + +#ifndef CONFIG_SYS_RAMBOOT + u32 msize_log2 = __ilog2(msize); + + out_be32(&im->sysconf.ddrlaw[0].bar, + (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000)); + out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + sync(); + + /* + * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], + * or the DDR2 controller may fail to initialize correctly. + */ + udelay(50000); + + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); + out_be32(&im->ddr.cs_config[0], config); + + /* currently we use only one CS, so disable the other banks */ + out_be32(&im->ddr.cs_config[1], 0); + out_be32(&im->ddr.cs_config[2], 0); + out_be32(&im->ddr.cs_config[3], 0); + + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); + + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); + + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); + sync(); + udelay(300); + + /* enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + /* now check the real size */ + disable_addr_trans(); + msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); + enable_addr_trans(); +#endif + return msize; +} + +static int setup_sdram(void) +{ + u32 msize = CONFIG_SYS_DDR_SIZE << 20; + long int size_01, size_02; + + size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG); + size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256); + + if (size_01 > size_02) + msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG); + else + msize = size_02; + + return msize; +} + +phys_size_t initdram(int board_type) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + fsl_lbc_t *lbc = &im->im_lbc; + u32 msize = 0; + + if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + msize = setup_sdram(); + + out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); + out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); + sync(); + + return msize; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif + +/* gpio mask for spi_cs */ +#define IDSCPLD_SPI_CS_MASK 0x00000001 +/* spi_cs multiplexed through cpld */ +#define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf) + +#if defined(CONFIG_MISC_INIT_R) +/* srp umcr mask for rts */ +#define IDSUMCR_RTS_MASK 0x04 +int misc_init_r(void) +{ + /*srp*/ + duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0]; + duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1]; + + gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; + + /* deactivate spi_cs channels */ + out_8(spi_base, 0); + /* deactivate the spi_cs */ + setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK); + /*srp - deactivate rts*/ + out_8(&uart1->umcr, IDSUMCR_RTS_MASK); + out_8(&uart2->umcr, IDSUMCR_RTS_MASK); + + + gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE; + return 0; +} +#endif + +#ifdef CONFIG_MPC8XXX_SPI +/* + * The following are used to control the SPI chip selects + */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && ((cs >= 0) && (cs <= 2)); +} + +void spi_cs_activate(struct spi_slave *slave) +{ + gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; + + /* select the spi_cs channel */ + out_8(spi_base, 1 << slave->cs); + /* activate the spi_cs */ + clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; + u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE; + + /* select the spi_cs channel */ + out_8(spi_base, 1 << slave->cs); + /* deactivate the spi_cs */ + setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK); +} +#endif /* CONFIG_HARD_SPI */ diff --git a/board/incaip/Makefile b/board/incaip/Makefile deleted file mode 100644 index 602d30ecee..0000000000 --- a/board/incaip/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = incaip.o flash.o -obj-y += lowlevel_init.o diff --git a/board/incaip/README b/board/incaip/README deleted file mode 100644 index 132915292e..0000000000 --- a/board/incaip/README +++ /dev/null @@ -1,57 +0,0 @@ - -Flash programming on the INCA-IP board is complicated because of the -EBU swapping unit. A BDI2000 can be used for flash programming only -if the EBU swapping unit is enabled; otherwise it will not detect the -flash memory. But the EBU swapping unit is disadbled after reset, so -if you program some code to flash with the swapping unit on, it will -not be runnable with the swapping unit off. - -The consequence is that you have to write a pre-swapped image to -flash using the BDI2000. A simple host-side tool "inca-swap-bytes" is -provided in the "tools/" directory. Use it as follows: - - bash$ ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp - -Note that the current BDI config file _disables_ the EBU swapping -unit for the flash bank 0. To enable it, (this is required for the -BDI flash commands to work) uncomment the following line in the -config file: - - ;WM32 0xb8000260 0x404161ff ; Swapping unit enabled - -and comment out - - WM32 0xb8000260 0x004161ff ; Swapping unit disabled - -Alternatively, you can use "mm 0xb8000260 <value>" commands to -enable/disable the swapping unit manually. - -Just for reference, here is the complete sequence of actions we took -to install a U-Boot image into flash. - - 1. ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp - - 2. From BDI: - - mm 0xb8000260 0x404161ff - erase 0xb0000000 - erase 0xb0010000 - prog 0xb0000000 /tftpboot/INCA/u-boot.bin.swp bin - mm 0xb8000260 0x004161ff - go 0xb0000000 - - -Ethernet autonegotiation needs some time to complete. Instead of -delaying the boot process in all cases, we just start the -autonegotiation process when U-Boot comes up and that is all. Most -likely, it will complete by the time the network transfer is -attempted for the first time. In the worst case, if a transfer is -attempted before the autonegotiation is complete, just a single -packet would be lost resulting in a single timeout error, and then -the transfer would proceed normally. So the time that we would have -lost unconditionally waiting for the autonegotiation to complete, we -have to wait only if the file transfer is started immediately after -reset. We've verified that this works for all the clock -configurations. - -(C) 2003 Wolfgang Denk diff --git a/board/incaip/config.mk b/board/incaip/config.mk deleted file mode 100644 index e854f8e655..0000000000 --- a/board/incaip/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# INCA-IP board with MIPS 4Kc CPU core -# - -# ROM version -CONFIG_SYS_TEXT_BASE = 0xB0000000 - -# RAM version -#CONFIG_SYS_TEXT_BASE = 0x80100000 diff --git a/board/incaip/flash.c b/board/incaip/flash.c deleted file mode 100644 index a786ac9327..0000000000 --- a/board/incaip/flash.c +++ /dev/null @@ -1,655 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/inca-ip.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -#if 0 -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa -#else -#define FLASH_CYCLE1 0x0554 -#define FLASH_CYCLE2 0x02ab -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; - ulong * buscon = (ulong *) - ((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2); - - /* Disable write protection */ - *buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS; - -#if 1 - memset(&flash_info[i], 0, sizeof(flash_info_t)); -#endif - - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", - i, flash_info[i].size); - } - - size += flash_info[i].size; - } - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CONFIG_SYS_MONITOR_BASE)); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - flash_get_info(CONFIG_ENV_ADDR)); -#endif - - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base < info->start[0] + info->size) - break; - } - - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[1] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) { - - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - /* show that we're waiting */ - if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - - return (res); -} diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c deleted file mode 100644 index 217b8afa34..0000000000 --- a/board/incaip/incaip.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <asm/addrspace.h> -#include <asm/inca-ip.h> -#include <asm/io.h> -#include <asm/reboot.h> - -extern uint incaip_get_cpuclk(void); - -void _machine_restart(void) -{ - *INCA_IP_WDT_RST_REQ = 0x3f; -} - -static ulong max_sdram_size(void) -{ - /* The only supported SDRAM data width is 16bit. - */ -#define CONFIG_SYS_DW 2 - - /* The only supported number of SDRAM banks is 4. - */ -#define CONFIG_SYS_NB 4 - - ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; - int cols = cfgpb0 & 0xF; - int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB; - - return size; -} - -phys_size_t initdram(int board_type) -{ - int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0; - ulong size, max_size = 0; - ulong our_address; - - asm volatile ("move %0, $25" : "=r" (our_address) :); - - /* Can't probe for RAM size unless we are running from Flash. - */ - if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1)) - { - return max_sdram_size(); - } - - for (cols = 0x8; cols <= 0xC; cols++) - { - for (rows = 0xB; rows <= 0xD; rows++) - { - *INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) | - (rows << 4) | cols; - size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - max_sdram_size()); - - if (size > max_size) - { - best_val = *INCA_IP_SDRAM_MC_CFGPB0; - max_size = size; - } - } - } - - *INCA_IP_SDRAM_MC_CFGPB0 = best_val; - return max_size; -} - -int checkboard (void) -{ - unsigned long chipid = *INCA_IP_WDT_CHIPID; - int part_num; - - puts ("Board: INCA-IP "); - part_num = (chipid >> 12) & 0xffff; - switch (part_num) { - case 0xc0: - printf ("Standard Version, "); - break; - case 0xc1: - printf ("Basic Version, "); - break; - default: - printf ("Unknown Part Number 0x%x ", part_num); - break; - } - - printf ("Chip V1.%ld, ", (chipid >> 28)); - - printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000); - - set_io_port_base(0); - - return 0; -} - -#if defined(CONFIG_INCA_IP_SWITCH) -int board_eth_init(bd_t *bis) -{ - return inca_switch_initialize(bis); -} -#endif diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S deleted file mode 100644 index b6cf6a9960..0000000000 --- a/board/incaip/lowlevel_init.S +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Memory sub-system initialization code for INCA-IP development board. - * - * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <asm/regdef.h> - - -#define EBU_MODUL_BASE 0xB8000200 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0100(value) -#define MC_ERRADDR(value) 0x0108(value) -#define MC_IOGP(value) 0x0800(value) -#define MC_SELFRFSH(value) 0x0A00(value) -#define MC_CTRLENA(value) 0x1000(value) -#define MC_MRSCODE(value) 0x1008(value) -#define MC_CFGDW(value) 0x1010(value) -#define MC_CFGPB0(value) 0x1018(value) -#define MC_LATENCY(value) 0x1038(value) -#define MC_TREFRESH(value) 0x1040(value) - -#define CGU_MODUL_BASE 0xBF107000 -#define CGU_PLL1CR(value) 0x0008(value) -#define CGU_DIVCR(value) 0x0010(value) -#define CGU_MUXCR(value) 0x0014(value) -#define CGU_PLL1SR(value) 0x000C(value) - - .set noreorder - - -/* - * void ebu_init(long) - * - * a0 has the clock value we are going to run at - */ - .globl ebu_init - .ent ebu_init -ebu_init: -__ebu_init: - - li t1, EBU_MODUL_BASE - li t2, 0xA0000041 - sw t2, EBU_ADDSEL0(t1) - li t2, 0xA0800041 - sw t2, EBU_ADDSEL2(t1) - li t2, 0xBE0000F1 - sw t2, EBU_ADDSEL1(t1) - - li t3, 100000000 - beq a0, t3, 1f - nop - li t3, 133000000 - beq a0, t3, 2f - nop - li t3, 150000000 - beq a0, t3, 2f - nop - b 3f - nop - - /* 100 MHz */ -1: - li t2, 0x8841417D - sw t2, EBU_BUSCON0(t1) - sw t2, EBU_BUSCON2(t1) - li t2, 0x684142BD - b 3f - sw t2, EBU_BUSCON1(t1) /* delay slot */ - - /* 133 or 150 MHz */ -2: - li t2, 0x8841417E - sw t2, EBU_BUSCON0(t1) - sw t2, EBU_BUSCON2(t1) - li t2, 0x684143FD - sw t2, EBU_BUSCON1(t1) -3: - jr ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: -__cgu_init: - - li t1, CGU_MODUL_BASE - - li t3, 100000000 - beq a0, t3, 1f - nop - li t3, 133000000 - beq a0, t3, 2f - nop - li t3, 150000000 - beq a0, t3, 3f - nop - b 5f - nop - - /* 100 MHz clock */ -1: - li t2, 0x80000014 - sw t2, CGU_DIVCR(t1) - li t2, 0x80000000 - sw t2, CGU_MUXCR(t1) - li t2, 0x800B0001 - b 5f - sw t2, CGU_PLL1CR(t1) /* delay slot */ - - /* 133 MHz clock */ -2: - li t2, 0x80000054 - sw t2, CGU_DIVCR(t1) - li t2, 0x80000000 - sw t2, CGU_MUXCR(t1) - li t2, 0x800B0001 - b 5f - sw t2, CGU_PLL1CR(t1) /* delay slot */ - - /* 150 MHz clock */ -3: - li t2, 0x80000017 - sw t2, CGU_DIVCR(t1) - li t2, 0xC00B0001 - sw t2, CGU_PLL1CR(t1) - li t3, 0x80000000 -4: - lw t2, CGU_PLL1SR(t1) - and t2, t2, t3 - beq t2, zero, 4b - nop - li t2, 0x80000001 - sw t2, CGU_MUXCR(t1) -5: - jr ra - nop - - .end cgu_init - - -/* - * void sdram_init(long) - * - * a0 has the clock value - */ - .globl sdram_init - .ent sdram_init -sdram_init: -__sdram_init: - - li t1, MC_MODUL_BASE - -#if 0 - /* Disable memory controller before changing any of its registers */ - sw zero, MC_CTRLENA(t1) -#endif - - li t2, 100000000 - beq a0, t2, 1f - nop - li t2, 133000000 - beq a0, t2, 2f - nop - li t2, 150000000 - beq a0, t2, 3f - nop - b 5f - nop - - /* 100 MHz clock */ -1: - /* Set clock ratio (clkrat=1:1, rddel=3) */ - li t2, 0x00000003 - sw t2, MC_IOGP(t1) - - /* Set sdram refresh rate (4K/64ms @ 100MHz) */ - li t2, 0x0000061A - b 4f - sw t2, MC_TREFRESH(t1) - - /* 133 MHz clock */ -2: - /* Set clock ratio (clkrat=1:1, rddel=3) */ - li t2, 0x00000003 - sw t2, MC_IOGP(t1) - - /* Set sdram refresh rate (4K/64ms @ 133MHz) */ - li t2, 0x00000822 - b 4f - sw t2, MC_TREFRESH(t1) - - /* 150 MHz clock */ -3: - /* Set clock ratio (clkrat=3:2, rddel=4) */ - li t2, 0x00000014 - sw t2, MC_IOGP(t1) - - /* Set sdram refresh rate (4K/64ms @ 150MHz) */ - li t2, 0x00000927 - sw t2, MC_TREFRESH(t1) - -4: - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Clear Power-down registers */ - sw zero, MC_SELFRFSH(t1) - - /* Set CAS Latency */ - li t2, 0x00000020 /* CL = 2 */ - sw t2, MC_MRSCODE(t1) - - /* Set word width to 16 bit */ - li t2, 0x2 - sw t2, MC_CFGDW(t1) - - /* Set CS0 to SDRAM parameters */ - li t2, 0x000014C9 - sw t2, MC_CFGPB0(t1) - - /* Set SDRAM latency parameters */ - li t2, 0x00026325 /* BC PC100 */ - sw t2, MC_LATENCY(t1) - -5: - /* Finally enable the controller */ - li t2, 0x00000001 - sw t2, MC_CTRLENA(t1) - - jr ra - nop - - .end sdram_init - - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - - /* Disable Watchdog. - */ - la t9, disable_incaip_wdt - jalr t9 - nop - - /* EBU, CGU and SDRAM Initialization. - */ - li a0, CONFIG_CPU_CLOCK_RATE - move t0, ra - - /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init() - * modify t0 and a0. - */ - bal __cgu_init - nop - bal __ebu_init - nop - bal __sdram_init - nop - move ra, t0 - - jr ra - nop - - .end lowlevel_init diff --git a/board/lubbock/Makefile b/board/lubbock/Makefile deleted file mode 100644 index 8aa513ac44..0000000000 --- a/board/lubbock/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := lubbock.o flash.o diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c deleted file mode 100644 index f6bb22c2e4..0000000000 --- a/board/lubbock/flash.c +++ /dev/null @@ -1,412 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/byteorder/swab.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c deleted file mode 100644 index 0daff9abf1..0000000000 --- a/board/lubbock/lubbock.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/pxa.h> -#include <asm/arch/pxa-regs.h> -#include <asm/arch/regs-mmc.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of Lubbock-Board */ - gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Configure GPIO6 and GPIO8 as OUT, AF1. */ - setbits_le32(GPDR0, (1 << 6) | (1 << 8)); - clrsetbits_le32(GAFR0_L, (3 << 12) | (3 << 16), (1 << 12) | (1 << 16)); - - return 0; -} - -#ifdef CONFIG_CMD_MMC -int board_mmc_init(bd_t *bis) -{ - pxa_mmc_register(0); - return 0; -} -#endif - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - -int dram_init(void) -{ - pxa2xx_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/mbx8xx/Makefile b/board/mbx8xx/Makefile deleted file mode 100644 index 2074b6b904..0000000000 --- a/board/mbx8xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = mbx8xx.o flash.o vpd.o pcmcia.o diff --git a/board/mbx8xx/README b/board/mbx8xx/README deleted file mode 100644 index c889fe9791..0000000000 --- a/board/mbx8xx/README +++ /dev/null @@ -1,68 +0,0 @@ -IMPORTANT NOTE - read before defining CONFIG_SYS_USE_OSCCLK in your board - config file!!! - - -WARNING: Wrong settings of this parameter have the potential to -damage hardware by running the MBX's CPU at frequencies that exceed -it's rating and/or overdriving the it's SPLL! - - -Ramblings: -1) Motorola offered 12 different variants of the MBX, 6 823s and 6 860s. -2) Of these 12 variants, only 2 were entry level boards. -3) I believe that the 2 entry level boards were the only ones that - used OSCM clocking. I can't be completely certain of this at this - point. -4) Motorola never offered an MBX that ran faster than 50Mhz. -5) The 10, non-entry level boards, ran at 40Mhz. -6) The EXTCLK input has a minimum clock of 15Mhz for the 823/860. -7) Motorola no longer sells MBXs. - -Based on this information, I can surmise that the default power-on -reset clocking was one of the following three options. - -Multiplier SPLL Options ------------------------------------- -513 OSCM is SPLL input -5 OSCM is SPLL input -1 EXTCLK is SPLL input - -The forth option: - -5 EXTCLK is SPLL input - -is not possible on MBXs. This is because the minimum EXTCLK input -frequency is 15Mhz. 5 * 15Mhz = 75 Mhz. There was no variant that ran -above 50 Mhz. - -The board I have borrowed definitely uses a multiplier of 1 for -EXTCLK and runs at 40Mhz. I even went so far as to put a scope on it. - -One of the two default OSCM modes are most likely what was used on -the entry level boards to cheapen them by eliminating the external -crystal oscillator. - -To add insult to injury, the stupid 860 PLPRCR register retains it's -multiplication factor through hard resets. You can't clear it out -because it is battery backed and once it is set wrong, it stays -wrong. The only way to reset it, so that it takes on it's default -multiplier is to disconnect all power including external, batteries, -as well discharging caps on the board. This precludes the fact that -your 860 may be quite DEAD by this time! - -If you don't setup the multiplication factor for boards that use the -OSCM input, they won't run correctly, but at least they won't be -dead. - -Addtionally, there is no good way to determine the clock input source -from CPU register data. The only way to deal with this is either hard -code it, determine the correct value with some rather NASTY timing -loops, or try to grok it from external data sources. Motorola -firmware opts for the NASTY timing loops, but needs to configure the -serial ports to do so. - - -You may have a legitimate need to define CONFIG_SYS_USE_OSCCLK if your -MBX8xx board is using the OSCM clocking mode. - -You better know what you are doing here. diff --git a/board/mbx8xx/csr.h b/board/mbx8xx/csr.h deleted file mode 100644 index 937060973e..0000000000 --- a/board/mbx8xx/csr.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __csr_h -#define __csr_h - -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * Control and Status Register definitions for the MBX - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* bits for control register #1 / status register #1 */ -#define CSR1_ETEN 0x80 /* Ethernet Transceiver Enabled */ -#define CSR1_ELEN 0x40 /* Ethernet XCVR in Internal Loopback */ -#define CSR1_EAEN 0x20 /* Auto selection TP/AUI Enabled */ -#define CSR1_TPEN 0x10 /* TP manually selected */ -#define CSR1_FDDIS 0x08 /* Full Duplex Mode disabled */ -#define CSR1_FCTEN 0x04 /* Collision Testing of XCVR disabled */ -#define CSR1_COM1EN 0x02 /* COM1 signals routed to RS232 Transceiver */ -#define CSR1_XCVRDIS 0x01 /* Onboard RS232 Transceiver Disabled */ - -/* bits for control register #2 */ -#define CR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ -#define CR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ -#define CR2_BRDFAIL 0x08 /* Board fail */ -#define CR2_SWS1 0x04 /* Software Status #2 LED */ -#define CR2_SWS2 0x02 /* Software Status #2 LED */ -#define CR2_QSPANRST 0x01 /* Reset QSPAN */ - -/* bits for status register #2 */ -#define SR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ -#define SR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ -#define SR2_BATGD 0x08 /* Low Voltage indication for onboard bat */ -#define SR2_NVBATGD 0x04 /* Low Voltage indication for NVRAM */ -#define SR2_RDY 0x02 /* Flash programming status bit */ -#define SR2_FT 0x01 /* Reserved for Factory test purposes */ - -#define MBX_CSR1 (*((uchar *)CONFIG_SYS_CSR_BASE)) -#define MBX_CSR2 (*((uchar *)CONFIG_SYS_CSR_BASE + 1)) - -#endif /* __csr_h */ diff --git a/board/mbx8xx/dimm.h b/board/mbx8xx/dimm.h deleted file mode 100644 index b40f112356..0000000000 --- a/board/mbx8xx/dimm.h +++ /dev/null @@ -1,98 +0,0 @@ -#ifndef __dimm_h -#define __dimm_h - -/* - * Module name: %M% - * Description: - * Serial Presence Detect Definitions Module - * SCCS identification: %I% - * Branch: %B% - * Sequence: %S% - * Date newest applied delta was created (MM/DD/YY): %G% - * Time newest applied delta was created (HH:MM:SS): %U% - * SCCS file name %F% - * Fully qualified SCCS file name: - * %P% - * Copyright: - * (C) COPYRIGHT MOTOROLA, INC. 1996 - * ALL RIGHTS RESERVED - * Notes: - * 1. All data was taken from an IBM application note titled - * "Serial Presence Detect Definitions". - * History: - * Date Who - * - * 10/24/96 Rob Baxter - * Initial release. - * - */ - -/* - * serial PD byte assignment address map (256 byte EEPROM) - */ -typedef struct dimm -{ - uchar n_bytes; /* 00 number of bytes written/used */ - uchar t_bytes; /* 01 total number of bytes in serial PD device */ - uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */ - uchar n_row; /* 03 number of rows */ - uchar n_col; /* 04 number of columns */ - uchar n_banks; /* 05 number of banks */ - uchar data_w_lo; /* 06 data width */ - uchar data_w_hi; /* 07 data width */ - uchar ifl; /* 08 interface levels */ - uchar a_ras; /* 09 RAS access */ - uchar a_cas; /* 0A CAS access */ - uchar ct; /* 0B configuration type (non-parity/parity/ECC) */ - uchar refresh_rt; /* 0C refresh rate/type */ - uchar p_dram_o; /* 0D primary DRAM organization */ - uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */ - uchar reserved[17]; /* 0F reserved fields for future offerings */ - uchar ss_info[32]; /* 20 superset information (may be used in the future) */ - uchar m_info[64]; /* 40 manufacturer information (optional) */ - uchar unused[128]; /* 80 unused storage locations */ -} dimm_t; - -/* - * memory type definitions - */ -#define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */ -#define DIMM_MT_EDO 2 /* EDO (extended data out) */ -#define DIMM_MT_PN 3 /* pipelined nibble */ -#define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */ - -/* - * row addresses definitions - */ -#define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */ -#define DIMM_RA_MASK 0x7f /* number of row addresses mask */ - -/* - * module interface levels definitions - */ -#define DIMM_IFL_TTL 0 /* TTL/5V tolerant */ -#define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */ -#define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */ -#define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */ -#define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */ - -/* - * DIMM configuration type definitions - */ -#define DIMM_CT_NONE 0 /* none */ -#define DIMM_CT_PARITY 1 /* parity */ -#define DIMM_CT_ECC 2 /* ECC */ - -/* - * row addresses definitions - */ -#define DIMM_RRT_SR (1<<7) /* self refresh flag */ -#define DIMM_RRT_MASK 0x7f /* refresh rate mask */ -#define DIMM_RRT_NRML 0x00 /* normal (15.625us) */ -#define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */ -#define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */ -#define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */ -#define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */ -#define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */ - -#endif /* __dimm_h */ diff --git a/board/mbx8xx/flash.c b/board/mbx8xx/flash.c deleted file mode 100644 index fa07152cc8..0000000000 --- a/board/mbx8xx/flash.c +++ /dev/null @@ -1,392 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger <mgroeger@sysgo.de> - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AM290[48]0B devices - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include "vpd.h" - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size, totsize; - int i; - ulong addr; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - totsize = 0; - addr = 0xfc000000; - for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - size = flash_get_size((vu_long *)addr, &flash_info[i]); - if (flash_info[i].flash_id == FLASH_UNKNOWN) - break; - totsize += size; - addr += size; - } - - addr = 0xfe000000; - for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - - size = flash_get_size((vu_long *)addr, &flash_info[i]); - if (flash_info[i].flash_id == FLASH_UNKNOWN) - break; - totsize += size; - addr += size; - } - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - return (totsize); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id >> 16) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - case AMD_ID_F080B: - printf ("AM29F080B (8 Mbit)\n"); - break; - case AMD_ID_F016D: - printf ("AM29F016D (16 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong vendor, devid; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x90909090; - - vendor = addr[0]; - devid = addr[1] & 0xff; - - /* only support AMD */ - if (vendor != 0x01010101) { - return 0; - } - - vendor &= 0xf; - devid &= 0xff; - - if (devid == AMD_ID_F040B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 8; - info->size = info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F080B) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 16; - info->size = 4 * info->sector_count * 0x10000; - } - else if (devid == AMD_ID_F016D) { - info->flash_id = vendor << 16 | devid; - info->sector_count = 32; - info->size = 4 * info->sector_count * 0x10000; - } - else { - printf ("## Unknown Flash Type: %08lx\n", devid); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* sector base address */ - info->start[i] = base + i * (info->size / info->sector_count); - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0XAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0x80808080; - addr[0x0555] = 0XAAAAAAAA; - addr[0x02AA] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0xAAAAAAAA; - addr[0x02AA] = 0x55555555; - addr[0x0555] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/mbx8xx/mbx8xx.c b/board/mbx8xx/mbx8xx.c deleted file mode 100644 index 98c723f047..0000000000 --- a/board/mbx8xx/mbx8xx.c +++ /dev/null @@ -1,383 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * Board specific routines for the MBX - * - * - initialisation - * - interface to VPD data (mac address, clock speeds) - * - memory controller - * - serial io initialisation - * - ethernet io initialisation - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <commproc.h> -#include <mpc8xx.h> -#include <net.h> -#include "dimm.h" -#include "vpd.h" -#include "csr.h" - -/* ------------------------------------------------------------------------- */ - -static const uint sdram_table_40[] = { - /* DRAM - single read. (offset 0 in upm RAM) - */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00, - 0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst read. (offset 8 in upm RAM) - */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08, - 0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08, - 0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - single write. (offset 18 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst write. (offset 20 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* refresh (offset 30 in upm RAM) - */ - 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, - 0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* exception. (offset 3c in upm RAM) - */ - 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, -}; - -static const uint sdram_table_50[] = { - /* DRAM - single read. (offset 0 in upm RAM) - */ - 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04, - 0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst read. (offset 8 in upm RAM) - */ - 0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04, - /* 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04, */ - 0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, - 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04, - /* 0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005, */ - 0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005, - - /* DRAM - single write. (offset 18 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804, - 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* DRAM - burst write. (offset 20 in upm RAM) - */ - 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, - 0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* refresh (offset 30 in upm RAM) - */ - 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, - 0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, - 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, - - /* exception. (offset 3c in upm RAM) - */ - 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, -}; - -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_SYS_USE_OSCCLK -static unsigned int get_reffreq(void); -#endif -static unsigned int board_get_cpufreq(void); - -void mbx_init (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - ulong speed, plprcr, sccr; - ulong br0_32 = memctl->memc_br0 & 0x400; - - /* real-time clock status and control register */ - immr->im_sitk.sitk_rtcsck = KAPWR_KEY; - immr->im_sit.sit_rtcsc = 0x00C3; - - /* SIEL and SIMASK Registers (see MBX PRG 2-3) */ - immr->im_siu_conf.sc_simask = 0x00000000; - immr->im_siu_conf.sc_siel = 0xAAAA0000; - immr->im_siu_conf.sc_tesr = 0xFFFFFFFF; - - /* - * Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus: - * 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h) - * 2. RAM Specs (see dimm.h) - * 2. DIMM Specs (see dimm.h) - */ - vpd_init (); - - /* system clock and reset control register */ - immr->im_clkrstk.cark_sccrk = KAPWR_KEY; - sccr = immr->im_clkrst.car_sccr; - sccr &= SCCR_MASK; - sccr |= CONFIG_SYS_SCCR; - immr->im_clkrst.car_sccr = sccr; - - speed = board_get_cpufreq (); - -#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0) - plprcr = CONFIG_SYS_PLPRCR; -#else - plprcr = immr->im_clkrst.car_plprcr; - plprcr &= PLPRCR_MF_MSK; /* isolate MF field */ - plprcr |= CONFIG_SYS_PLPRCR; /* reset control bits */ -#endif - -#ifdef CONFIG_SYS_USE_OSCCLK /* See doc/README.MBX ! */ - plprcr |= ((speed + get_reffreq() / 2) / refclock - 1) << 20; -#endif - - immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; - immr->im_clkrst.car_plprcr = plprcr; - - /* - * preliminary setup of memory controller: - * - map Flash, otherwise configuration/status - * registers won't be accessible when read - * by board_init_f. - * - map NVRAM and configuation/status registers. - * - map pci registers. - * - DON'T map ram yet, this is done in initdram(). - */ - switch (speed / 1000000) { - case 40: - memctl->memc_br0 = 0xFE000000 | br0_32 | 1; - memctl->memc_or0 = 0xFF800930; - memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x920; - memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401; - break; - case 50: - memctl->memc_br0 = 0xFE000000 | br0_32 | 1; - memctl->memc_or0 = 0xFF800940; - memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x930; - memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401; - break; - default: - hang (); - break; - } -#ifdef CONFIG_USE_PCI - memctl->memc_or5 = CONFIG_SYS_PCIMEM_OR; - memctl->memc_br5 = CONFIG_SYS_PCIMEM_BASE | 0x001; - memctl->memc_or6 = CONFIG_SYS_PCIBRIDGE_OR; - memctl->memc_br6 = CONFIG_SYS_PCIBRIDGE_BASE | 0x001; -#endif - /* - * FIXME: I do not understand why I have to call this to - * initialise the control register here before booting from - * the PCMCIA card but if I do not the Linux kernel falls - * over in a big heap. If you can answer this question I - * would like to know about it. - */ - board_ether_init(); -} - -void board_serial_init (void) -{ - MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS); -} - -void board_ether_init (void) -{ - MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN); - MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS; -} - -static unsigned int board_get_cpufreq (void) -{ -#ifndef CONFIG_8xx_GCLK_FREQ - vpd_packet_t *packet; - ulong *p; - - packet = vpd_find_packet (VPD_PID_ICS); - p = (ulong *)packet->data; - return *p; -#else - return((unsigned int)CONFIG_8xx_GCLK_FREQ ); -#endif /* CONFIG_8xx_GCLK_FREQ */ -} - -#ifdef CONFIG_SYS_USE_OSCCLK -static unsigned int get_reffreq (void) -{ - vpd_packet_t *packet; - ulong *p; - - packet = vpd_find_packet (VPD_PID_RCS); - p = (ulong *)packet->data; - return *p; -} -#endif - -static void board_get_enetaddr(uchar *addr) -{ - int i; - vpd_packet_t *packet; - - packet = vpd_find_packet (VPD_PID_EA); - for (i = 0; i < 6; i++) - addr[i] = packet->data[i]; -} - -int misc_init_r(void) -{ - uchar enetaddr[6]; - - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - board_get_enetaddr(enetaddr); - eth_setenv_enetaddr("ethaddr", enetaddr); - } - - return 0; -} - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - vpd_packet_t *packet; - int i; - const char *const fmt = - "\n *** Warning: Low Battery Status - %s Battery ***"; - - puts ("Board: "); - - packet = vpd_find_packet (VPD_PID_PID); - for (i = 0; i < packet->size; i++) { - serial_putc (packet->data[i]); - } - packet = vpd_find_packet (VPD_PID_MT); - for (i = 0; i < packet->size; i++) { - serial_putc (packet->data[i]); - } - serial_putc ('('); - packet = vpd_find_packet (VPD_PID_FAN); - for (i = 0; i < packet->size; i++) { - serial_putc (packet->data[i]); - } - serial_putc (')'); - - if (!(MBX_CSR2 & SR2_BATGD)) - printf (fmt, "On-Board"); - if (!(MBX_CSR2 & SR2_NVBATGD)) - printf (fmt, "NVRAM"); - - serial_putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -static ulong get_ramsize (dimm_t * dimm) -{ - ulong size = 0; - - if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3 - || dimm->fmt == 4) { - size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks * - ((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8); - } - - return size; -} - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long ram_sz = 0; - unsigned long dimm_sz = 0; - dimm_t vpd_dimm, vpd_dram; - unsigned int speed = board_get_cpufreq () / 1000000; - - if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) { - dimm_sz = get_ramsize (&vpd_dimm); - } - if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) { - ram_sz = get_ramsize (&vpd_dram); - } - - /* - * Only initialize memory controller when running from FLASH. - * When running from RAM, don't touch it. - */ - if ((ulong) initdram & 0xff000000) { - ulong dimm_bank; - ulong br0_32 = memctl->memc_br0 & 0x400; - - switch (speed) { - case 40: - upmconfig (UPMA, (uint *) sdram_table_40, - sizeof (sdram_table_40) / sizeof (uint)); - memctl->memc_mptpr = 0x0200; - memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000; - memctl->memc_or7 = 0xff800930; - memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; - break; - case 50: - upmconfig (UPMA, (uint *) sdram_table_50, - sizeof (sdram_table_50) / sizeof (uint)); - memctl->memc_mptpr = 0x0200; - memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100; - memctl->memc_or7 = 0xff800940; - memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1; - break; - default: - hang (); - break; - } - - /* now map ram and dimm, largest one first */ - dimm_bank = dimm_sz / 2; - if (!dimm_sz) { - memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81; - memctl->memc_br2 = 0; - memctl->memc_br3 = 0; - } else if (ram_sz > dimm_bank) { - memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81; - memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE + ram_sz) | 0x81; - memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + ram_sz + dimm_bank) \ - | 0x81; - } else { - memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x81; - memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + dimm_bank) | 0x81; - memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE + dimm_sz) | 0x81; - } - } - - return ram_sz + dimm_sz; -} diff --git a/board/mbx8xx/pcmcia.c b/board/mbx8xx/pcmcia.c deleted file mode 100644 index 497e260a0a..0000000000 --- a/board/mbx8xx/pcmcia.c +++ /dev/null @@ -1,156 +0,0 @@ -#include <common.h> -#include <mpc8xx.h> -#include <pcmcia.h> - -#include "csr.h" - -#undef CONFIG_PCMCIA - -#if defined(CONFIG_CMD_PCMCIA) -#define CONFIG_PCMCIA -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -#define CONFIG_PCMCIA -#endif - -#ifdef CONFIG_PCMCIA - -/* A lot of this has been taken from the RPX code in this file it works from me. - I have added the voltage selection for the MBX board. */ - -/* MBX voltage bit in control register #2 */ -#define CR2_VPP12 ((uchar)0x10) -#define CR2_VPPVDD ((uchar)0x20) -#define CR2_VDD5 ((uchar)0x40) -#define CR2_VDD3 ((uchar)0x80) - -#define PCMCIA_BOARD_MSG "MBX860" - -int pcmcia_voltage_set (int slot, int vcc, int vpp) -{ - uchar reg = 0; - - debug ("voltage_set: PCMCIA_BOARD_MSG Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", - 'A' + slot, vcc / 10, vcc % 10, vpp / 10, vcc % 10); - - switch (vcc) { - case 0: - break; - case 33: - reg |= CR2_VDD3; - break; - case 50: - reg |= CR2_VDD5; - break; - default: - return 1; - } - - switch (vpp) { - case 0: - break; - case 33: - case 50: - if (vcc == vpp) { - reg |= CR2_VPPVDD; - } else { - return 1; - } - break; - case 120: - reg |= CR2_VPP12; - break; - default: - return 1; - } - - /* first, turn off all power */ - MBX_CSR2 &= ~(CR2_VDDSEL | CR2_VPPSEL); - - /* enable new powersettings */ - MBX_CSR2 |= reg; - debug ("MBX_CSR2 read = 0x%02x\n", MBX_CSR2); - - return (0); -} - -int pcmcia_hardware_enable (int slot) -{ - volatile pcmconf8xx_t *pcmp; - uint reg, mask; - - debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", - 'A' + slot); - - udelay (10000); - - pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia)); - - /* clear interrupt state, and disable interrupts */ - pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); - pcmp->pcmc_per &= ~PCMCIA_MASK (_slot_); - - /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ - debug ("Disable PCMCIA buffers and assert RESET\n"); - reg = 0; - reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX (_slot_) = reg; - udelay (500); - - /* remove all power */ - pcmcia_voltage_set (slot, 0, 0); - /* - * Make sure there is a card in the slot, then configure the interface. - */ - udelay(10000); - debug ("[%d] %s: PIPR(%p)=0x%x\n", - __LINE__,__FUNCTION__, - &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); - if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) { - printf (" No Card found\n"); - return (1); - } - - /* - * Power On. - */ - mask = PCMCIA_VS1 (_slot_) | PCMCIA_VS2 (_slot_); - reg = pcmp->pcmc_pipr; - debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg, - (reg & PCMCIA_VS1 (slot)) ? "n" : "ff", - (reg & PCMCIA_VS2 (slot)) ? "n" : "ff"); - - if ((reg & mask) == mask) { - pcmcia_voltage_set (_slot_, 50, 0); - printf (" 5.0V card found: "); - } else { - pcmcia_voltage_set (_slot_, 33, 0); - printf (" 3.3V card found: "); - } - - debug ("Enable PCMCIA buffers and stop RESET\n"); - reg = PCMCIA_PGCRX (_slot_); - reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ - reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ - PCMCIA_PGCRX (_slot_) = reg; - - udelay (250000); /* some cards need >150 ms to come up :-( */ - - debug ("# hardware_enable done\n"); - - return (0); - } - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_hardware_disable (int slot) -{ - return 0; /* No hardware to disable */ -} -#endif - -#endif /* CONFIG_PCMCIA */ diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/mbx8xx/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug deleted file mode 100644 index 7cfed1f1d5..0000000000 --- a/board/mbx8xx/u-boot.lds.debug +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mbx8xx/vpd.c b/board/mbx8xx/vpd.c deleted file mode 100644 index 1ba754ee23..0000000000 --- a/board/mbx8xx/vpd.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * Code in faintly related to linux/arch/powerpc/8xx_io: - * MPC8xx CPM I2C interface. Copyright (c) 1999 Dan Malek (dmalek@jlc.net). - * - * This file implements functions to read the MBX's Vital Product Data - * (VPD). I can't use the more general i2c code in mpc8xx/... since I need - * the VPD at a time where there is no RAM available yet. Hence the VPD is - * read into a special area in the DPRAM (see config_MBX.h::CFG_DPRAMVPD). - * - * ----------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#ifdef CONFIG_8xx -#include <commproc.h> -#endif -#include "vpd.h" - -/* Location of receive/transmit buffer descriptors - * Allocate one transmit bd and one receive bd. - * IIC_BD_FREE points to free bd space which we'll use as tx buffer. - */ -#define IIC_BD_TX1 (BD_IIC_START + 0*sizeof(cbd_t)) -#define IIC_BD_TX2 (BD_IIC_START + 1*sizeof(cbd_t)) -#define IIC_BD_RX (BD_IIC_START + 2*sizeof(cbd_t)) -#define IIC_BD_FREE (BD_IIC_START + 3*sizeof(cbd_t)) - -/* FIXME -- replace 0x2000 with offsetof */ -#define VPD_P ((vpd_t *)(CONFIG_SYS_IMMR + 0x2000 + CONFIG_SYS_DPRAMVPD)) - -/* transmit/receive buffers */ -#define IIC_RX_LENGTH 128 - -#define WITH_MICROCODE_PATCH - -vpd_packet_t * vpd_find_packet(u_char ident) -{ - vpd_packet_t *packet; - vpd_t *vpd = VPD_P; - - packet = (vpd_packet_t *)&vpd->packets; - while ((packet->identifier != ident) && packet->identifier != 0xFF) - { - packet = (vpd_packet_t *)((char *)packet + packet->size + 2); - } - return packet; -} - -void vpd_init(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); - volatile iic_t *iip; -#ifdef WITH_MICROCODE_PATCH - ulong reloc = 0; -#endif - - iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; - - /* - * kludge: when running from flash, no microcode patch can be - * installed. However, the DPMEM usually contains non-zero - * garbage at the relocatable patch base location, so lets clear - * it now. This way the rest of the code can support the microcode - * patch dynamically. - */ - if ((ulong)vpd_init & 0xff000000) - iip->iic_rpbase = 0; - -#ifdef WITH_MICROCODE_PATCH - /* Check for and use a microcode relocation patch. */ - if ((reloc = iip->iic_rpbase)) - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#endif - /* Initialize Port B IIC pins */ - cp->cp_pbpar |= 0x00000030; - cp->cp_pbdir |= 0x00000030; - cp->cp_pbodr |= 0x00000030; - - i2c->i2c_i2mod = 0x04; /* filter clock */ - i2c->i2c_i2add = 0x34; /* select an arbitrary (unique) address */ - i2c->i2c_i2brg = 0x07; /* make clock run maximum slow */ - i2c->i2c_i2cmr = 0x00; /* disable interrupts */ - i2c->i2c_i2cer = 0x1f; /* clear events */ - i2c->i2c_i2com = 0x01; /* configure i2c to work as master */ - - if (vpd_read(0xa4, (uchar*)VPD_P, VPD_EEPROM_SIZE, 0) != VPD_EEPROM_SIZE) - { - hang(); - } -} - - -/* Read from I2C. - * This is a two step process. First, we send the "dummy" write - * to set the device offset for the read. Second, we perform - * the read operation. - */ -int vpd_read(uint iic_device, uchar *buf, int count, int offset) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); - volatile iic_t *iip; - volatile cbd_t *tbdf1, *tbdf2, *rbdf; - uchar *tb; - uchar event; -#ifdef WITH_MICROCODE_PATCH - ulong reloc = 0; -#endif - - iip = (iic_t *)&cp->cp_dparam[PROFF_IIC]; -#ifdef WITH_MICROCODE_PATCH - /* Check for and use a microcode relocation patch. */ - if ((reloc = iip->iic_rpbase)) - iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase]; -#endif - tbdf1 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX1]; - tbdf2 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX2]; - rbdf = (cbd_t *)&cp->cp_dpmem[IIC_BD_RX]; - - /* Send a "dummy write" operation. This is a write request with - * only the offset sent, followed by another start condition. - * This will ensure we start reading from the first location - * of the EEPROM. - */ - tb = (uchar*)&cp->cp_dpmem[IIC_BD_FREE]; - tb[0] = iic_device & 0xfe; /* device address */ - tb[1] = offset; /* offset */ - tbdf1->cbd_bufaddr = (uint)tb; - tbdf1->cbd_datlen = 2; - tbdf1->cbd_sc = 0x8400; - - tb += 2; - tb[0] = iic_device | 1; /* device address */ - tbdf2->cbd_bufaddr = (uint)tb; - tbdf2->cbd_datlen = count+1; - tbdf2->cbd_sc = 0xbc00; - - rbdf->cbd_bufaddr = (uint)buf; - rbdf->cbd_datlen = 0; - rbdf->cbd_sc = 0xb000; - - iip->iic_tbase = IIC_BD_TX1; - iip->iic_tbptr = IIC_BD_TX1; - iip->iic_rbase = IIC_BD_RX; - iip->iic_rbptr = IIC_BD_RX; - iip->iic_rfcr = 0x15; - iip->iic_tfcr = 0x15; - iip->iic_mrblr = count; - iip->iic_rstate = 0; - iip->iic_tstate = 0; - - i2c->i2c_i2cer = 0x1f; /* clear event mask */ - i2c->i2c_i2mod |= 1; /* enable iic operation */ - i2c->i2c_i2com |= 0x80; /* start master */ - - /* wait for IIC transfer */ - do { - __asm__ volatile ("eieio"); - event = i2c->i2c_i2cer; - } while (event == 0); - - if ((event & 0x10) || (event & 0x04)) { - count = -1; - goto bailout; - } - -bailout: - i2c->i2c_i2mod &= ~1; /* turn off iic operation */ - i2c->i2c_i2cer = 0x1f; /* clear event mask */ - - return count; -} diff --git a/board/mbx8xx/vpd.h b/board/mbx8xx/vpd.h deleted file mode 100644 index 1d9eb7fe20..0000000000 --- a/board/mbx8xx/vpd.h +++ /dev/null @@ -1,119 +0,0 @@ -#ifndef __vpd_h -#define __vpd_h - -/* - * Module name: %M% - * Description: - * Vital Product Data (VPD) Header Module - * SCCS identification: %I% - * Branch: %B% - * Sequence: %S% - * Date newest applied delta was created (MM/DD/YY): %G% - * Time newest applied delta was created (HH:MM:SS): %U% - * SCCS file name %F% - * Fully qualified SCCS file name: - * %P% - * Copyright: - * (C) COPYRIGHT MOTOROLA, INC. 1996 - * ALL RIGHTS RESERVED - * Notes: - * History: - * Date Who - * - * 10/24/96 Rob Baxter - * Initial release. - * - */ - -#define VPD_EEPROM_SIZE 256 /* EEPROM size in bytes */ - -/* - * packet tuple identifiers - * - * 0x0D - 0xBF reserved - * 0xC0 - 0xFE user defined - */ -#define VPD_PID_GI 0x00 /* guaranteed illegal */ -#define VPD_PID_PID 0x01 /* product identifier (ASCII) */ -#define VPD_PID_FAN 0x02 /* factory assembly-number (ASCII) */ -#define VPD_PID_SN 0x03 /* serial-number (ASCII) */ -#define VPD_PID_PCO 0x04 /* product configuration options(binary) */ -#define VPD_PID_ICS 0x05 /* internal clock speed in HZ (integer) */ -#define VPD_PID_ECS 0x06 /* external clock speed in HZ (integer) */ -#define VPD_PID_RCS 0x07 /* reference clock speed in HZ(integer) */ -#define VPD_PID_EA 0x08 /* ethernet address (binary) */ -#define VPD_PID_MT 0x09 /* microprocessor type (ASCII) */ -#define VPD_PID_CRC 0x0A /* EEPROM CRC (integer) */ -#define VPD_PID_FMC 0x0B /* FLASH memory configuration (binary) */ -#define VPD_PID_VLSI 0x0C /* VLSI revisions/versions (binary) */ -#define VPD_PID_TERM 0xFF /* termination */ - -/* - * VPD structure (format) - */ -#define VPD_EYE_SIZE 8 /* eyecatcher size */ -typedef struct vpd_header -{ - uchar eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "MOTOROLA" */ - ushort size; /* size of EEPROM */ -} vpd_header_t; - -#define VPD_DATA_SIZE (VPD_EEPROM_SIZE-sizeof(vpd_header_t)) -typedef struct vpd -{ - vpd_header_t header; /* header */ - uchar packets[VPD_DATA_SIZE]; /* data */ -} vpd_t; - -/* - * packet tuple structure (format) - */ -typedef struct vpd_packet -{ - uchar identifier; /* identifier (PIDs above) */ - uchar size; /* size of the following data area */ - uchar data[1]; /* data (size is dependent upon PID) */ -} vpd_packet_t; - -/* - * MBX product configuration options bit definitions - * - * Notes: - * 1. The bit numbering is reversed in perspective with the C compiler. - */ -#define PCO_BBRAM (1<<0) /* battery-backed RAM (BBRAM) and socket */ -#define PCO_BOOTROM (1<<1) /* boot ROM and socket (i.e., socketed FLASH) */ -#define PCO_KAPWR (1<<2) /* keep alive power source (lithium battey) and control circuit */ -#define PCO_ENET_TP (1<<3) /* ethernet twisted pair (TP) connector (RJ45) */ -#define PCO_ENET_AUI (1<<4) /* ethernet attachment unit interface (AUI) header */ -#define PCO_PCMCIA (1<<5) /* PCMCIA socket */ -#define PCO_DIMM (1<<6) /* DIMM module socket */ -#define PCO_DTT (1<<7) /* digital thermometer and thermostat (DTT) device */ -#define PCO_LCD (1<<8) /* liquid crystal display (LCD) device */ -#define PCO_PCI (1<<9) /* PCI-Bus bridge device (QSpan) and ISA-Bus bridge device (Winbond) */ -#define PCO_PCIO (1<<10) /* PC I/O (COM1, COM2, FDC, LPT, Keyboard/Mouse) */ -#define PCO_EIDE (1<<11) /* enhanced IDE (EIDE) header */ -#define PCO_FDC (1<<12) /* floppy disk controller (FDC) header */ -#define PCO_LPT_8XX (1<<13) /* parallel port header via MPC8xx */ -#define PCO_LPT_PCIO (1<<14) /* parallel port header via PC I/O */ - -/* - * FLASH memory configuration packet data - */ -typedef struct vpd_fmc -{ - ushort mid; /* manufacturer's idenitfier */ - ushort did; /* manufacturer's device idenitfier */ - uchar ddw; /* device data width (e.g., 8-bits, 16-bits) */ - uchar nod; /* number of devices present */ - uchar noc; /* number of columns */ - uchar cw; /* column width in bits */ - uchar wedw; /* write/erase data width */ -} vpd_fmc_t; - -/* function prototypes */ -extern void vpd_init(void); -extern int vpd_read(uint iic_device, uchar *buf, int count, int offset); -extern vpd_packet_t *vpd_find_packet(u_char ident); - -#endif /* __vpd_h */ diff --git a/board/mousse/README b/board/mousse/README deleted file mode 100644 index d5dda7a8e7..0000000000 --- a/board/mousse/README +++ /dev/null @@ -1,346 +0,0 @@ - -U-Boot for MOUSSE/MPC8240 (KAHLUA) ----------------------------------- -James Dougherty (jfd@broadcom.com), 09/10/01 - -The Broadcom/Vooha Mousse board is a 3U Compact PCI system board -which uses the MPC8240, a 64MB SDRAM SIMM, and has onboard -DEC 21143, NS16550 UART, an SGS M48T59Y TOD, and 4MB FLASH. -See also: http://www.vooha.com/ - -* NVRAM setenv/printenv/savenv supported. -* Date Command -* Serial Console support -* Network support -* FLASH of kernel images is supported. -* FLASH of U-Boot to onboard and PLCC boot region. -* Kernel command line options from NVRAM is supported. -* IP PNP options supported. - -U-Boot Loading... - - -U-Boot 1.0.5 (Sep 10 2001 - 00:22:25) - -CPU: MPC8240 Revision 1.1 at 198 MHz: 16 kB I-Cache 16 kB D-Cache -Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B) -Built: Sep 10 2001 at 01:01:50 -MPLD: Revision 127 -Local Bus: 33 MHz -RTC: M48T589 TOD/NVRAM (8176) bytes - Current date/time: 9/10/2001 0:18:52 -DRAM: 64 MB -FLASH: 1.960 MB -PCI: scanning bus0 ... - bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE - 00 00 00 1057 0003 060000 11 00000008 00000000 01 00 - 00 0d 00 1011 0019 020000 41 80000001 80000000 01 01 - 00 0e 00 105a 4d38 018000 01 a0000001 a0001001 01 03 -In: serial -Out: serial -Err: serial - -Hit any key to stop autoboot: 0 -=> - -I. Root FileSystem/IP Configuration - -bootcmd=tftp 100000 vmlinux.img;bootm -bootdelay=3 -baudrate=9600 -ipaddr=<IP ADDRESS> -netmask=<NETMASK> -hostname=<NAME> -serverip=<NFS SERVER IP ADDRESS> -ethaddr=00:00:10:20:30:44 -nfsroot=<NFS SERVER IP ADDRESS>:/boot/root-fs -gateway=<IP ADDRESS> -root=/dev/nfs -stdin=serial -stdout=serial -stderr=serial - -NVRAM environment variables. - -use the command: - -setenv <attribute> <value> - -type "saveenv" to write to NVRAM. - - -II. To boot from a hard drive: - -setenv root /dev/hda1 - - -III. IP options which configure the network: - -ipaddr=<IP ADDRESS OF MACHINE> -netmask=<NETMASK> -hostname=mousse -ethaddr=00:00:10:20:30:44 -gateway=<IP ADDRESS OF GATEWAY/ROUTER> - - -IV. IP Options which configure NFS Root/Boot Support - -root=/dev/nfs -serverip=<NFS SERVER IP ADDRESS> -nfsroot=<NFS SERVER IP ADDRESS>:/boot/root-fs - -V. U-Boot Image Support - -The U-Boot boot loader assumes that after you build -your kernel (vmlinux), you will create a U-Boot image -using the following commands or script: - -#!/bin/csh -/bin/touch vmlinux.img -/bin/rm vmlinux.img -set path=($TOOLBASE/bin $path) -set path=($U_BOOT/tools $path) -powerpc-linux-objcopy -S -O binary vmlinux vmlinux.bin -gzip -vf vmlinux.bin -mkimage -A ppc -O linux -T kernel -C gzip -a 0 -e 0 -n vmlinux.bin.gz -d vmlinux.bin.gz vmlinux.img -ls -l vmlinux.img - - -VI. ONBOARD FLASH Support - -FLASH support is provided for the onboard FLASH chip Bootrom area. -U-Boot is loaded into either the ROM boot region of the FLASH chip, -after first being boot-strapped from a pre-progammed AMD29F040 PLCC -bootrom. The PLCC needs to be programmed with a ROM burner using -AMD 29F040 ROM parts and the u-boot.bin or u-boot.hex (S-Record) -images. - -The PLCC overlays this same region of flash as the onboard FLASH, -the jumper J100 is a chip-select for which flash chip you want to -progam. When jumper J100 is connected to pins 2-3, you boot from -PLCC FLASH. - -To bringup a system, simply flash a flash an AMD29F040 PLCC -bootrom, and put this in the PLCC socket. Move jumper J100 to -pins 2-3 and boot from the PLCC. - - -Now, while the system is running, move Jumper J100 to -pins 1-2 and follow the procedure below to FLASH a bootrom -(u-boot.bin) image into the onboard bootrom region (AMD29LV160DB): - -tftp 100000 u-boot.bin -protect off FFF00000 FFF7FFFF -erase FFF00000 FFF7FFFF -cp.b 100000 FFF00000 \${filesize}\ - - -Here is an example: - -=>tftp 100000 u-boot.bin -eth_halt -eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) -DEC Ethernet iobase=0x80000000 -ARP broadcast 1 -Filename 'u-boot.bin'. -Load address: 0x100000 -Loading: ######################### -done -Bytes transferred = 123220 (1e154 hex) -eth_halt -=>protect off FFF00000 FFF7FFFF -Un-Protected 8 sectors -=>erase FFF00000 FFF7FFFF -Erase Flash from 0xfff00000 to 0xfff7ffff -Erase FLASH[PLCC_BOOT] -8 sectors:........ done -Erased 8 sectors -=>cp.b 100000 FFF00000 1e154 -Copy to Flash... FLASH[PLCC_BOOT]:..done -=> - - -B. FLASH RAMDISK REGION - -FLASH support is provided for an Onboard 512K RAMDISK region. - -TThe following commands will FLASH a bootrom (u-boot.bin) image -into the onboard FLASH region (AMD29LV160DB 2MB FLASH): - -tftp 100000 u-boot.bin -protect off FFF80000 FFFFFFFF -erase FFF80000 FFFFFFFF -cp.b 100000 FFF80000 \${filesize}\ - - -C. FLASH KERNEL REGION (960KB) - -FLASH support is provided for the 960KB onboard FLASH1 segment. -This allows flashing of kernel images which U-Boot can load -and run (standalone) from the onboard FLASH chip. It also assumes - -The following commands will FLASH a kernel image to 0xffe10000 - -tftp 100000 vmlinux.img -protect off FFE10000 FFEFFFFF -erase FFE10000 FFEFFFFF -cp.b 100000 FFE10000 \${filesize}\ -reset - -Here is an example: - - -=>tftp 100000 vmlinux.img -eth_halt -eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) -DEC Ethernet iobase=0x80000000 -ARP broadcast 1 -TFTP from server 209.128.93.133; our IP address is 209.128.93.138 -Filename 'vmlinux.img'. -Load address: 0x100000 -Loading: ##################################################################################################################################################### -done -Bytes transferred = 760231 (b99a7 hex) -eth_halt -=>protect off FFE10000 FFEFFFFF -Un-Protected 15 sectors -=>erase FFE10000 FFEFFFFF -Erase Flash from 0xffe10000 to 0xffefffff -Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done -Erased 15 sectors -=>cp.b 100000 FFE10000 b99a7 -Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done -=> - - -When finished, use the command: - -bootm ffe10000 - -to start the kernel. - -Finally, to make this the default boot command, use -the following commands: - -setenv bootcmd bootm ffe10000 -savenv - -to make it automatically boot the kernel from FLASH. - - -To go back to development mode (NFS boot) - -setenv bootcmd tftp 100000 vmlinux.img\;bootm -savenv - - -=>tftp 100000 vmlinux.img -eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0) -DEC Ethernet iobase=0x80000000 -ARP broadcast 1 -Filename 'vmlinux.img'. -Load address: 0x100000 -Loading: #################################################################################################################################################### -done -Bytes transferred = 752717 (b7c4d hex) -eth_halt -=>protect off FFE10000 FFEFFFFF -Un-Protected 15 sectors -=>erase FFE10000 FFEFFFFF -Erase Flash from 0xffe10000 to 0xffefffff -Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done -Erased 15 sectors -=>cp.b 100000 FFE10000 b7c4d -Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done -=>bootm ffe10000 -## Booting image at ffe10000 ... - Image Name: vmlinux.bin.gz - Image Type: PowerPC Linux Kernel Image (gzip compressed) - Data Size: 752653 Bytes = 735 kB = 0 MB - Load Address: 00000000 - Entry Point: 00000000 - Verifying Checksum ... OK - Uncompressing Kernel Image ... OK -Total memory = 64MB; using 0kB for hash table (at 00000000) -Linux version 2.4.2_hhl20 (jfd@atlantis) (gcc version 2.95.2 19991024 (release)) #597 Wed Sep 5 23:23:23 PDT 2001 -cpu0: MPC8240/KAHLUA : MOUSSE Platform : 64MB RAM: MPLD Rev. 7f -Sandpoint port (C) 2000, 2001 MontaVista Software, Inc. (source@mvista.com) -IP PNP: 802.3 Ethernet Address=<0:0:10:20:30:44> -NOTICE: mounting root file system via NFS -On node 0 totalpages: 16384 -zone(0): 16384 pages. -zone(1): 0 pages. -zone(2): 0 pages. -time_init: decrementer frequency = 16.665914 MHz -time_init: MPC8240 PCI Bus frequency = 33.331828 MHz -Calibrating delay loop... 133.12 BogoMIPS -Memory: 62436k available (1336k kernel code, 500k data, 88k init, 0k highmem) -Dentry-cache hash table entries: 8192 (order: 4, 65536 bytes) -Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes) -Page-cache hash table entries: 16384 (order: 4, 65536 bytes) -Inode-cache hash table entries: 4096 (order: 3, 32768 bytes) -POSIX conformance testing by UNIFIX -PCI: Probing PCI hardware -Linux NET4.0 for Linux 2.4 -Based upon Swansea University Computer Society NET3.039 -Initializing RT netlink socket -Starting kswapd v1.8 -pty: 256 Unix98 ptys configured -block: queued sectors max/low 41394kB/13798kB, 128 slots per queue -Uniform Multi-Platform E-IDE driver Revision: 6.31 -ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx -PDC20262: IDE controller on PCI bus 00 dev 70 -PDC20262: chipset revision 1 -PDC20262: not 100% native mode: will probe irqs later -PDC20262: ROM enabled at 0x000d0000 -PDC20262: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode. -PDC20262: FORCING BURST BIT 0x00 -> 0x01 ACTIVE -PDC20262: irq=3 dev->irq=3 - ide0: BM-DMA at 0xbfff00-0xbfff07, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0xbfff08-0xbfff0f, BIOS settings: hdc:pio, hdd:pio -hda: WDC WD300AB-00BVA0, ATA DISK drive -hdc: SONY CD-RW CRX160E, ATAPI CD/DVD-ROM drive -ide0 at 0xbfff78-0xbfff7f,0xbfff76 on irq 3 -ide1 at 0xbfff68-0xbfff6f,0xbfff66 on irq 3 -hda: 58633344 sectors (30020 MB) w/2048KiB Cache, CHS=58168/16/63, UDMA(66) -hdc: ATAPI 32X CD-ROM CD-R/RW drive, 4096kB Cache -Uniform CD-ROM driver Revision: 3.12 -Partition check: - /dev/ide/host0/bus0/target0/lun0: p1 p2 -hd: unable to get major 3 for hard disk -udf: registering filesystem -loop: loaded (max 8 devices) -Serial driver version 5.02 (2000-08-09) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled -ttyS00 at 0xffe08080 (irq = 4) is a ST16650 -Linux Tulip driver version 0.9.13a (January 20, 2001) -eth0: Digital DS21143 Tulip rev 65 at 0xbfff80, EEPROM not present, 00:00:10:20:30:44, IRQ 1. -eth0: MII transceiver #0 config 3000 status 7829 advertising 01e1. -NET4: Linux TCP/IP 1.0 for NET4.0 -IP Protocols: ICMP, UDP, TCP -IP: routing cache hash table of 512 buckets, 4Kbytes -TCP: Hash tables configured (established 4096 bind 4096) -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. -devfs: v0.102 (20000622) Richard Gooch (rgooch@atnf.csiro.au) -devfs: boot_options: 0x0 -VFS: Mounted root (nfs filesystem). -Mounted devfs on /dev -Freeing unused kernel memory: 88k init 4k openfirmware -eth0: Setting full-duplex based on MII#0 link partner capability of 45e1. -INIT: version 2.78 booting -INIT: Entering runlevel: 2 - - -Welcome to Linux/PPC -MPC8240/MOUSSE - - -mousse login: root -Password: -PAM_unix[13]: (login) session opened for user root by LOGIN(uid=0) -Last login: Thu Sep 6 00:16:51 2001 on console - - -Welcome to Linux/PPC -MPC8240/MOUSSE - - -mousse# diff --git a/board/mousse/flash.c b/board/mousse/flash.c deleted file mode 100644 index acedcb1aa1..0000000000 --- a/board/mousse/flash.c +++ /dev/null @@ -1,917 +0,0 @@ -/* - * MOUSSE/MPC8240 Board definitions. - * Flash Routines for MOUSSE onboard AMD29LV106DB devices - * - * (C) Copyright 2000 - * Marius Groeger <mgroeger@sysgo.de> - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <malloc.h> -#include "mousse.h" -#include "flash.h" - -int flashLibDebug = 0; -int flashLibInited = 0; - -#define OK 0 -#define ERROR -1 -#define STATUS int -#define PRINTF if (flashLibDebug) printf -#if 0 -#define PRIVATE static -#else -#define PRIVATE -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define SLEEP_DELAY 166 -#define FLASH_SECTOR_SIZE (64*1024) -/*********************************************************************** - * - * Virtual Flash Devices on Mousse board - * - * These must be kept in sync with the definitions in flashLib.h. - * - ***********************************************************************/ - -PRIVATE flash_dev_t flashDev[] = { - /* Bank 0 sector SA0 (16 kB) */ - { "SA0",FLASH0_BANK, FLASH0_SEG0_START, 1, 14, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sector SA1 (8 kB) */ - { "SA1", FLASH0_BANK, FLASH0_SEG0_START + 0x4000, 1, 13, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sector SA2 (8 kB) */ - { "SA2", FLASH0_BANK, FLASH0_SEG0_START + 0x6000, 1, 13, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sector SA3 is occluded by Mousse I/O devices */ - /* Bank 0 sectors SA4-SA18, after Mousse devices up to PLCC (960 kB) */ - { "KERNEL", FLASH0_BANK, FLASH0_SEG1_START, 15, 16, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sectors SA19-SA26, jumper can occlude this by PLCC (512 kB) */ - /* This is where the Kahlua boot vector and boot ROM code resides. */ - { "BOOT",FLASH0_BANK, FLASH0_SEG2_START, 8, 16, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, - /* Bank 0 sectors SA27-SA34 (512 kB) */ - { "RAMDISK",FLASH0_BANK, FLASH0_SEG3_START, 8, 16, - FLASH0_VENDOR_ID, FLASH0_DEVICE_ID - }, -}; - -int flashDevCount = (sizeof (flashDev) / sizeof (flashDev[0])); - -#define DEV(no) (&flashDev[no]) -#define DEV_NO(dev) ((dev) - flashDev) - -/*********************************************************************** - * - * Private Flash Routines - * - ***********************************************************************/ - -/* - * The convention is: - * - * "addr" is always the PROM raw address, which is the address of an - * 8-bit quantity for flash 0 and 16-bit quantity for flash 1. - * - * "pos" is always a logical byte position from the PROM beginning. - */ - -#define FLASH0_ADDR(dev, addr) \ - ((unsigned char *) ((dev)->base + (addr))) - -#define FLASH0_WRITE(dev, addr, value) \ - (*FLASH0_ADDR(dev, addr) = (value)) - -#define FLASH0_READ(dev, addr) \ - (*FLASH0_ADDR(dev, addr)) - -PRIVATE int flashCheck (flash_dev_t * dev) -{ - if (!flashLibInited) { - printf ("flashCheck: flashLib not initialized\n"); - return ERROR; - } - - if (dev < &flashDev[0] || dev >= &flashDev[flashDevCount]) { - printf ("flashCheck: Bad dev parameter\n"); - return ERROR; - } - - if (!dev->found) { - printf ("flashCheck: Device %d not available\n", DEV_NO (dev)); - return ERROR; - } - - return OK; -} - -PRIVATE void flashReset (flash_dev_t * dev) -{ - PRINTF ("flashReset: dev=%d\n", DEV_NO (dev)); - - if (dev->bank == FLASH0_BANK) { - FLASH0_WRITE (dev, 0x555, 0xaa); - FLASH0_WRITE (dev, 0xaaa, 0x55); - FLASH0_WRITE (dev, 0x555, 0xf0); - } - - udelay (SLEEP_DELAY); - - PRINTF ("flashReset: done\n"); -} - -PRIVATE int flashProbe (flash_dev_t * dev) -{ - int rv, deviceID, vendorID; - - PRINTF ("flashProbe: dev=%d\n", DEV_NO (dev)); - - if (dev->bank != FLASH0_BANK) { - rv = ERROR; - goto DONE; - } - - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, 0xaaa, 0x90); - - udelay (SLEEP_DELAY); - - vendorID = FLASH0_READ (dev, 0); - deviceID = FLASH0_READ (dev, 2); - - FLASH0_WRITE (dev, 0, 0xf0); - - PRINTF ("flashProbe: vendor=0x%x device=0x%x\n", vendorID, deviceID); - - if (vendorID == dev->vendorID && deviceID == dev->deviceID) - rv = OK; - else - rv = ERROR; - - DONE: - PRINTF ("flashProbe: rv=%d\n", rv); - - return rv; -} - -PRIVATE int flashWait (flash_dev_t * dev, int addr, int expect, int erase) -{ - int rv = ERROR; - int i, data; - int polls; - -#if 0 - PRINTF ("flashWait: dev=%d addr=0x%x expect=0x%x erase=%d\n", - DEV_NO (dev), addr, expect, erase); -#endif - - if (dev->bank != FLASH0_BANK) { - rv = ERROR; - goto done; - } - - if (erase) - polls = FLASH_ERASE_SECTOR_TIMEOUT; /* Ticks */ - else - polls = FLASH_PROGRAM_POLLS; /* Loops */ - - for (i = 0; i < polls; i++) { - if (erase) - udelay (SLEEP_DELAY); - - data = FLASH0_READ (dev, addr); - - if (((data ^ expect) & 0x80) == 0) { - rv = OK; - goto done; - } - - if (data & 0x20) { - /* - * If the 0x20 bit has come on, it could actually be because - * the operation succeeded, so check the done bit again. - */ - - data = FLASH0_READ (dev, addr); - - if (((data ^ expect) & 0x80) == 0) { - rv = OK; - goto done; - } - - printf ("flashWait: Program error (dev: %d, addr: 0x%x)\n", - DEV_NO (dev), addr); - - flashReset (dev); - rv = ERROR; - goto done; - } - } - - printf ("flashWait: Timeout %s (dev: %d, addr: 0x%x)\n", - erase ? "erasing sector" : "programming byte", - DEV_NO (dev), addr); - - done: - -#if 0 - PRINTF ("flashWait: rv=%d\n", rv); -#endif - - return rv; -} - -/*********************************************************************** - * - * Public Flash Routines - * - ***********************************************************************/ - -STATUS flashLibInit (void) -{ - int i; - - PRINTF ("flashLibInit: devices=%d\n", flashDevCount); - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - /* - * For bank 1, probe both without and with byte swappage, - * so that this module works on both old and new Mousse boards. - */ - - flashReset (dev); - - if (flashProbe (dev) != ERROR) - dev->found = 1; - - flashReset (dev); - - if (flashProbe (dev) != ERROR) - dev->found = 1; - - dev->swap = 0; - - if (dev->found) { - PRINTF ("\n FLASH %s[%d]: iobase=0x%x - %d sectors %d KB", - flashDev[i].name, i, flashDev[i].base, - flashDev[i].sectors, - (flashDev[i].sectors * FLASH_SECTOR_SIZE) / 1024); - - } - } - - flashLibInited = 1; - - PRINTF ("flashLibInit: done\n"); - - return OK; -} - -STATUS flashEraseSector (flash_dev_t * dev, int sector) -{ - int pos, addr; - - PRINTF ("flashErasesector: dev=%d sector=%d\n", DEV_NO (dev), sector); - - if (flashCheck (dev) == ERROR) - return ERROR; - - if (sector < 0 || sector >= dev->sectors) { - printf ("flashEraseSector: Sector out of range (dev: %d, sector: %d)\n", DEV_NO (dev), sector); - return ERROR; - } - - pos = FLASH_SECTOR_POS (dev, sector); - - if (dev->bank != FLASH0_BANK) { - return ERROR; - } - - addr = pos; - - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, 0xaaa, 0x80); - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, addr, 0x30); - - return flashWait (dev, addr, 0xff, 1); -} - -/* - * Note: it takes about as long to flash all sectors together with Chip - * Erase as it does to flash them one at a time (about 30 seconds for 2 - * MB). Also since we want to be able to treat subsets of sectors as if - * they were complete devices, we don't use Chip Erase. - */ - -STATUS flashErase (flash_dev_t * dev) -{ - int sector; - - PRINTF ("flashErase: dev=%d sectors=%d\n", DEV_NO (dev), dev->sectors); - - if (flashCheck (dev) == ERROR) - return ERROR; - - for (sector = 0; sector < dev->sectors; sector++) { - if (flashEraseSector (dev, sector) == ERROR) - return ERROR; - } - return OK; -} - -/* - * Read and write bytes - */ - -STATUS flashRead (flash_dev_t * dev, int pos, char *buf, int len) -{ - int addr, words; - - PRINTF ("flashRead: dev=%d pos=0x%x buf=0x%x len=0x%x\n", - DEV_NO (dev), pos, (int) buf, len); - - if (flashCheck (dev) == ERROR) - return ERROR; - - if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { - printf ("flashRead: Position out of range " - "(dev: %d, pos: 0x%x, len: 0x%x)\n", - DEV_NO (dev), pos, len); - return ERROR; - } - - if (len == 0) - return OK; - - if (dev->bank == FLASH0_BANK) { - addr = pos; - words = len; - - PRINTF ("flashRead: memcpy(0x%x, 0x%x, 0x%x)\n", - (int) buf, (int) FLASH0_ADDR (dev, pos), len); - - memcpy (buf, FLASH0_ADDR (dev, addr), words); - - } - PRINTF ("flashRead: rv=OK\n"); - - return OK; -} - -STATUS flashWrite (flash_dev_t * dev, int pos, char *buf, int len) -{ - int addr, words; - - PRINTF ("flashWrite: dev=%d pos=0x%x buf=0x%x len=0x%x\n", - DEV_NO (dev), pos, (int) buf, len); - - if (flashCheck (dev) == ERROR) - return ERROR; - - if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { - printf ("flashWrite: Position out of range " - "(dev: %d, pos: 0x%x, len: 0x%x)\n", - DEV_NO (dev), pos, len); - return ERROR; - } - - if (len == 0) - return OK; - - if (dev->bank == FLASH0_BANK) { - unsigned char tmp; - - addr = pos; - words = len; - - while (words--) { - tmp = *buf; - if (~FLASH0_READ (dev, addr) & tmp) { - printf ("flashWrite: Attempt to program 0 to 1 " - "(dev: %d, addr: 0x%x, data: 0x%x)\n", - DEV_NO (dev), addr, tmp); - return ERROR; - } - FLASH0_WRITE (dev, 0xaaa, 0xaa); - FLASH0_WRITE (dev, 0x555, 0x55); - FLASH0_WRITE (dev, 0xaaa, 0xa0); - FLASH0_WRITE (dev, addr, tmp); - if (flashWait (dev, addr, tmp, 0) < 0) - return ERROR; - buf++; - addr++; - } - } - - PRINTF ("flashWrite: rv=OK\n"); - - return OK; -} - -/* - * flashWritable returns true if a range contains all F's. - */ - -STATUS flashWritable (flash_dev_t * dev, int pos, int len) -{ - int addr, words; - int rv = ERROR; - - PRINTF ("flashWritable: dev=%d pos=0x%x len=0x%x\n", - DEV_NO (dev), pos, len); - - if (flashCheck (dev) == ERROR) - goto done; - - if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) { - printf ("flashWritable: Position out of range " - "(dev: %d, pos: 0x%x, len: 0x%x)\n", - DEV_NO (dev), pos, len); - goto done; - } - - if (len == 0) { - rv = 1; - goto done; - } - - if (dev->bank == FLASH0_BANK) { - addr = pos; - words = len; - - while (words--) { - if (FLASH0_READ (dev, addr) != 0xff) { - rv = 0; - goto done; - } - addr++; - } - } - - rv = 1; - - done: - PRINTF ("flashWrite: rv=%d\n", rv); - return rv; -} - - -/* - * NOTE: the below code cannot run from FLASH!!! - */ -/*********************************************************************** - * - * Flash Diagnostics - * - ***********************************************************************/ - -STATUS flashDiag (flash_dev_t * dev) -{ - unsigned int *buf = 0; - int i, len, sector; - int rv = ERROR; - - if (flashCheck (dev) == ERROR) - return ERROR; - - printf ("flashDiag: Testing device %d, " - "base: 0x%x, %d sectors @ %d kB = %d kB\n", - DEV_NO (dev), dev->base, - dev->sectors, - 1 << (dev->lgSectorSize - 10), - dev->sectors << (dev->lgSectorSize - 10)); - - len = 1 << dev->lgSectorSize; - - printf ("flashDiag: Erasing\n"); - - if (flashErase (dev) == ERROR) { - printf ("flashDiag: Erase failed\n"); - goto done; - } - printf ("%d bytes requested ...\n", len); - buf = malloc (len); - printf ("allocated %d bytes ...\n", len); - if (buf == 0) { - printf ("flashDiag: Out of memory\n"); - goto done; - } - - /* - * Write unique counting pattern to each sector - */ - - for (sector = 0; sector < dev->sectors; sector++) { - printf ("flashDiag: Write sector %d\n", sector); - - for (i = 0; i < len / 4; i++) - buf[i] = sector << 24 | i; - - if (flashWrite (dev, - sector << dev->lgSectorSize, - (char *) buf, len) == ERROR) { - printf ("flashDiag: Write failed (dev: %d, sector: %d)\n", - DEV_NO (dev), sector); - goto done; - } - } - - /* - * Verify - */ - - for (sector = 0; sector < dev->sectors; sector++) { - printf ("flashDiag: Verify sector %d\n", sector); - - if (flashRead (dev, - sector << dev->lgSectorSize, - (char *) buf, len) == ERROR) { - printf ("flashDiag: Read failed (dev: %d, sector: %d)\n", - DEV_NO (dev), sector); - goto done; - } - - for (i = 0; i < len / 4; i++) { - if (buf[i] != (sector << 24 | i)) { - printf ("flashDiag: Verify error " - "(dev: %d, sector: %d, offset: 0x%x)\n", - DEV_NO (dev), sector, i); - printf ("flashDiag: Expected 0x%08x, got 0x%08x\n", - sector << 24 | i, buf[i]); - - goto done; - } - } - } - - printf ("flashDiag: Erasing\n"); - - if (flashErase (dev) == ERROR) { - printf ("flashDiag: Final erase failed\n"); - goto done; - } - - rv = OK; - - done: - if (buf) - free (buf); - - if (rv == OK) - printf ("flashDiag: Device %d passed\n", DEV_NO (dev)); - else - printf ("flashDiag: Device %d failed\n", DEV_NO (dev)); - - return rv; -} - -STATUS flashDiagAll (void) -{ - int i; - int rv = OK; - - PRINTF ("flashDiagAll: devices=%d\n", flashDevCount); - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - if (dev->found && flashDiag (dev) == ERROR) - rv = ERROR; - } - - if (rv == OK) - printf ("flashDiagAll: Passed\n"); - else - printf ("flashDiagAll: Failed because of earlier errors\n"); - - return OK; -} - - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - flash_dev_t *dev = NULL; - - flashLibInit (); - - /* - * Provide info for FLASH (up to 960K) of Kernel Image data. - */ - dev = FLASH_DEV_BANK0_LOW; - flash_info[FLASH_BANK_KERNEL].flash_id = - (dev->vendorID << 16) | dev->deviceID; - flash_info[FLASH_BANK_KERNEL].sector_count = dev->sectors; - flash_info[FLASH_BANK_KERNEL].size = - flash_info[FLASH_BANK_KERNEL].sector_count * FLASH_SECTOR_SIZE; - flash_info[FLASH_BANK_KERNEL].start[FIRST_SECTOR] = dev->base; - size += flash_info[FLASH_BANK_KERNEL].size; - - /* - * Provide info for 512K PLCC FLASH ROM (U-Boot) - */ - dev = FLASH_DEV_BANK0_BOOT; - flash_info[FLASH_BANK_BOOT].flash_id = - (dev->vendorID << 16) | dev->deviceID; - flash_info[FLASH_BANK_BOOT].sector_count = dev->sectors; - flash_info[FLASH_BANK_BOOT].size = - flash_info[FLASH_BANK_BOOT].sector_count * FLASH_SECTOR_SIZE; - flash_info[FLASH_BANK_BOOT].start[FIRST_SECTOR] = dev->base; - size += flash_info[FLASH_BANK_BOOT].size; - - - /* - * Provide info for 512K FLASH0 segment (U-Boot) - */ - dev = FLASH_DEV_BANK0_HIGH; - flash_info[FLASH_BANK_AUX].flash_id = - (dev->vendorID << 16) | dev->deviceID; - flash_info[FLASH_BANK_AUX].sector_count = dev->sectors; - flash_info[FLASH_BANK_AUX].size = - flash_info[FLASH_BANK_AUX].sector_count * FLASH_SECTOR_SIZE; - flash_info[FLASH_BANK_AUX].start[FIRST_SECTOR] = dev->base; - size += flash_info[FLASH_BANK_AUX].size; - - - return size; -} - -/* - * Get flash device from U-Boot flash info. - */ -flash_dev_t *getFlashDevFromInfo (flash_info_t * info) -{ - int i; - - if (!info) - return NULL; - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - if (dev->found && (dev->base == info->start[0])) - return dev; - } - printf ("ERROR: notice, no FLASH mapped at address 0x%x\n", - (unsigned int) info->start[0]); - return NULL; -} - -ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - int i; - - for (i = 0; i < flashDevCount; i++) { - flash_dev_t *dev = &flashDev[i]; - - if (dev->found) { - if (dev->base == (unsigned int) addr) { - info->flash_id = (dev->vendorID << 16) | dev->deviceID; - info->sector_count = dev->sectors; - info->size = info->sector_count * FLASH_SECTOR_SIZE; - return dev->sectors * FLASH_SECTOR_SIZE; - } - } - } - return 0; -} - -void flash_print_info (flash_info_t * info) -{ - int i; - unsigned int chip; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch ((info->flash_id >> 16) & 0xff) { - case 0x1: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - chip = (unsigned int) info->flash_id & 0x000000ff; - - switch (chip) { - - case AMD_ID_F040B: - printf ("AM29F040B (4 Mbit)\n"); - break; - - case AMD_ID_LV160B: - case FLASH_AM160LV: - case 0x49: - printf ("AM29LV160B (16 Mbit / 2M x 8bit)\n"); - break; - - default: - printf ("Unknown Chip Type:0x%x\n", chip); - break; - } - - printf (" Size: %ld bytes in %d Sectors\n", - info->size, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[FIRST_SECTOR] + i * FLASH_SECTOR_SIZE, - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - - -/* - * Erase a range of flash sectors. - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect; - flash_dev_t *dev = NULL; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors */ - dev = getFlashDevFromInfo (info); - if (dev) { - printf ("Erase FLASH[%s] -%d sectors:", dev->name, dev->sectors); - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - printf ("."); - if (ERROR == flashEraseSector (dev, sect)) { - printf ("ERROR: could not erase sector %d on FLASH[%s]\n", sect, dev->name); - return 1; - } - } - } - } - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - - flash_dev_t *dev = getFlashDevFromInfo (info); - int addr = dest - info->start[0]; - - if (!dev) - return 1; - - if (OK != flashWrite (dev, addr, (char *) &data, sizeof (ulong))) { - printf ("ERROR: could not write to addr=0x%x, data=0x%x\n", - (unsigned int) addr, (unsigned) data); - return 1; - } - - if ((addr % FLASH_SECTOR_SIZE) == 0) - printf ("."); - - - PRINTF ("write_word:0x%x, base=0x%x, addr=0x%x, data=0x%x\n", - (unsigned) info->start[0], - (unsigned) dest, - (unsigned) (dest - info->start[0]), (unsigned) data); - - return (0); -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - flash_dev_t *dev = getFlashDevFromInfo (info); - - if (dev) { - printf ("FLASH[%s]:", dev->name); - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); - } - return 1; -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/mousse/flash.h b/board/mousse/flash.h deleted file mode 100644 index b7e4619c01..0000000000 --- a/board/mousse/flash.h +++ /dev/null @@ -1,78 +0,0 @@ -#ifndef FLASH_LIB_H -#define FLASH_LIB_H - -#include <common.h> - -/* PIO operations max */ -#define FLASH_PROGRAM_POLLS 100000 - -/* 10 Seconds default */ -#define FLASH_ERASE_SECTOR_TIMEOUT (10*1000 /*SEC*/ ) - -/* Flash device info structure */ -typedef struct flash_dev_s { - char name[24]; /* Bank Name */ - int bank; /* Bank 0 or 1 */ - unsigned int base; /* Base address */ - int sectors; /* Sector count */ - int lgSectorSize; /* Log2(usable bytes/sector) */ - int vendorID; /* Expected vendor ID */ - int deviceID; /* Expected device ID */ - int found; /* Set if found by flashLibInit */ - int swap; /* Set for bank 1 if byte swap req'd */ -} flash_dev_t; - -#define FLASH_MAX_POS(dev) \ - ((dev)->sectors << (dev)->lgSectorSize) - -#define FLASH_SECTOR_POS(dev, sector) \ - ((sector) << (dev)->lgSectorSize) - -/* AMD 29F040 */ -#define FLASH0_BANK 0 -#define FLASH0_VENDOR_ID 0x01 -#define FLASH0_DEVICE_ID 0x49 - -/* AMD29LV160DB */ -#define FLASH1_BANK 1 -#define FLASH1_VENDOR_ID 0x0001 -#define FLASH1_DEVICE_ID 0x2249 - -extern flash_dev_t flashDev[]; -extern int flashDevCount; - -/* - * Device pointers - * - * These must be kept in sync with the table in flashLib.c. - */ -#define FLASH_DEV_BANK0_SA0 (&flashDev[0]) -#define FLASH_DEV_BANK0_SA1 (&flashDev[1]) -#define FLASH_DEV_BANK0_SA2 (&flashDev[2]) -#define FLASH_DEV_BANK0_LOW (&flashDev[3]) /* 960K */ -#define FLASH_DEV_BANK0_BOOT (&flashDev[4]) /* PLCC */ -#define FLASH_DEV_BANK0_HIGH (&flashDev[5]) /* 512K PLCC shadow */ - -unsigned long flash_init(void); -int flashEraseSector(flash_dev_t *dev, int sector); -int flashErase(flash_dev_t *dev); -int flashRead(flash_dev_t *dev, int pos, char *buf, int len); -int flashWrite(flash_dev_t *dev, int pos, char *buf, int len); -int flashWritable(flash_dev_t *dev, int pos, int len); -int flashDiag(flash_dev_t *dev); -int flashDiagAll(void); - -ulong flash_get_size (vu_long *addr, flash_info_t *info); -void flash_print_info (flash_info_t *info); -int flash_erase (flash_info_t *info, int s_first, int s_last); -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt); - -/* - * Flash info indices. - */ -#define FLASH_BANK_KERNEL 0 -#define FLASH_BANK_BOOT 1 -#define FLASH_BANK_AUX 2 -#define FIRST_SECTOR 0 - -#endif /* !FLASH_LIB_H */ diff --git a/board/mousse/m48t59y.c b/board/mousse/m48t59y.c deleted file mode 100644 index 9a70dbeab1..0000000000 --- a/board/mousse/m48t59y.c +++ /dev/null @@ -1,308 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and - * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD) - * registers which are used to set/get the internal date/time functions. - * - * This module implements Y2K compliance by taking full year numbers - * and translating back and forth from the TOD 2-digit year. - * - * NOTE: for proper interaction with an operating system, the TOD should - * be used to store Universal Coordinated Time (GMT) and timezone - * conversions should be used. - * - * Here is a diagram of the memory layout: - * - * +---------------------------------------------+ 0xffe0a000 - * | Non-volatile memory | . - * | | . - * | (8176 bytes of Non-volatile memory) | . - * | | . - * +---------------------------------------------+ 0xffe0bff0 - * | Flags | - * +---------------------------------------------+ 0xffe0bff1 - * | Unused | - * +---------------------------------------------+ 0xffe0bff2 - * | Alarm Seconds | - * +---------------------------------------------+ 0xffe0bff3 - * | Alarm Minutes | - * +---------------------------------------------+ 0xffe0bff4 - * | Alarm Date | - * +---------------------------------------------+ 0xffe0bff5 - * | Interrupts | - * +---------------------------------------------+ 0xffe0bff6 - * | WatchDog | - * +---------------------------------------------+ 0xffe0bff7 - * | Calibration | - * +---------------------------------------------+ 0xffe0bff8 - * | Seconds | - * +---------------------------------------------+ 0xffe0bff9 - * | Minutes | - * +---------------------------------------------+ 0xffe0bffa - * | Hours | - * +---------------------------------------------+ 0xffe0bffb - * | Day | - * +---------------------------------------------+ 0xffe0bffc - * | Date | - * +---------------------------------------------+ 0xffe0bffd - * | Month | - * +---------------------------------------------+ 0xffe0bffe - * | Year (2 digits only) | - * +---------------------------------------------+ 0xffe0bfff - */ -#include <common.h> -#include <rtc.h> -#include "mousse.h" - -/* - * Imported from mousse.h: - * - * TOD_REG_BASE Base of m48t59y TOD registers - * SYS_TOD_UNPROTECT() Disable NVRAM write protect - * SYS_TOD_PROTECT() Re-enable NVRAM write protect - */ - -#define YEAR 0xf -#define MONTH 0xe -#define DAY 0xd -#define DAY_OF_WEEK 0xc -#define HOUR 0xb -#define MINUTE 0xa -#define SECOND 0x9 -#define CONTROL 0x8 -#define WATCH 0x7 -#define INTCTL 0x6 -#define WD_DATE 0x5 -#define WD_HOUR 0x4 -#define WD_MIN 0x3 -#define WD_SEC 0x2 -#define _UNUSED 0x1 -#define FLAGS 0x0 - -#define M48_ADDR ((volatile unsigned char *) TOD_REG_BASE) - -int m48_tod_init(void) -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] = 0; - M48_ADDR[WATCH] = 0; - M48_ADDR[INTCTL] = 0; - - /* - * If the oscillator is currently stopped (as on a new part shipped - * from the factory), start it running. - * - * Here is an example of the TOD bytes on a brand new M48T59Y part: - * 00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01 - */ - - if (M48_ADDR[SECOND] & 0x80) - M48_ADDR[SECOND] = 0; - - /* Is battery low */ - if ( M48_ADDR[FLAGS] & 0x10) { - printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n"); - } - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * m48_tod_set - */ - -static int to_bcd(int value) -{ - return value / 10 * 16 + value % 10; -} - -static int from_bcd(int value) -{ - return value / 16 * 10 + value % 16; -} - -static int day_of_week(int y, int m, int d) /* 0-6 ==> Sun-Sat */ -{ - static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4}; - y -= m < 3; - return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_set(int year, /* 1980-2079 */ - int month, /* 01-12 */ - int day, /* 01-31 */ - int hour, /* 00-23 */ - int minute, /* 00-59 */ - int second) /* 00-59 */ - -{ - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x80; /* Set WRITE bit */ - - M48_ADDR[YEAR] = to_bcd(year % 100); - M48_ADDR[MONTH] = to_bcd(month); - M48_ADDR[DAY] = to_bcd(day); - M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1; - M48_ADDR[HOUR] = to_bcd(hour); - M48_ADDR[MINUTE] = to_bcd(minute); - M48_ADDR[SECOND] = to_bcd(second); - - M48_ADDR[CONTROL] &= ~0x80; /* Clear WRITE bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -/* - * Note: the TOD should store the current GMT - */ - -int m48_tod_get(int *year, /* 1980-2079 */ - int *month, /* 01-12 */ - int *day, /* 01-31 */ - int *hour, /* 00-23 */ - int *minute, /* 00-59 */ - int *second) /* 00-59 */ -{ - int y; - - SYS_TOD_UNPROTECT(); - - M48_ADDR[CONTROL] |= 0x40; /* Set READ bit */ - - y = from_bcd(M48_ADDR[YEAR]); - *year = y < 80 ? 2000 + y : 1900 + y; - *month = from_bcd(M48_ADDR[MONTH]); - *day = from_bcd(M48_ADDR[DAY]); - /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */ - *hour = from_bcd(M48_ADDR[HOUR]); - *minute = from_bcd(M48_ADDR[MINUTE]); - *second = from_bcd(M48_ADDR[SECOND] & 0x7f); - - M48_ADDR[CONTROL] &= ~0x40; /* Clear READ bit */ - - SYS_TOD_PROTECT(); - - return 0; -} - -int m48_tod_get_second(void) -{ - return from_bcd(M48_ADDR[SECOND] & 0x7f); -} - -/* - * Watchdog function - * - * If usec is 0, the watchdog timer is disarmed. - * - * If usec is non-zero, the watchdog timer is armed (or re-armed) for - * approximately usec microseconds (if the exact requested usec is - * not supported by the chip, the next higher available value is used). - * - * Minimum watchdog timeout = 62500 usec - * Maximum watchdog timeout = 124 sec (124000000 usec) - */ - -void m48_watchdog_arm(int usec) -{ - int mpy, res; - - SYS_TOD_UNPROTECT(); - - if (usec == 0) { - res = 0; - mpy = 0; - } else if (usec < 2000000) { /* Resolution: 1/16s if below 2s */ - res = 0; - mpy = (usec + 62499) / 62500; - } else if (usec < 8000000) { /* Resolution: 1/4s if below 8s */ - res = 1; - mpy = (usec + 249999) / 250000; - } else if (usec < 32000000) { /* Resolution: 1s if below 32s */ - res = 2; - mpy = (usec + 999999) / 1000000; - } else { /* Resolution: 4s up to 124s */ - res = 3; - mpy = (usec + 3999999) / 4000000; - if (mpy > 31) - mpy = 31; - } - - M48_ADDR[WATCH] = (0x80 | /* Steer to RST signal (IRQ = N/C) */ - mpy << 2 | - res); - - SYS_TOD_PROTECT(); -} - -/* - * U-Boot RTC support. - */ -int -rtc_get( struct rtc_time *tmp ) -{ - m48_tod_get(&tmp->tm_year, - &tmp->tm_mon, - &tmp->tm_mday, - &tmp->tm_hour, - &tmp->tm_min, - &tmp->tm_sec); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif - - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - m48_tod_set(tmp->tm_year, /* 1980-2079 */ - tmp->tm_mon, /* 01-12 */ - tmp->tm_mday, /* 01-31 */ - tmp->tm_hour, /* 00-23 */ - tmp->tm_min, /* 00-59 */ - tmp->tm_sec); /* 00-59 */ - -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -void -rtc_reset (void) -{ - m48_tod_init(); -} diff --git a/board/mousse/m48t59y.h b/board/mousse/m48t59y.h deleted file mode 100644 index 2c7c092d14..0000000000 --- a/board/mousse/m48t59y.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * SGS M48-T59Y TOD/NVRAM Driver - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp. - * - * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __M48_T59_Y_H -#define __M48_T59_Y_H - -/* - * M48 T59Y -Timekeeping Battery backed SRAM. - */ - -int m48_tod_init(void); - -int m48_tod_set(int year, - int month, - int day, - int hour, - int minute, - int second); - -int m48_tod_get(int *year, - int *month, - int *day, - int *hour, - int *minute, - int *second); - -int m48_tod_get_second(void); - -void m48_watchdog_arm(int usec); - -#endif /*!__M48_T59_Y_H */ diff --git a/board/mousse/mousse.c b/board/mousse/mousse.c deleted file mode 100644 index e1724e657d..0000000000 --- a/board/mousse/mousse.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * MOUSSE Board Support - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty, jfd@cs.stanford.edu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc824x.h> -#include <netdev.h> -#include <asm/processor.h> -#include <timestamp.h> - -#include "mousse.h" -#include "m48t59y.h" -#include <pci.h> - - -int checkboard (void) -{ - ulong busfreq = get_bus_freq (0); - char buf[32]; - - puts ("Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)\n"); - printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); - printf ("MPLD: Revision %d\n", SYS_REVID_GET ()); - printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq)); - - return 0; -} - -int checkflash (void) -{ - printf ("checkflash\n"); - flash_init (); - return 0; -} - -phys_size_t initdram (int board_type) -{ - return CONFIG_SYS_RAM_SIZE; -} - - -void get_tod (void) -{ - int year, month, day, hour, minute, second; - - m48_tod_get (&year, &month, &day, &hour, &minute, &second); - - printf (" Current date/time: %d/%d/%d %d:%d:%d \n", - month, day, year, hour, minute, second); - -} - -/* - * EPIC, PCI, and I/O devices. - * Initialize Mousse Platform, probe for PCI devices, - * Query configuration parameters if not set. - */ -int misc_init_f (void) -{ - m48_tod_init (); /* Init SGS M48T59Y TOD/NVRAM */ - printf ("RTC: M48T589 TOD/NVRAM (%d) bytes\n", TOD_NVRAM_SIZE); - get_tod (); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/mousse/mousse.h b/board/mousse/mousse.h deleted file mode 100644 index ce8a054175..0000000000 --- a/board/mousse/mousse.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * MOUSSE/MPC8240 Board definitions. - * For more info, see http://www.vooha.com/ - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MOUSSE_H -#define __MOUSSE_H - -/* System addresses */ - -#define PCI_SPECIAL_BASE 0xfe000000 -#define PCI_SPECIAL_SIZE 0x01000000 - -/* PORTX Device Addresses for Mousse */ - -#define PORTX_DEV_BASE 0xff000000 -#define PORTX_DEV_SIZE 0x01000000 - -#define ENET_DEV_BASE 0x80000000 - -#define PLD_REG_BASE (PORTX_DEV_BASE | 0xe09000) -#define PLD_REG(off) (*(volatile unsigned char *) \ - (PLD_REG_BASE + (off))) - -#define PLD_REVID_B1 0x7f -#define PLD_REVID_B2 0x01 - -/* MPLD */ -#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */ -#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f) -#define SYS_LED_OFF() (PLD_REG(1) |= 0x80) -#define SYS_LED_ON() (PLD_REG(1) &= ~0x80) -#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80) -#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80) -#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80) -#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80) - -/* SGS M48T59Y */ -#define TOD_BASE (PORTX_DEV_BASE | 0xe0a000) -#define TOD_REG_BASE (TOD_BASE | 0x1ff0) -#define TOD_NVRAM_BASE TOD_BASE -#define TOD_NVRAM_SIZE 0x1ff0 -#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE) - -/* NS16552 SIO */ -#define SERIAL_BASE(_x) (PORTX_DEV_BASE | 0xe08000 | ((_x) ? 0 : 0x80)) -#define N_SIO_CHANNELS 2 -#define N_COM_PORTS N_SIO_CHANNELS - -/* - * On-board Dec21143 PCI Ethernet - * Note: The PCI MBAR chosen here was used from MPC8240UM which states - * that PCI memory is at: 0x80000 - 0xFDFFFFFF, if AMBOR[CPU_FD_ALIAS] - * is set, then PCI memory maps 1-1 with this address range in the - * correct byte order. - */ -#define PCI_ENET_IOADDR 0x80000000 -#define PCI_ENET_MEMADDR 0x80000000 - -/* - * Flash Memory Layout - * - * 2 MB Flash Bank 0 runs in 8-bit mode. In Flash Bank 0, the 32 kB - * sector SA3 is obscured by the 32 kB serial/TOD access space, and - * the 64 kB sectors SA19-SA26 are obscured by the 512 kB PLCC - * containing the fixed boot ROM. (If the 512 kB PLCC is - * deconfigured by jumper, this window to Flash Bank 0 becomes - * visible, but it still contains the fixed boot code and should be - * considered read-only). Flash Bank 0 sectors SA0 (16 kB), SA1 (8 - * kB), and SA2 (8 kB) are currently unused. - * - * 2 MB Flash Bank 1 runs in 16-bit mode. Flash Bank 1 is fully - * usable, but it's a 16-bit wide device on a 64-bit bus. Therefore - * 16-bit words only exist at addresses that are multiples of 8. All - * PROM data and control addresses must be multiplied by 8. - * - * See flashMap.c for description of flash filesystem layout. - */ - -/* - * FLASH memory address space: 8-bit wide FLASH memory spaces. - */ -#define FLASH0_SEG0_START 0xffe00000 /* Baby 32Kb segment */ -#define FLASH0_SEG0_END 0xffe07fff /* 16 kB + 8 kB + 8 kB */ -#define FLASH0_SEG0_SIZE 0x00008000 /* (sectors SA0-SA2) */ - -#define FLASH0_SEG1_START 0xffe10000 /* 1MB - 64Kb FLASH0 seg */ -#define FLASH0_SEG1_END 0xffefffff /* 960 kB */ -#define FLASH0_SEG1_SIZE 0x000f0000 - -#define FLASH0_SEG2_START 0xfff00000 /* Boot Loader stored here */ -#define FLASH0_SEG2_END 0xfff7ffff /* 512 kB FLASH0/PLCC seg */ -#define FLASH0_SEG2_SIZE 0x00080000 - -#define FLASH0_SEG3_START 0xfff80000 /* 512 kB FLASH0 seg */ -#define FLASH0_SEG3_END 0xffffffff -#define FLASH0_SEG3_SIZE 0x00080000 - -/* Where Kahlua starts */ -#define FLASH_RESET_VECT 0xfff00100 - -/* - * CHRP / PREP (MAP A/B) definitions. - */ - -#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */ -#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */ -/* MPC107 (MPC8240 internal EUMBBAR mapped) */ -#define CHRP_REG_ADDR 0xfec00000 /* MPC106 Config, Map B */ -#define CHRP_REG_DATA 0xfee00000 /* MPC106 Config, Map B */ - -/* - * Mousse PCI IDSEL Assignments (Device Number) - */ -#define MOUSSE_IDSEL_ENET 13 /* On-board 21143 Ethernet */ -#define MOUSSE_IDSEL_LPCI 14 /* On-board PCI slot */ -#define MOUSSE_IDSEL_82371 15 /* That other thing */ -#define MOUSSE_IDSEL_CPCI2 31 /* CPCI slot 2 */ -#define MOUSSE_IDSEL_CPCI3 30 /* CPCI slot 3 */ -#define MOUSSE_IDSEL_CPCI4 29 /* CPCI slot 4 */ -#define MOUSSE_IDSEL_CPCI5 28 /* CPCI slot 5 */ -#define MOUSSE_IDSEL_CPCI6 27 /* CPCI slot 6 */ - -/* - * Mousse Interrupt Mapping: - * - * IRQ1 Enet (intA|intB|intC|intD) - * IRQ2 CPCI intA (See below) - * IRQ3 Local PCI slot intA|intB|intC|intD - * IRQ4 COM1 Serial port (Actually higher addressed port on duart) - * - * PCI Interrupt Mapping in CPCI chassis: - * - * | CPCI Slot - * | 1 (CPU) 2 3 4 5 6 - * -----------+--------+-------+-------+-------+-------+-------+ - * intA | X X X - * intB | X X X - * intC | X X X - * intD | X X X - */ - - -#define EPIC_VECTOR_EXT0 0 -#define EPIC_VECTOR_EXT1 1 -#define EPIC_VECTOR_EXT2 2 -#define EPIC_VECTOR_EXT3 3 -#define EPIC_VECTOR_EXT4 4 -#define EPIC_VECTOR_TM0 16 -#define EPIC_VECTOR_TM1 17 -#define EPIC_VECTOR_TM2 18 -#define EPIC_VECTOR_TM3 19 -#define EPIC_VECTOR_I2C 20 -#define EPIC_VECTOR_DMA0 21 -#define EPIC_VECTOR_DMA1 22 -#define EPIC_VECTOR_I2O 23 - - -#define INT_VEC_IRQ0 0 -#define INT_NUM_IRQ0 INT_VEC_IRQ0 -#define MOUSSE_IRQ_ENET EPIC_VECTOR_EXT1 /* Hardwired */ -#define MOUSSE_IRQ_CPCI EPIC_VECTOR_EXT2 /* Hardwired */ -#define MOUSSE_IRQ_LPCI EPIC_VECTOR_EXT3 /* Hardwired */ -#define MOUSSE_IRQ_DUART EPIC_VECTOR_EXT4 /* Hardwired */ - -/* Onboard DEC 21143 Ethernet */ -#define PCI_ENET_MEMADDR 0x80000000 -#define PCI_ENET_IOADDR 0x80000000 - -/* Some other PCI device */ -#define PCI_SLOT_MEMADDR 0x81000000 -#define PCI_SLOT_IOADDR 0x81000000 - -/* Promise ATA66 PCI Device (ATA controller) */ -#define PROMISE_MBAR0 0xa0000000 -#define PROMISE_MBAR1 (PROMISE_MBAR0 + 0x1000) -#define PROMISE_MBAR2 (PROMISE_MBAR0 + 0x2000) -#define PROMISE_MBAR3 (PROMISE_MBAR0 + 0x3000) -#define PROMISE_MBAR4 (PROMISE_MBAR0 + 0x4000) -#define PROMISE_MBAR5 (PROMISE_MBAR0 + 0x5000) - -/* ATA/66 Controller offsets */ -#define CONFIG_SYS_ATA_BASE_ADDR PROMISE_MBAR0 -#define CONFIG_SYS_IDE_MAXBUS 2 /* ide0/ide1 */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 2 drives per controller */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x3000 -/* - * Definitions for accessing IDE controller registers - */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_ALT_OFFSET (0x1000) - -/* - * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS - * are defined in config.h and Makefile. - * All definitions for these constants must be identical. - */ -#define ROM_BASE_ADRS 0xfff00000 /* base address of ROM */ -#define ROM_TEXT_ADRS (ROM_BASE_ADRS+0x0100) /* with PC & SP */ -#define ROM_WARM_ADRS (ROM_TEXT_ADRS+0x0004) /* warm reboot entry */ -#define ROM_SIZE 0x00080000 /* 512KB ROM space */ -#define RAM_LOW_ADRS 0x00010000 /* RAM address for vxWorks */ -#define RAM_HIGH_ADRS 0x00c00000 /* RAM address for bootrom */ - -/* - * NVRAM configuration - * NVRAM is implemented via the SGS Thomson M48T59Y - * 64Kbit (8Kbx8) Timekeeper SRAM. - * This 8KB NVRAM also has a TOD. See m48t59y.{h,c} for more information. - */ - -#define NV_RAM_ADRS TOD_NVRAM_BASE -#define NV_RAM_INTRVL 1 -#define NV_RAM_WR_ENBL SYS_TOD_UNPROTECT() -#define NV_RAM_WR_DSBL SYS_TOD_PROTECT() - -#define NV_OFF_BOOT0 0x0000 /* Boot string 0 (256b) */ -#define NV_OFF_BOOT1 0x0100 /* Boot string 1 (256b) */ -#define NV_OFF_BOOT2 0x0200 /* Boot string 2 (256b)*/ -#define NV_OFF_MACADDR 0x0400 /* 21143 MAC address (6b) */ -#define NV_OFF_ACTIVEBOOT 0x0406 /* Active boot string, 0 to 2 (1b) */ -#define NV_OFF_UNUSED1 0x0407 /* Unused (1b) */ -#define NV_OFF_BINDFIX 0x0408 /* See sysLib.c:sysBindFix() (1b) */ -#define NV_OFF_UNUSED2 0x0409 /* Unused (7b) */ -#define NV_OFF_TIMEZONE 0x0410 /* TIMEZONE env var (64b) */ -#define NV_OFF_VXWORKS_END 0x07FF /* 2047 VxWorks Total */ -#define NV_OFF_U_BOOT 0x0800 /* 2048 U-Boot boot-loader */ -#define NV_OFF_U_BOOT_ADDR (TOD_BASE + NV_OFF_U_BOOT) /* sysaddr*/ -#define NV_U_BOOT_ENV_SIZE 2048 /* 2K - U-Boot Total */ -#define NV_OFF__next_free (NV_U_BOOT_ENVSIZE +1) -#define NV_RAM_SIZE 8176 /* NVRAM End */ - -#endif /* __MOUSSE_H */ diff --git a/board/mousse/pci.c b/board/mousse/pci.c deleted file mode 100644 index a64144b130..0000000000 --- a/board/mousse/pci.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001 - * James Dougherty (jfd@cs.stanford.edu) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * PCI Configuration space access support for MPC824x/MPC107 PCI Bridge - */ -#include <common.h> -#include <mpc824x.h> -#include <pci.h> - -#include "mousse.h" - -/* - * Promise ATA/66 support. - */ -#define XFER_PIO_4 0x0C /* 0000|1100 */ -#define XFER_PIO_3 0x0B /* 0000|1011 */ -#define XFER_PIO_2 0x0A /* 0000|1010 */ -#define XFER_PIO_1 0x09 /* 0000|1001 */ -#define XFER_PIO_0 0x08 /* 0000|1000 */ -#define XFER_PIO_SLOW 0x00 /* 0000|0000 */ - -/* Promise Regs */ -#define REG_A 0x01 -#define REG_B 0x02 -#define REG_C 0x04 -#define REG_D 0x08 - -void -pdc202xx_decode_registers (unsigned char registers, unsigned char value) -{ - unsigned char bit = 0, bit1 = 0, bit2 = 0; - switch(registers) { - case REG_A: - bit2 = 0; - printf(" A Register "); - if (value & 0x80) printf("SYNC_IN "); - if (value & 0x40) printf("ERRDY_EN "); - if (value & 0x20) printf("IORDY_EN "); - if (value & 0x10) printf("PREFETCH_EN "); - if (value & 0x08) { printf("PA3 ");bit2 |= 0x08; } - if (value & 0x04) { printf("PA2 ");bit2 |= 0x04; } - if (value & 0x02) { printf("PA1 ");bit2 |= 0x02; } - if (value & 0x01) { printf("PA0 ");bit2 |= 0x01; } - printf("PIO(A) = %d ", bit2); - break; - case REG_B: - bit1 = 0;bit2 = 0; - printf(" B Register "); - if (value & 0x80) { printf("MB2 ");bit1 |= 0x80; } - if (value & 0x40) { printf("MB1 ");bit1 |= 0x40; } - if (value & 0x20) { printf("MB0 ");bit1 |= 0x20; } - printf("DMA(B) = %d ", bit1 >> 5); - if (value & 0x10) printf("PIO_FORCED/PB4 "); - if (value & 0x08) { printf("PB3 ");bit2 |= 0x08; } - if (value & 0x04) { printf("PB2 ");bit2 |= 0x04; } - if (value & 0x02) { printf("PB1 ");bit2 |= 0x02; } - if (value & 0x01) { printf("PB0 ");bit2 |= 0x01; } - printf("PIO(B) = %d ", bit2); - break; - case REG_C: - bit2 = 0; - printf(" C Register "); - if (value & 0x80) printf("DMARQp "); - if (value & 0x40) printf("IORDYp "); - if (value & 0x20) printf("DMAR_EN "); - if (value & 0x10) printf("DMAW_EN "); - - if (value & 0x08) { printf("MC3 ");bit2 |= 0x08; } - if (value & 0x04) { printf("MC2 ");bit2 |= 0x04; } - if (value & 0x02) { printf("MC1 ");bit2 |= 0x02; } - if (value & 0x01) { printf("MC0 ");bit2 |= 0x01; } - printf("DMA(C) = %d ", bit2); - break; - case REG_D: - printf(" D Register "); - break; - default: - return; - } - printf("\n %s ", (registers & REG_D) ? "DP" : - (registers & REG_C) ? "CP" : - (registers & REG_B) ? "BP" : - (registers & REG_A) ? "AP" : "ERROR"); - for (bit=128;bit>0;bit/=2) - printf("%s", (value & bit) ? "1" : "0"); - printf("\n"); -} - -/* - * Promise ATA/66 Support: configure Promise ATA66 card in specified mode. - */ -int -pdc202xx_tune_chipset (pci_dev_t dev, int drive, unsigned char speed) -{ - unsigned short drive_conf; - int err = 0; - unsigned char drive_pci, AP, BP, CP, DP; - unsigned char TA = 0, TB = 0; - - switch (drive) { - case 0: drive_pci = 0x60; break; - case 1: drive_pci = 0x64; break; - case 2: drive_pci = 0x68; break; - case 3: drive_pci = 0x6c; break; - default: return -1; - } - - pci_read_config_word(dev, drive_pci, &drive_conf); - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_read_config_byte(dev, (drive_pci)|0x02, &CP); - pci_read_config_byte(dev, (drive_pci)|0x03, &DP); - - if ((AP & 0x0F) || (BP & 0x07)) { - /* clear PIO modes of lower 8421 bits of A Register */ - pci_write_config_byte(dev, (drive_pci), AP & ~0x0F); - pci_read_config_byte(dev, (drive_pci), &AP); - - /* clear PIO modes of lower 421 bits of B Register */ - pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - } - - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_read_config_byte(dev, (drive_pci)|0x02, &CP); - - switch(speed) { - case XFER_PIO_4: TA = 0x01; TB = 0x04; break; - case XFER_PIO_3: TA = 0x02; TB = 0x06; break; - case XFER_PIO_2: TA = 0x03; TB = 0x08; break; - case XFER_PIO_1: TA = 0x05; TB = 0x0C; break; - case XFER_PIO_0: - default: TA = 0x09; TB = 0x13; break; - } - - pci_write_config_byte(dev, (drive_pci), AP|TA); - pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB); - - pci_read_config_byte(dev, (drive_pci), &AP); - pci_read_config_byte(dev, (drive_pci)|0x01, &BP); - pci_read_config_byte(dev, (drive_pci)|0x02, &CP); - pci_read_config_byte(dev, (drive_pci)|0x03, &DP); - - -#ifdef PDC202XX_DEBUG - pdc202xx_decode_registers(REG_A, AP); - pdc202xx_decode_registers(REG_B, BP); - pdc202xx_decode_registers(REG_C, CP); - pdc202xx_decode_registers(REG_D, DP); -#endif - return err; -} -/* - * Show/Init PCI devices on the specified bus number. - */ - -void pci_mousse_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned int line; - - switch(PCI_DEV(dev)) { - case 0x0d: - line = 0x00000101; - break; - - case 0x0e: - default: - line = 0x00000303; - break; - } - - pci_write_config_dword(dev, PCI_INTERRUPT_LINE, line); -} - -void pci_mousse_setup_pdc202xx(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *_) -{ - unsigned short vendorId; - unsigned int mbar0, cmd; - int bar, a; - - pci_read_config_word(dev, PCI_VENDOR_ID, &vendorId); - - if(vendorId == PCI_VENDOR_ID_PROMISE || vendorId == PCI_VENDOR_ID_CMD){ - /* PDC 202xx card is handled differently, it is a bootable - * device and needs all 5 MBAR's configured - */ - for(bar = 0; bar < 5; bar++){ - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, ~0); - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); -#ifdef DEBUG - printf(" ATA_bar[%d] = %dbytes\n", bar, - ~(mbar0 & PCI_BASE_ADDRESS_MEM_MASK) + 1); -#endif - } - - /* Program all BAR's */ - pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PROMISE_MBAR0); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, PROMISE_MBAR1); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, PROMISE_MBAR2); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, PROMISE_MBAR3); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, PROMISE_MBAR4); - pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, PROMISE_MBAR5); - - for(bar = 0; bar < 5; bar++){ - pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0); -#ifdef DEBUG - printf(" ATA_bar[%d]@0x%x\n", bar, mbar0); -#endif - } - - /* Enable ROM Expansion base */ - pci_write_config_dword(dev, PCI_ROM_ADDRESS, PROMISE_MBAR5|1); - - /* Io enable, Memory enable, master enable */ - pci_read_config_dword(dev, PCI_COMMAND, &cmd); - cmd &= ~0xffff0000; - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config_dword(dev, PCI_COMMAND, cmd); - - /* Breath some life into the controller */ - for( a = 0; a < 4; a++) - pdc202xx_tune_chipset(dev, a, XFER_PIO_0); - } -} - -static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0e, 0x00, - pci_mousse_setup_pdc202xx }, -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0d, 0x00, - pci_cfgfunc_config_device, {PCI_ENET_IOADDR, - PCI_ENET_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_SLOT_IOADDR, - PCI_SLOT_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, -#endif - { } -}; - -struct pci_controller hose = { - config_table: pci_sandpoint_config_table, - fixup_irq: pci_mousse_fixup_irq, -}; - -void pci_init_board(void) -{ - pci_mpc824x_init(&hose); -} diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds deleted file mode 100644 index f49161c67f..0000000000 --- a/board/mousse/u-boot.lds +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .text : - { - arch/powerpc/cpu/mpc824x/start.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram deleted file mode 100644 index c0281311c5..0000000000 --- a/board/mousse/u-boot.lds.ram +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems Ltd. robt@flyingpig.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -MEMORY { - ram (!rx) : org = 0x00000000 , LENGTH = 8M - code (!rx) : org = 0x00002000 , LENGTH = (4M - 0x2000) - rom (rx) : org = 0xfff00000 , LENGTH = 512K -} - -SECTIONS -{ - _f_init = .; - PROVIDE(_f_init = .); - _f_init_rom = .; - PROVIDE(_f_init_rom = .); - - .init : { - arch/powerpc/cpu/mpc824x/start.o (.text) - *(.init) - } > ram - _init_size = SIZEOF(.init); - PROVIDE(_init_size = SIZEOF(.init)); - - ENTRY(_start) - -/* _ftext = .; - _ftext_rom = .; - _text_size = SIZEOF(.text); - */ - .text : { - *(.text) - *(.got1) - } > ram - .rodata : { *(.rodata) } > ram - .dtors : { *(.dtors) } > ram - .data : { *(.data) } > ram - .sdata : { *(.sdata) } > ram - .sdata2 : { *(.sdata2) - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } > ram - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .sbss : { *(.sbss) } > ram - .sbss2 : { *(.sbss2) } > ram - .bss : { *(.bss) } > ram - .debug : { *(.debug) } > ram - .line : { *(.line) } > ram - .symtab : { *(.symtab) } > ram - .shrstrtab : { *(.shstrtab) } > ram - .strtab : { *(.strtab) } > ram - /* .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } > ram - */ - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } > ram - __stop___ex_table = .; - - - .ppcenv : - { - common/env_embedded.o (.ppcenv) - } > ram - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom deleted file mode 100644 index f162ae365b..0000000000 --- a/board/mousse/u-boot.lds.rom +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc824x/start.o (.text) - common/board.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - lib/zlib.o (.text) - - . = env_offset; - common/env_embedded.o (.text) - - *(.text) - - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/nx823/Makefile b/board/nx823/Makefile deleted file mode 100644 index a22be5c3e6..0000000000 --- a/board/nx823/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = nx823.o flash.o diff --git a/board/nx823/flash.c b/board/nx823/flash.c deleted file mode 100644 index fbe17dd966..0000000000 --- a/board/nx823/flash.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -DECLARE_GLOBAL_DATA_PTR; - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE+monitor_flash_len-1, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - printf ("28F320J3A\n"); break; - case FLASH_28F640J3A: - printf ("28F640J3A\n"); break; - case FLASH_28F128J3A: - printf ("28F128J3A\n"); break; - default: printf ("Unknown Chip Type\n"); break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW)0x00AA00AA; - addr[0x2AAA] = (FPW)0x00550055; - addr[0x5555] = (FPW)0x00900090; - - value = addr[0]; - - switch (value) { - case (FPW)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW)0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case (FPW)INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FPW)INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (FPW)INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW)0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *)(info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW)0x00B000B0; /* suspend erase */ - *addr = (FPW)0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW)0x00FF00FF; /* reset to read mode */ - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* save sernum if needed */ - if (addr >= CONFIG_SYS_FLASH_SN_SECTOR && addr < CONFIG_SYS_FLASH_SN_BASE) - { - u_long dest = CONFIG_SYS_FLASH_SN_BASE; - u_short *sn = (u_short *)gd->bd->bi_sernum; - - printf("(saving sernum)"); - for (i=0; i<4; i++) - { - if ((rc = write_data(info, dest, sn[i])) != 0) { - return (rc); - } - dest += port_width; - } - } - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<port_width && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i=0; i<port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) - { - putc('.'); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_data(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *)dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf("not erased at %08lx (%x)\n",(ulong)addr,*addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *addr = (FPW)0x00400040; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW)0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW)0x00FF00FF; /* restore read mode */ - - return (0); -} diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c deleted file mode 100644 index d49fa8ca21..0000000000 --- a/board/nx823/nx823.c +++ /dev/null @@ -1,374 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <malloc.h> -#include <mpc8xx.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -static long int dram_size (long int, long int *, long int); - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = { -#if (MPC8XX_SPEED <= 50000000L) - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07, - 0xFFFFFFFF, - - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FE7F434, 0xEFABE834, 0x1FA7D435, - - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00, - 0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00, - 0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF -#else - - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800, - 0x1FF7F447, - - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF7F434, 0xEFEBE834, 0x1FB7D435, - - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -#endif -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - */ - -int checkboard (void) -{ - printf ("Board: Nexus NX823"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0, size_b1, size8, size9; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Up to 2 Banks of 64Mbit x 2 devices - * Initial builds only have 1 - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; - memctl->memc_mar = 0x00000088; - - /* - * Map controller SDRAM bank 0 - */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - udelay (200); - - /* - * Map controller SDRAM bank 1 - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - - /* - * Perform SDRAM initializsation sequence - */ - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ - udelay (1); - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, - SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size_b0 = size9; -/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); -/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ - } - - /* - * Check Bank 1 Memory Size - * use current column settings - * [9 column SDRAM may also be used in 8 column mode, - * but then only half the real size will be used.] - */ - size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM, - SDRAM_MAX_SIZE); -/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */ - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type, both banks - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping: map bigger bank first - */ - if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - - memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b0 > 0) { - /* - * Position Bank 0 immediately above Bank 1 - */ - memctl->memc_or1 = - ((-size_b0) & 0xFFFF0000) | - CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | - BR_V) - + size_b1; - } else { - unsigned long reg; - - /* - * No bank 0 - * - * invalidate bank - */ - memctl->memc_br1 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - - } else { /* SDRAM Bank 0 is bigger - map first */ - - memctl->memc_or1 = - ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br1 = - (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - if (size_b1 > 0) { - /* - * Position Bank 1 immediately above Bank 0 - */ - memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | - CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = - ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | - BR_V) - + size_b0; - } else { - unsigned long reg; - - /* - * No bank 1 - * - * invalidate bank - */ - memctl->memc_br2 = 0; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - } - } - - udelay (10000); - - return (size_b0 + size_b1); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -int misc_init_r (void) -{ - int i; - char tmp[50]; - uchar ethaddr[6]; - bd_t *bd = gd->bd; - ulong *my_sernum = (unsigned long *)&bd->bi_sernum; - - /* load unique serial number */ - for (i = 0; i < 8; ++i) - bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i); - - /* save env variables according to sernum */ - sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]); - setenv ("serial#", tmp); - - if (!eth_getenv_enetaddr("ethaddr", ethaddr)) { - ethaddr[0] = 0x10; - ethaddr[1] = 0x20; - ethaddr[2] = 0x30; - ethaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2]; - ethaddr[4] = bd->bi_sernum[5]; - ethaddr[5] = bd->bi_sernum[6]; - } - - return 0; -} diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds deleted file mode 100644 index 7ae91ffb2e..0000000000 --- a/board/nx823/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2001-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug deleted file mode 100644 index b0091db0c6..0000000000 --- a/board/nx823/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/ppmc8260/strataflash.c b/board/ppmc8260/strataflash.c deleted file mode 100644 index ea3c42eed4..0000000000 --- a/board/ppmc8260/strataflash.c +++ /dev/null @@ -1,736 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8260.h> -#include <asm/processor.h> - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CONFIG_SYS_FLASH_BASE; - size = 0; - - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CONFIG_SYS_FLASH_INCREMENT; - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, - flash_info[0].size, flash_info[i].size<<20); - } - } - - /* Monitor protection ON by default */ -#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n"); - printf (" %08lX%5s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;i<aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - - for(; (i< info->portwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i<info->portwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; i<info->sector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/board/prodrive/common/flash.c b/board/prodrive/common/flash.c deleted file mode 100644 index 9954051852..0000000000 --- a/board/prodrive/common/flash.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * Functions - */ -static int write_word(flash_info_t *info, ulong dest, ulong data); - -void flash_print_info(flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("ST "); break; - case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_SST020: printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n"); - break; - case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { -#ifdef CONFIG_SYS_FLASH_EMPTY_INFO - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - /* print empty and read-only info */ - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size(vu_long *addr, flash_info_t *info) -{ - short i; - short n; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090; - - value = addr2[CONFIG_SYS_FLASH_READ0]; - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT: - info->flash_id = FLASH_MAN_EXCEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */ - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020: - info->flash_id += FLASH_SST020; - info->sector_count = 64; - info->size = 0x00040000; - break; /* => 256 kB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040: - info->flash_id += FLASH_SST040; - info->sector_count = 128; - info->size = 0x00080000; - break; /* => 512 kB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00001000); - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (i < info->sector_count) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) - info->protect[i] = 0; - else - info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf ("- missing\n"); - else - printf ("- no sectors to erase\n"); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) - if (info->protect[sect]) - prot++; - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - else - printf ("\n"); - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ - - /* re-enable interrupts if necessary */ - if (flag) { - enable_interrupts(); - flag = 0; - } - - /* data polling for D7 */ - start = get_timer (0); - while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - } else { - if (sect == s_first) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - } - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) - data = (data << 8) | *src++; - if ((rc = write_word(info, wp, data)) != 0) - return (rc); - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return (0); - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) - data = (data << 8) | (*(uchar *)cp); - - return (write_word(info, wp, data)); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word(flash_info_t *info, ulong dest, ulong data) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return (2); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - } - - return (0); -} diff --git a/board/prodrive/common/fpga.c b/board/prodrive/common/fpga.c deleted file mode 100644 index 9dce131376..0000000000 --- a/board/prodrive/common/fpga.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2001-2004 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <command.h> - -/* ------------------------------------------------------------------------- */ - -#ifdef FPGA_DEBUG -#define DBG(x...) printf(x) -#else -#define DBG(x...) -#endif /* DEBUG */ - -#define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (cpu output)*/ -#define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (cpu output) */ -#define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (cpu output) */ -#define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (cpu input) */ -#define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (cpu input) */ - -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ - -#ifndef OLD_VAL -# define OLD_VAL 0 -#endif - -#if 0 /* test-only */ -#define FPGA_WRITE_1 { \ - SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set data to 1 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set clock to 0 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | 0 | 0 ); /* set data to 0 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0 ); /* set clock to 1 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ -#else -#define FPGA_WRITE_1 { \ - SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set data to 1 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(OLD_VAL | FPGA_PRG | 0 | 0 ); /* set data to 0 */ \ - SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0 );} /* set data to 1 */ -#endif - -static int fpga_boot(unsigned char *fpgadata, int size) -{ - int i,index,len; - int count; - int j; - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = fpgadata[index]; - DBG("FPGA: %s\n", &(fpgadata[index+1])); - index += len+3; - } - - /* search for preamble 0xFFFFFFFF */ - while (1) { - if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) && - (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff)) - break; /* preamble found */ - else - index++; - } - - DBG("FPGA: configdata starts at position 0x%x\n",index); - DBG("FPGA: length of fpga-data %d\n", size-index); - - /* - * Setup port pins for fpga programming - */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */ - - DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); - DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA(0 | FPGA_CLK | FPGA_DATA); /* set prog active */ - - /* Wait for FPGA init line low */ - count = 0; - while (FPGA_INIT_STATE) { - udelay(1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) { - DBG("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } - } - - DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); - DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - - /* deassert PROGRAM* */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set prog inactive */ - - /* Wait for FPGA end of init period . */ - count = 0; - while (!(FPGA_INIT_STATE)) { - udelay(1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } - } - - DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); - DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - - DBG("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ - - /* - * Load uncompressed image into fpga - */ - for (i=index; i<size; i++) { - for (j=0; j<8; j++) { - if ((fpgadata[i] & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - fpgadata[i] <<= 1; - } - } - - DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); - DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - - /* - * Check if fpga's DONE signal - correctly booted ? - */ - - /* Wait for FPGA end of programming period . */ - count = 0; - while (!(FPGA_DONE_STATE)) { - udelay(1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } - } - - DBG("FPGA: Booting successful!\n"); - return 0; -} diff --git a/board/rpxsuper/Makefile b/board/rpxsuper/Makefile deleted file mode 100644 index 239b419ab2..0000000000 --- a/board/rpxsuper/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := rpxsuper.o flash.o mii_phy.o diff --git a/board/rpxsuper/flash.c b/board/rpxsuper/flash.c deleted file mode 100644 index 24bcd7c0a3..0000000000 --- a/board/rpxsuper/flash.c +++ /dev/null @@ -1,416 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger <mgroeger@sysgo.de> - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AMD 29F080B devices - * Added support for 64bit and AMD 29DL323B - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#include <asm/io.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define RD_SWP32(x) in_le32((volatile u32*)x) - -/*----------------------------------------------------------------------- - * Functions - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* for now, only support the 4 MB Flash SIMM */ - (void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE, - &flash_info[0]); - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -#ifndef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD "); - break; - case (FUJ_MANUFACT & FLASH_VENDMASK): - printf ("FUJITSU "); - break; - case (SST_MANUFACT & FLASH_VENDMASK): - printf ("SST "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_DL323B & FLASH_TYPEMASK): - printf("AM29DL323B (32 MBit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - vu_long vendor[2], devid[2]; - ulong base = (ulong)addr; - - /* Reset and Write auto select command: read Manufacturer ID */ - addr[0] = 0xf0f0f0f0; - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0x90909090; - addr[1] = 0xf0f0f0f0; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0x90909090; - udelay (1000); - - vendor[0] = RD_SWP32(&addr[0]); - vendor[1] = RD_SWP32(&addr[1]); - if (vendor[0] != vendor[1] || vendor[0] != AMD_MANUFACT) { - info->size = 0; - goto out; - } - - devid[0] = RD_SWP32(&addr[2]); - devid[1] = RD_SWP32(&addr[3]); - - if (devid[0] == AMD_ID_DL323B) { - /* - * we have 2 Banks - * Bank 1 (23 Sectors): 0-7=8kbyte, 8-22=64kbyte - * Bank 2 (48 Sectors): 23-70=64kbyte - */ - info->flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_DL323B & FLASH_TYPEMASK); - info->sector_count = 71; - info->size = 4 * (8 * 8 + 63 * 64) * 1024; - } - else { - info->size = 0; - goto out; - } - - /* set up sector start address table */ - for (i = 0; i < 8; i++) { - info->start[i] = base + (i * 0x8000); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x40000) + 8 * 0x8000 - 8 * 0x40000; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address */ - addr = (volatile unsigned long *)(info->start[i]); - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0x90909090; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0x90909090; - udelay (1000); - base = RD_SWP32(&addr[4]); - base |= RD_SWP32(&addr[5]); - info->protect[i] = base & 0x00010001 ? 1 : 0; - } - addr = (vu_long*)info->start[0]; - -out: - /* reset command */ - addr[0] = 0xf0f0f0f0; - addr[1] = 0xf0f0f0f0; - - return info->size; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0x80808080; - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0x80808080; - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - udelay (100); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x30303030; - addr[1] = 0x30303030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ( (addr[0] & 0x80808080) != 0x80808080 || - (addr[1] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - addr[1] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if ((dest & 0x00000004) == 0) { - addr[2 * 0x0555] = 0xAAAAAAAA; - addr[2 * 0x02AA] = 0x55555555; - addr[2 * 0x0555] = 0xA0A0A0A0; - } - else { - addr[2 * 0x0555 + 1] = 0xAAAAAAAA; - addr[2 * 0x02AA + 1] = 0x55555555; - addr[2 * 0x0555 + 1] = 0xA0A0A0A0; - } - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/rpxsuper/mii_phy.c b/board/rpxsuper/mii_phy.c deleted file mode 100644 index 12e23f487f..0000000000 --- a/board/rpxsuper/mii_phy.c +++ /dev/null @@ -1,107 +0,0 @@ -#include <common.h> -#include <mii_phy.h> -#include "rpxsuper.h" - -#define MII_MDIO 0x01 -#define MII_MDCK 0x02 -#define MII_MDIR 0x04 - -void -mii_discover_phy(void) -{ - int known; - unsigned short phy_reg; - unsigned long phy_id; - - known = 0; - printf("Discovering phy @ 0: "); - phy_id = mii_phy_read(2) << 16; - phy_id |= mii_phy_read(3); - if ((phy_id & 0xFFFFFC00) == 0x00137800) { - printf("Level One "); - if ((phy_id & 0x000003F0) == 0xE0) { - printf("LXT971A Revision %d\n", (int)(phy_id & 0xF)); - known = 1; - } - else printf("unknown type\n"); - } - else printf("unknown OUI = 0x%08lX\n", phy_id); - - phy_reg = mii_phy_read(1); - if (!(phy_reg & 0x0004)) printf("Link is down\n"); - if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n"); - if (phy_reg & 0x0002) printf("Jabber condition detected\n"); - if (phy_reg & 0x0010) printf("Remote fault condition detected \n"); - - if (known) { - phy_reg = mii_phy_read(17); - if (phy_reg & 0x0400) - printf("Phy operating at %d MBit/s in %s-duplex mode\n", - phy_reg & 0x4000 ? 100 : 10, - phy_reg & 0x0200 ? "full" : "half"); - else - printf("bad link!!\n"); -/* -left off: no link, green 100MBit, yellow 10MBit -right off: no activity, green full-duplex, yellow half-duplex -*/ - mii_phy_write(20, 0x0452); - } -} - -unsigned short -mii_phy_read(unsigned short reg) -{ - int i; - unsigned short tmp, val = 0, adr = 0; - t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - - tmp = 0x6002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - regs->bcsr4 |= MII_MDIR; - for (i = 0; i < 16; i++) { - val <<= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK); - if (regs->bcsr4 & MII_MDIO) val |= 1; - regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK); - } - return val; -} - -void -mii_phy_write(unsigned short reg, unsigned short val) -{ - int i; - unsigned short tmp, adr = 0; - t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - - tmp = 0x5002 | (adr << 7) | (reg << 2); - regs->bcsr4 = 0xC3; - for (i = 0; i < 64; i++) { - regs->bcsr4 ^= MII_MDCK; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - tmp <<= 1; - } - for (i = 0; i < 16; i++) { - regs->bcsr4 &= ~MII_MDCK; - if (val & 0x8000) regs->bcsr4 |= MII_MDIO; - else regs->bcsr4 &= ~MII_MDIO; - regs->bcsr4 |= MII_MDCK; - val <<= 1; - } -} diff --git a/board/rpxsuper/readme b/board/rpxsuper/readme deleted file mode 100644 index 21267bdd8c..0000000000 --- a/board/rpxsuper/readme +++ /dev/null @@ -1,30 +0,0 @@ -Hi, - -so this is the port to the Embedded Planet RPX Super Board. - -ATTENTION -This code is only tested on the AY-Version, which is an early release with some -hardware bugs. The main problem is that this board uses the default Hard Reset -Configuration Word and not the 4 bytes located at start of FLASH because at -0xFE000000 is no FLASH. The FLASH consists out of 4 chips each 16bits wide. Be -carefull, the bytes are swapped. So DQ0-7 is the high byte, DQ8-15 ist the low -byte. - -The icache can only manually be enabled after reset. -The FLASH and main SDRAM is working with icache enabled. -The local SDRAM can only be used as data memory when icache is enabled. -If U-Boot runs in local SDRAM, TFTP does not work. -The functions in mii_phy.c are all working. Call mii_phy_discover() out of -eth_init() and solve the linker error. -I2C, RTC/NVRAM and PCMCIA are not working yet. - -TODO -The 32MB local SDRAM is working but not shown in the startup messages of -U-Boot. If you locate U-Boot or any other program to this area it won't run. -Turning the ichache off does not solve this problem. - -As I won't buy another RPX Super there might be some little work to do for you -getting this U-Boot port running on the final board. - - -frank.morauf@salzbrenner.com diff --git a/board/rpxsuper/rpxsuper.c b/board/rpxsuper/rpxsuper.c deleted file mode 100644 index dc558707fa..0000000000 --- a/board/rpxsuper/rpxsuper.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2001 - * Advent Networks, Inc. <http://www.adventnetworks.com> - * Jay Monkman <jtm@smoothsmoothie.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> -#include "rpxsuper.h" - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */ - /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */ - /* PA29 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */ - /* PA28 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */ - /* PA27 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */ - /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */ - /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ - /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 1, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 1, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 1, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */ - /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */ - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ - /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* PD22 */ - /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* PD21 */ - /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* PD20 */ - /* PD19 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Setup CS4 to enable the Board Control/Status registers. - * Otherwise the smcs won't work. -*/ -int board_early_init_f (void) -{ - volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; - regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */ - regs->bcsr2 = 0x20; /* mut be written to enable writing FLASH */ - return 0; -} - -void -reset_phy(void) -{ - volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - regs->bcsr4 = 0xC3; -} - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ - volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; - printf ("Board: Embedded Planet RPX Super, Revision %d\n", - regs->bcsr0 >> 4); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr; - ulong psdmr, lsdmr, bcr; - long size = 0; - int i; - - psdmr = CONFIG_SYS_PSDMR; - lsdmr = CONFIG_SYS_LSDMR; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - size = CONFIG_SYS_SDRAM0_SIZE; - bcr = immap->im_siu_conf.sc_bcr; - immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - ramaddr = (uchar *)(CONFIG_SYS_SDRAM0_BASE); - memctl->memc_psrt = CONFIG_SYS_PSRT; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - immap->im_siu_conf.sc_bcr = bcr; - -#ifndef CONFIG_SYS_RAMBOOT -/* size += CONFIG_SYS_SDRAM1_SIZE; */ - ramaddr = (uchar *)(CONFIG_SYS_SDRAM1_BASE); - memctl->memc_lsrt = CONFIG_SYS_LSRT; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; -#endif - - /* return total ram size */ - return (size * 1024 * 1024); -} diff --git a/board/rpxsuper/rpxsuper.h b/board/rpxsuper/rpxsuper.h deleted file mode 100644 index af31060a7b..0000000000 --- a/board/rpxsuper/rpxsuper.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __RPX8260_H__ -#define __RPX8260_H__ - -typedef struct tt_rpx_regs -{ - volatile unsigned char bcsr0; - volatile unsigned char bcsr1; - volatile unsigned char bcsr2; - volatile unsigned char bcsr3; - volatile unsigned char bcsr4; - volatile unsigned char bcsr5; - volatile unsigned char bcsr6; - volatile unsigned char bcsr7; - volatile unsigned char bcsr8; - volatile unsigned char bcsr9; - volatile unsigned char bcsr10; - volatile unsigned char bcsr11; - volatile unsigned char bcsr12; - volatile unsigned char bcsr13; - volatile unsigned char bcsr14; - volatile unsigned char bcsr15; -} t_rpx_regs; -typedef t_rpx_regs* tp_rpx_regs; - -#endif diff --git a/board/rsdproto/Makefile b/board/rsdproto/Makefile deleted file mode 100644 index 9351e94e74..0000000000 --- a/board/rsdproto/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := rsdproto.o flash.o -obj-y += flash_asm.o diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c deleted file mode 100644 index 37326d587a..0000000000 --- a/board/rsdproto/flash.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * (C) Copyright 2000 - * Marius Groeger <mgroeger@sysgo.de> - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AM290[48]0B devices - * - *-------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> - -/* flash hardware ids */ -#define VENDOR_AMD 0x0001 -#define AMD_29DL323C_B 0x2253 - -/* Define this to include autoselect sequence in flash_init(). Does NOT - * work when executing from flash itself, so this should be turned - * on only when debugging the RAM version. - */ -#undef WITH_AUTOSELECT - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if 1 -#define D(x) -#else -#define D(x) printf x -#endif - -/*----------------------------------------------------------------------- - * Functions - */ - -static unsigned char write_ull(flash_info_t *info, - unsigned long address, - volatile unsigned long long data); - -/* from flash_asm.S */ -extern void ull_write(unsigned long long volatile *address, - unsigned long long volatile *data); -extern void ull_read(unsigned long long volatile *address, - unsigned long long volatile *data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong addr; - -#ifdef WITH_AUTOSELECT - { - unsigned long long *f_addr = (unsigned long long *)PHYS_FLASH; - unsigned long long f_command, vendor, device; - /* Perform Autoselect */ - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x0090009000900090ULL; - ull_write(&f_addr[0x555], &f_command); - ull_read(&f_addr[0], &vendor); - vendor &= 0xffff; - ull_read(&f_addr[1], &device); - device &= 0xffff; - f_command = 0x00F000F000F000F0ULL; - ull_write(&f_addr[0x555], &f_command); - if (vendor != VENDOR_AMD || device != AMD_29DL323C_B) - return 0; - } -#endif - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* 1st bank: 8 x 32 KB sectors */ - flash_info[0].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B; - flash_info[0].sector_count = 8; - flash_info[0].size = flash_info[0].sector_count * 32 * 1024; - addr = PHYS_FLASH; - for(i = 0; i < flash_info[0].sector_count; i++) { - flash_info[0].start[i] = addr; - addr += flash_info[0].size / flash_info[0].sector_count; - } - /* 1st bank: 63 x 256 KB sectors */ - flash_info[1].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B; - flash_info[1].sector_count = 63; - flash_info[1].size = flash_info[1].sector_count * 256 * 1024; - for(i = 0; i < flash_info[1].sector_count; i++) { - flash_info[1].start[i] = addr; - addr += flash_info[1].size / flash_info[1].sector_count; - } - - /* - * protect monitor and environment sectors - */ - -#if CONFIG_SYS_MONITOR_BASE >= PHYS_FLASH - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[1]); -#endif - - return flash_info[0].size + flash_info[1].size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id >> 16) { - case VENDOR_AMD: - printf ("AMD "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case AMD_29DL323C_B: - printf ("AM29DL323CB (32 Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start; - unsigned long long volatile *f_addr; - unsigned long long volatile f_command; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x0080008000800080ULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (l_sect = -1, sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - - f_addr = - (unsigned long long *)(info->start[sect]); - f_command = 0x0030003000300030ULL; - ull_write(f_addr, &f_command); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - do - { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) - { /* write reset command, command address is unimportant */ - /* this command turns the flash back to read mode */ - f_addr = - (unsigned long long *)(info->start[l_sect]); - f_command = 0x00F000F000F000F0ULL; - ull_write(f_addr, &f_command); - printf (" timeout\n"); - return 1; - } - } while(*f_addr != 0xFFFFFFFFFFFFFFFFULL); - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - unsigned long cp, wp; - unsigned long long data; - int i, l, rc; - - wp = (addr & ~7); /* get lower long long aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<8 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<8; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_ull(info, wp, data)) != 0) { - return rc; - } - wp += 4; - } - - /* - * handle long long aligned part - */ - while (cnt >= 8) { - data = 0; - for (i=0; i<8; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_ull(info, wp, data)) != 0) { - return rc; - } - wp += 8; - cnt -= 8; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<8; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return write_ull(info, wp, data); -} - -/*--------------------------------------------------------------------------- -* -* FUNCTION NAME: write_ull -* -* DESCRIPTION: writes 8 bytes to flash -* -* EXTERNAL EFFECT: nothing -* -* PARAMETERS: 32 bit long pointer to address, 64 bit long pointer to data -* -* RETURNS: 0 if OK, 1 if timeout, 4 if parameter error -*--------------------------------------------------------------------------*/ - -static unsigned char write_ull(flash_info_t *info, - unsigned long address, - volatile unsigned long long data) -{ - static unsigned long long f_command; - static unsigned long long *f_addr; - ulong start; - - /* address muss be 8-aligned! */ - if (address & 0x7) - return ERR_ALIGN; - - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00AA00AA00AA00AAULL; - ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; - ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x00A000A000A000A0ULL; - ull_write(&f_addr[0x555], &f_command); - - f_addr = (unsigned long long *)address; - f_command = data; - ull_write(f_addr, &f_command); - - start = get_timer (0); - do - { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - { - /* write reset command, command address is unimportant */ - /* this command turns the flash back to read mode */ - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00F000F000F000F0ULL; - ull_write(f_addr, &f_command); - return ERR_TIMOUT; - } - } while(*((unsigned long long *)address) != data); - - return 0; -} diff --git a/board/rsdproto/flash_asm.S b/board/rsdproto/flash_asm.S deleted file mode 100644 index 557cac0279..0000000000 --- a/board/rsdproto/flash_asm.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * -*- mode:c -*- - * - * (C) Copyright 2000 - * Marius Groeger <mgroeger@sysgo.de> - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * - * void ull_write(unsigned long long volatile *address, - * unsigned long long volatile *data) - * r3 = address - * r4 = data - * - * void ull_read(unsigned long long volatile *address, - * unsigned long long volatile *data) - * r3 = address - * r4 = data - * - * Uses the floating point unit to read and write 64 bit wide - * data (unsigned long long) on the 60x bus. This is necessary - * because all 4 flash chips use the /WE line from byte lane 0 - * - * IMPORTANT: data should always be 8-aligned, otherwise an exception will - * occur. - */ - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - - .globl ull_write -ull_write: - lfd 0,0(r4) - stfd 0,0(r3) - blr - - .globl ull_read -ull_read: - lfd 0, 0(r3) - stfd 0, 0(r4) - blr diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c deleted file mode 100644 index 1e85c2710d..0000000000 --- a/board/rsdproto/rsdproto.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ioports.h> -#include <mpc8260.h> -#include <i2c.h> -#include <bcd.h> - -/* define to initialise the SDRAM on the local bus */ -#undef INIT_LOCAL_BUS_SDRAM - -/* I2C Bus adresses for PPC & Protocol board */ -#define PPC8260_I2C_ADR 0x30 /*(0)011.0000 */ -#define LM84_PPC_I2C_ADR 0x2A /*(0)010.1010 */ -#define LM84_SHARC_I2C_ADR 0x29 /*(0)010.1001 */ -#define VIRTEX_I2C_ADR 0x25 /*(0)010.0101 */ -#define X24645_PPC_I2C_ADR 0x00 /*(0)00X.XXXX -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */ -#define RS5C372_PPC_I2C_ADR 0x32 /*(0)011.0010 -> this adress is programmed by the manufacturer and cannot be changed !!! */ - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 0, 0, 0 }, - /* PA30 */ { 0, 0, 0, 0, 0, 0 }, - /* PA29 */ { 0, 0, 0, 0, 0, 0 }, - /* PA28 */ { 0, 0, 0, 0, 0, 0 }, - /* PA27 */ { 0, 0, 0, 0, 0, 0 }, - /* PA26 */ { 0, 0, 0, 0, 0, 0 }, - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, - /* PA21 */ { 0, 0, 0, 0, 0, 0 }, - /* PA20 */ { 0, 0, 0, 0, 0, 0 }, - /* PA19 */ { 0, 0, 0, 0, 0, 0 }, - /* PA18 */ { 0, 0, 0, 0, 0, 0 }, - /* PA17 */ { 0, 0, 0, 0, 0, 0 }, - /* PA16 */ { 0, 0, 0, 0, 0, 0 }, - /* PA15 */ { 0, 0, 0, 0, 0, 0 }, - /* PA14 */ { 0, 0, 0, 0, 0, 0 }, - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, - /* PA9 */ { 0, 0, 0, 0, 0, 0 }, - /* PA8 */ { 0, 0, 0, 0, 0, 0 }, - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, - /* PA0 */ { 0, 0, 0, 0, 0, 0 } - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, - /* PC25 */ { 0, 0, 0, 0, 0, 0 }, - /* PC24 */ { 0, 0, 0, 0, 0, 0 }, - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* ETHRXCLK: CLK14 */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* ETHTXCLK: CLK15 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, - /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART CD/ */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, - /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDC: GP */ - /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDIO: GP */ - /* PC8 */ { 0, 0, 0, 0, 0, 0 }, - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, - /* PC0 */ { 0, 0, 0, 0, 0, 0 } - }, - - - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, - /* PD22 */ { 0, 0, 0, 0, 0, 0 }, - /* PD21 */ { 0, 0, 0, 0, 0, 0 }, - /* PD20 */ { 0, 0, 0, 0, 0, 0 }, - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - -/* ------------------------------------------------------------------------- */ - -struct tm { - unsigned int tm_sec; - unsigned int tm_min; - unsigned int tm_hour; - unsigned int tm_wday; - unsigned int tm_mday; - unsigned int tm_mon; - unsigned int tm_year; -}; - -void read_RS5C372_time (struct tm *timedate) -{ - unsigned char buffer[8]; - - if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) { - timedate->tm_sec = bcd2bin (buffer[0]); - timedate->tm_min = bcd2bin (buffer[1]); - timedate->tm_hour = bcd2bin (buffer[2]); - timedate->tm_wday = bcd2bin (buffer[3]); - timedate->tm_mday = bcd2bin (buffer[4]); - timedate->tm_mon = bcd2bin (buffer[5]); - timedate->tm_year = bcd2bin (buffer[6]) + 2000; - } else { - /*printf("i2c error %02x\n", rc); */ - memset (timedate, 0, sizeof (struct tm)); - } -} - -/* ------------------------------------------------------------------------- */ - -int read_LM84_temp (int address) -{ - unsigned char buffer[8]; - /*int rc;*/ - - if (! i2c_read (address, 0, 1, buffer, 1)) { - return (int) buffer[0]; - } else { - /*printf("i2c error %02x\n", rc); */ - return -42; - } -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - struct tm timedate; - unsigned int ppctemp, prottemp; - - puts ("Board: Rohde & Schwarz 8260 Protocol Board\n"); - - /* initialise i2c */ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - read_RS5C372_time (&timedate); - printf (" Time: %02d:%02d:%02d\n", - timedate.tm_hour, timedate.tm_min, timedate.tm_sec); - printf (" Date: %02d-%02d-%04d\n", - timedate.tm_mday, timedate.tm_mon, timedate.tm_year); - ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR); - prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR); - printf (" Temp: PPC %d C, Protocol Board %d C\n", - ppctemp, prottemp); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations while still - * running in flash - */ - -int misc_init_f (void) -{ - return 0; -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - -#ifdef INIT_LOCAL_BUS_SDRAM - volatile uchar *ramaddr8; -#endif - volatile ulong *ramaddr32; - ulong sdmr; - int i; - - /* - * Only initialize SDRAM when running from FLASH. - * When running from RAM, don't touch it. - */ - if ((ulong) initdram & 0xff000000) { - immap->im_siu_conf.sc_ppc_acr = 0x02; - immap->im_siu_conf.sc_ppc_alrh = 0x01267893; - immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; - immap->im_siu_conf.sc_lcl_acr = 0x02; - immap->im_siu_conf.sc_lcl_alrh = 0x01234567; - immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; - /* - * Program local/60x bus Transfer Error Status and Control Regs: - * Disable parity errors - */ - immap->im_siu_conf.sc_tescr1 = 0x00040000; - immap->im_siu_conf.sc_ltescr1 = 0x00040000; - - /* - * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2) - * - * The appropriate BRx/ORx registers have already - * been set when we get here (see cpu_init_f). The - * SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - memctl->memc_mptpr = 0x2000; - memctl->memc_mar = 0x0200; -#ifdef INIT_LOCAL_BUS_SDRAM - /* initialise local bus ram - * - * (using the PSRMR_ definitions is NOT an error here - * - the LSDMR has the same fields as the PSDMR!) - */ - memctl->memc_lsrt = 0x0b; - memctl->memc_lurt = 0x00; - ramaddr = (uchar *) PHYS_SDRAM_LOCAL; - sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); - memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA; - *ramaddr = 0xff; - for (i = 0; i < 8; i++) { - memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR; - *ramaddr = 0xff; - } - memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW; - *ramaddr = 0xff; - memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM; -#endif - /* initialise 60x bus ram */ - memctl->memc_psrt = 0x0b; - memctl->memc_purt = 0x08; - ramaddr32 = (ulong *) PHYS_SDRAM_60X; - sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); - memctl->memc_psdmr = sdmr | PSDMR_OP_PREA; - ramaddr32[0] = 0x00ff00ff; - ramaddr32[1] = 0x00ff00ff; - memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) { - ramaddr32[0] = 0x00ff00ff; - ramaddr32[1] = 0x00ff00ff; - } - memctl->memc_psdmr = sdmr | PSDMR_OP_MRW; - ramaddr32[0] = 0x00ff00ff; - ramaddr32[1] = 0x00ff00ff; - memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - } - - /* return the size of the 60x bus ram */ - return PHYS_SDRAM_60X_SIZE; -} - -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations after monitor - * has been relocated into ram - */ - -int misc_init_r (void) -{ - printf ("misc_init_r\n"); - return (0); -} diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds deleted file mode 100644 index 44bcd19fb1..0000000000 --- a/board/rsdproto/u-boot.lds +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc8260/start.o (.text) - *(.text) - *(.got1) - /*. = env_offset; */ - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/samsung/common/ums.c b/board/samsung/common/ums.c index dc155ad0e5..cebabe920a 100644 --- a/board/samsung/common/ums.c +++ b/board/samsung/common/ums.c @@ -66,11 +66,9 @@ static struct ums *ums_disk_init(struct mmc *mmc) struct ums *ums_init(unsigned int dev_num) { - struct mmc *mmc = NULL; + struct mmc *mmc = find_mmc_device(dev_num); - mmc = find_mmc_device(dev_num); - if (!mmc) + if (!mmc || mmc_init(mmc)) return NULL; - return ums_disk_init(mmc); } diff --git a/board/samsung/goni/mem_setup.S b/board/samsung/goni/mem_setup.S deleted file mode 100644 index 5dc980cf5b..0000000000 --- a/board/samsung/goni/mem_setup.S +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electrnoics - * Minkyu Kang <mk7.kang@samsung.com> - * Kyungmin Park <kyungmin.park@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> - - .globl mem_ctrl_asm_init -mem_ctrl_asm_init: - cmp r7, r8 - - ldreq r0, =S5PC100_DMC_BASE @ 0xE6000000 - ldrne r0, =S5PC110_DMC0_BASE @ 0xF0000000 - ldrne r6, =S5PC110_DMC1_BASE @ 0xF1400000 - - /* DLL parameter setting */ - ldr r1, =0x50101000 - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET - ldr r1, =0x000000f4 - str r1, [r0, #0x01C] @ PHYCONTROL1_OFFSET - strne r1, [r6, #0x01C] @ PHYCONTROL1_OFFSET - ldreq r1, =0x0 - streq r1, [r0, #0x020] @ PHYCONTROL2_OFFSET - - /* DLL on */ - ldr r1, =0x50101002 - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET - - /* DLL start */ - ldr r1, =0x50101003 - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET - - mov r2, #0x4000 -wait: subs r2, r2, #0x1 - cmp r2, #0x0 - bne wait - - cmp r7, r8 - /* Force value locking for DLL off */ - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET - - /* DLL off */ - ldr r1, =0x50101009 - str r1, [r0, #0x018] @ PHYCONTROL0_OFFSET - strne r1, [r6, #0x018] @ PHYCONTROL0_OFFSET - - /* auto refresh off */ - ldr r1, =0xff001010 | (1 << 7) - ldr r2, =0xff001010 | (1 << 7) - str r1, [r0, #0x000] @ CONCONTROL_OFFSET - strne r2, [r6, #0x000] @ CONCONTROL_OFFSET - - /* - * Burst Length 4, 2 chips, 32-bit, LPDDR - * OFF: dynamic self refresh, force precharge, dynamic power down off - */ - ldr r1, =0x00212100 - ldr r2, =0x00212100 - str r1, [r0, #0x004] @ MEMCONTROL_OFFSET - strne r2, [r6, #0x004] @ MEMCONTROL_OFFSET - - /* - * Note: - * If Bank0 has Mobile RAM we place it at 0x3800'0000 (s5pc100 only) - * So finally Bank1 OneDRAM should address start at at 0x3000'0000 - */ - - /* - * DMC0: CS0 : S5PC100/S5PC110 - * 0x30 -> 0x30000000 - * 0xf8 -> 0x37FFFFFF - * [15:12] 0: Linear - * [11:8 ] 2: 9 bits - * [ 7:4 ] 2: 14 bits - * [ 3:0 ] 2: 4 banks - */ - ldr r3, =0x30f80222 - ldr r4, =0x40f00222 -swap_memory: - str r3, [r0, #0x008] @ MEMCONFIG0_OFFSET - str r4, [r0, #0x00C] @ dummy write - - /* - * DMC1: CS0 : S5PC110 - * 0x40 -> 0x40000000 - * 0xf8 -> 0x47FFFFFF (1Gib) - * 0x40 -> 0x40000000 - * 0xf0 -> 0x4FFFFFFF (2Gib) - * [15:12] 0: Linear - * [11:8 ] 2: 9 bits - Col (1Gib) - * [11:8 ] 3: 10 bits - Col (2Gib) - * [ 7:4 ] 2: 14 bits - Row - * [ 3:0 ] 2: 4 banks - */ - /* Default : 2GiB */ - ldr r4, =0x40f01322 @ 2Gib: MCP B - ldr r5, =0x50f81312 @ dummy: MCP D - cmp r9, #1 - ldreq r4, =0x40f81222 @ 1Gib: MCP A - cmp r9, #3 - ldreq r5, =0x50f81312 @ 2Gib + 1Gib: MCP D - cmp r9, #4 - ldreq r5, =0x50f01312 @ 2Gib + 2Gib: MCP E - - cmp r7, r8 - strne r4, [r6, #0x008] @ MEMCONFIG0_OFFSET - strne r5, [r6, #0x00C] @ MEMCONFIG1_OFFSET - - /* - * DMC0: CS1: S5PC100 - * 0x38 -> 0x38000000 - * 0xf8 -> 0x3fFFFFFF - * [15:12] 0: Linear - * [11:8 ] 2: 9 bits - * [ 7:4 ] 2: 14 bits - * [ 3:0 ] 2: 4 banks - */ - eoreq r3, r3, #0x08000000 - streq r3, [r0, #0xc] @ MEMCONFIG1_OFFSET - - ldr r1, =0x20000000 - str r1, [r0, #0x014] @ PRECHCONFIG_OFFSET - strne r1, [r0, #0x014] @ PRECHCONFIG_OFFSET - strne r1, [r6, #0x014] @ PRECHCONFIG_OFFSET - - /* - * S5PC100: - * DMC: CS0: 166MHz - * CS1: 166MHz - * S5PC110: - * DMC0: CS0: 166MHz - * DMC1: CS0: 200MHz - * - * 7.8us * 200MHz %LE %LONG1560(0x618) - * 7.8us * 166MHz %LE %LONG1294(0x50E) - * 7.8us * 133MHz %LE %LONG1038(0x40E), - * 7.8us * 100MHz %LE %LONG780(0x30C), - */ - ldr r1, =0x0000050E - str r1, [r0, #0x030] @ TIMINGAREF_OFFSET - ldrne r1, =0x00000618 - strne r1, [r6, #0x030] @ TIMINGAREF_OFFSET - - ldr r1, =0x14233287 - str r1, [r0, #0x034] @ TIMINGROW_OFFSET - ldrne r1, =0x182332c8 - strne r1, [r6, #0x034] @ TIMINGROW_OFFSET - - ldr r1, =0x12130005 - str r1, [r0, #0x038] @ TIMINGDATA_OFFSET - ldrne r1, =0x13130005 - strne r1, [r6, #0x038] @ TIMINGDATA_OFFSET - - ldr r1, =0x0E140222 - str r1, [r0, #0x03C] @ TIMINGPOWER_OFFSET - ldrne r1, =0x0E180222 - strne r1, [r6, #0x03C] @ TIMINGPOWER_OFFSET - - /* chip0 Deselect */ - ldr r1, =0x07000000 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip0 PALL */ - ldr r1, =0x01000000 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip0 REFA */ - ldr r1, =0x05000000 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - /* chip0 REFA */ - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip0 MRS */ - ldr r1, =0x00000032 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip0 EMRS */ - ldr r1, =0x00020020 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip1 Deselect */ - ldr r1, =0x07100000 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip1 PALL */ - ldr r1, =0x01100000 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip1 REFA */ - ldr r1, =0x05100000 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - /* chip1 REFA */ - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip1 MRS */ - ldr r1, =0x00100032 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* chip1 EMRS */ - ldr r1, =0x00120020 - str r1, [r0, #0x010] @ DIRECTCMD_OFFSET - strne r1, [r6, #0x010] @ DIRECTCMD_OFFSET - - /* auto refresh on */ - ldr r1, =0xFF002030 | (1 << 7) - str r1, [r0, #0x000] @ CONCONTROL_OFFSET - strne r1, [r6, #0x000] @ CONCONTROL_OFFSET - - /* PwrdnConfig */ - ldr r1, =0x00100002 - str r1, [r0, #0x028] @ PWRDNCONFIG_OFFSET - strne r1, [r6, #0x028] @ PWRDNCONFIG_OFFSET - - ldr r1, =0x00212113 - str r1, [r0, #0x004] @ MEMCONTROL_OFFSET - strne r1, [r6, #0x004] @ MEMCONTROL_OFFSET - - /* Skip when S5PC110 */ - bne 1f - - /* Check OneDRAM access area at s5pc100 */ - ldreq r3, =0x38f80222 - ldreq r1, =0x37ffff00 - str r3, [r1] - ldr r2, [r1] - cmp r2, r3 - beq swap_memory -1: - mov pc, lr - - .ltorg diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c index d502f02d3d..a539267a1c 100644 --- a/board/samsung/origen/origen.c +++ b/board/samsung/origen/origen.c @@ -30,13 +30,6 @@ int board_usb_init(int index, enum usb_init_type init) return 0; } -#ifdef CONFIG_USB_CABLE_CHECK -int usb_cable_connected(void) -{ - return 0; -} -#endif - #ifdef CONFIG_BOARD_EARLY_INIT_F int exynos_early_init_f(void) { diff --git a/board/samsung/smdkc100/mem_setup.S b/board/samsung/smdkc100/mem_setup.S deleted file mode 100644 index 2f2df0b7eb..0000000000 --- a/board/samsung/smdkc100/mem_setup.S +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx - * - * Copyright (C) 2009 Samsung Electrnoics - * Inki Dae <inki.dae@samsung.com> - * Heungjun Kim <riverful.kim@samsung.com> - * Minkyu Kang <mk7.kang@samsung.com> - * Kyungmin Park <kyungmin.park@samsung.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> - - .globl mem_ctrl_asm_init -mem_ctrl_asm_init: - ldr r6, =S5PC100_DMC_BASE @ 0xE6000000 - - /* DLL parameter setting */ - ldr r1, =0x50101000 - str r1, [r6, #0x018] @ PHYCONTROL0 - ldr r1, =0xf4 - str r1, [r6, #0x01C] @ PHYCONTROL1 - ldr r1, =0x0 - str r1, [r6, #0x020] @ PHYCONTROL2 - - /* DLL on */ - ldr r1, =0x50101002 - str r1, [r6, #0x018] @ PHYCONTROL0 - - /* DLL start */ - ldr r1, =0x50101003 - str r1, [r6, #0x018] @ PHYCONTROL0 - - /* Force value locking for DLL off */ - str r1, [r6, #0x018] @ PHYCONTROL0 - - /* DLL off */ - ldr r1, =0x50101001 - str r1, [r6, #0x018] @ PHYCONTROL0 - - /* auto refresh off */ - ldr r1, =0xff001010 - str r1, [r6, #0x000] @ CONCONTROL - - /* - * Burst Length 4, 2 chips, 32-bit, LPDDR - * OFF: dynamic self refresh, force precharge, dynamic power down off - */ - ldr r1, =0x00212100 - str r1, [r6, #0x004] @ MEMCONTROL - - /* - * Note: - * If Bank0 has OneDRAM we place it at 0x2800'0000 - * So finally Bank1 should address start at at 0x2000'0000 - */ - mov r4, #0x0 - -swap_memory: - /* - * Bank0 - * 0x30 -> 0x30000000 - * 0xf8 -> 0x37FFFFFF - * [15:12] 0: Linear - * [11:8 ] 2: 9 bits - * [ 7:4 ] 2: 14 bits - * [ 3:0 ] 2: 4 banks - */ - ldr r1, =0x30f80222 - /* if r4 is 1, swap the bank */ - cmp r4, #0x1 - orreq r1, r1, #0x08000000 - str r1, [r6, #0x008] @ MEMCONFIG0 - - /* - * Bank1 - * 0x38 -> 0x38000000 - * 0xf8 -> 0x3fFFFFFF - * [15:12] 0: Linear - * [11:8 ] 2: 9 bits - * [ 7:4 ] 2: 14 bits - * [ 3:0 ] 2: 4 banks - */ - ldr r1, =0x38f80222 - /* if r4 is 1, swap the bank */ - cmp r4, #0x1 - biceq r1, r1, #0x08000000 - str r1, [r6, #0x00c] @ MEMCONFIG1 - - ldr r1, =0x20000000 - str r1, [r6, #0x014] @ PRECHCONFIG - - /* - * FIXME: Please verify these values - * 7.8us * 166MHz %LE %LONG1294(0x50E) - * 7.8us * 133MHz %LE %LONG1038(0x40E), - * 7.8us * 100MHz %LE %LONG780(0x30C), - * 7.8us * 20MHz %LE %LONG156(0x9C), - * 7.8us * 10MHz %LE %LONG78(0x4E) - */ - ldr r1, =0x0000050e - str r1, [r6, #0x030] @ TIMINGAREF - - /* 166 MHz */ - ldr r1, =0x0c233287 - str r1, [r6, #0x034] @ TIMINGROW - - /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */ - ldr r1, =0x32330303 - str r1, [r6, #0x038] @ TIMINGDATA - - /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */ - ldr r1, =0x04141433 - str r1, [r6, #0x03C] @ TIMINGPOWER - - /* chip0 Deselect */ - ldr r1, =0x07000000 - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip0 PALL */ - ldr r1, =0x01000000 - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip0 REFA */ - ldr r1, =0x05000000 - str r1, [r6, #0x010] @ DIRECTCMD - /* chip0 REFA */ - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */ - ldr r1, =0x00000032 - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip1 Deselect */ - ldr r1, =0x07100000 - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip1 PALL */ - ldr r1, =0x01100000 - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip1 REFA */ - ldr r1, =0x05100000 - str r1, [r6, #0x010] @ DIRECTCMD - /* chip1 REFA */ - str r1, [r6, #0x010] @ DIRECTCMD - - /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */ - ldr r1, =0x00100032 - str r1, [r6, #0x010] @ DIRECTCMD - - /* auto refresh on */ - ldr r1, =0xff002030 - str r1, [r6, #0x000] @ CONCONTROL - - /* PwrdnConfig */ - ldr r1, =0x00100002 - str r1, [r6, #0x028] @ PWRDNCONFIG - - /* BL%LE %LONG */ - ldr r1, =0xff212100 - str r1, [r6, #0x004] @ MEMCONTROL - - - /* Try to test memory area */ - cmp r4, #0x1 - beq 1f - - mov r4, #0x1 - ldr r1, =0x37ffff00 - str r4, [r1] - str r4, [r1, #0x4] @ dummy write - ldr r0, [r1] - cmp r0, r4 - bne swap_memory - -1: - mov pc, lr - - .ltorg diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 7c79e7b73a..ab0ad1d650 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -430,8 +430,7 @@ int board_usb_init(int index, enum usb_init_type init) return s3c_udc_probe(&s5pc210_otg_data); } -#ifdef CONFIG_USB_CABLE_CHECK -int usb_cable_connected(void) +int g_dnl_board_usb_cable_connected(void) { struct pmic *muic = pmic_get("MAX8997_MUIC"); if (!muic) @@ -440,7 +439,6 @@ int usb_cable_connected(void) return !!muic->chrg->chrg_type(muic); } #endif -#endif static void pmic_reset(void) { diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index f558ef97a9..47095252a7 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -312,8 +312,7 @@ int board_usb_init(int index, enum usb_init_type init) return s3c_udc_probe(&s5pc210_otg_data); } -#ifdef CONFIG_USB_CABLE_CHECK -int usb_cable_connected(void) +int g_dnl_board_usb_cable_connected(void) { struct pmic *muic = pmic_get("MAX77693_MUIC"); if (!muic) @@ -322,7 +321,6 @@ int usb_cable_connected(void) return !!muic->chrg->chrg_type(muic); } #endif -#endif static int pmic_init_max77686(void) { diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index f9d71b617d..8e49195fe1 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -197,13 +197,6 @@ int board_usb_init(int index, enum usb_init_type init) return s3c_udc_probe(&s5pc210_otg_data); } -#ifdef CONFIG_USB_CABLE_CHECK -int usb_cable_connected(void) -{ - return 0; -} -#endif - int exynos_early_init_f(void) { wdt_stop(); diff --git a/board/sandpoint/early_init.S b/board/sandpoint/early_init.S deleted file mode 100644 index 5a9b924ef9..0000000000 --- a/board/sandpoint/early_init.S +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2001 - * Thomas Koeller, tkoeller@gmx.net - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASSEMBLY__ -#define __ASSEMBLY__ 1 -#endif - -#include <asm-offsets.h> -#include <config.h> -#include <asm/processor.h> -#include <mpc824x.h> -#include <ppc_asm.tmpl> - -#if defined(USE_DINK32) - /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ - #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) -#else - #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) -#endif - - .text - - /* Values to program into memory controller registers */ -tbl: .long MCCR1, MCCR1VAL - .long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT - .long MCCR3 - .long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ - (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \ - (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT) - .long MCCR4 - .long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ - (CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \ - (((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ - ((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \ - (CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ - (CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ - ((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) - .long MSAR1 - .long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR1 - .long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MSAR2 - .long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMSAR2 - .long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR1 - .long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR1 - .long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long MEAR2 - .long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) - .long EMEAR2 - .long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) - .long 0 - - - /* - * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This - * must be done in assembly, since we have no stack at this point. - */ - .global early_init_f -early_init_f: - mflr r10 - - /* basic memory controller configuration */ - lis r3, CONFIG_ADDR_HIGH - lis r4, CONFIG_DATA_HIGH - bl lab -lab: mflr r5 - lwzu r0, tbl - lab(r5) -loop: lwz r1, 4(r5) - stwbrx r0, 0, r3 - eieio - stwbrx r1, 0, r4 - eieio - lwzu r0, 8(r5) - cmpli cr0, 0, r0, 0 - bne cr0, loop - - /* set bank enable bits */ - lis r0, MBER@h - ori r0, 0, MBER@l - li r1, CONFIG_SYS_BANK_ENABLE - stwbrx r0, 0, r3 - eieio - stb r1, 0(r4) - eieio - - /* delay loop */ - lis r0, 0x0003 - mtctr r0 -delay: bdnz delay - - /* enable memory controller */ - lis r0, MCCR1@h - ori r0, 0, MCCR1@l - stwbrx r0, 0, r3 - eieio - lwbrx r0, 0, r4 - oris r0, 0, MCCR1_MEMGO@h - stwbrx r0, 0, r4 - eieio - - /* set up stack pointer */ - lis r1, CONFIG_SYS_INIT_SP_OFFSET@h - ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l - - mtlr r10 - blr |