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-rw-r--r--board/AndesTech/ax25-ae350/MAINTAINERS2
-rw-r--r--board/AndesTech/ax25-ae350/ax25-ae350.c4
-rw-r--r--board/emulation/qemu-riscv/Kconfig3
-rw-r--r--board/google/Kconfig8
-rw-r--r--board/google/chromebook_samus/Kconfig14
-rw-r--r--board/google/chromebook_samus/MAINTAINERS7
-rw-r--r--board/mikrotik/crs305-1g-4s/.gitignore1
-rw-r--r--board/mikrotik/crs305-1g-4s/MAINTAINERS7
-rw-r--r--board/mikrotik/crs305-1g-4s/Makefile14
-rw-r--r--board/mikrotik/crs305-1g-4s/README23
-rw-r--r--board/mikrotik/crs305-1g-4s/binary.011
-rw-r--r--board/mikrotik/crs305-1g-4s/crs305-1g-4s.c75
-rw-r--r--board/mikrotik/crs305-1g-4s/kwbimage.cfg.in12
-rw-r--r--board/sunxi/MAINTAINERS12
-rw-r--r--board/ti/ks2_evm/mux-k2g.h36
15 files changed, 204 insertions, 25 deletions
diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS b/board/AndesTech/ax25-ae350/MAINTAINERS
index b0a99e4ac4..feed5d1298 100644
--- a/board/AndesTech/ax25-ae350/MAINTAINERS
+++ b/board/AndesTech/ax25-ae350/MAINTAINERS
@@ -5,3 +5,5 @@ F: board/AndesTech/ax25-ae350/
F: include/configs/ax25-ae350.h
F: configs/ae350_rv32_defconfig
F: configs/ae350_rv64_defconfig
+F: configs/ae350_rv32_xip_defconfig
+F: configs/ae350_rv64_xip_defconfig
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
index d343453f22..3d65ce7b75 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -67,10 +67,6 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
void *board_fdt_blob_setup(void)
{
- void **ptr = (void *)&prior_stage_fdt_address;
- if (fdt_magic(*ptr) == FDT_MAGIC)
- return (void *)*ptr;
-
return (void *)CONFIG_SYS_FDT_BASE;
}
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index cf057e7de6..20ea6dc59b 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -14,7 +14,8 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0x80000000 if !RISCV_SMODE
- default 0x80200000 if RISCV_SMODE
+ default 0x80200000 if RISCV_SMODE && ARCH_RV64I
+ default 0x80400000 if RISCV_SMODE && ARCH_RV32I
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
diff --git a/board/google/Kconfig b/board/google/Kconfig
index d98a5e818f..679a0f1023 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -52,6 +52,14 @@ config TARGET_CHROMEBOOK_SAMUS
Chrome OS EC connected on LPC, and it provides a 2560x1700 high
resolution touch-enabled LCD display.
+config TARGET_CHROMEBOOK_SAMUS_TPL
+ bool "Chromebook samus booting from TPL"
+ help
+ This is a version of Samus which boots into TPL, then to SPL and
+ U-Boot proper. This is useful where verified boot must select
+ between different A/B versions of SPL/U-Boot, to allow upgrading of
+ almost all U-Boot code in the field.
+
endchoice
source "board/google/chromebook_link/Kconfig"
diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig
index afbfe53deb..90c23cba1b 100644
--- a/board/google/chromebook_samus/Kconfig
+++ b/board/google/chromebook_samus/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_CHROMEBOOK_SAMUS
+if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL
config SYS_BOARD
default "chromebook_samus"
@@ -10,7 +10,8 @@ config SYS_SOC
default "broadwell"
config SYS_CONFIG_NAME
- default "chromebook_samus"
+ default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS
+ default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL
config SYS_TEXT_BASE
default 0xffe00000
@@ -39,3 +40,12 @@ config SYS_CAR_SIZE
default 0x40000
endif
+
+if TARGET_CHROMEBOOK_SAMUS_TPL
+
+config BOARD_SPECIFIC_OPTIONS_TPL # dummy
+ def_bool y
+ select SPL
+ select TPL
+
+endif
diff --git a/board/google/chromebook_samus/MAINTAINERS b/board/google/chromebook_samus/MAINTAINERS
index 5500e46b40..ca4b16500a 100644
--- a/board/google/chromebook_samus/MAINTAINERS
+++ b/board/google/chromebook_samus/MAINTAINERS
@@ -4,3 +4,10 @@ S: Maintained
F: board/google/chromebook_samus/
F: include/configs/chromebook_samus.h
F: configs/chromebook_samus_defconfig
+
+CHROMEBOOK SAMUS TPL BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/chromebook_samus/
+F: include/configs/chromebook_samus.h
+F: configs/chromebook_samus_tpl_defconfig
diff --git a/board/mikrotik/crs305-1g-4s/.gitignore b/board/mikrotik/crs305-1g-4s/.gitignore
new file mode 100644
index 0000000000..775b9346b8
--- /dev/null
+++ b/board/mikrotik/crs305-1g-4s/.gitignore
@@ -0,0 +1 @@
+kwbimage.cfg
diff --git a/board/mikrotik/crs305-1g-4s/MAINTAINERS b/board/mikrotik/crs305-1g-4s/MAINTAINERS
new file mode 100644
index 0000000000..3823489600
--- /dev/null
+++ b/board/mikrotik/crs305-1g-4s/MAINTAINERS
@@ -0,0 +1,7 @@
+CRS305-1G-4S BOARD
+M: Luka Kovacic <me@lukakovacic.xyz>
+S: Maintained
+F: board/mikrotik/crs305-1g-4s/
+F: include/configs/crs305-1g-4s.h
+F: configs/crs305-1g-4s_defconfig
+F: arch/arm/dts/armada-xp-crs305-1g-4s.dts
diff --git a/board/mikrotik/crs305-1g-4s/Makefile b/board/mikrotik/crs305-1g-4s/Makefile
new file mode 100644
index 0000000000..895331beb8
--- /dev/null
+++ b/board/mikrotik/crs305-1g-4s/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+
+obj-y := crs305-1g-4s.o
+extra-y := kwbimage.cfg
+
+quiet_cmd_sed = SED $@
+ cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F)
+
+SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|"
+$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
+ include/config/auto.conf
+ $(call if_changed,sed)
diff --git a/board/mikrotik/crs305-1g-4s/README b/board/mikrotik/crs305-1g-4s/README
new file mode 100644
index 0000000000..f420aabfbf
--- /dev/null
+++ b/board/mikrotik/crs305-1g-4s/README
@@ -0,0 +1,23 @@
+MikroTik CRS305-1G-4S+IN
+========================
+
+CRS305-1G-4S+IN is a 4x SFP+ switch with a Gigabit Ethernet port for management.
+Specifications:
+ - Marvell Prestera 98DX3236 switch with an integrated ARMv7 CPU
+ - 512 MB DDR3 RAM
+ - UART @ 115200bps
+ - 4x SFP+
+ - Gigabit Ethernet (AR8033)
+ - 16 MB SPI flash (Winbond 25Q128JVSM)
+
+Currently supported hardware:
+ - UART boot (using kwboot) and console
+ - SPI boot, environment and load kernel
+
+Planned:
+ - Gigabit Ethernet support
+
+Getting binary.0
+================
+binary.0 (DDR3 init phase) can be retrieved/extracted from the integrated bootloader on the SPI flash.
+Then binary.0 can be replaced with the extracted blob.
diff --git a/board/mikrotik/crs305-1g-4s/binary.0 b/board/mikrotik/crs305-1g-4s/binary.0
new file mode 100644
index 0000000000..8dd687286a
--- /dev/null
+++ b/board/mikrotik/crs305-1g-4s/binary.0
@@ -0,0 +1,11 @@
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
diff --git a/board/mikrotik/crs305-1g-4s/crs305-1g-4s.c b/board/mikrotik/crs305-1g-4s/crs305-1g-4s.c
new file mode 100644
index 0000000000..d1d1f40092
--- /dev/null
+++ b/board/mikrotik/crs305-1g-4s/crs305-1g-4s.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * These values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2016_T1.0.eng_drop_v6"
+ */
+#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) \
+ | BIT(6) | BIT(12) | BIT(13) \
+ | BIT(16) | BIT(17) | BIT(20) \
+ | BIT(29) | BIT(30)))
+#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0))
+#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) \
+ | BIT(6) | BIT(12) | BIT(13) \
+ | BIT(16) | BIT(17) | BIT(20) \
+ | BIT(29) | BIT(30))
+#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0
+#define DB_DX_AC3_GPP_POL_LOW 0x0
+#define DB_DX_AC3_GPP_POL_MID 0x0
+
+int board_early_init_f(void)
+{
+ /* Configure MPP */
+ writel(0x00142222, MVEBU_MPP_BASE + 0x00);
+ writel(0x11122000, MVEBU_MPP_BASE + 0x04);
+ writel(0x44444004, MVEBU_MPP_BASE + 0x08);
+ writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
+ writel(0x00000001, MVEBU_MPP_BASE + 0x10);
+
+ /*
+ * MVEBU_GPIO0_BASE is the User LED
+ * MVEBU_GPIO1_BASE is the Reset Button (currently not used)
+ */
+
+ /* Set GPP Out value */
+ writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ /* writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); */
+
+ /* Set GPP Polarity */
+ writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+ /* writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); */
+
+ /* Set GPP Out Enable */
+ writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ /* writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); */
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: " CONFIG_SYS_BOARD "\n");
+
+ return 0;
+}
diff --git a/board/mikrotik/crs305-1g-4s/kwbimage.cfg.in b/board/mikrotik/crs305-1g-4s/kwbimage.cfg.in
new file mode 100644
index 0000000000..2dbbbd0246
--- /dev/null
+++ b/board/mikrotik/crs305-1g-4s/kwbimage.cfg.in
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/mikrotik/crs305-1g-4s/binary.0 0000005b 00000068
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 338f374e56..bdd1854197 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -166,6 +166,12 @@ M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/bananapi_m64_defconfig
+BEELINK GS1
+M: Clément Péron <peron.clem@gmail.com>
+S: Maintained
+F: configs/beelink_gs1_defconfig
+F: arch/arm/dts/sun50i-h6-beelink-gs1.dts
+
COLOMBUS BOARD
M: Maxime Ripard <maxime.ripard@bootlin.com>
S: Maintained
@@ -352,6 +358,12 @@ S: Maintained
F: configs/A20-Olimex-SOM204-EVB_defconfig
F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+OLIMEX TERES-I BOARD
+M: Jonas Smedegaard <dr@jones.dk>
+M: Icenowy Zheng <icenowy@aosc.io>
+S: Maintained
+F: configs/teres_i_defconfig
+
ORANGEPI LITE2 BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h
index 89c49f9e4f..6aa785ea42 100644
--- a/board/ti/ks2_evm/mux-k2g.h
+++ b/board/ti/ks2_evm/mux-k2g.h
@@ -126,22 +126,22 @@ struct pin_cfg k2g_evm_pin_cfg[] = {
{ 71, MODE(0) }, /* MMC1POW TP124 */
/* EMAC */
- { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
- { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
+ { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
{ 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */
+ { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
+ { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
{ 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */
- { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
- { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
- { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
- { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
+ { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
{ 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */
+ { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
+ { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
+ { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
+ { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
{ 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */
- { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
- { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
/* MDIO */
- { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
{ 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */
+ { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
/* PWM */
{ 73, MODE(4) }, /* SOC_EHRPWM3A */
@@ -350,22 +350,22 @@ struct pin_cfg k2g_ice_evm_pin_cfg[] = {
{ 135, MODE(0) }, /* SOC_QSPI_CSN0 */
/* EMAC */
- { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
- { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
+ { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
{ 77, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD3 */
+ { 78, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD2 */
+ { 79, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD1 */
{ 80, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXD0 */
- { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
- { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
- { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
- { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
+ { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
{ 85, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXC */
+ { 91, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD3 */
+ { 92, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD2 */
+ { 93, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD1 */
+ { 94, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXD0 */
{ 95, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_TXCTL */
- { 72, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXC */
- { 81, BUFFER_CLASS_D | PIN_PDIS | MODE(1) }, /* RGMII_RXCTL */
/* MDIO */
- { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
{ 98, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_DATA */
+ { 99, BUFFER_CLASS_B | PIN_PDIS | MODE(0) }, /* MDIO_CLK */
{ MAX_PIN_N, }
};
generated by cgit (git 2.34.1) at 2025-02-25 05:30:05 +0000