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-rw-r--r--cpu/ppc4xx/405gp_enet.c1062
-rw-r--r--cpu/ppc4xx/405gp_pci.c73
-rw-r--r--cpu/ppc4xx/4xx_enet.c (renamed from cpu/ppc4xx/440gx_enet.c)603
-rw-r--r--cpu/ppc4xx/Makefile4
-rw-r--r--cpu/ppc4xx/bedbug_405.c2
-rw-r--r--cpu/ppc4xx/cpu.c291
-rw-r--r--cpu/ppc4xx/cpu_init.c2
-rw-r--r--cpu/ppc4xx/i2c.c2
-rw-r--r--cpu/ppc4xx/miiphy.c215
-rw-r--r--cpu/ppc4xx/miiphy_440.c259
-rw-r--r--cpu/ppc4xx/sdram.c70
-rw-r--r--cpu/ppc4xx/serial.c17
-rw-r--r--cpu/ppc4xx/spd_sdram.c505
-rw-r--r--cpu/ppc4xx/speed.c9
-rw-r--r--cpu/ppc4xx/start.S24
-rw-r--r--cpu/ppc4xx/vecnum.h30
16 files changed, 1166 insertions, 2002 deletions
diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c
deleted file mode 100644
index 968f0ced44..0000000000
--- a/cpu/ppc4xx/405gp_enet.c
+++ /dev/null
@@ -1,1062 +0,0 @@
-/*-----------------------------------------------------------------------------+
- *
- * This source code has been made available to you by IBM on an AS-IS
- * basis. Anyone receiving this source is licensed under IBM
- * copyrights to use it in any way he or she deems fit, including
- * copying it, modifying it, compiling it, and redistributing it either
- * with or without modifications. No license under IBM patents or
- * patent applications is to be implied by the copyright license.
- *
- * Any user of this software should understand that IBM cannot provide
- * technical support for this software and will not be responsible for
- * any consequences resulting from the use of this software.
- *
- * Any person who transfers this source code or any derivative work
- * must include the IBM copyright notice, this paragraph, and the
- * preceding two paragraphs in the transferred software.
- *
- * COPYRIGHT I B M CORPORATION 1995
- * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
- *-----------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------+
- *
- * File Name: enetemac.c
- *
- * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
- *
- * Author: Mark Wisner
- *
- * Change Activity-
- *
- * Date Description of Change BY
- * --------- --------------------- ---
- * 05-May-99 Created MKW
- * 27-Jun-99 Clean up JWB
- * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
- * 29-Jul-99 Added Full duplex support MKW
- * 06-Aug-99 Changed names for Mal CR reg MKW
- * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
- * 24-Aug-99 Marked descriptor empty after call_xlc MKW
- * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
- * to avoid chaining maximum sized packets. Push starting
- * RX descriptor address up to the next cache line boundary.
- * 16-Jan-00 Added support for booting with IP of 0x0 MKW
- * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
- * EMAC_RXM register. JWB
- * 12-Mar-01 anne-sophie.harnois@nextream.fr
- * - Variables are compatible with those already defined in
- * include/net.h
- * - Receive buffer descriptor ring is used to send buffers
- * to the user
- * - Info print about send/received/handled packet number if
- * INFO_405_ENET is set
- * 17-Apr-01 stefan.roese@esd-electronics.com
- * - MAL reset in "eth_halt" included
- * - Enet speed and duplex output now in one line
- * 08-May-01 stefan.roese@esd-electronics.com
- * - MAL error handling added (eth_init called again)
- * 13-Nov-01 stefan.roese@esd-electronics.com
- * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
- * 04-Jan-02 stefan.roese@esd-electronics.com
- * - Wait for PHY auto negotiation to complete added
- * 06-Feb-02 stefan.roese@esd-electronics.com
- * - Bug fixed in waiting for auto negotiation to complete
- * 26-Feb-02 stefan.roese@esd-electronics.com
- * - rx and tx buffer descriptors now allocated (no fixed address
- * used anymore)
- * 17-Jun-02 stefan.roese@esd-electronics.com
- * - MAL error debug printf 'M' removed (rx de interrupt may
- * occur upon many incoming packets with only 4 rx buffers).
- * 21-Nov-03 pavel.bartusek@sysgo.com
- * - set ZMII bridge speed on 440
- *
- *-----------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <asm/processor.h>
-#include <ppc4xx.h>
-#include <commproc.h>
-#include <405gp_enet.h>
-#include <405_mal.h>
-#include <miiphy.h>
-#include <net.h>
-#include <malloc.h>
-#include "vecnum.h"
-
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
- ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI))
-
-#if !defined(CONFIG_NET_MULTI) || !defined(CONFIG_405EP)
-/* 405GP, 440 with !CONFIG_NET_MULTI. For 440 only EMAC0 is supported */
-#define EMAC_NUM_DEV 1
-#else
-/* 440EP && CONFIG_NET_MULTI */
-#define EMAC_NUM_DEV 2
-#endif
-
-#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
-#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
-
-/* Ethernet Transmit and Receive Buffers */
-/* AS.HARNOIS
- * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
- * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
- */
-#define ENET_MAX_MTU PKTSIZE
-#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
-
-/* define the number of channels implemented */
-#define EMAC_RXCHL EMAC_NUM_DEV
-#define EMAC_TXCHL EMAC_NUM_DEV
-
-/*-----------------------------------------------------------------------------+
- * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
- * Interrupt Controller).
- *-----------------------------------------------------------------------------*/
-#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
-#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
-#define EMAC_UIC_DEF UIC_ENET
-#define EMAC_UIC_DEF1 UIC_ENET1
-#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
-
-
-/*-----------------------------------------------------------------------------+
- * Global variables. TX and RX descriptors and buffers.
- *-----------------------------------------------------------------------------*/
-/* IER globals */
-static uint32_t mal_ier;
-
-#if !defined(CONFIG_NET_MULTI)
-struct eth_device *emac0_dev;
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Prototypes and externals.
- *-----------------------------------------------------------------------------*/
-static void enet_rcv (struct eth_device *dev, unsigned long malisr);
-
-int enetInt (struct eth_device *dev);
-static void mal_err (struct eth_device *dev, unsigned long isr,
- unsigned long uic, unsigned long maldef,
- unsigned long mal_errr);
-static void emac_err (struct eth_device *dev, unsigned long isr);
-
-/*-----------------------------------------------------------------------------+
-| ppc_405x_eth_halt
-| Disable MAL channel, and EMACn
-|
-|
-+-----------------------------------------------------------------------------*/
-static void ppc_4xx_eth_halt (struct eth_device *dev)
-{
- EMAC_405_HW_PST hw_p = dev->priv;
- uint32_t failsafe = 10000;
-
- mtdcr (malier, 0x00000000); /* disable mal interrupts */
- out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
-
- /* 1st reset MAL channel */
- /* Note: writing a 0 to a channel has no effect */
- mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
- mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
-
- /* wait for reset */
- while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
- udelay (1000); /* Delay 1 MS so as not to hammer the register */
- failsafe--;
- if (failsafe == 0)
- break;
- }
-
- /* EMAC RESET */
- out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
-
- hw_p->print_speed = 1; /* print speed message again next time */
-
- return;
-}
-
-static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
-{
- int i;
- unsigned long reg;
- unsigned long msr;
- unsigned long speed;
- unsigned long duplex;
- unsigned long failsafe;
- unsigned mode_reg;
- unsigned short devnum;
- unsigned short reg_short;
-
- EMAC_405_HW_PST hw_p = dev->priv;
- /* before doing anything, figure out if we have a MAC address */
- /* if not, bail */
- if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
- return -1;
-
- msr = mfmsr ();
- mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
-
- devnum = hw_p->devnum;
-
-#ifdef INFO_405_ENET
- /* AS.HARNOIS
- * We should have :
- * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
- * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
- * is possible that new packets (without relationship with
- * current transfer) have got the time to arrived before
- * netloop calls eth_halt
- */
- printf ("About preceeding transfer (eth%d):\n"
- "- Sent packet number %d\n"
- "- Received packet number %d\n"
- "- Handled packet number %d\n",
- hw_p->devnum,
- hw_p->stats.pkts_tx,
- hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
-
- hw_p->stats.pkts_tx = 0;
- hw_p->stats.pkts_rx = 0;
- hw_p->stats.pkts_handled = 0;
-#endif
-
- /* MAL RESET */
- mtdcr (malmcr, MAL_CR_MMSR);
- /* wait for reset */
- while (mfdcr (malmcr) & MAL_CR_MMSR) {
- };
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- out32 (ZMII_FER, 0);
- udelay(100);
- /* set RII mode */
- out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
-#elif defined(CONFIG_440)
- /* set RMII mode */
- out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
-#endif /* CONFIG_440 */
-
- /* MAL Channel RESET */
- /* 1st reset MAL channel */
- /* Note: writing a 0 to a channel has no effect */
- mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum * 2)));
- mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
-
- /* wait for reset */
- /* TBS: should have udelay and failsafe here */
- failsafe = 10000;
- /* wait for reset */
- while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
- udelay (1000); /* Delay 1 MS so as not to hammer the register */
- failsafe--;
- if (failsafe == 0)
- break;
-
- }
-
- hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
- hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
-
- hw_p->rx_slot = 0; /* MAL Receive Slot */
- hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
- hw_p->rx_u_index = 0; /* Receive User Queue Index */
-
- hw_p->tx_slot = 0; /* MAL Transmit Slot */
- hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
- hw_p->tx_u_index = 0; /* Transmit User Queue Index */
-
- __asm__ volatile ("eieio");
-
- /* reset emac so we have access to the phy */
-
- out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
- __asm__ volatile ("eieio");
-
- failsafe = 1000;
- while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
- udelay (1000);
- failsafe--;
- }
-
-#if defined(CONFIG_NET_MULTI)
- reg = hw_p->devnum ? CONFIG_PHY1_ADDR : CONFIG_PHY_ADDR;
-#else
- reg = CONFIG_PHY_ADDR;
-#endif
- /* wait for PHY to complete auto negotiation */
- reg_short = 0;
-#ifndef CONFIG_CS8952_PHY
- miiphy_read (reg, PHY_BMSR, &reg_short);
-
- /*
- * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
- */
- if ((reg_short & PHY_BMSR_AUTN_ABLE)
- && !(reg_short & PHY_BMSR_AUTN_COMP)) {
- puts ("Waiting for PHY auto negotiation to complete");
- i = 0;
- while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
- /*
- * Timeout reached ?
- */
- if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
- puts (" TIMEOUT !\n");
- break;
- }
-
- if ((i++ % 1000) == 0) {
- putc ('.');
- }
- udelay (1000); /* 1 ms */
- miiphy_read (reg, PHY_BMSR, &reg_short);
- }
- puts (" done\n");
- udelay (500000); /* another 500 ms (results in faster booting) */
- }
-#endif
- speed = miiphy_speed (reg);
- duplex = miiphy_duplex (reg);
-
- if (hw_p->print_speed) {
- hw_p->print_speed = 0;
- printf ("ENET Speed is %d Mbps - %s duplex connection\n",
- (int) speed, (duplex == HALF) ? "HALF" : "FULL");
- }
-
- mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
- /* Errata 1.12: MAL_1 -- Disable MAL bursting */
- if (get_pvr() == PVR_440GP_RB) {
- mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
- }
-
- /* Free "old" buffers */
- if (hw_p->alloc_tx_buf)
- free (hw_p->alloc_tx_buf);
- if (hw_p->alloc_rx_buf)
- free (hw_p->alloc_rx_buf);
-
- /*
- * Malloc MAL buffer desciptors, make sure they are
- * aligned on cache line boundary size
- * (401/403/IOP480 = 16, 405 = 32)
- * and doesn't cross cache block boundaries.
- */
- hw_p->alloc_tx_buf =
- (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
- ((2 * CFG_CACHELINE_SIZE) - 2));
- if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
- hw_p->tx =
- (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
- CFG_CACHELINE_SIZE -
- ((int) hw_p->
- alloc_tx_buf & CACHELINE_MASK));
- } else {
- hw_p->tx = hw_p->alloc_tx_buf;
- }
-
- hw_p->alloc_rx_buf =
- (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
- ((2 * CFG_CACHELINE_SIZE) - 2));
- if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
- hw_p->rx =
- (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
- CFG_CACHELINE_SIZE -
- ((int) hw_p->
- alloc_rx_buf & CACHELINE_MASK));
- } else {
- hw_p->rx = hw_p->alloc_rx_buf;
- }
-
- for (i = 0; i < NUM_TX_BUFF; i++) {
- hw_p->tx[i].ctrl = 0;
- hw_p->tx[i].data_len = 0;
- if (hw_p->first_init == 0)
- hw_p->txbuf_ptr =
- (char *) malloc (ENET_MAX_MTU_ALIGNED);
- hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
- if ((NUM_TX_BUFF - 1) == i)
- hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
- hw_p->tx_run[i] = -1;
-#if 0
- printf ("TX_BUFF %d @ 0x%08lx\n", i,
- (ulong) hw_p->tx[i].data_ptr);
-#endif
- }
-
- for (i = 0; i < NUM_RX_BUFF; i++) {
- hw_p->rx[i].ctrl = 0;
- hw_p->rx[i].data_len = 0;
- /* rx[i].data_ptr = (char *) &rx_buff[i]; */
- hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
- if ((NUM_RX_BUFF - 1) == i)
- hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
- hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
- hw_p->rx_ready[i] = -1;
-#if 0
- printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
-#endif
- }
-
- reg = 0x00000000;
- reg |= dev->enetaddr[0]; /* set high address */
- reg = reg << 8;
- reg |= dev->enetaddr[1];
-
- out32 (EMAC_IAH + hw_p->hw_addr, reg);
-
- reg = 0x00000000;
- reg |= dev->enetaddr[2]; /* set low address */
- reg = reg << 8;
- reg |= dev->enetaddr[3];
- reg = reg << 8;
- reg |= dev->enetaddr[4];
- reg = reg << 8;
- reg |= dev->enetaddr[5];
-
- out32 (EMAC_IAL + hw_p->hw_addr, reg);
-
- switch (devnum) {
-#if defined(CONFIG_NET_MULTI)
- case 1:
- /* setup MAL tx & rx channel pointers */
- /* For 405EP, the EMAC1 tx channel 0 is MAL tx channel 2 */
- mtdcr (maltxctp2r, hw_p->tx);
- mtdcr (malrxctp1r, hw_p->rx);
- /* set RX buffer size */
- mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
- break;
-#endif
- case 0:
- default:
- /* setup MAL tx & rx channel pointers */
- mtdcr (maltxctp0r, hw_p->tx);
- mtdcr (malrxctp0r, hw_p->rx);
- /* set RX buffer size */
- mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
- break;
- }
-
- /* Enable MAL transmit and receive channels */
- mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum * 2)));
- mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
-
- /* set transmit enable & receive enable */
- out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
-
- /* set receive fifo to 4k and tx fifo to 2k */
- mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
- mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
-
- /* set speed */
- if (speed == _100BASET)
- mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
- else
- mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
- if (duplex == FULL)
- mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
-
- out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
-
-#if defined(CONFIG_440)
- /* set speed in the ZMII bridge */
- if (speed == _100BASET)
- out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
- else
- out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- mfsdr(sdr_mfr, reg);
- /* set speed */
- if (speed == _100BASET) {
- out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
- reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
- } else {
- reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
- out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
- }
- mtsdr(sdr_mfr, reg);
-#endif
-#endif
-
- /* Enable broadcast and indvidual address */
- /* TBS: enabling runts as some misbehaved nics will send runts */
- out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
-
- /* we probably need to set the tx mode1 reg? maybe at tx time */
-
- /* set transmit request threshold register */
- out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
-
-#if defined(CONFIG_440)
- /* 440GP has a 64 byte burst length */
- out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
- out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
-#else
- /* 405s have a 16 byte burst length */
- out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
-#endif
-
- /* Frame gap set */
- out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
-
- /* Set EMAC IER */
- hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
- EMAC_ISR_ORE | EMAC_ISR_IRE;
- if (speed == _100BASET)
- hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
-
- out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
- out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
-
- if (hw_p->first_init == 0) {
- /*
- * Connect interrupt service routines
- */
- irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
- (interrupt_handler_t *) enetInt, dev);
- }
-
- mtmsr (msr); /* enable interrupts again */
-
- hw_p->bis = bis;
- hw_p->first_init = 1;
-
- return (1);
-}
-
-
-static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, int len)
-{
- struct enet_frame *ef_ptr;
- ulong time_start, time_now;
- unsigned long temp_txm0;
- EMAC_405_HW_PST hw_p = dev->priv;
-
- ef_ptr = (struct enet_frame *) ptr;
-
- /*-----------------------------------------------------------------------+
- * Copy in our address into the frame.
- *-----------------------------------------------------------------------*/
- (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
-
- /*-----------------------------------------------------------------------+
- * If frame is too long or too short, modify length.
- *-----------------------------------------------------------------------*/
- /* TBS: where does the fragment go???? */
- if (len > ENET_MAX_MTU)
- len = ENET_MAX_MTU;
-
- /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
- memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
-
- /*-----------------------------------------------------------------------+
- * set TX Buffer busy, and send it
- *-----------------------------------------------------------------------*/
- hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
- EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
- ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
- if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
- hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
-
- hw_p->tx[hw_p->tx_slot].data_len = (short) len;
- hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
-
- __asm__ volatile ("eieio");
-
- out32 (EMAC_TXM0 + hw_p->hw_addr,
- in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
-#ifdef INFO_405_ENET
- hw_p->stats.pkts_tx++;
-#endif
-
- /*-----------------------------------------------------------------------+
- * poll unitl the packet is sent and then make sure it is OK
- *-----------------------------------------------------------------------*/
- time_start = get_timer (0);
- while (1) {
- temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
- /* loop until either TINT turns on or 3 seconds elapse */
- if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
- /* transmit is done, so now check for errors
- * If there is an error, an interrupt should
- * happen when we return
- */
- time_now = get_timer (0);
- if ((time_now - time_start) > 3000) {
- return (-1);
- }
- } else {
- return (len);
- }
- }
-}
-
-#if defined(CONFIG_440)
-int enetInt (struct eth_device *dev)
-{
- int serviced;
- int rc = -1; /* default to not us */
- unsigned long mal_isr;
- unsigned long emac_isr = 0;
- unsigned long mal_rx_eob;
- unsigned long my_uic0msr, my_uic1msr;
- EMAC_405_HW_PST hw_p;
-
- /*
- * Because the mal is generic, we need to get the current
- * eth device
- */
-#if defined(CONFIG_NET_MULTI)
- dev = eth_get_dev();
-#else
- dev = emac0_dev;
-#endif
- hw_p = dev->priv;
-
- /* enter loop that stays in interrupt code until nothing to service */
- do {
- serviced = 0;
-
- my_uic0msr = mfdcr (uic0msr);
- my_uic1msr = mfdcr (uic1msr);
-
- if (!(my_uic0msr & UIC_MRE)
- && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
- /* not for us */
- return (rc);
- }
-
- /* get and clear controller status interrupts */
- /* look at Mal and EMAC interrupts */
- if ((my_uic0msr & UIC_MRE)
- || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- /* we have a MAL interrupt */
- mal_isr = mfdcr (malesr);
- /* look for mal error */
- if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
- mal_err (dev, mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR);
- serviced = 1;
- rc = 0;
- }
- }
- if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
- emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
- if ((hw_p->emac_ier & emac_isr) != 0) {
- emac_err (dev, emac_isr);
- serviced = 1;
- rc = 0;
- }
- }
- if ((hw_p->emac_ier & emac_isr)
- || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (uic0sr, UIC_MRE); /* Clear */
- mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
- return (rc); /* we had errors so get out */
- }
-
- /* handle MAL RX EOB interupt from a receive */
- /* check for EOB on valid channels */
- if (my_uic0msr & UIC_MRE) {
- mal_rx_eob = mfdcr (malrxeobisr);
- if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel 0 */
- /* clear EOB
- mtdcr(malrxeobisr, mal_rx_eob); */
- enet_rcv (dev, emac_isr);
- /* indicate that we serviced an interrupt */
- serviced = 1;
- rc = 0;
- }
- }
- mtdcr (uic0sr, UIC_MRE); /* Clear */
- mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
- } while (serviced);
-
- return (rc);
-}
-
-#else /* CONFIG_440 */
-
-int enetInt (struct eth_device *dev)
-{
- int serviced;
- int rc = -1; /* default to not us */
- unsigned long mal_isr;
- unsigned long emac_isr = 0;
- unsigned long mal_rx_eob;
- unsigned long my_uicmsr;
-
- EMAC_405_HW_PST hw_p;
-
- /*
- * Because the mal is generic, we need to get the current
- * eth device
- */
-#if defined(CONFIG_NET_MULTI)
- dev = eth_get_dev();
-#else
- dev = emac0_dev;
-#endif
-
- hw_p = dev->priv;
-
- /* enter loop that stays in interrupt code until nothing to service */
- do {
- serviced = 0;
-
- my_uicmsr = mfdcr (uicmsr);
-
- if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
- return (rc);
- }
- /* get and clear controller status interrupts */
- /* look at Mal and EMAC interrupts */
- if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
- mal_isr = mfdcr (malesr);
- /* look for mal error */
- if ((my_uicmsr & MAL_UIC_ERR) != 0) {
- mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
- serviced = 1;
- rc = 0;
- }
- }
-
- /* port by port dispatch of emac interrupts */
-
- if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
- emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
- if ((hw_p->emac_ier & emac_isr) != 0) {
- emac_err (dev, emac_isr);
- serviced = 1;
- rc = 0;
- }
- }
- if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
- mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
- return (rc); /* we had errors so get out */
- }
-
- /* handle MAX TX EOB interrupt from a tx */
- if (my_uicmsr & UIC_MAL_TXEOB) {
- mal_rx_eob = mfdcr (maltxeobisr);
- mtdcr (maltxeobisr, mal_rx_eob);
- mtdcr (uicsr, UIC_MAL_TXEOB);
- }
- /* handle MAL RX EOB interupt from a receive */
- /* check for EOB on valid channels */
- if (my_uicmsr & UIC_MAL_RXEOB)
- {
- mal_rx_eob = mfdcr (malrxeobisr);
- if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
- /* clear EOB
- mtdcr(malrxeobisr, mal_rx_eob); */
- enet_rcv (dev, emac_isr);
- /* indicate that we serviced an interrupt */
- serviced = 1;
- rc = 0;
- }
- }
- mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
- }
- while (serviced);
-
- return (rc);
-}
-#endif
-/*-----------------------------------------------------------------------------+
- * MAL Error Routine
- *-----------------------------------------------------------------------------*/
-static void mal_err (struct eth_device *dev, unsigned long isr,
- unsigned long uic, unsigned long maldef,
- unsigned long mal_errr)
-{
- EMAC_405_HW_PST hw_p = dev->priv;
-
- mtdcr (malesr, isr); /* clear interrupt */
-
- /* clear DE interrupt */
- mtdcr (maltxdeir, 0xC0000000);
- mtdcr (malrxdeir, 0x80000000);
-
-#ifdef INFO_405_ENET
- printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
-#endif
-
- eth_init (hw_p->bis); /* start again... */
-}
-
-/*-----------------------------------------------------------------------------+
- * EMAC Error Routine
- *-----------------------------------------------------------------------------*/
-static void emac_err (struct eth_device *dev, unsigned long isr)
-{
- EMAC_405_HW_PST hw_p = dev->priv;
-
- printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
- out32 (EMAC_ISR + hw_p->hw_addr, isr);
-}
-
-/*-----------------------------------------------------------------------------+
- * enet_rcv() handles the ethernet receive data
- *-----------------------------------------------------------------------------*/
-static void enet_rcv (struct eth_device *dev, unsigned long malisr)
-{
- struct enet_frame *ef_ptr;
- unsigned long data_len;
- unsigned long rx_eob_isr;
- EMAC_405_HW_PST hw_p = dev->priv;
-
- int handled = 0;
- int i;
- int loop_count = 0;
-
- rx_eob_isr = mfdcr (malrxeobisr);
- if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
- /* clear EOB */
- mtdcr (malrxeobisr, rx_eob_isr);
-
- /* EMAC RX done */
- while (1) { /* do all */
- i = hw_p->rx_slot;
-
- if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
- || (loop_count >= NUM_RX_BUFF))
- break;
- loop_count++;
- hw_p->rx_slot++;
- if (NUM_RX_BUFF == hw_p->rx_slot)
- hw_p->rx_slot = 0;
- handled++;
- data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
- if (data_len) {
- if (data_len > ENET_MAX_MTU) /* Check len */
- data_len = 0;
- else {
- if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
- data_len = 0;
- hw_p->stats.rx_err_log[hw_p->
- rx_err_index]
- = hw_p->rx[i].ctrl;
- hw_p->rx_err_index++;
- if (hw_p->rx_err_index ==
- MAX_ERR_LOG)
- hw_p->rx_err_index =
- 0;
- } /* emac_erros */
- } /* data_len < max mtu */
- } /* if data_len */
- if (!data_len) { /* no data */
- hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
-
- hw_p->stats.data_len_err++; /* Error at Rx */
- }
-
- /* !data_len */
- /* AS.HARNOIS */
- /* Check if user has already eaten buffer */
- /* if not => ERROR */
- else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
- if (hw_p->is_receiving)
- printf ("ERROR : Receive buffers are full!\n");
- break;
- } else {
- hw_p->stats.rx_frames++;
- hw_p->stats.rx += data_len;
- ef_ptr = (struct enet_frame *) hw_p->rx[i].
- data_ptr;
-#ifdef INFO_405_ENET
- hw_p->stats.pkts_rx++;
-#endif
- /* AS.HARNOIS
- * use ring buffer
- */
- hw_p->rx_ready[hw_p->rx_i_index] = i;
- hw_p->rx_i_index++;
- if (NUM_RX_BUFF == hw_p->rx_i_index)
- hw_p->rx_i_index = 0;
-
- /* printf("X"); /|* test-only *|/ */
-
- /* AS.HARNOIS
- * free receive buffer only when
- * buffer has been handled (eth_rx)
- rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
- */
- } /* if data_len */
- } /* while */
- } /* if EMACK_RXCHL */
-}
-
-
-static int ppc_4xx_eth_rx (struct eth_device *dev)
-{
- int length;
- int user_index;
- unsigned long msr;
- EMAC_405_HW_PST hw_p = dev->priv;
-
- hw_p->is_receiving = 1; /* tell driver */
-
- for (;;) {
- /* AS.HARNOIS
- * use ring buffer and
- * get index from rx buffer desciptor queue
- */
- user_index = hw_p->rx_ready[hw_p->rx_u_index];
- if (user_index == -1) {
- length = -1;
- break; /* nothing received - leave for() loop */
- }
-
- msr = mfmsr ();
- mtmsr (msr & ~(MSR_EE));
-
- length = hw_p->rx[user_index].data_len;
-
- /* Pass the packet up to the protocol layers. */
- /* NetReceive(NetRxPackets[rxIdx], length - 4); */
- /* NetReceive(NetRxPackets[i], length); */
- NetReceive (NetRxPackets[user_index], length - 4);
- /* Free Recv Buffer */
- hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
- /* Free rx buffer descriptor queue */
- hw_p->rx_ready[hw_p->rx_u_index] = -1;
- hw_p->rx_u_index++;
- if (NUM_RX_BUFF == hw_p->rx_u_index)
- hw_p->rx_u_index = 0;
-
-#ifdef INFO_405_ENET
- hw_p->stats.pkts_handled++;
-#endif
-
- mtmsr (msr); /* Enable IRQ's */
- }
-
- hw_p->is_receiving = 0; /* tell driver */
-
- return length;
-}
-
-static int virgin = 0;
-int ppc_4xx_eth_initialize (bd_t * bis)
-{
- struct eth_device *dev;
- int eth_num = 0;
-
- EMAC_405_HW_PST hw = NULL;
-
- for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
-
- /* Allocate device structure */
- dev = (struct eth_device *) malloc (sizeof (*dev));
- if (dev == NULL) {
- printf ("ppc_405x_eth_initialize: "
- "Cannot allocate eth_device %d\n", eth_num);
- return (-1);
- }
- memset(dev, 0, sizeof(*dev));
- /* Allocate our private use data */
- hw = (EMAC_405_HW_PST) malloc (sizeof (*hw));
- if (hw == NULL) {
- printf ("ppc_405x_eth_initialize: "
- "Cannot allocate private hw data for eth_device %d",
- eth_num);
- free (dev);
- return (-1);
- }
- memset(hw, 0, sizeof(*hw));
-
- switch (eth_num) {
- case 0:
- hw->hw_addr = 0;
- memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
- break;
-#if defined(CONFIG_NET_MULTI)
- case 1:
- hw->hw_addr = 0x100;
- memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
- break;
-#endif
- default:
- hw->hw_addr = 0;
- memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
- break;
- }
-
- hw->devnum = eth_num;
- hw->print_speed = 1;
-
- sprintf (dev->name, "ppc_405x_eth%d", eth_num);
- dev->priv = (void *) hw;
- dev->init = ppc_4xx_eth_init;
- dev->halt = ppc_4xx_eth_halt;
- dev->send = ppc_4xx_eth_send;
- dev->recv = ppc_4xx_eth_rx;
-
- if (0 == virgin) {
- /* set the MAL IER ??? names may change with new spec ??? */
- mal_ier =
- MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
- MAL_IER_OPBE | MAL_IER_PLBE;
- mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
- mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
- mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
- mtdcr (malier, mal_ier);
-
- /* install MAL interrupt handler */
- irq_install_handler (VECNUM_MS,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_MTE,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_MRE,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_TXDE,
- (interrupt_handler_t *) enetInt,
- dev);
- irq_install_handler (VECNUM_RXDE,
- (interrupt_handler_t *) enetInt,
- dev);
- virgin = 1;
- }
-
-#if defined(CONFIG_NET_MULTI)
- eth_register (dev);
-#else
- emac0_dev = dev;
-#endif
-
- } /* end for each supported device */
-
- return (1);
-}
-
-#if !defined(CONFIG_NET_MULTI)
-void eth_halt (void) {
- if (emac0_dev) {
- ppc_4xx_eth_halt(emac0_dev);
- free(emac0_dev);
- emac0_dev = NULL;
- }
-}
-
-int eth_init (bd_t *bis)
-{
- ppc_4xx_eth_initialize(bis);
- return(ppc_4xx_eth_init(emac0_dev, bis));
-}
-
-int eth_send(volatile void *packet, int length)
-{
-
- return (ppc_4xx_eth_send(emac0_dev, packet, length));
-}
-
-int eth_rx(void)
-{
- return (ppc_4xx_eth_rx(emac0_dev));
-}
-#endif
-
-#endif /* CONFIG_405 */
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 89be137a86..f6b29e9d6e 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -81,6 +81,10 @@
#ifdef CONFIG_PCI
+#if defined(CONFIG_PMC405)
+ushort pmc405_pci_subsys_deviceid(void);
+#endif
+
/*#define DEBUG*/
/*-----------------------------------------------------------------------------+
@@ -96,13 +100,10 @@ void pci_405gp_init(struct pci_controller *hose)
unsigned short temp_short;
unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
- unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart};
- unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
char *ptmla_str, *ptmms_str;
-#else
+#endif
unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
-#endif
#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
@@ -431,27 +432,33 @@ static struct pci_controller ppc440_hose = {0};
void pci_440_init (struct pci_controller *hose)
{
int reg_num = 0;
- unsigned long strap;
+#ifndef CONFIG_DISABLE_PISE_TEST
/*--------------------------------------------------------------------------+
* The PCI initialization sequence enable bit must be set ... if not abort
* pci setup since updating the bit requires chip reset.
*--------------------------------------------------------------------------*/
-#if defined (CONFIG_440GX) || defined (CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+ unsigned long strap;
+
mfsdr(sdr_sdstp1,strap);
- if ( (strap & 0x00010000) == 0 ){
+ if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
return;
}
-#else
+#elif defined(CONFIG_440GP)
+ unsigned long strap;
+
strap = mfdcr(cpc0_strp1);
- if( (strap & 0x00040000) == 0 ){
+ if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
printf("PCI: CPC0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
return;
}
#endif
+#endif /* CONFIG_DISABLE_PISE_TEST */
+
/*--------------------------------------------------------------------------+
* PCI controller init
*--------------------------------------------------------------------------*/
@@ -460,26 +467,26 @@ void pci_440_init (struct pci_controller *hose)
pci_set_region(hose->regions + reg_num++,
0x00000000,
- PCIX0_IOBASE,
- 0x10000,
- PCI_REGION_IO);
+ PCIX0_IOBASE,
+ 0x10000,
+ PCI_REGION_IO);
pci_set_region(hose->regions + reg_num++,
CFG_PCI_TARGBASE,
- CFG_PCI_MEMBASE,
- 0x10000000,
- PCI_REGION_MEM );
+ CFG_PCI_MEMBASE,
+ 0x10000000,
+ PCI_REGION_MEM );
hose->region_count = reg_num;
pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
#if defined(CFG_PCI_PRE_INIT)
- /* Let board change/modify hose & do initial checks */
- if( pci_pre_init (hose) == 0 ){
- printf("PCI: Board-specific initialization failed.\n");
- printf("PCI: Configuration aborted.\n");
- return;
- }
+ /* Let board change/modify hose & do initial checks */
+ if (pci_pre_init (hose) == 0) {
+ printf("PCI: Board-specific initialization failed.\n");
+ printf("PCI: Configuration aborted.\n");
+ return;
+ }
#endif
pci_register_hose( hose );
@@ -490,9 +497,9 @@ void pci_440_init (struct pci_controller *hose)
#if defined(CFG_PCI_TARGET_INIT)
pci_target_init(hose); /* Let board setup pci target */
#else
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
- out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
+ out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
+ out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif
#if defined(CONFIG_440GX)
@@ -518,24 +525,24 @@ void pci_440_init (struct pci_controller *hose)
out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
out32r( PCIX0_POM0PCIAH, 0x00000000 );
out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
- out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
+ out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
#endif
/*--------------------------------------------------------------------------+
* PCI host configuration -- we don't make any assumptions here ... the
- * _board_must_indicate_ what to do -- there's just too many runtime
- * scenarios in environments like cPCI, PPMC, etc. to make a determination
- * based on hard-coded values or state of arbiter enable.
+ * _board_must_indicate_ what to do -- there's just too many runtime
+ * scenarios in environments like cPCI, PPMC, etc. to make a determination
+ * based on hard-coded values or state of arbiter enable.
*--------------------------------------------------------------------------*/
- if( is_pci_host(hose) ){
+ if (is_pci_host(hose)) {
#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
- out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
+ out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
#endif
- hose->last_busno = pci_hose_scan(hose);
- }
+ hose->last_busno = pci_hose_scan(hose);
+ }
}
diff --git a/cpu/ppc4xx/440gx_enet.c b/cpu/ppc4xx/4xx_enet.c
index d0b6c15864..86dc2d066e 100644
--- a/cpu/ppc4xx/440gx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -1,111 +1,120 @@
/*-----------------------------------------------------------------------------+
*
- * This source code has been made available to you by IBM on an AS-IS
- * basis. Anyone receiving this source is licensed under IBM
- * copyrights to use it in any way he or she deems fit, including
- * copying it, modifying it, compiling it, and redistributing it either
- * with or without modifications. No license under IBM patents or
- * patent applications is to be implied by the copyright license.
+ * This source code has been made available to you by IBM on an AS-IS
+ * basis. Anyone receiving this source is licensed under IBM
+ * copyrights to use it in any way he or she deems fit, including
+ * copying it, modifying it, compiling it, and redistributing it either
+ * with or without modifications. No license under IBM patents or
+ * patent applications is to be implied by the copyright license.
*
- * Any user of this software should understand that IBM cannot provide
- * technical support for this software and will not be responsible for
- * any consequences resulting from the use of this software.
+ * Any user of this software should understand that IBM cannot provide
+ * technical support for this software and will not be responsible for
+ * any consequences resulting from the use of this software.
*
- * Any person who transfers this source code or any derivative work
- * must include the IBM copyright notice, this paragraph, and the
- * preceding two paragraphs in the transferred software.
+ * Any person who transfers this source code or any derivative work
+ * must include the IBM copyright notice, this paragraph, and the
+ * preceding two paragraphs in the transferred software.
*
- * COPYRIGHT I B M CORPORATION 1995
- * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+ * COPYRIGHT I B M CORPORATION 1995
+ * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
*-----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------+
*
- * File Name: enetemac.c
+ * File Name: enetemac.c
*
- * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
+ * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
*
- * Author: Mark Wisner
+ * Author: Mark Wisner
*
* Change Activity-
*
- * Date Description of Change BY
- * --------- --------------------- ---
- * 05-May-99 Created MKW
- * 27-Jun-99 Clean up JWB
- * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
- * 29-Jul-99 Added Full duplex support MKW
- * 06-Aug-99 Changed names for Mal CR reg MKW
- * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
- * 24-Aug-99 Marked descriptor empty after call_xlc MKW
- * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
- * to avoid chaining maximum sized packets. Push starting
- * RX descriptor address up to the next cache line boundary.
- * 16-Jan-00 Added support for booting with IP of 0x0 MKW
- * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
- * EMAC_RXM register. JWB
- * 12-Mar-01 anne-sophie.harnois@nextream.fr
- * - Variables are compatible with those already defined in
- * include/net.h
- * - Receive buffer descriptor ring is used to send buffers
- * to the user
- * - Info print about send/received/handled packet number if
- * INFO_405_ENET is set
- * 17-Apr-01 stefan.roese@esd-electronics.com
- * - MAL reset in "eth_halt" included
- * - Enet speed and duplex output now in one line
- * 08-May-01 stefan.roese@esd-electronics.com
- * - MAL error handling added (eth_init called again)
- * 13-Nov-01 stefan.roese@esd-electronics.com
- * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
- * 04-Jan-02 stefan.roese@esd-electronics.com
- * - Wait for PHY auto negotiation to complete added
- * 06-Feb-02 stefan.roese@esd-electronics.com
- * - Bug fixed in waiting for auto negotiation to complete
- * 26-Feb-02 stefan.roese@esd-electronics.com
- * - rx and tx buffer descriptors now allocated (no fixed address
- * used anymore)
- * 17-Jun-02 stefan.roese@esd-electronics.com
- * - MAL error debug printf 'M' removed (rx de interrupt may
- * occur upon many incoming packets with only 4 rx buffers).
+ * Date Description of Change BY
+ * --------- --------------------- ---
+ * 05-May-99 Created MKW
+ * 27-Jun-99 Clean up JWB
+ * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
+ * 29-Jul-99 Added Full duplex support MKW
+ * 06-Aug-99 Changed names for Mal CR reg MKW
+ * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
+ * 24-Aug-99 Marked descriptor empty after call_xlc MKW
+ * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
+ * to avoid chaining maximum sized packets. Push starting
+ * RX descriptor address up to the next cache line boundary.
+ * 16-Jan-00 Added support for booting with IP of 0x0 MKW
+ * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
+ * EMAC_RXM register. JWB
+ * 12-Mar-01 anne-sophie.harnois@nextream.fr
+ * - Variables are compatible with those already defined in
+ * include/net.h
+ * - Receive buffer descriptor ring is used to send buffers
+ * to the user
+ * - Info print about send/received/handled packet number if
+ * INFO_405_ENET is set
+ * 17-Apr-01 stefan.roese@esd-electronics.com
+ * - MAL reset in "eth_halt" included
+ * - Enet speed and duplex output now in one line
+ * 08-May-01 stefan.roese@esd-electronics.com
+ * - MAL error handling added (eth_init called again)
+ * 13-Nov-01 stefan.roese@esd-electronics.com
+ * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
+ * 04-Jan-02 stefan.roese@esd-electronics.com
+ * - Wait for PHY auto negotiation to complete added
+ * 06-Feb-02 stefan.roese@esd-electronics.com
+ * - Bug fixed in waiting for auto negotiation to complete
+ * 26-Feb-02 stefan.roese@esd-electronics.com
+ * - rx and tx buffer descriptors now allocated (no fixed address
+ * used anymore)
+ * 17-Jun-02 stefan.roese@esd-electronics.com
+ * - MAL error debug printf 'M' removed (rx de interrupt may
+ * occur upon many incoming packets with only 4 rx buffers).
*-----------------------------------------------------------------------------*
- * 17-Nov-03 travis.sawyer@sandburst.com
- * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
- * in the 440GX. This port should work with the 440GP
- * (2 EMACs) also
+ * 17-Nov-03 travis.sawyer@sandburst.com
+ * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
+ * in the 440GX. This port should work with the 440GP
+ * (2 EMACs) also
+ * 15-Aug-05 sr@denx.de
+ * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
+ now handling all 4xx cpu's.
*-----------------------------------------------------------------------------*/
#include <config.h>
-#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
-
#include <common.h>
#include <net.h>
#include <asm/processor.h>
-#include <ppc440.h>
#include <commproc.h>
-#include <440gx_enet.h>
+#include <ppc4xx.h>
+#include <ppc4xx_enet.h>
#include <405_mal.h>
#include <miiphy.h>
#include <malloc.h>
#include "vecnum.h"
+/*
+ * Only compile for platform with AMCC EMAC ethernet controller and
+ * network support enabled.
+ * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
-#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
-#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
+#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
+#error "CONFIG_MII has to be defined!"
+#endif
+
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
+#error "CONFIG_NET_MULTI has to be defined for NetConsole"
+#endif
+#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
+#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
/* Ethernet Transmit and Receive Buffers */
/* AS.HARNOIS
* In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
* PKTSIZE and PKTSIZE_ALIGN (include/net.h)
*/
-#define ENET_MAX_MTU PKTSIZE
+#define ENET_MAX_MTU PKTSIZE
#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
-
-/* define the number of channels implemented */
-#define EMAC_RXCHL EMAC_NUM_DEV
-#define EMAC_TXCHL EMAC_NUM_DEV
-
/*-----------------------------------------------------------------------------+
* Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
* Interrupt Controller).
@@ -113,19 +122,40 @@
#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
#define EMAC_UIC_DEF UIC_ENET
+#define EMAC_UIC_DEF1 UIC_ENET1
+#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
-#undef INFO_440_ENET
+#undef INFO_4XX_ENET
-#define BI_PHYMODE_NONE 0
-#define BI_PHYMODE_ZMII 1
+#define BI_PHYMODE_NONE 0
+#define BI_PHYMODE_ZMII 1
#define BI_PHYMODE_RGMII 2
+
/*-----------------------------------------------------------------------------+
* Global variables. TX and RX descriptors and buffers.
*-----------------------------------------------------------------------------*/
/* IER globals */
static uint32_t mal_ier;
+#if !defined(CONFIG_NET_MULTI)
+struct eth_device *emac0_dev = NULL;
+#endif
+
+/*
+ * Get count of EMAC devices (doesn't have to be the max. possible number
+ * supported by the cpu)
+ */
+#if defined(CONFIG_HAS_ETH3)
+#define LAST_EMAC_NUM 4
+#elif defined(CONFIG_HAS_ETH2)
+#define LAST_EMAC_NUM 3
+#elif defined(CONFIG_HAS_ETH1)
+#define LAST_EMAC_NUM 2
+#else
+#define LAST_EMAC_NUM 1
+#endif
+
/*-----------------------------------------------------------------------------+
* Prototypes and externals.
*-----------------------------------------------------------------------------*/
@@ -137,46 +167,52 @@ static void mal_err (struct eth_device *dev, unsigned long isr,
unsigned long mal_errr);
static void emac_err (struct eth_device *dev, unsigned long isr);
+extern int phy_setup_aneg (char *devname, unsigned char addr);
+extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+
/*-----------------------------------------------------------------------------+
-| ppc_440x_eth_halt
+| ppc_4xx_eth_halt
| Disable MAL channel, and EMACn
-|
-|
+-----------------------------------------------------------------------------*/
-static void ppc_440x_eth_halt (struct eth_device *dev)
+static void ppc_4xx_eth_halt (struct eth_device *dev)
{
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
uint32_t failsafe = 10000;
out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
+#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
+#else
mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
+#endif
mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
/* wait for reset */
- while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
+ while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
udelay (1000); /* Delay 1 MS so as not to hammer the register */
failsafe--;
if (failsafe == 0)
break;
-
}
/* EMAC RESET */
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
+#ifndef CONFIG_NETCONSOLE
hw_p->print_speed = 1; /* print speed message again next time */
+#endif
return;
}
-extern int phy_setup_aneg (unsigned char addr);
-extern int miiphy_reset (unsigned char addr);
-
#if defined (CONFIG_440GX)
-int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
+int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
unsigned long pfc1;
unsigned long zmiifer;
@@ -267,10 +303,10 @@ int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
}
#endif
-static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
+static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
{
int i, j;
- unsigned long reg;
+ unsigned long reg = 0;
unsigned long msr;
unsigned long speed;
unsigned long duplex;
@@ -278,30 +314,36 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
unsigned mode_reg;
unsigned short devnum;
unsigned short reg_short;
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
sys_info_t sysinfo;
#if defined(CONFIG_440GX)
- int ethgroup;
+ int ethgroup = -1;
+#endif
#endif
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
/* before doing anything, figure out if we have a MAC address */
/* if not, bail */
- if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
+ if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
+ printf("ERROR: ethaddr not set!\n");
return -1;
+ }
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
/* Need to get the OPB frequency so we can access the PHY */
get_sys_info (&sysinfo);
+#endif
msr = mfmsr ();
mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
devnum = hw_p->devnum;
-#ifdef INFO_440_ENET
+#ifdef INFO_4XX_ENET
/* AS.HARNOIS
* We should have :
- * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
+ * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
* In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
* is possible that new packets (without relationship with
* current transfer) have got the time to arrived before
@@ -320,31 +362,8 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
hw_p->stats.pkts_handled = 0;
#endif
- /* MAL Channel RESET */
- /* 1st reset MAL channel */
- /* Note: writing a 0 to a channel has no effect */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
-#else
- mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
-#endif
-
- mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
-
- /* wait for reset */
- /* TBS: should have udelay and failsafe here */
- failsafe = 10000;
- /* wait for reset */
- while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
- udelay (1000); /* Delay 1 MS so as not to hammer the register */
- failsafe--;
- if (failsafe == 0)
- break;
-
- }
-
- hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
- hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
+ hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
+ hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
hw_p->rx_slot = 0; /* MAL Receive Slot */
hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
@@ -354,6 +373,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
hw_p->tx_u_index = 0; /* Transmit User Queue Index */
+#if defined(CONFIG_440) && !defined(CONFIG_440SP)
/* set RMII mode */
/* NOTE: 440GX spec states that mode is mutually exclusive */
/* NOTE: Therefore, disable all other EMACS, since we handle */
@@ -363,9 +383,12 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
udelay (100);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
- out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
+ out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
#elif defined(CONFIG_440GX)
- ethgroup = ppc_440x_eth_setup_bridge(devnum, bis);
+ ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
+#elif defined(CONFIG_440GP)
+ /* set RMII mode */
+ out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
#else
if ((devnum == 0) || (devnum == 1)) {
out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
@@ -378,6 +401,8 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
#endif
out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
+#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
+
__asm__ volatile ("eieio");
/* reset emac so we have access to the phy */
@@ -391,7 +416,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
failsafe--;
}
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
/* Whack the M1 register */
mode_reg = 0x0;
mode_reg &= ~0x00000038;
@@ -406,7 +431,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
mode_reg |= EMAC_M1_OBCI_GT100;
out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
-#endif /* defined(CONFIG_440GX) */
+#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
/* wait for PHY to complete auto negotiation */
reg_short = 0;
@@ -415,9 +440,11 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
case 0:
reg = CONFIG_PHY_ADDR;
break;
+#if defined (CONFIG_PHY1_ADDR)
case 1:
reg = CONFIG_PHY1_ADDR;
break;
+#endif
#if defined (CONFIG_440GX)
case 2:
reg = CONFIG_PHY2_ADDR;
@@ -433,15 +460,15 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
bis->bi_phynum[devnum] = reg;
-#ifndef CONFIG_NO_PHY_RESET
+#if defined(CONFIG_PHY_RESET)
/*
* Reset the phy, only if its the first time through
* otherwise, just check the speeds & feeds
*/
if (hw_p->first_init == 0) {
- miiphy_reset (reg);
+ miiphy_reset (dev->name, reg);
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_CIS8201_PHY)
/*
* Cicada 8201 PHY needs to have an extended register whacked
@@ -449,9 +476,9 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
*/
if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
#if defined(CONFIG_CIS8201_SHORT_ETCH)
- miiphy_write (reg, 23, 0x1300);
+ miiphy_write (dev->name, reg, 23, 0x1300);
#else
- miiphy_write (reg, 23, 0x1000);
+ miiphy_write (dev->name, reg, 23, 0x1000);
#endif
/*
* Vitesse VSC8201/Cicada CIS8201 errata:
@@ -459,26 +486,26 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
* This work around (provided by Vitesse) changes
* the default timer convergence from 8ms to 12ms
*/
- miiphy_write (reg, 0x1f, 0x2a30);
- miiphy_write (reg, 0x08, 0x0200);
- miiphy_write (reg, 0x1f, 0x52b5);
- miiphy_write (reg, 0x02, 0x0004);
- miiphy_write (reg, 0x01, 0x0671);
- miiphy_write (reg, 0x00, 0x8fae);
- miiphy_write (reg, 0x1f, 0x2a30);
- miiphy_write (reg, 0x08, 0x0000);
- miiphy_write (reg, 0x1f, 0x0000);
+ miiphy_write (dev->name, reg, 0x1f, 0x2a30);
+ miiphy_write (dev->name, reg, 0x08, 0x0200);
+ miiphy_write (dev->name, reg, 0x1f, 0x52b5);
+ miiphy_write (dev->name, reg, 0x02, 0x0004);
+ miiphy_write (dev->name, reg, 0x01, 0x0671);
+ miiphy_write (dev->name, reg, 0x00, 0x8fae);
+ miiphy_write (dev->name, reg, 0x1f, 0x2a30);
+ miiphy_write (dev->name, reg, 0x08, 0x0000);
+ miiphy_write (dev->name, reg, 0x1f, 0x0000);
/* end Vitesse/Cicada errata */
}
#endif
#endif
/* Start/Restart autonegotiation */
- phy_setup_aneg (reg);
+ phy_setup_aneg (dev->name, reg);
udelay (1000);
}
-#endif /* CONFIG_NO_PHY_RESET */
+#endif /* defined(CONFIG_PHY_RESET) */
- miiphy_read (reg, PHY_BMSR, &reg_short);
+ miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
/*
* Wait if PHY is capable of autonegotiation and autonegotiation is not complete
@@ -500,15 +527,16 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
putc ('.');
}
udelay (1000); /* 1 ms */
- miiphy_read (reg, PHY_BMSR, &reg_short);
+ miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
}
puts (" done\n");
udelay (500000); /* another 500 ms (results in faster booting) */
}
-#endif
- speed = miiphy_speed (reg);
- duplex = miiphy_duplex (reg);
+#endif /* #ifndef CONFIG_CS8952_PHY */
+
+ speed = miiphy_speed (dev->name, reg);
+ duplex = miiphy_duplex (dev->name, reg);
if (hw_p->print_speed) {
hw_p->print_speed = 0;
@@ -516,6 +544,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
}
+#if defined(CONFIG_440) && !defined(CONFIG_440SP)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(sdr_mfr, reg);
if (speed == 100) {
@@ -543,9 +572,10 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
out32 (RGMII_SSR, reg);
}
+#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
/* set the Mal configuration reg */
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
#else
@@ -632,7 +662,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
for (i = 0; i < NUM_RX_BUFF; i++) {
hw_p->rx[i].ctrl = 0;
hw_p->rx[i].data_len = 0;
- /* rx[i].data_ptr = (char *) &rx_buff[i]; */
+ /* rx[i].data_ptr = (char *) &rx_buff[i]; */
hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
if ((NUM_RX_BUFF - 1) == i)
hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
@@ -665,13 +695,15 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
switch (devnum) {
case 1:
/* setup MAL tx & rx channel pointers */
-#if defined (CONFIG_440EP) || defined (CONFIG_440GR)
+#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
mtdcr (maltxctp2r, hw_p->tx);
#else
mtdcr (maltxctp1r, hw_p->tx);
#endif
+#if defined(CONFIG_440)
mtdcr (maltxbattr, 0x0);
mtdcr (malrxbattr, 0x0);
+#endif
mtdcr (malrxctp1r, hw_p->rx);
/* set RX buffer size */
mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
@@ -680,8 +712,8 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
case 2:
/* setup MAL tx & rx channel pointers */
mtdcr (maltxbattr, 0x0);
- mtdcr (maltxctp2r, hw_p->tx);
mtdcr (malrxbattr, 0x0);
+ mtdcr (maltxctp2r, hw_p->tx);
mtdcr (malrxctp2r, hw_p->rx);
/* set RX buffer size */
mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
@@ -699,9 +731,11 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
case 0:
default:
/* setup MAL tx & rx channel pointers */
+#if defined(CONFIG_440)
mtdcr (maltxbattr, 0x0);
- mtdcr (maltxctp0r, hw_p->tx);
mtdcr (malrxbattr, 0x0);
+#endif
+ mtdcr (maltxctp0r, hw_p->tx);
mtdcr (malrxctp0r, hw_p->rx);
/* set RX buffer size */
mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
@@ -709,7 +743,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
}
/* Enable MAL transmit and receive channels */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
#else
mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
@@ -724,9 +758,16 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
/* set speed */
- if (speed == _1000BASET)
+ if (speed == _1000BASET) {
+#if defined(CONFIG_440SP)
+#define SDR0_PFC1_EM_1000 0x00200000
+ unsigned long pfc1;
+ mfsdr (sdr_pfc1, pfc1);
+ pfc1 |= SDR0_PFC1_EM_1000;
+ mtsdr (sdr_pfc1, pfc1);
+#endif
mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
- else if (speed == _100BASET)
+ } else if (speed == _100BASET)
mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
else
mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
@@ -744,9 +785,14 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
/* set transmit request threshold register */
out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
- /* set receive low/high water mark register */
+ /* set receive low/high water mark register */
+#if defined(CONFIG_440)
/* 440GP has a 64 byte burst length */
out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
+#else
+ /* 405s have a 16 byte burst length */
+ out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
+#endif /* defined(CONFIG_440) */
out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
/* Set fifo limit entry in tx mode 0 */
@@ -755,8 +801,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
/* Set EMAC IER */
- hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
- EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
+ hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
if (speed == _100BASET)
hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
@@ -767,8 +812,6 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
/*
* Connect interrupt service routines
*/
- irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
- (interrupt_handler_t *) enetInt, dev);
irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
(interrupt_handler_t *) enetInt, dev);
}
@@ -782,13 +825,13 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
}
-static int ppc_440x_eth_send (struct eth_device *dev, volatile void *ptr,
+static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
int len)
{
struct enet_frame *ef_ptr;
ulong time_start, time_now;
unsigned long temp_txm0;
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
ef_ptr = (struct enet_frame *) ptr;
@@ -823,7 +866,7 @@ static int ppc_440x_eth_send (struct eth_device *dev, volatile void *ptr,
out32 (EMAC_TXM0 + hw_p->hw_addr,
in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
-#ifdef INFO_440_ENET
+#ifdef INFO_4XX_ENET
hw_p->stats.pkts_tx++;
#endif
@@ -850,6 +893,20 @@ static int ppc_440x_eth_send (struct eth_device *dev, volatile void *ptr,
}
+#if defined (CONFIG_440)
+
+#if defined(CONFIG_440SP)
+/*
+ * Hack: On 440SP all enet irq sources are located on UIC1
+ * Needs some cleanup. --sr
+ */
+#define UIC0MSR uic1msr
+#define UIC0SR uic1sr
+#else
+#define UIC0MSR uic0msr
+#define UIC0SR uic0sr
+#endif
+
int enetInt (struct eth_device *dev)
{
int serviced;
@@ -862,30 +919,31 @@ int enetInt (struct eth_device *dev)
#if defined(CONFIG_440GX)
unsigned long my_uic2msr;
#endif
- EMAC_440GX_HW_PST hw_p;
+ EMAC_4XX_HW_PST hw_p;
/*
* Because the mal is generic, we need to get the current
* eth device
*/
- dev = eth_get_dev ();
+#if defined(CONFIG_NET_MULTI)
+ dev = eth_get_dev();
+#else
+ dev = emac0_dev;
+#endif
hw_p = dev->priv;
-
/* enter loop that stays in interrupt code until nothing to service */
do {
serviced = 0;
- my_uic0msr = mfdcr (uic0msr);
+ my_uic0msr = mfdcr (UIC0MSR);
my_uic1msr = mfdcr (uic1msr);
#if defined(CONFIG_440GX)
my_uic2msr = mfdcr (uic2msr);
#endif
if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
- && !(my_uic1msr &
- (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
- UIC_MRDE))) {
+ && !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
/* not for us */
return (rc);
}
@@ -923,12 +981,13 @@ int enetInt (struct eth_device *dev)
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
+ mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
return (rc); /* we had errors so get out */
}
}
+#if !defined(CONFIG_440SP)
if (hw_p->devnum == 1) {
if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
@@ -940,7 +999,7 @@ int enetInt (struct eth_device *dev)
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
+ mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
return (rc); /* we had errors so get out */
}
@@ -957,7 +1016,7 @@ int enetInt (struct eth_device *dev)
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
+ mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
mtdcr (uic2sr, UIC_ETH2);
return (rc); /* we had errors so get out */
@@ -975,24 +1034,26 @@ int enetInt (struct eth_device *dev)
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
+ mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
mtdcr (uic2sr, UIC_ETH3);
return (rc); /* we had errors so get out */
}
}
#endif /* CONFIG_440GX */
+#endif /* !CONFIG_440SP */
+
/* handle MAX TX EOB interrupt from a tx */
if (my_uic0msr & UIC_MTE) {
mal_rx_eob = mfdcr (maltxeobisr);
mtdcr (maltxeobisr, mal_rx_eob);
- mtdcr (uic0sr, UIC_MTE);
+ mtdcr (UIC0SR, UIC_MTE);
}
/* handle MAL RX EOB interupt from a receive */
/* check for EOB on valid channels */
if (my_uic0msr & UIC_MRE) {
mal_rx_eob = mfdcr (malrxeobisr);
- if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
+ if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
/* clear EOB
mtdcr(malrxeobisr, mal_rx_eob); */
enet_rcv (dev, emac_isr);
@@ -1001,7 +1062,8 @@ int enetInt (struct eth_device *dev)
rc = 0;
}
}
- mtdcr (uic0sr, UIC_MRE); /* Clear */
+
+ mtdcr (UIC0SR, UIC_MRE); /* Clear */
mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
switch (hw_p->devnum) {
case 0:
@@ -1026,6 +1088,96 @@ int enetInt (struct eth_device *dev)
return (rc);
}
+#else /* CONFIG_440 */
+
+int enetInt (struct eth_device *dev)
+{
+ int serviced;
+ int rc = -1; /* default to not us */
+ unsigned long mal_isr;
+ unsigned long emac_isr = 0;
+ unsigned long mal_rx_eob;
+ unsigned long my_uicmsr;
+
+ EMAC_4XX_HW_PST hw_p;
+
+ /*
+ * Because the mal is generic, we need to get the current
+ * eth device
+ */
+#if defined(CONFIG_NET_MULTI)
+ dev = eth_get_dev();
+#else
+ dev = emac0_dev;
+#endif
+
+ hw_p = dev->priv;
+
+ /* enter loop that stays in interrupt code until nothing to service */
+ do {
+ serviced = 0;
+
+ my_uicmsr = mfdcr (uicmsr);
+
+ if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
+ return (rc);
+ }
+ /* get and clear controller status interrupts */
+ /* look at Mal and EMAC interrupts */
+ if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
+ mal_isr = mfdcr (malesr);
+ /* look for mal error */
+ if ((my_uicmsr & MAL_UIC_ERR) != 0) {
+ mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
+ serviced = 1;
+ rc = 0;
+ }
+ }
+
+ /* port by port dispatch of emac interrupts */
+
+ if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
+ emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
+ if ((hw_p->emac_ier & emac_isr) != 0) {
+ emac_err (dev, emac_isr);
+ serviced = 1;
+ rc = 0;
+ }
+ }
+ if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
+ mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
+ return (rc); /* we had errors so get out */
+ }
+
+ /* handle MAX TX EOB interrupt from a tx */
+ if (my_uicmsr & UIC_MAL_TXEOB) {
+ mal_rx_eob = mfdcr (maltxeobisr);
+ mtdcr (maltxeobisr, mal_rx_eob);
+ mtdcr (uicsr, UIC_MAL_TXEOB);
+ }
+ /* handle MAL RX EOB interupt from a receive */
+ /* check for EOB on valid channels */
+ if (my_uicmsr & UIC_MAL_RXEOB)
+ {
+ mal_rx_eob = mfdcr (malrxeobisr);
+ if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
+ /* clear EOB
+ mtdcr(malrxeobisr, mal_rx_eob); */
+ enet_rcv (dev, emac_isr);
+ /* indicate that we serviced an interrupt */
+ serviced = 1;
+ rc = 0;
+ }
+ }
+ mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
+ }
+ while (serviced);
+
+ return (rc);
+}
+
+#endif /* CONFIG_440 */
+
/*-----------------------------------------------------------------------------+
* MAL Error Routine
*-----------------------------------------------------------------------------*/
@@ -1033,7 +1185,7 @@ static void mal_err (struct eth_device *dev, unsigned long isr,
unsigned long uic, unsigned long maldef,
unsigned long mal_errr)
{
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
mtdcr (malesr, isr); /* clear interrupt */
@@ -1041,8 +1193,8 @@ static void mal_err (struct eth_device *dev, unsigned long isr,
mtdcr (maltxdeir, 0xC0000000);
mtdcr (malrxdeir, 0x80000000);
-#ifdef INFO_440_ENET
- printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
+#ifdef INFO_4XX_ENET
+ printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
#endif
eth_init (hw_p->bis); /* start again... */
@@ -1053,7 +1205,7 @@ static void mal_err (struct eth_device *dev, unsigned long isr,
*-----------------------------------------------------------------------------*/
static void emac_err (struct eth_device *dev, unsigned long isr)
{
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
out32 (EMAC_ISR + hw_p->hw_addr, isr);
@@ -1067,7 +1219,7 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr)
struct enet_frame *ef_ptr;
unsigned long data_len;
unsigned long rx_eob_isr;
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
int handled = 0;
int i;
@@ -1127,7 +1279,7 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr)
hw_p->stats.rx += data_len;
ef_ptr = (struct enet_frame *) hw_p->rx[i].
data_ptr;
-#ifdef INFO_440_ENET
+#ifdef INFO_4XX_ENET
hw_p->stats.pkts_rx++;
#endif
/* AS.HARNOIS
@@ -1138,8 +1290,6 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr)
if (NUM_RX_BUFF == hw_p->rx_i_index)
hw_p->rx_i_index = 0;
- /* printf("X"); /|* test-only *|/ */
-
/* AS.HARNOIS
* free receive buffer only when
* buffer has been handled (eth_rx)
@@ -1151,14 +1301,14 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr)
}
-static int ppc_440x_eth_rx (struct eth_device *dev)
+static int ppc_4xx_eth_rx (struct eth_device *dev)
{
int length;
int user_index;
unsigned long msr;
- EMAC_440GX_HW_PST hw_p = dev->priv;
+ EMAC_4XX_HW_PST hw_p = dev->priv;
- hw_p->is_receiving = 1; /* tell driver */
+ hw_p->is_receiving = 1; /* tell driver */
for (;;) {
/* AS.HARNOIS
@@ -1177,8 +1327,8 @@ static int ppc_440x_eth_rx (struct eth_device *dev)
length = hw_p->rx[user_index].data_len;
/* Pass the packet up to the protocol layers. */
- /* NetReceive(NetRxPackets[rxIdx], length - 4); */
- /* NetReceive(NetRxPackets[i], length); */
+ /* NetReceive(NetRxPackets[rxIdx], length - 4); */
+ /* NetReceive(NetRxPackets[i], length); */
NetReceive (NetRxPackets[user_index], length - 4);
/* Free Recv Buffer */
hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
@@ -1188,24 +1338,24 @@ static int ppc_440x_eth_rx (struct eth_device *dev)
if (NUM_RX_BUFF == hw_p->rx_u_index)
hw_p->rx_u_index = 0;
-#ifdef INFO_440_ENET
+#ifdef INFO_4XX_ENET
hw_p->stats.pkts_handled++;
#endif
mtmsr (msr); /* Enable IRQ's */
}
- hw_p->is_receiving = 0; /* tell driver */
+ hw_p->is_receiving = 0; /* tell driver */
return length;
}
-int ppc_440x_eth_initialize (bd_t * bis)
+int ppc_4xx_eth_initialize (bd_t * bis)
{
static int virgin = 0;
struct eth_device *dev;
int eth_num = 0;
- EMAC_440GX_HW_PST hw = NULL;
+ EMAC_4XX_HW_PST hw = NULL;
#if defined(CONFIG_440GX)
unsigned long pfc1;
@@ -1229,11 +1379,11 @@ int ppc_440x_eth_initialize (bd_t * bis)
bis->bi_phymode[3] = 2;
#if defined (CONFIG_440GX)
- ppc_440x_eth_setup_bridge(0, bis);
+ ppc_4xx_eth_setup_bridge(0, bis);
#endif
#endif
- for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
+ for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
/* See if we can actually bring up the interface, otherwise, skip it */
switch (eth_num) {
@@ -1273,16 +1423,16 @@ int ppc_440x_eth_initialize (bd_t * bis)
/* Allocate device structure */
dev = (struct eth_device *) malloc (sizeof (*dev));
if (dev == NULL) {
- printf ("ppc_440x_eth_initialize: "
+ printf ("ppc_4xx_eth_initialize: "
"Cannot allocate eth_device %d\n", eth_num);
return (-1);
}
memset(dev, 0, sizeof(*dev));
/* Allocate our private use data */
- hw = (EMAC_440GX_HW_PST) malloc (sizeof (*hw));
+ hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
if (hw == NULL) {
- printf ("ppc_440x_eth_initialize: "
+ printf ("ppc_4xx_eth_initialize: "
"Cannot allocate private hw data for eth_device %d",
eth_num);
free (dev);
@@ -1319,12 +1469,12 @@ int ppc_440x_eth_initialize (bd_t * bis)
hw->devnum = eth_num;
hw->print_speed = 1;
- sprintf (dev->name, "ppc_440x_eth%d", eth_num);
+ sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
dev->priv = (void *) hw;
- dev->init = ppc_440x_eth_init;
- dev->halt = ppc_440x_eth_halt;
- dev->send = ppc_440x_eth_send;
- dev->recv = ppc_440x_eth_rx;
+ dev->init = ppc_4xx_eth_init;
+ dev->halt = ppc_4xx_eth_halt;
+ dev->send = ppc_4xx_eth_send;
+ dev->recv = ppc_4xx_eth_rx;
if (0 == virgin) {
/* set the MAL IER ??? names may change with new spec ??? */
@@ -1355,9 +1505,60 @@ int ppc_440x_eth_initialize (bd_t * bis)
virgin = 1;
}
+#if defined(CONFIG_NET_MULTI)
eth_register (dev);
+#else
+ emac0_dev = dev;
+#endif
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register (dev->name,
+ emac4xx_miiphy_read, emac4xx_miiphy_write);
+#endif
} /* end for each supported device */
return (1);
}
-#endif /* CONFIG_440 && CONFIG_NET_MULTI */
+
+
+#if !defined(CONFIG_NET_MULTI)
+void eth_halt (void) {
+ if (emac0_dev) {
+ ppc_4xx_eth_halt(emac0_dev);
+ free(emac0_dev);
+ emac0_dev = NULL;
+ }
+}
+
+int eth_init (bd_t *bis)
+{
+ ppc_4xx_eth_initialize(bis);
+ if (emac0_dev) {
+ return ppc_4xx_eth_init(emac0_dev, bis);
+ } else {
+ printf("ERROR: ethaddr not set!\n");
+ return -1;
+ }
+}
+
+int eth_send(volatile void *packet, int length)
+{
+ return (ppc_4xx_eth_send(emac0_dev, packet, length));
+}
+
+int eth_rx(void)
+{
+ return (ppc_4xx_eth_rx(emac0_dev));
+}
+
+int emac4xx_miiphy_initialize (bd_t * bis)
+{
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register ("ppc_4xx_eth0",
+ emac4xx_miiphy_read, emac4xx_miiphy_write);
+#endif
+
+ return 0;
+}
+#endif /* !defined(CONFIG_NET_MULTI) */
+
+#endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index 5b16754c50..c563457005 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -27,10 +27,10 @@ LIB = lib$(CPU).a
START = start.o resetvec.o kgdb.o
AOBJS = dcr.o
-COBJS = 405gp_enet.o 405gp_pci.o 440gx_enet.o \
+COBJS = 405gp_pci.o 4xx_enet.o \
bedbug_405.o commproc.o \
cpu.o cpu_init.o i2c.o interrupts.o \
- miiphy.o miiphy_440.o sdram.o serial.o \
+ miiphy.o sdram.o serial.o \
spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o
OBJS = $(AOBJS) $(COBJS)
diff --git a/cpu/ppc4xx/bedbug_405.c b/cpu/ppc4xx/bedbug_405.c
index 23752f3940..a3c2119764 100644
--- a/cpu/ppc4xx/bedbug_405.c
+++ b/cpu/ppc4xx/bedbug_405.c
@@ -25,7 +25,7 @@ int bedbug405_clear __P ((int));
/* ======================================================================
- * Initialize the global bug_ctx structure for the IBM PPC405. Clear all
+ * Initialize the global bug_ctx structure for the AMCC PPC405. Clear all
* of the breakpoints.
* ====================================================================== */
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index a9bb89ad0a..a26533c59c 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -39,121 +39,146 @@
#if defined(CONFIG_440)
-static int do_chip_reset( unsigned long sys0, unsigned long sys1 );
+#define FREQ_EBC (sys_info.freqEPB)
+#else
+#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv)
#endif
-/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
-int checkcpu (void)
+#define PCI_ASYNC
+
+int pci_async_enabled(void)
{
-#if defined(CONFIG_405GP) || \
- defined(CONFIG_405CR) || \
- defined(CONFIG_405EP) || \
- defined(CONFIG_440) || \
- defined(CONFIG_IOP480)
- uint pvr = get_pvr();
+#if defined(CONFIG_405GP)
+ return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
#endif
-#if defined(CONFIG_405GP) || \
- defined(CONFIG_405CR) || \
- defined(CONFIG_405EP) || \
- defined(CONFIG_IOP480)
- DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+ unsigned long val;
+
+ mfsdr(sdr_sdstp1, val);
+ return (val & SDR0_SDSTP1_PAME_MASK);
+#endif
+}
+#endif
+
+#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405)
+int pci_arbiter_enabled(void)
+{
+#if defined(CONFIG_405GP)
+ return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
+#endif
+
+#if defined(CONFIG_405EP)
+ return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
+#endif
+
+#if defined(CONFIG_440GP)
+ return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+ unsigned long val;
+
+ mfsdr(sdr_sdstp1, val);
+ return (val & SDR0_SDSTP1_PAE_MASK);
+#endif
+}
+#endif
+
+#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440GX) || defined(CONFIG_440SP)
+
+#define I2C_BOOTROM
+
+int i2c_bootrom_enabled(void)
+{
+#if defined(CONFIG_405EP)
+ return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+ unsigned long val;
+
+ mfsdr(sdr_sdcs, val);
+ return (val & SDR0_SDCS_SDD);
+#endif
+}
+#endif
+
+
+#if defined(CONFIG_440)
+static int do_chip_reset(unsigned long sys0, unsigned long sys1);
+#endif
+
+
+int checkcpu (void)
+{
+#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
+ DECLARE_GLOBAL_DATA_PTR;
+ uint pvr = get_pvr();
ulong clock = gd->cpu_clk;
char buf[32];
-#endif
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
- PPC405_SYS_INFO sys_info;
+#if !defined(CONFIG_IOP480)
+ sys_info_t sys_info;
puts ("CPU: ");
get_sys_info(&sys_info);
-#ifdef CONFIG_405GP
- puts ("AMCC PowerPC 405GP");
- if (pvr == PVR_405GPR_RB) {
- putc('r');
- }
- puts (" Rev. ");
-#endif
-#ifdef CONFIG_405CR
- puts ("AMCC PowerPC 405CR Rev. ");
+ puts("AMCC PowerPC 4");
+
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
+ puts("05");
#endif
-#ifdef CONFIG_405EP
- puts ("AMCC PowerPC 405EP Rev. ");
+#if defined(CONFIG_440)
+ puts("40");
#endif
+
switch (pvr) {
case PVR_405GP_RB:
- case PVR_405GPR_RB:
- putc('B');
+ puts("GP Rev. B");
break;
+
case PVR_405GP_RC:
-#ifdef CONFIG_405CR
- case PVR_405CR_RC:
-#endif
- putc('C');
+ puts("GP Rev. C");
break;
+
case PVR_405GP_RD:
- putc('D');
+ puts("GP Rev. D");
break;
+
#ifdef CONFIG_405GP
- case PVR_405GP_RE:
- putc('E');
+ case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
+ puts("GP Rev. E");
break;
#endif
+
case PVR_405CR_RA:
- putc('A');
+ puts("CR Rev. A");
break;
+
case PVR_405CR_RB:
- case PVR_405EP_RB:
- putc('B');
+ puts("CR Rev. B");
break;
- default:
- printf ("? (PVR=%08x)", pvr);
- break;
- }
- printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
- sys_info.freqPLB / 1000000,
- sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
- sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000);
-
-#if defined(CONFIG_405GP)
- if (mfdcr(strap) & PSR_PCI_ASYNC_EN) {
- printf (" PCI async ext clock used, ");
- } else {
- printf (" PCI sync clock at %lu MHz, ",
- sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
- }
- printf ("%sternal PCI arbiter enabled\n",
- (mfdcr(strap) & PSR_PCI_ARBIT_EN) ? "in" : "ex");
-#elif defined(CONFIG_405EP)
- printf (" IIC Boot EEPROM %sabled\n",
- (mfdcr(cpc0_boot) & CPC0_BOOT_SEP) ? "en" : "dis");
- printf (" PCI async ext clock used, ");
- printf ("%sternal PCI arbiter enabled\n",
- (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN) ? "in" : "ex");
+#ifdef CONFIG_405CR
+ case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
+ puts("CR Rev. C");
+ break;
#endif
-#if defined(CONFIG_405EP)
- printf (" 16 kB I-Cache 16 kB D-Cache");
-#else
- printf (" 16 kB I-Cache %d kB D-Cache",
- ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
-#endif
-#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
+ case PVR_405GPR_RB:
+ puts("GPr Rev. B");
+ break;
-#ifdef CONFIG_IOP480
- printf ("PLX IOP480 (PVR=%08x)", pvr);
- printf (" at %s MHz:", strmhz(buf, clock));
- printf (" %u kB I-Cache", 4);
- printf (" %u kB D-Cache", 2);
-#endif
+ case PVR_405EP_RB:
+ puts("EP Rev. B");
+ break;
#if defined(CONFIG_440)
- puts ("AMCC PowerPC 440");
- switch(pvr) {
case PVR_440GP_RB:
puts("GP Rev. B");
/* See errata 1.12: CHIP_4 */
@@ -166,40 +191,103 @@ int checkcpu (void)
mfdcr(cpc0_strp1) );
}
break;
+
case PVR_440GP_RC:
puts("GP Rev. C");
break;
+
case PVR_440GX_RA:
puts("GX Rev. A");
break;
+
case PVR_440GX_RB:
puts("GX Rev. B");
break;
+
case PVR_440GX_RC:
puts("GX Rev. C");
break;
-#if defined(CONFIG_440GR)
- case PVR_440EP_RA:
- puts("GR Rev. A");
- break;
- case PVR_440EP_RB:
- puts("GR Rev. B");
+
+ case PVR_440GX_RF:
+ puts("GX Rev. F");
break;
-#else
+
case PVR_440EP_RA:
puts("EP Rev. A");
break;
- case PVR_440EP_RB:
+
+#ifdef CONFIG_440EP
+ case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
puts("EP Rev. B");
break;
-#endif
+#endif /* CONFIG_440EP */
+
+#ifdef CONFIG_440GR
+ case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
+ puts("GR Rev. A");
+ break;
+#endif /* CONFIG_440GR */
+#endif /* CONFIG_440 */
+
+ case PVR_440SP_RA:
+ puts("SP Rev. A");
+ break;
+
+ case PVR_440SP_RB:
+ puts("SP Rev. B");
+ break;
default:
printf (" UNKNOWN (PVR=%08x)", pvr);
break;
}
+
+ printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
+ sys_info.freqPLB / 1000000,
+ sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
+ FREQ_EBC / 1000000);
+
+#if defined(I2C_BOOTROM)
+ printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
+#endif
+
+#if defined(CONFIG_PCI)
+ printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
+#endif
+
+#if defined(PCI_ASYNC)
+ if (pci_async_enabled()) {
+ printf (", PCI async ext clock used");
+ } else {
+ printf (", PCI sync clock at %lu MHz",
+ sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
+ }
+#endif
+
+#if defined(CONFIG_PCI)
+ putc('\n');
#endif
- puts ("\n");
+
+#if defined(CONFIG_405EP)
+ printf (" 16 kB I-Cache 16 kB D-Cache");
+#elif defined(CONFIG_440)
+ printf (" 32 kB I-Cache 32 kB D-Cache");
+#else
+ printf (" 16 kB I-Cache %d kB D-Cache",
+ ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
+#endif
+#endif /* !defined(CONFIG_IOP480) */
+
+#if defined(CONFIG_IOP480)
+ printf ("PLX IOP480 (PVR=%08x)", pvr);
+ printf (" at %s MHz:", strmhz(buf, clock));
+ printf (" %u kB I-Cache", 4);
+ printf (" %u kB D-Cache", 2);
+#endif
+
+#endif /* !defined(CONFIG_405) */
+
+ putc ('\n');
return 0;
}
@@ -230,8 +318,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
#if defined(CONFIG_440)
-static
-int do_chip_reset (unsigned long sys0, unsigned long sys1)
+static int do_chip_reset (unsigned long sys0, unsigned long sys1)
{
/* Changes to cpc0_sys0 and cpc0_sys1 require chip
* reset.
@@ -252,31 +339,13 @@ int do_chip_reset (unsigned long sys0, unsigned long sys1)
*/
unsigned long get_tbclk (void)
{
-#if defined(CONFIG_440)
-
+#if !defined(CONFIG_IOP480)
sys_info_t sys_info;
get_sys_info(&sys_info);
return (sys_info.freqProcessor);
-
-#elif defined(CONFIG_405GP) || \
- defined(CONFIG_405CR) || \
- defined(CONFIG_405) || \
- defined(CONFIG_405EP)
-
- PPC405_SYS_INFO sys_info;
-
- get_sys_info(&sys_info);
- return (sys_info.freqProcessor);
-
-#elif defined(CONFIG_IOP480)
-
- return (66000000);
-
#else
-
-# error get_tbclk() not implemented
-
+ return (66000000);
#endif
}
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 68e1a450ca..79cfba3a45 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -23,7 +23,7 @@
#include <common.h>
#include <watchdog.h>
-#include <405gp_enet.h>
+#include <ppc4xx_enet.h>
#include <asm/processor.h>
#include <ppc4xx.h>
diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
index 3a644a4cc4..be94b571ff 100644
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -428,7 +428,7 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
*/
uchar i2c_reg_read(uchar i2c_addr, uchar reg)
{
- char buf;
+ uchar buf;
i2c_read(i2c_addr, reg, 1, &buf, 1);
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index cb9dccdc35..f26f2a203a 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -1,42 +1,44 @@
/*-----------------------------------------------------------------------------+
|
- | This source code has been made available to you by IBM on an AS-IS
- | basis. Anyone receiving this source is licensed under IBM
- | copyrights to use it in any way he or she deems fit, including
- | copying it, modifying it, compiling it, and redistributing it either
- | with or without modifications. No license under IBM patents or
- | patent applications is to be implied by the copyright license.
+ | This source code has been made available to you by IBM on an AS-IS
+ | basis. Anyone receiving this source is licensed under IBM
+ | copyrights to use it in any way he or she deems fit, including
+ | copying it, modifying it, compiling it, and redistributing it either
+ | with or without modifications. No license under IBM patents or
+ | patent applications is to be implied by the copyright license.
|
- | Any user of this software should understand that IBM cannot provide
- | technical support for this software and will not be responsible for
- | any consequences resulting from the use of this software.
+ | Any user of this software should understand that IBM cannot provide
+ | technical support for this software and will not be responsible for
+ | any consequences resulting from the use of this software.
|
- | Any person who transfers this source code or any derivative work
- | must include the IBM copyright notice, this paragraph, and the
- | preceding two paragraphs in the transferred software.
+ | Any person who transfers this source code or any derivative work
+ | must include the IBM copyright notice, this paragraph, and the
+ | preceding two paragraphs in the transferred software.
|
- | COPYRIGHT I B M CORPORATION 1995
- | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+ | COPYRIGHT I B M CORPORATION 1995
+ | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+-----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------+
|
- | File Name: miiphy.c
+ | File Name: miiphy.c
|
- | Function: This module has utilities for accessing the MII PHY through
+ | Function: This module has utilities for accessing the MII PHY through
| the EMAC3 macro.
|
- | Author: Mark Wisner
+ | Author: Mark Wisner
|
| Change Activity-
|
- | Date Description of Change BY
- | --------- --------------------- ---
- | 05-May-99 Created MKW
- | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
- | better match OPB speed. Also modified delay times. JWB
- | 29-Jul-99 Added Full duplex support MKW
- | 24-Aug-99 Removed printf from dp83843_duplex() JWB
- | 19-Jul-00 Ported to esd cpci405 sr
+ | Date Description of Change BY
+ | --------- --------------------- ---
+ | 05-May-99 Created MKW
+ | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
+ | better match OPB speed. Also modified delay times. JWB
+ | 29-Jul-99 Added Full duplex support MKW
+ | 24-Aug-99 Removed printf from dp83843_duplex() JWB
+ | 19-Jul-00 Ported to esd cpci405 sr
+ | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
+ | <travis.sawyer@sandburst.com>
|
+-----------------------------------------------------------------------------*/
@@ -44,25 +46,23 @@
#include <asm/processor.h>
#include <ppc_asm.tmpl>
#include <commproc.h>
-#include <405gp_enet.h>
+#include <ppc4xx_enet.h>
#include <405_mal.h>
#include <miiphy.h>
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
- (defined(CONFIG_440) && !defined(CONFIG_NET_MULTI))
/***********************************************************/
-/* Dump out to the screen PHY regs */
+/* Dump out to the screen PHY regs */
/***********************************************************/
-void miiphy_dump (unsigned char addr)
+void miiphy_dump (char *devname, unsigned char addr)
{
unsigned long i;
unsigned short data;
for (i = 0; i < 0x1A; i++) {
- if (miiphy_read (addr, i, &data)) {
+ if (miiphy_read (devname, addr, i, &data)) {
printf ("read error for reg %lx\n", i);
return;
}
@@ -72,75 +72,128 @@ void miiphy_dump (unsigned char addr)
if (i == 0x07)
i = 0x0f;
- } /* end for loop */
-} /* end dump */
+ } /* end for loop */
+} /* end dump */
/***********************************************************/
-/* read a phy reg and return the value with a rc */
-/* Note: We are referencing to EMAC_STACR register */
-/* @(EMAC_BASE + 92) because of: */
-/* - 405EP has only STACR for EMAC0 pinned out */
-/* - 405GP has onle one EMAC0 */
-/* - For 440 this module gets compiled only for */
-/* !CONFIG_NET_MULTI, i.e. only EMAC0 is supported. */
+/* (Re)start autonegotiation */
/***********************************************************/
+int phy_setup_aneg (char *devname, unsigned char addr)
+{
+ unsigned short ctl, adv;
+
+ /* Setup standard advertise */
+ miiphy_read (devname, addr, PHY_ANAR, &adv);
+ adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
+ PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
+ PHY_ANLPAR_10);
+ miiphy_write (devname, addr, PHY_ANAR, adv);
-int miiphy_read (unsigned char addr, unsigned char reg,
- unsigned short *value)
+ /* Start/Restart aneg */
+ miiphy_read (devname, addr, PHY_BMCR, &ctl);
+ ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+ miiphy_write (devname, addr, PHY_BMCR, ctl);
+
+ return 0;
+}
+
+
+/***********************************************************/
+/* read a phy reg and return the value with a rc */
+/***********************************************************/
+unsigned int miiphy_getemac_offset (void)
{
- unsigned long sta_reg; /* STA scratch area */
+#if (defined(CONFIG_440) && !defined(CONFIG_440SP)) && defined(CONFIG_NET_MULTI)
+ unsigned long zmii;
+ unsigned long eoffset;
+
+ /* Need to find out which mdi port we're using */
+ zmii = in32 (ZMII_FER);
+
+ if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
+ /* using port 0 */
+ eoffset = 0;
+ } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
+ /* using port 1 */
+ eoffset = 0x100;
+ } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
+ /* using port 2 */
+ eoffset = 0x400;
+ } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
+ /* using port 3 */
+ eoffset = 0x600;
+ } else {
+ /* None of the mdi ports are enabled! */
+ /* enable port 0 */
+ zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
+ out32 (ZMII_FER, zmii);
+ eoffset = 0;
+ /* need to soft reset port 0 */
+ zmii = in32 (EMAC_M0);
+ zmii |= EMAC_M0_SRST;
+ out32 (EMAC_M0, zmii);
+ }
+
+ return (eoffset);
+#else
+ return 0;
+#endif
+}
+
+
+int emac4xx_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
+{
+ unsigned long sta_reg; /* STA scratch area */
unsigned long i;
+ unsigned long emac_reg;
+
+ emac_reg = miiphy_getemac_offset ();
/* see if it is ready for 1000 nsec */
i = 0;
/* see if it is ready for sec */
- while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) {
+ while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
udelay (7);
if (i > 5) {
-#if 0 /* test-only */
+#if 0
printf ("read err 1\n");
#endif
return -1;
}
i++;
}
- sta_reg = reg; /* reg address */
+ sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
+#if defined(CONFIG_440GX)
+ sta_reg |= EMAC_STACR_READ;
+#else
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
-#ifdef CONFIG_PHY_CLK_FREQ
+#endif
+
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
#endif
sta_reg = sta_reg | (addr << 5); /* Phy address */
- out32 (EMAC_STACR, sta_reg);
-#if 0 /* test-only */
+ out32 (EMAC_STACR + emac_reg, sta_reg);
+#if 0 /* test-only */
printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
#endif
-#ifdef CONFIG_PHY_CMD_DELAY
- udelay (CONFIG_PHY_CMD_DELAY); /* Intel LXT971A needs this */
-#endif
- sta_reg = in32 (EMAC_STACR);
+ sta_reg = in32 (EMAC_STACR + emac_reg);
i = 0;
while ((sta_reg & EMAC_STACR_OC) == 0) {
udelay (7);
if (i > 5) {
-#if 0 /* test-only */
- printf ("read err 2\n");
-#endif
return -1;
}
i++;
- sta_reg = in32 (EMAC_STACR);
+ sta_reg = in32 (EMAC_STACR + emac_reg);
}
if ((sta_reg & EMAC_STACR_PHYE) != 0) {
-#if 0 /* test-only */
- printf ("read err 3\n");
- printf ("a2: read: EMAC_STACR=0x%0lx, i=%d\n",
- sta_reg, (int) i); /* test-only */
-#endif
return -1;
}
@@ -148,58 +201,60 @@ int miiphy_read (unsigned char addr, unsigned char reg,
return 0;
-} /* phy_read */
+} /* phy_read */
/***********************************************************/
-/* write a phy reg and return the value with a rc */
+/* write a phy reg and return the value with a rc */
/***********************************************************/
-int miiphy_write (unsigned char addr, unsigned char reg,
- unsigned short value)
+int emac4xx_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
- unsigned long sta_reg; /* STA scratch area */
+ unsigned long sta_reg; /* STA scratch area */
unsigned long i;
+ unsigned long emac_reg;
+ emac_reg = miiphy_getemac_offset ();
/* see if it is ready for 1000 nsec */
i = 0;
- while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) {
+ while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
if (i > 5)
return -1;
udelay (7);
i++;
}
sta_reg = 0;
- sta_reg = reg; /* reg address */
+ sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
+#if defined(CONFIG_440GX)
+ sta_reg |= EMAC_STACR_WRITE;
+#else
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
-#ifdef CONFIG_PHY_CLK_FREQ
- sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
+#endif
+
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
+ sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
#endif
sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
memcpy (&sta_reg, &value, 2); /* put in data */
- out32 (EMAC_STACR, sta_reg);
+ out32 (EMAC_STACR + emac_reg, sta_reg);
-#ifdef CONFIG_PHY_CMD_DELAY
- udelay (CONFIG_PHY_CMD_DELAY); /* Intel LXT971A needs this */
-#endif
/* wait for completion */
i = 0;
- sta_reg = in32 (EMAC_STACR);
+ sta_reg = in32 (EMAC_STACR + emac_reg);
while ((sta_reg & EMAC_STACR_OC) == 0) {
udelay (7);
if (i > 5)
return -1;
i++;
- sta_reg = in32 (EMAC_STACR);
+ sta_reg = in32 (EMAC_STACR + emac_reg);
}
if ((sta_reg & EMAC_STACR_PHYE) != 0)
return -1;
return 0;
-} /* phy_read */
-
-#endif /* CONFIG_405GP */
+} /* phy_write */
diff --git a/cpu/ppc4xx/miiphy_440.c b/cpu/ppc4xx/miiphy_440.c
deleted file mode 100644
index 6320feaba7..0000000000
--- a/cpu/ppc4xx/miiphy_440.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/*-----------------------------------------------------------------------------+
- |
- | This source code has been made available to you by IBM on an AS-IS
- | basis. Anyone receiving this source is licensed under IBM
- | copyrights to use it in any way he or she deems fit, including
- | copying it, modifying it, compiling it, and redistributing it either
- | with or without modifications. No license under IBM patents or
- | patent applications is to be implied by the copyright license.
- |
- | Any user of this software should understand that IBM cannot provide
- | technical support for this software and will not be responsible for
- | any consequences resulting from the use of this software.
- |
- | Any person who transfers this source code or any derivative work
- | must include the IBM copyright notice, this paragraph, and the
- | preceding two paragraphs in the transferred software.
- |
- | COPYRIGHT I B M CORPORATION 1995
- | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
- +-----------------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------------+
- |
- | File Name: miiphy.c
- |
- | Function: This module has utilities for accessing the MII PHY through
- | the EMAC3 macro.
- |
- | Author: Mark Wisner
- |
- | Change Activity-
- |
- | Date Description of Change BY
- | --------- --------------------- ---
- | 05-May-99 Created MKW
- | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to
- | better match OPB speed. Also modified delay times. JWB
- | 29-Jul-99 Added Full duplex support MKW
- | 24-Aug-99 Removed printf from dp83843_duplex() JWB
- | 19-Jul-00 Ported to esd cpci405 sr
- | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
- | <travis.sawyer@sandburst.com>
- |
- +-----------------------------------------------------------------------------*/
-
-#include <common.h>
-#include <asm/processor.h>
-#include <ppc_asm.tmpl>
-#include <commproc.h>
-#include <440gx_enet.h>
-#include <405_mal.h>
-#include <miiphy.h>
-
-#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
-
-
-/***********************************************************/
-/* Dump out to the screen PHY regs */
-/***********************************************************/
-
-void miiphy_dump (unsigned char addr)
-{
- unsigned long i;
- unsigned short data;
-
-
- for (i = 0; i < 0x1A; i++) {
- if (miiphy_read (addr, i, &data)) {
- printf ("read error for reg %lx\n", i);
- return;
- }
- printf ("Phy reg %lx ==> %4x\n", i, data);
-
- /* jump to the next set of regs */
- if (i == 0x07)
- i = 0x0f;
-
- } /* end for loop */
-} /* end dump */
-
-
-/***********************************************************/
-/* (Re)start autonegotiation */
-/***********************************************************/
-int phy_setup_aneg (unsigned char addr)
-{
- unsigned short ctl, adv;
-
- /* Setup standard advertise */
- miiphy_read (addr, PHY_ANAR, &adv);
- adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
- PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
- PHY_ANLPAR_10);
- miiphy_write (addr, PHY_ANAR, adv);
-
- /* Start/Restart aneg */
- miiphy_read (addr, PHY_BMCR, &ctl);
- ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
- miiphy_write (addr, PHY_BMCR, ctl);
-
- return 0;
-}
-
-
-/***********************************************************/
-/* read a phy reg and return the value with a rc */
-/***********************************************************/
-unsigned int miiphy_getemac_offset (void)
-{
- unsigned long zmii;
- unsigned long eoffset;
-
- /* Need to find out which mdi port we're using */
- zmii = in32 (ZMII_FER);
-
- if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) {
- /* using port 0 */
- eoffset = 0;
- } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) {
- /* using port 1 */
- eoffset = 0x100;
- } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) {
- /* using port 2 */
- eoffset = 0x400;
- } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) {
- /* using port 3 */
- eoffset = 0x600;
- } else {
- /* None of the mdi ports are enabled! */
- /* enable port 0 */
- zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
- out32 (ZMII_FER, zmii);
- eoffset = 0;
- /* need to soft reset port 0 */
- zmii = in32 (EMAC_M0);
- zmii |= EMAC_M0_SRST;
- out32 (EMAC_M0, zmii);
- }
-
- return (eoffset);
-
-}
-
-
-int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
-{
- unsigned long sta_reg; /* STA scratch area */
- unsigned long i;
- unsigned long emac_reg;
-
-
- emac_reg = miiphy_getemac_offset ();
- /* see if it is ready for 1000 nsec */
- i = 0;
-
- /* see if it is ready for sec */
- while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
- udelay (7);
- if (i > 5) {
-#if 0
- printf ("read err 1\n");
-#endif
- return -1;
- }
- i++;
- }
- sta_reg = reg; /* reg address */
- /* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX)
- sta_reg |= EMAC_STACR_READ;
-#else
- sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
-#endif
-
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
- sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
-#endif
- sta_reg = sta_reg | (addr << 5); /* Phy address */
-
- out32 (EMAC_STACR + emac_reg, sta_reg);
-#if 0 /* test-only */
- printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
-#endif
-
- sta_reg = in32 (EMAC_STACR + emac_reg);
- i = 0;
- while ((sta_reg & EMAC_STACR_OC) == 0) {
- udelay (7);
- if (i > 5) {
- return -1;
- }
- i++;
- sta_reg = in32 (EMAC_STACR + emac_reg);
- }
- if ((sta_reg & EMAC_STACR_PHYE) != 0) {
- return -1;
- }
-
- *value = *(short *) (&sta_reg);
- return 0;
-
-
-} /* phy_read */
-
-
-/***********************************************************/
-/* write a phy reg and return the value with a rc */
-/***********************************************************/
-
-int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
-{
- unsigned long sta_reg; /* STA scratch area */
- unsigned long i;
- unsigned long emac_reg;
-
- emac_reg = miiphy_getemac_offset ();
- /* see if it is ready for 1000 nsec */
- i = 0;
-
- while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) {
- if (i > 5)
- return -1;
- udelay (7);
- i++;
- }
- sta_reg = 0;
- sta_reg = reg; /* reg address */
- /* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX)
- sta_reg |= EMAC_STACR_WRITE;
-#else
- sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
-#endif
-
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX)
- sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
-#endif
- sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
- memcpy (&sta_reg, &value, 2); /* put in data */
-
- out32 (EMAC_STACR + emac_reg, sta_reg);
-
- /* wait for completion */
- i = 0;
- sta_reg = in32 (EMAC_STACR + emac_reg);
- while ((sta_reg & EMAC_STACR_OC) == 0) {
- udelay (7);
- if (i > 5)
- return -1;
- i++;
- sta_reg = in32 (EMAC_STACR + emac_reg);
- }
-
- if ((sta_reg & EMAC_STACR_PHYE) != 0)
- return -1;
- return 0;
-
-} /* phy_write */
-
-#endif /* CONFIG_405GP */
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index d1ad21203d..e9548cdcf3 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -1,4 +1,7 @@
/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* (C) Copyright 2002-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
@@ -39,6 +42,7 @@ struct sdram_conf_s {
typedef struct sdram_conf_s sdram_conf_t;
+#ifndef CFG_SDRAM_TABLE
sdram_conf_t mb0cf[] = {
{(128 << 20), 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */
{(64 << 20), 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */
@@ -46,9 +50,18 @@ sdram_conf_t mb0cf[] = {
{(16 << 20), 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */
{(4 << 20), 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */
};
+#else
+sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
+#endif
+
#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#ifndef CONFIG_440
+
+/*
+ * Autodetect onboard SDRAM on 405 platforms
+ */
void sdram_init(void)
{
ulong sdtr1;
@@ -105,4 +118,61 @@ void sdram_init(void)
}
}
+#else /* CONFIG_440 */
+
+/*
+ * Autodetect onboard DDR SDRAM on 440 platforms
+ *
+ * NOTE: Some of the hardcoded values are hardware dependant,
+ * so this should be extended for other future boards
+ * using this routine!
+ */
+long int initdram(int board_type)
+{
+ int i;
+
+ for (i=0; i<N_MB0CF; i++) {
+ /*
+ * Disable memory controller.
+ */
+ mtsdram(mem_cfg0, 0x00000000);
+
+ /*
+ * Setup some default
+ */
+ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
+ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram(mem_b0cr, mb0cf[i].reg);
+ mtsdram(mem_tr0, 0x41094012);
+ mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
+ mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20µs @ 133MHz PLB*/
+ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
+ udelay(400); /* Delay 200 usecs (min) */
+
+ /*
+ * Enable the controller, then wait for DCEN to complete
+ */
+ mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ udelay(10000);
+
+ if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
+ /*
+ * OK, size detected -> all done
+ */
+ return mb0cf[i].size;
+ }
+ }
+
+ return 0; /* nothing found ! */
+}
+
+#endif /* CONFIG_440 */
+
#endif /* CONFIG_SDRAM_BANK0 */
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index 8cf7dab3a2..e7f6bcbe1e 100644
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -276,7 +276,12 @@ int serial_tstc ()
#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
#endif
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+#if defined(CONFIG_440SP)
+#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#define CR0_MASK 0xdfffffff
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
@@ -306,21 +311,21 @@ int serial_tstc ()
#if defined(CONFIG_UART1_CONSOLE)
#define ACTING_UART0_BASE UART1_BASE
#define ACTING_UART1_BASE UART0_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#define UART0_SDR sdr_uart1
#define UART1_SDR sdr_uart0
#endif /* CONFIG_440GX */
#else
#define ACTING_UART0_BASE UART0_BASE
#define ACTING_UART1_BASE UART1_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#endif /* CONFIG_440GX */
#endif
#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
-#error "External serial clock not supported on IBM PPC405EP!"
+#error "External serial clock not supported on AMCC PPC405EP!"
#endif
#define UART_RBR 0x00
@@ -436,7 +441,7 @@ int serial_init(void)
unsigned long tmp;
#endif
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
mfsdr(UART0_SDR,reg);
@@ -465,7 +470,7 @@ int serial_init(void)
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
#if defined(CONFIG_SERIAL_MULTI)
if (UART0_BASE == dev_base) {
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
index a8cfcd4e75..ebd5f3998f 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -14,7 +14,7 @@
*
* (C) Copyright 2002
* Jun Gu, Artesyn Technology, jung@artesyncp.com
- * Support for IBM 440 based on OpenBIOS draminit.c from IBM.
+ * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
@@ -48,49 +48,49 @@
/*
* Set default values
*/
-#ifndef CFG_I2C_SPEED
-#define CFG_I2C_SPEED 50000
+#ifndef CFG_I2C_SPEED
+#define CFG_I2C_SPEED 50000
#endif
-#ifndef CFG_I2C_SLAVE
-#define CFG_I2C_SLAVE 0xFE
+#ifndef CFG_I2C_SLAVE
+#define CFG_I2C_SLAVE 0xFE
#endif
-#define ONE_BILLION 1000000000
+#define ONE_BILLION 1000000000
-#ifndef CONFIG_440 /* for 405 WALNUT/SYCAMORE/BUBINGA boards */
+#ifndef CONFIG_440 /* for 405 WALNUT/SYCAMORE/BUBINGA boards */
-#define SDRAM0_CFG_DCE 0x80000000
-#define SDRAM0_CFG_SRE 0x40000000
-#define SDRAM0_CFG_PME 0x20000000
-#define SDRAM0_CFG_MEMCHK 0x10000000
-#define SDRAM0_CFG_REGEN 0x08000000
-#define SDRAM0_CFG_ECCDD 0x00400000
-#define SDRAM0_CFG_EMDULR 0x00200000
-#define SDRAM0_CFG_DRW_SHIFT (31-6)
-#define SDRAM0_CFG_BRPF_SHIFT (31-8)
+#define SDRAM0_CFG_DCE 0x80000000
+#define SDRAM0_CFG_SRE 0x40000000
+#define SDRAM0_CFG_PME 0x20000000
+#define SDRAM0_CFG_MEMCHK 0x10000000
+#define SDRAM0_CFG_REGEN 0x08000000
+#define SDRAM0_CFG_ECCDD 0x00400000
+#define SDRAM0_CFG_EMDULR 0x00200000
+#define SDRAM0_CFG_DRW_SHIFT (31-6)
+#define SDRAM0_CFG_BRPF_SHIFT (31-8)
-#define SDRAM0_TR_CASL_SHIFT (31-8)
-#define SDRAM0_TR_PTA_SHIFT (31-13)
-#define SDRAM0_TR_CTP_SHIFT (31-15)
-#define SDRAM0_TR_LDF_SHIFT (31-17)
-#define SDRAM0_TR_RFTA_SHIFT (31-29)
-#define SDRAM0_TR_RCD_SHIFT (31-31)
+#define SDRAM0_TR_CASL_SHIFT (31-8)
+#define SDRAM0_TR_PTA_SHIFT (31-13)
+#define SDRAM0_TR_CTP_SHIFT (31-15)
+#define SDRAM0_TR_LDF_SHIFT (31-17)
+#define SDRAM0_TR_RFTA_SHIFT (31-29)
+#define SDRAM0_TR_RCD_SHIFT (31-31)
-#define SDRAM0_RTR_SHIFT (31-15)
-#define SDRAM0_ECCCFG_SHIFT (31-11)
+#define SDRAM0_RTR_SHIFT (31-15)
+#define SDRAM0_ECCCFG_SHIFT (31-11)
/* SDRAM0_CFG enable macro */
#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
-#define SDRAM0_BXCR_SZ_MASK 0x000e0000
-#define SDRAM0_BXCR_AM_MASK 0x0000e000
+#define SDRAM0_BXCR_SZ_MASK 0x000e0000
+#define SDRAM0_BXCR_AM_MASK 0x0000e000
-#define SDRAM0_BXCR_SZ_SHIFT (31-14)
-#define SDRAM0_BXCR_AM_SHIFT (31-18)
+#define SDRAM0_BXCR_SZ_SHIFT (31-14)
+#define SDRAM0_BXCR_AM_SHIFT (31-18)
-#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
-#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
+#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
+#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
#ifdef CONFIG_SPDDRAM_SILENT
# define SPD_ERR(x) do { return 0; } while (0)
@@ -108,7 +108,7 @@ int spd_read(uint addr);
* This function is reading data from the DIMM module EEPROM over the SPD bus
* and uses that to program the sdram controller.
*
- * This works on boards that has the same schematics that the IBM walnut has.
+ * This works on boards that has the same schematics that the AMCC walnut has.
*
* Input: null for default I2C spd functions or a pointer to a custom function
* returning spd_data.
@@ -175,7 +175,7 @@ long int spd_sdram(int(read_spd)(uint addr))
* data from DIMM:
* 27 IN Row Precharge Time ( t RP)
* 29 MIN RAS to CAS Delay ( t RCD)
- * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
+ * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
* -------------------------------------------------------------------*/
/*
@@ -184,18 +184,18 @@ long int spd_sdram(int(read_spd)(uint addr))
*/
tmp = read_spd(127) & 0x6;
- if (tmp == 0x02){ /* only cas = 2 supported */
+ if (tmp == 0x02) { /* only cas = 2 supported */
min_cas = 2;
-/* t_ck = read_spd(9); */
-/* t_ac = read_spd(10); */
- } else if (tmp == 0x04) { /* only cas = 3 supported */
+/* t_ck = read_spd(9); */
+/* t_ac = read_spd(10); */
+ } else if (tmp == 0x04) { /* only cas = 3 supported */
min_cas = 3;
-/* t_ck = read_spd(9); */
-/* t_ac = read_spd(10); */
- } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */
+/* t_ck = read_spd(9); */
+/* t_ac = read_spd(10); */
+ } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */
min_cas = 2;
-/* t_ck = read_spd(23); */
-/* t_ac = read_spd(24); */
+/* t_ck = read_spd(23); */
+/* t_ac = read_spd(24); */
} else {
SPD_ERR("SDRAM - unsupported CAS latency \n");
}
@@ -263,7 +263,7 @@ long int spd_sdram(int(read_spd)(uint addr))
}
/* convert from nsec to bus cycles */
tmp = (tmp * 10) / bus_period_x_10;
- sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT;
+ sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT;
/*------------------------------------------------------------------
* determine the number of banks used
@@ -292,7 +292,7 @@ long int spd_sdram(int(read_spd)(uint addr))
else if (tmp==4)
bank_cnt *= 4;
else
- bank_cnt = 8; /* 8 is an error code */
+ bank_cnt = 8; /* 8 is an error code */
if (bank_cnt > 4) /* we only have 4 banks to work with */
SPD_ERR("SDRAM - unsupported module rows for this width\n");
@@ -323,7 +323,7 @@ long int spd_sdram(int(read_spd)(uint addr))
total_size *= read_spd(5); /* mult by module rows (dimm sides) */
/*------------------------------------------------------------------
- * map rows * cols * banks to a mode
+ * map rows * cols * banks to a mode
* -------------------------------------------------------------------*/
switch (row) {
@@ -388,9 +388,9 @@ long int spd_sdram(int(read_spd)(uint addr))
bank_size = total_size / bank_cnt;
/* convert bank size to bank size code for ppc4xx
by takeing log2(bank_size) - 22 */
- tmp = bank_size; /* start with tmp = bank_size */
+ tmp = bank_size; /* start with tmp = bank_size */
bank_code = 0; /* and bank_code = 0 */
- while (tmp > 1) { /* this takes log2 of tmp */
+ while (tmp > 1) { /* this takes log2 of tmp */
bank_code++; /* and stores result in bank_code */
tmp = tmp >> 1;
} /* bank_code is now log2(bank_size) */
@@ -444,7 +444,7 @@ long int spd_sdram(int(read_spd)(uint addr))
#endif
mtsdram0( mem_sdtr1 , sdram0_tr );
- /* SDRAM have a power on delay, 500 micro should do */
+ /* SDRAM have a power on delay, 500 micro should do */
udelay(500);
sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
if (ecc_on)
@@ -456,7 +456,7 @@ long int spd_sdram(int(read_spd)(uint addr))
int spd_read(uint addr)
{
- char data[2];
+ uchar data[2];
if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
return (int)data[0];
@@ -464,172 +464,172 @@ int spd_read(uint addr)
return 0;
}
-#else /* CONFIG_440 */
+#else /* CONFIG_440 */
/*-----------------------------------------------------------------------------
| Memory Controller Options 0
+-----------------------------------------------------------------------------*/
-#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
-#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
-#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
-#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
-#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
-#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
-#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
-#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
-#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
-#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
-#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
-#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
+#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
+#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
+#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
+#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
+#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
+#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
+#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
+#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
+#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
+#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
+#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
+#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
/*-----------------------------------------------------------------------------
| Memory Controller Options 1
+-----------------------------------------------------------------------------*/
-#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
-#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
+#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
+#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
/*-----------------------------------------------------------------------------+
| SDRAM DEVPOT Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_DEVOPT_DLL 0x80000000
-#define SDRAM_DEVOPT_DS 0x40000000
+#define SDRAM_DEVOPT_DLL 0x80000000
+#define SDRAM_DEVOPT_DS 0x40000000
/*-----------------------------------------------------------------------------+
| SDRAM MCSTS Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_MCSTS_MRSC 0x80000000
-#define SDRAM_MCSTS_SRMS 0x40000000
-#define SDRAM_MCSTS_CIS 0x20000000
+#define SDRAM_MCSTS_MRSC 0x80000000
+#define SDRAM_MCSTS_SRMS 0x40000000
+#define SDRAM_MCSTS_CIS 0x20000000
/*-----------------------------------------------------------------------------
| SDRAM Refresh Timer Register
+-----------------------------------------------------------------------------*/
-#define SDRAM_RTR_RINT_MASK 0xFFFF0000
+#define SDRAM_RTR_RINT_MASK 0xFFFF0000
#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
-#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
+#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
/*-----------------------------------------------------------------------------+
| SDRAM UABus Base Address Reg
+-----------------------------------------------------------------------------*/
-#define SDRAM_UABBA_UBBA_MASK 0x0000000F
+#define SDRAM_UABBA_UBBA_MASK 0x0000000F
/*-----------------------------------------------------------------------------+
| Memory Bank 0-7 configuration
+-----------------------------------------------------------------------------*/
-#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
-#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
-#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
-#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
-#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
-#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
-#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
-#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
-#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
-#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
-#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
-#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
-#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
-#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
-#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
+#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
+#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
+#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
+#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
+#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
+#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
+#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
+#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
+#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
+#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
+#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
+#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
+#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
+#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
+#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
/*-----------------------------------------------------------------------------+
| SDRAM TR0 Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_TR0_SDWR_MASK 0x80000000
-#define SDRAM_TR0_SDWR_2_CLK 0x00000000
-#define SDRAM_TR0_SDWR_3_CLK 0x80000000
-#define SDRAM_TR0_SDWD_MASK 0x40000000
-#define SDRAM_TR0_SDWD_0_CLK 0x00000000
-#define SDRAM_TR0_SDWD_1_CLK 0x40000000
-#define SDRAM_TR0_SDCL_MASK 0x01800000
-#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
-#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
-#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
-#define SDRAM_TR0_SDPA_MASK 0x000C0000
-#define SDRAM_TR0_SDPA_2_CLK 0x00040000
-#define SDRAM_TR0_SDPA_3_CLK 0x00080000
-#define SDRAM_TR0_SDPA_4_CLK 0x000C0000
-#define SDRAM_TR0_SDCP_MASK 0x00030000
-#define SDRAM_TR0_SDCP_2_CLK 0x00000000
-#define SDRAM_TR0_SDCP_3_CLK 0x00010000
-#define SDRAM_TR0_SDCP_4_CLK 0x00020000
-#define SDRAM_TR0_SDCP_5_CLK 0x00030000
-#define SDRAM_TR0_SDLD_MASK 0x0000C000
-#define SDRAM_TR0_SDLD_1_CLK 0x00000000
-#define SDRAM_TR0_SDLD_2_CLK 0x00004000
-#define SDRAM_TR0_SDRA_MASK 0x0000001C
-#define SDRAM_TR0_SDRA_6_CLK 0x00000000
-#define SDRAM_TR0_SDRA_7_CLK 0x00000004
-#define SDRAM_TR0_SDRA_8_CLK 0x00000008
-#define SDRAM_TR0_SDRA_9_CLK 0x0000000C
-#define SDRAM_TR0_SDRA_10_CLK 0x00000010
-#define SDRAM_TR0_SDRA_11_CLK 0x00000014
-#define SDRAM_TR0_SDRA_12_CLK 0x00000018
-#define SDRAM_TR0_SDRA_13_CLK 0x0000001C
-#define SDRAM_TR0_SDRD_MASK 0x00000003
-#define SDRAM_TR0_SDRD_2_CLK 0x00000001
-#define SDRAM_TR0_SDRD_3_CLK 0x00000002
-#define SDRAM_TR0_SDRD_4_CLK 0x00000003
+#define SDRAM_TR0_SDWR_MASK 0x80000000
+#define SDRAM_TR0_SDWR_2_CLK 0x00000000
+#define SDRAM_TR0_SDWR_3_CLK 0x80000000
+#define SDRAM_TR0_SDWD_MASK 0x40000000
+#define SDRAM_TR0_SDWD_0_CLK 0x00000000
+#define SDRAM_TR0_SDWD_1_CLK 0x40000000
+#define SDRAM_TR0_SDCL_MASK 0x01800000
+#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
+#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
+#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
+#define SDRAM_TR0_SDPA_MASK 0x000C0000
+#define SDRAM_TR0_SDPA_2_CLK 0x00040000
+#define SDRAM_TR0_SDPA_3_CLK 0x00080000
+#define SDRAM_TR0_SDPA_4_CLK 0x000C0000
+#define SDRAM_TR0_SDCP_MASK 0x00030000
+#define SDRAM_TR0_SDCP_2_CLK 0x00000000
+#define SDRAM_TR0_SDCP_3_CLK 0x00010000
+#define SDRAM_TR0_SDCP_4_CLK 0x00020000
+#define SDRAM_TR0_SDCP_5_CLK 0x00030000
+#define SDRAM_TR0_SDLD_MASK 0x0000C000
+#define SDRAM_TR0_SDLD_1_CLK 0x00000000
+#define SDRAM_TR0_SDLD_2_CLK 0x00004000
+#define SDRAM_TR0_SDRA_MASK 0x0000001C
+#define SDRAM_TR0_SDRA_6_CLK 0x00000000
+#define SDRAM_TR0_SDRA_7_CLK 0x00000004
+#define SDRAM_TR0_SDRA_8_CLK 0x00000008
+#define SDRAM_TR0_SDRA_9_CLK 0x0000000C
+#define SDRAM_TR0_SDRA_10_CLK 0x00000010
+#define SDRAM_TR0_SDRA_11_CLK 0x00000014
+#define SDRAM_TR0_SDRA_12_CLK 0x00000018
+#define SDRAM_TR0_SDRA_13_CLK 0x0000001C
+#define SDRAM_TR0_SDRD_MASK 0x00000003
+#define SDRAM_TR0_SDRD_2_CLK 0x00000001
+#define SDRAM_TR0_SDRD_3_CLK 0x00000002
+#define SDRAM_TR0_SDRD_4_CLK 0x00000003
/*-----------------------------------------------------------------------------+
| SDRAM TR1 Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_TR1_RDSS_MASK 0xC0000000
-#define SDRAM_TR1_RDSS_TR0 0x00000000
-#define SDRAM_TR1_RDSS_TR1 0x40000000
-#define SDRAM_TR1_RDSS_TR2 0x80000000
-#define SDRAM_TR1_RDSS_TR3 0xC0000000
-#define SDRAM_TR1_RDSL_MASK 0x00C00000
-#define SDRAM_TR1_RDSL_STAGE1 0x00000000
-#define SDRAM_TR1_RDSL_STAGE2 0x00400000
-#define SDRAM_TR1_RDSL_STAGE3 0x00800000
-#define SDRAM_TR1_RDCD_MASK 0x00000800
-#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
-#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
-#define SDRAM_TR1_RDCT_MASK 0x000001FF
-#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
-#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
-#define SDRAM_TR1_RDCT_MIN 0x00000000
-#define SDRAM_TR1_RDCT_MAX 0x000001FF
+#define SDRAM_TR1_RDSS_MASK 0xC0000000
+#define SDRAM_TR1_RDSS_TR0 0x00000000
+#define SDRAM_TR1_RDSS_TR1 0x40000000
+#define SDRAM_TR1_RDSS_TR2 0x80000000
+#define SDRAM_TR1_RDSS_TR3 0xC0000000
+#define SDRAM_TR1_RDSL_MASK 0x00C00000
+#define SDRAM_TR1_RDSL_STAGE1 0x00000000
+#define SDRAM_TR1_RDSL_STAGE2 0x00400000
+#define SDRAM_TR1_RDSL_STAGE3 0x00800000
+#define SDRAM_TR1_RDCD_MASK 0x00000800
+#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
+#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
+#define SDRAM_TR1_RDCT_MASK 0x000001FF
+#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
+#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
+#define SDRAM_TR1_RDCT_MIN 0x00000000
+#define SDRAM_TR1_RDCT_MAX 0x000001FF
/*-----------------------------------------------------------------------------+
| SDRAM WDDCTR Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
-#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
-#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
-#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
-#define SDRAM_WDDCTR_DCD_MASK 0x000001FF
+#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
+#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
+#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
+#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
+#define SDRAM_WDDCTR_DCD_MASK 0x000001FF
/*-----------------------------------------------------------------------------+
| SDRAM CLKTR Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
-#define SDRAM_CLKTR_CLKP_0DEG 0x00000000
-#define SDRAM_CLKTR_CLKP_90DEG 0x40000000
-#define SDRAM_CLKTR_CLKP_180DEG 0x80000000
-#define SDRAM_CLKTR_DCDT_MASK 0x000001FF
+#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
+#define SDRAM_CLKTR_CLKP_0DEG 0x00000000
+#define SDRAM_CLKTR_CLKP_90DEG 0x40000000
+#define SDRAM_CLKTR_CLKP_180DEG 0x80000000
+#define SDRAM_CLKTR_DCDT_MASK 0x000001FF
/*-----------------------------------------------------------------------------+
| SDRAM DLYCAL Options
+-----------------------------------------------------------------------------*/
-#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
-#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
-#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
+#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
+#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
+#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
/*-----------------------------------------------------------------------------+
| General Definition
+-----------------------------------------------------------------------------*/
-#define DEFAULT_SPD_ADDR1 0x53
-#define DEFAULT_SPD_ADDR2 0x52
-#define MAXBANKS 4 /* at most 4 dimm banks */
-#define MAX_SPD_BYTES 256
-#define NUMHALFCYCLES 4
-#define NUMMEMTESTS 8
-#define NUMMEMWORDS 8
-#define MAXBXCR 4
-#define TRUE 1
-#define FALSE 0
+#define DEFAULT_SPD_ADDR1 0x53
+#define DEFAULT_SPD_ADDR2 0x52
+#define MAXBANKS 4 /* at most 4 dimm banks */
+#define MAX_SPD_BYTES 256
+#define NUMHALFCYCLES 4
+#define NUMMEMTESTS 8
+#define NUMMEMWORDS 8
+#define MAXBXCR 4
+#define TRUE 1
+#define FALSE 0
const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
{0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
@@ -650,42 +650,53 @@ const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
0xAA55AA55, 0xAA55AA55}
};
+/* bank_parms is used to sort the bank sizes by descending order */
+struct bank_param {
+ unsigned long cr;
+ unsigned long bank_size_bytes;
+};
+
+typedef struct bank_param BANKPARMS;
+
+#ifdef CFG_SIMULATE_SPD_EEPROM
+extern unsigned char cfg_simulate_spd_eeprom[128];
+#endif
unsigned char spd_read(uchar chip, uint addr);
void get_spd_info(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void check_mem_type
(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void check_volt_type
(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void program_cfg0(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void program_cfg1(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void program_rtr (unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void program_tr0 (unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned long num_dimm_banks);
void program_tr1 (void);
-void program_ecc (unsigned long num_bytes);
+void program_ecc (unsigned long num_bytes);
unsigned
long program_bxcr(unsigned long* dimm_populated,
@@ -696,7 +707,7 @@ long program_bxcr(unsigned long* dimm_populated,
* This function is reading data from the DIMM module EEPROM over the SPD bus
* and uses that to program the sdram controller.
*
- * This works on boards that has the same schematics that the IBM walnut has.
+ * This works on boards that has the same schematics that the AMCC walnut has.
*
* BUG: Don't handle ECC memory
* BUG: A few values in the TR register is currently hardcoded
@@ -708,7 +719,7 @@ long int spd_sdram(void) {
unsigned long total_size;
unsigned long cfg0;
unsigned long mcsts;
- unsigned long num_dimm_banks; /* on board dimm banks */
+ unsigned long num_dimm_banks; /* on board dimm banks */
num_dimm_banks = sizeof(iic0_dimm_addr);
@@ -806,9 +817,19 @@ long int spd_sdram(void) {
return total_size;
}
-unsigned char spd_read(uchar chip, uint addr) {
+unsigned char spd_read(uchar chip, uint addr)
+{
unsigned char data[2];
+#ifdef CFG_SIMULATE_SPD_EEPROM
+ if (chip == CFG_SIMULATE_SPD_EEPROM) {
+ /*
+ * Onboard spd eeprom requested -> simulate values
+ */
+ return cfg_simulate_spd_eeprom[addr];
+ }
+#endif /* CFG_SIMULATE_SPD_EEPROM */
+
if (i2c_probe(chip) == 0) {
if (i2c_read(chip, addr, 1, data, 1) == 0) {
return data[0];
@@ -820,7 +841,7 @@ unsigned char spd_read(uchar chip, uint addr) {
void get_spd_info(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long dimm_found;
@@ -910,7 +931,7 @@ void check_volt_type(unsigned long* dimm_populated,
void program_cfg0(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long cfg0;
@@ -1000,7 +1021,7 @@ void program_cfg0(unsigned long* dimm_populated,
void program_cfg1(unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned long num_dimm_banks)
{
unsigned long cfg1;
mfsdram(mem_cfg1, cfg1);
@@ -1018,7 +1039,7 @@ void program_cfg1(unsigned long* dimm_populated,
void program_rtr (unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long bus_period_x_10;
@@ -1079,7 +1100,7 @@ void program_rtr (unsigned long* dimm_populated,
void program_tr0 (unsigned long* dimm_populated,
unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long tr0;
@@ -1138,7 +1159,7 @@ void program_tr0 (unsigned long* dimm_populated,
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
- t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
+ t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
@@ -1213,7 +1234,7 @@ void program_tr0 (unsigned long* dimm_populated,
/*
* Program SD_WR and SD_WCSBC fields
*/
- tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
+ tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
switch (wcsbc) {
case 0:
tr0 |= SDRAM_TR0_SDWD_0_CLK;
@@ -1591,35 +1612,56 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
{
unsigned long dimm_num;
unsigned long bank_base_addr;
- unsigned long bank_size_bytes;
unsigned long cr;
unsigned long i;
+ unsigned long j;
unsigned long temp;
unsigned char num_row_addr;
unsigned char num_col_addr;
unsigned char num_banks;
unsigned char bank_size_id;
-
-#ifndef CONFIG_BAMBOO
- unsigned long bxcr_num;
+ unsigned long ctrl_bank_num[MAXBANKS];
+ unsigned long bx_cr_num;
+ unsigned long largest_size_index;
+ unsigned long largest_size;
+ unsigned long current_size_index;
+ BANKPARMS bank_parms[MAXBXCR];
+ unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
+ unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
/*
* Set the BxCR regs. First, wipe out the bank config registers.
*/
- for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
- mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
+ for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
+ mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2));
mtdcr(memcfgd, 0x00000000);
+ bank_parms[bx_cr_num].bank_size_bytes = 0;
}
+
+#ifdef CONFIG_BAMBOO
+ /*
+ * This next section is hardware dependent and must be programmed
+ * to match the hardware. For bammboo, the following holds...
+ * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0
+ * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
+ * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
+ * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
+ * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
+ */
+ ctrl_bank_num[0] = 0;
+ ctrl_bank_num[1] = 1;
+ ctrl_bank_num[2] = 3;
+#else
+ ctrl_bank_num[0] = 0;
+ ctrl_bank_num[1] = 1;
+ ctrl_bank_num[2] = 2;
+ ctrl_bank_num[3] = 3;
#endif
/*
* reset the bank_base address
*/
-#ifndef CONFIG_BAMBOO
bank_base_addr = CFG_SDRAM_BASE;
-#else
- bank_base_addr = CFG_SDRAM_ONBOARD_SIZE;
-#endif
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
@@ -1632,7 +1674,6 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
* Set the SDRAM0_BxCR regs
*/
cr = 0;
- bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
switch (bank_size_id) {
case 0x02:
cr |= SDRAM_BXCR_SDSZ_8;
@@ -1691,50 +1732,60 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
*/
cr |= SDRAM_BXCR_SDBE;
- /*------------------------------------------------------------------
- | This next section is hardware dependent and must be programmed
- | to match the hardware.
- +-----------------------------------------------------------------*/
- if (dimm_num == 0) {
- for (i = 0; i < num_banks; i++) {
-#ifndef CONFIG_BAMBOO
- mtdcr(memcfga, mem_b0cr + (i << 2));
-#else
- mtdcr(memcfga, mem_b1cr + (i << 2));
-#endif
- temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
- SDRAM_BXCR_SDSZ_MASK |
- SDRAM_BXCR_SDAM_MASK |
- SDRAM_BXCR_SDBE);
- cr |= temp;
- cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
- mtdcr(memcfgd, cr);
- bank_base_addr += bank_size_bytes;
- }
- } else {
- for (i = 0; i < num_banks; i++) {
-#ifndef CONFIG_BAMBOO
- mtdcr(memcfga, mem_b2cr + (i << 2));
-#else
- mtdcr(memcfga, mem_b3cr + (i << 2));
-#endif
- temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
- SDRAM_BXCR_SDSZ_MASK |
- SDRAM_BXCR_SDAM_MASK |
- SDRAM_BXCR_SDBE);
- cr |= temp;
- cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
- mtdcr(memcfgd, cr);
- bank_base_addr += bank_size_bytes;
- }
+ for (i = 0; i < num_banks; i++) {
+ bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
+ (4 * 1024 * 1024) * bank_size_id;
+ bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
}
}
}
+ /* Initialize sort tables */
+ for (i = 0; i < MAXBXCR; i++) {
+ sorted_bank_num[i] = i;
+ sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
+ }
+
+ for (i = 0; i < MAXBXCR-1; i++) {
+ largest_size = sorted_bank_size[i];
+ largest_size_index = 255;
+
+ /* Find the largest remaining value */
+ for (j = i + 1; j < MAXBXCR; j++) {
+ if (sorted_bank_size[j] > largest_size) {
+ /* Save largest remaining value and its index */
+ largest_size = sorted_bank_size[j];
+ largest_size_index = j;
+ }
+ }
+
+ if (largest_size_index != 255) {
+ /* Swap the current and largest values */
+ current_size_index = sorted_bank_num[largest_size_index];
+ sorted_bank_size[largest_size_index] = sorted_bank_size[i];
+ sorted_bank_size[i] = largest_size;
+ sorted_bank_num[largest_size_index] = sorted_bank_num[i];
+ sorted_bank_num[i] = current_size_index;
+ }
+ }
+
+ /* Set the SDRAM0_BxCR regs thanks to sort tables */
+ for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
+ if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
+ mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
+ temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
+ SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
+ temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
+ bank_parms[sorted_bank_num[bx_cr_num]].cr;
+ mtdcr(memcfgd, temp);
+ bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
+ }
+ }
+
return(bank_base_addr);
}
-void program_ecc (unsigned long num_bytes)
+void program_ecc (unsigned long num_bytes)
{
unsigned long bank_base_addr;
unsigned long current_address;
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 469f97d6f0..553c491e24 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -283,7 +283,7 @@ ulong get_PCI_freq (void)
return sys_info.freqPCI;
}
-#elif !defined(CONFIG_440GX)
+#elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP)
void get_sys_info (sys_info_t * sysInfo)
{
unsigned long strp0;
@@ -381,6 +381,13 @@ ulong get_OPB_freq (void)
extern void get_sys_info (sys_info_t * sysInfo);
extern ulong get_PCI_freq (void);
+#elif defined(CONFIG_AP1000)
+void get_sys_info (sys_info_t * sysInfo) {
+ sysInfo->freqProcessor = 240 * 1000 * 1000;
+ sysInfo->freqPLB = 80 * 1000 * 1000;
+ sysInfo->freqPCI = 33 * 1000 * 1000;
+}
+
#elif defined(CONFIG_405)
void get_sys_info (sys_info_t * sysInfo) {
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 003c5b6bf1..48b430d14d 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -42,7 +42,7 @@
/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
/*------------------------------------------------------------------------------- */
-/* U-Boot - Startup Code for IBM 4xx PowerPC based Embedded Boards
+/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
*
*
* The processor starts at 0xfffffffc and the code is executed
@@ -166,7 +166,7 @@ _start_440:
mtspr srr1,r0
mtspr csrr0,r0
mtspr csrr1,r0
-#if defined (CONFIG_440GX) /* NOTE: 440GX adds machine check status regs */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) /* NOTE: 440GX adds machine check status regs */
mtspr mcsrr0,r0
mtspr mcsrr1,r0
mfspr r1, mcsr
@@ -394,7 +394,7 @@ __440gx_msr_continue:
addi r3,r3,32
bdnz ..d_ag
#else
-#if defined (CONFIG_440GX)
+#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
#endif
mtdcr isram0_sb1cr,r0 /* Disable bank 1 */
@@ -409,7 +409,7 @@ __440gx_msr_continue:
mtdcr isram0_pmeg,r1
lis r1,0x8000 /* BAS = 8000_0000 */
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
ori r1,r1,0x0980 /* first 64k */
mtdcr isram0_sb0cr,r1
lis r1,0x8001
@@ -432,7 +432,6 @@ __440gx_msr_continue:
/*----------------------------------------------------------------*/
lis r1,CFG_INIT_RAM_ADDR@h
ori r1,r1,CFG_INIT_SP_OFFSET@l
-
li r0,0
stwu r0,-4(r1)
stwu r0,-4(r1) /* Terminate call chain */
@@ -444,6 +443,8 @@ __440gx_msr_continue:
stw r0,+12(r1) /* Save return addr (underflow vect) */
GET_GOT
+
+ bl cpu_init_f /* run low-level CPU init code (from Flash) */
bl board_init_f
#endif /* CONFIG_440 */
@@ -975,12 +976,8 @@ invalidate_icache:
invalidate_dcache:
addi r6,0,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
-#else
- addi r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
-#endif
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
..dcloop:
@@ -1001,15 +998,10 @@ flush_dcache:
mtdccr r10
/* do loop for # of congruence classes. */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */
ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
-#else
- addi r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
- addi r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
-#endif
mtctr r10
addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
add r11,r10,r11 /* add to get to other side of cache line */
@@ -1231,9 +1223,9 @@ relocate_code:
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
dccci 0,0 /* Invalidate data cache, now no longer our stack */
sync
- addi r1,r0,0x0000 /* Tlb entry #0 */
+ addi r1,r0,0x0000 /* TLB entry #0 */
tlbre r0,r1,0x0002 /* Read contents */
- ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
+ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
tlbwe r0,r1,0x0002 /* Save it out */
isync
#endif
diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h
index 1038975a2d..cbfe41db9c 100644
--- a/cpu/ppc4xx/vecnum.h
+++ b/cpu/ppc4xx/vecnum.h
@@ -31,7 +31,35 @@
#ifndef _VECNUMS_H_
#define _VECNUMS_H_
-#if defined(CONFIG_440)
+#if defined(CONFIG_440SP)
+
+/* UIC 0 */
+#define VECNUM_U0 0 /* UART0 */
+#define VECNUM_U1 1 /* UART1 */
+#define VECNUM_IIC0 2 /* IIC0 */
+#define VECNUM_IIC1 3 /* IIC1 */
+#define VECNUM_PIM 4 /* PCI inbound message */
+#define VECNUM_PCRW 5 /* PCI command reg write */
+#define VECNUM_PPM 6 /* PCI power management */
+#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
+#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
+
+/* UIC 1 */
+#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */
+#define VECNUM_MS (32 + 1) /* MAL SERR */
+#define VECNUM_TXDE (32 + 2) /* MAL TXDE */
+#define VECNUM_RXDE (32 + 3) /* MAL RXDE */
+#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */
+#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */
+#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */
+#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */
+#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */
+#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */
+#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */
+#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
+#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
+
+#elif defined(CONFIG_440)
/* UIC 0 */
#define VECNUM_U0 0 /* UART0 */
generated by cgit (git 2.34.1) at 2024-12-27 21:05:10 +0000