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-rw-r--r--cpu/mpc85xx/Makefile1
-rw-r--r--cpu/mpc85xx/cpu_init.c67
-rw-r--r--cpu/mpc85xx/cpu_init_early.c76
-rw-r--r--cpu/mpc85xx/start.S55
-rw-r--r--cpu/mpc85xx/tlb.c60
-rw-r--r--cpu/mpc85xx/traps.c9
-rw-r--r--cpu/mpc85xx/u-boot-nand.lds138
-rw-r--r--cpu/mpc8xxx/ddr/ctrl_regs.c10
-rw-r--r--cpu/mpc8xxx/ddr/ddr3_dimm_params.c4
-rw-r--r--cpu/ppc4xx/40x_spd_sdram.c2
-rw-r--r--cpu/ppc4xx/44x_spd_ddr.c20
-rw-r--r--cpu/ppc4xx/4xx_pci.c10
-rw-r--r--cpu/ppc4xx/4xx_uart.c28
-rw-r--r--cpu/ppc4xx/cpu.c38
-rw-r--r--cpu/ppc4xx/cpu_init.c68
-rw-r--r--cpu/ppc4xx/fdt.c4
-rw-r--r--cpu/ppc4xx/sdram.c4
-rw-r--r--cpu/ppc4xx/speed.c148
-rw-r--r--cpu/ppc4xx/start.S112
-rw-r--r--cpu/ppc4xx/usbdev.c4
20 files changed, 524 insertions, 334 deletions
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index a177f427ef..3ef00e8506 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -65,6 +65,7 @@ COBJS-$(CONFIG_CPM2) += serial_scc.o
COBJS = $(COBJS-y)
COBJS += cpu.o
COBJS += cpu_init.o
+COBJS += cpu_init_early.o
COBJS += interrupts.o
COBJS += speed.o
COBJS += tlb.o
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a54cf5d157..a6d1e999b6 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007 Freescale Semiconductor.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
*
* (C) Copyright 2003 Motorola Inc.
* Modified by Xianghua Xiao, X.Xiao@motorola.com
@@ -129,41 +129,6 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
}
#endif
-/* We run cpu_init_early_f in AS = 1 */
-void cpu_init_early_f(void)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
- /* Clear initial global data */
- memset ((void *) gd, 0, sizeof (gd_t));
-
- set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 1, 0, BOOKE_PAGESZ_4K, 0);
-
- /* set up CCSR if we want it moved */
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
- {
- u32 temp;
- volatile u32 *ccsr_virt =
- (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
-
- set_tlb(0, (u32)ccsr_virt, CONFIG_SYS_CCSRBAR_DEFAULT,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 1, 1, BOOKE_PAGESZ_4K, 0);
-
- temp = in_be32(ccsr_virt);
- out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
- temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
- }
-#endif
-
- init_laws();
- invalidate_tlb(0);
- init_tlbs();
-}
-
/*
* Breathe some life into the CPU...
*
@@ -291,6 +256,25 @@ int cpu_init_r(void)
asm("msync;isync");
cache_ctl = l2cache->l2ctl;
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ if (cache_ctl & MPC85xx_L2CTL_L2E) {
+ /* Clear L2 SRAM memory-mapped base address */
+ out_be32(&l2cache->l2srbar0, 0x0);
+ out_be32(&l2cache->l2srbar1, 0x0);
+
+ /* set MBECCDIS=0, SBECCDIS=0 */
+ clrbits_be32(&l2cache->l2errdis,
+ (MPC85xx_L2ERRDIS_MBECC |
+ MPC85xx_L2ERRDIS_SBECC));
+
+ /* set L2E=0, L2SRAM=0 */
+ clrbits_be32(&l2cache->l2ctl,
+ (MPC85xx_L2CTL_L2E |
+ MPC85xx_L2CTL_L2SRAM_ENTIRE));
+ }
+#endif
+
l2siz_field = (cache_ctl >> 28) & 0x3;
switch (l2siz_field) {
@@ -380,5 +364,16 @@ extern void setup_ivors(void);
void arch_preboot_os(void)
{
+ u32 msr;
+
+ /*
+ * We are changing interrupt offsets and are about to boot the OS so
+ * we need to make sure we disable all async interrupts. EE is already
+ * disabled by the time we get called.
+ */
+ msr = mfmsr();
+ msr &= ~(MSR_ME|MSR_CE|MSR_DE);
+ mtmsr(msr);
+
setup_ivors();
}
diff --git a/cpu/mpc85xx/cpu_init_early.c b/cpu/mpc85xx/cpu_init_early.c
new file mode 100644
index 0000000000..7886f868f2
--- /dev/null
+++ b/cpu/mpc85xx/cpu_init_early.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* We run cpu_init_early_f in AS = 1 */
+void cpu_init_early_f(void)
+{
+ u32 mas0, mas1, mas2, mas3, mas7;
+ int i;
+
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+ /*
+ * Clear initial global data
+ * we don't use memset so we can share this code with NAND_SPL
+ */
+ for (i = 0; i < sizeof(gd_t); i++)
+ ((char *)gd)[i] = 0;
+
+ mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);
+ mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
+ mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
+ mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
+ mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
+
+ write_tlb(mas0, mas1, mas2, mas3, mas7);
+
+ /* set up CCSR if we want it moved */
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
+ {
+ u32 temp;
+ volatile u32 *ccsr_virt =
+ (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
+
+ mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
+ /* mas1 is the same as above */
+ mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G);
+ mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0,
+ MAS3_SW|MAS3_SR);
+ mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);
+
+ write_tlb(mas0, mas1, mas2, mas3, mas7);
+
+ temp = in_be32(ccsr_virt);
+ out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
+ temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
+ }
+#endif
+
+ init_laws();
+ invalidate_tlb(0);
+ init_tlbs();
+}
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index e21a4eb876..c9e91a90da 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -1,5 +1,5 @@
/*
- * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright 2004, 2007-2009 Freescale Semiconductor.
* Copyright (C) 2003 Motorola,Inc.
*
* See file CREDITS for list of people who contributed to this
@@ -57,10 +57,12 @@
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
+#ifndef CONFIG_NAND_SPL
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
+#endif
GOT_ENTRY(__init_end)
GOT_ENTRY(_end)
@@ -156,6 +158,10 @@ _start_e500:
mtspr MCSR,r0 /* machine check syndrome register */
mtxer r0 /* clear integer exception register */
+#ifdef CONFIG_SYS_BOOK3E_HV
+ mtspr MAS8,r0 /* make sure MAS8 is clear */
+#endif
+
/* Enable Time Base and Select Time Base Clock */
lis r0,HID0_EMCP@h /* Enable machine check */
#if defined(CONFIG_ENABLE_36BIT_PHYS)
@@ -235,10 +241,11 @@ _start_e500:
#endif /* CONFIG_MPC8569 */
- /* create a temp mapping in AS=1 to the 4M boot window */
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
+#ifndef CONFIG_SYS_RAMBOOT
+ /* create a temp mapping in AS=1 to the 4M boot window */
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
@@ -248,6 +255,20 @@ _start_e500:
/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#else
+ /*
+ * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main
+ * image has been relocated to TEXT_BASE on the second stage.
+ */
+ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
+ ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
+
+ lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
+ ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
+
+ lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#endif
mtspr MAS0,r6
mtspr MAS1,r7
@@ -278,8 +299,8 @@ _start_e500:
msync
tlbwe
- lis r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h
- ori r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l
+ lis r6,MSR_IS|MSR_DS@h
+ ori r6,r6,MSR_IS|MSR_DS@l
lis r7,switch_as@h
ori r7,r7,switch_as@l
@@ -359,6 +380,7 @@ _start_cont:
bl board_init_f
isync
+#ifndef CONFIG_NAND_SPL
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
_start_of_vectors:
@@ -813,10 +835,33 @@ in32:
in32r:
lwbrx r3,r0,r3
blr
+#endif /* !CONFIG_NAND_SPL */
/*------------------------------------------------------------------------------*/
/*
+ * void write_tlb(mas0, mas1, mas2, mas3, mas7)
+ */
+ .globl write_tlb
+write_tlb:
+ mtspr MAS0,r3
+ mtspr MAS1,r4
+ mtspr MAS2,r5
+ mtspr MAS3,r6
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+ mtspr MAS7,r7
+#endif
+ li r3,0
+#ifdef CONFIG_SYS_BOOK3E_HV
+ mtspr MAS8,r3
+#endif
+ isync
+ tlbwe
+ msync
+ isync
+ blr
+
+/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
@@ -975,6 +1020,7 @@ clear_bss:
mr r4,r10 /* Destination Address */
bl board_init_r
+#ifndef CONFIG_NAND_SPL
/*
* Copy exception vector code to low memory
*
@@ -1128,3 +1174,4 @@ setup_ivors:
#include "fixed_ivor.S"
blr
+#endif /* !CONFIG_NAND_SPL */
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 0497a29ba8..6e94c237ad 100644
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -32,6 +32,30 @@
DECLARE_GLOBAL_DATA_PTR;
+void invalidate_tlb(u8 tlb)
+{
+ if (tlb == 0)
+ mtspr(MMUCSR0, 0x4);
+ if (tlb == 1)
+ mtspr(MMUCSR0, 0x2);
+}
+
+void init_tlbs(void)
+{
+ int i;
+
+ for (i = 0; i < num_tlb_entries; i++) {
+ write_tlb(tlb_table[i].mas0,
+ tlb_table[i].mas1,
+ tlb_table[i].mas2,
+ tlb_table[i].mas3,
+ tlb_table[i].mas7);
+ }
+
+ return ;
+}
+
+#ifndef CONFIG_NAND_SPL
void set_tlb(u8 tlb, u32 epn, u64 rpn,
u8 perms, u8 wimge,
u8 ts, u8 esel, u8 tsize, u8 iprot)
@@ -42,16 +66,9 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
_mas2 = FSL_BOOKE_MAS2(epn, wimge);
_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
- _mas7 = rpn >> 32;
+ _mas7 = FSL_BOOKE_MAS7(rpn);
- mtspr(MAS0, _mas0);
- mtspr(MAS1, _mas1);
- mtspr(MAS2, _mas2);
- mtspr(MAS3, _mas3);
-#ifdef CONFIG_ENABLE_36BIT_PHYS
- mtspr(MAS7, _mas7);
-#endif
- asm volatile("isync;msync;tlbwe;isync");
+ write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
#ifdef CONFIG_ADDR_MAP
if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
@@ -84,28 +101,6 @@ void disable_tlb(u8 esel)
#endif
}
-void invalidate_tlb(u8 tlb)
-{
- if (tlb == 0)
- mtspr(MMUCSR0, 0x4);
- if (tlb == 1)
- mtspr(MMUCSR0, 0x2);
-}
-
-void init_tlbs(void)
-{
- int i;
-
- for (i = 0; i < num_tlb_entries; i++) {
- set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn,
- tlb_table[i].perms, tlb_table[i].wimge,
- tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize,
- tlb_table[i].iprot);
- }
-
- return ;
-}
-
static void tlbsx (const volatile unsigned *addr)
{
__asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
@@ -215,3 +210,4 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
*/
return memsize_in_meg;
}
+#endif /* !CONFIG_NAND_SPL */
diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c
index 1045cc1e7d..9d16b9b55e 100644
--- a/cpu/mpc85xx/traps.c
+++ b/cpu/mpc85xx/traps.c
@@ -287,6 +287,7 @@ UnknownException(struct pt_regs *regs)
regs->nip, regs->msr, regs->trap);
_exception(0, regs);
}
+
void
ExtIntException(struct pt_regs *regs)
{
@@ -305,14 +306,6 @@ ExtIntException(struct pt_regs *regs)
printf(" irq IACK0@%05x=%d\n",(int)&pic->iack0,vect);
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
- machinecheck_count++;
-#ifdef EXTINT_NOSKIP
- printf("Returning back to 0x%08x\n",regs->nip);
-#else
- regs->nip += 4; /* skip offending instruction */
- printf("Skipping current instr, Returning to 0x%08lx\n",regs->nip);
-#endif
-
}
void
diff --git a/cpu/mpc85xx/u-boot-nand.lds b/cpu/mpc85xx/u-boot-nand.lds
new file mode 100644
index 0000000000..a0fc8f1388
--- /dev/null
+++ b/cpu/mpc85xx/u-boot-nand.lds
@@ -0,0 +1,138 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ } :text
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } :text
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ .bootpg ADDR(.text) - 0x1000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ } :text = 0xffff
+
+ . = ADDR(.text) + 0x80000;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ } :bss
+
+ . = ALIGN(4);
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 5e63c5df3a..2505041450 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -675,12 +675,12 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
esdmode = (0
| ((qoff & 0x1) << 12)
| ((tdqs_en & 0x1) << 11)
- | ((rtt & 0x4) << 9) /* rtt field is split */
+ | ((rtt & 0x4) << 7) /* rtt field is split */
| ((wrlvl_en & 0x1) << 7)
- | ((rtt & 0x2) << 6) /* rtt field is split */
- | ((dic & 0x2) << 5) /* DIC field is split */
+ | ((rtt & 0x2) << 5) /* rtt field is split */
+ | ((dic & 0x2) << 4) /* DIC field is split */
| ((al & 0x3) << 3)
- | ((rtt & 0x1) << 2) /* rtt field is split */
+ | ((rtt & 0x1) << 2) /* rtt field is split */
| ((dic & 0x1) << 1) /* DIC field is split */
| ((dll_en & 0x1) << 0)
);
diff --git a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index 13d234e933..d4199baa82 100644
--- a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* calculate the organization and timing parameter
@@ -71,7 +71,7 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd)
bsize = 1ULL << (nbit_sdram_cap_bsize - 3
+ nbit_primary_bus_width - nbit_sdram_width);
- debug("DDR: DDR III rank density = 0x%08x\n", bsize);
+ debug("DDR: DDR III rank density = 0x%16lx\n", bsize);
return bsize;
}
diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c
index 75bd70dc66..83fa709da2 100644
--- a/cpu/ppc4xx/40x_spd_sdram.c
+++ b/cpu/ppc4xx/40x_spd_sdram.c
@@ -422,7 +422,7 @@ long int spd_sdram(int(read_spd)(uint addr))
* program all the registers.
* -------------------------------------------------------------------*/
-#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
+#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
/* disable memcontroller so updates work */
mtsdram0( mem_mcopt1, 0 );
diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index f26fcdaa1e..c93f23a679 100644
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -192,8 +192,8 @@ long int spd_sdram(void) {
/*
* Soft-reset SDRAM controller.
*/
- mtsdr(sdr_srst, SDR0_SRST_DMC);
- mtsdr(sdr_srst, 0x00000000);
+ mtsdr(SDR0_SRST, SDR0_SRST_DMC);
+ mtsdr(SDR0_SRST, 0x00000000);
#endif
/*
@@ -848,11 +848,11 @@ static int short_mem_test(void)
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
- mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
- if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
+ mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bxcr_num << 2));
+ if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
/* Bank is enabled */
membase = (unsigned long*)
- (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
+ (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK);
/*
* Run the short memory test
@@ -1086,8 +1086,8 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
* Set the BxCR regs. First, wipe out the bank config registers.
*/
for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
- mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2));
- mtdcr(memcfgd, 0x00000000);
+ mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bx_cr_num << 2));
+ mtdcr(SDRAM0_CFGDATA, 0x00000000);
bank_parms[bx_cr_num].bank_size_bytes = 0;
}
@@ -1232,12 +1232,12 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
/* Set the SDRAM0_BxCR regs thanks to sort tables */
for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
- mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
- temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
+ mtdcr(SDRAM0_CFGADDR, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
+ temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
bank_parms[sorted_bank_num[bx_cr_num]].cr;
- mtdcr(memcfgd, temp);
+ mtdcr(SDRAM0_CFGDATA, temp);
bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
}
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index 184cef5d11..e97f32c7b0 100644
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -100,7 +100,7 @@ int __pci_pre_init(struct pci_controller *hose)
* The arbiter is enabled in this place because of
* compatibility reasons.
*/
- mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_ARBIT_EN);
+ mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
#endif /* CONFIG_405EP */
return 1;
@@ -118,10 +118,10 @@ ushort pmc405_pci_subsys_deviceid(void);
int __is_pci_host(struct pci_controller *hose)
{
#if defined(CONFIG_405GP)
- if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+ if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
return 1;
#elif defined (CONFIG_405EP)
- if (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN)
+ if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
return 1;
#endif
return 0;
@@ -491,7 +491,7 @@ int pci_440_init (struct pci_controller *hose)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long strap;
- mfsdr(sdr_sdstp1,strap);
+ mfsdr(SDR0_SDSTP1,strap);
if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
@@ -500,7 +500,7 @@ int pci_440_init (struct pci_controller *hose)
#elif defined(CONFIG_440GP)
unsigned long strap;
- strap = mfdcr(cpc0_strp1);
+ strap = mfdcr(CPC0_STRP1);
if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
printf("PCI: CPC0_STRP1[PISE] not set.\n");
printf("PCI: Configuration aborted.\n");
diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c
index 0780624e4a..8de65425c9 100644
--- a/cpu/ppc4xx/4xx_uart.c
+++ b/cpu/ppc4xx/4xx_uart.c
@@ -90,7 +90,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define CR0_EXTCLK_ENA 0x00600000
#define CR0_UDIV_POS 16
#define UDIV_SUBTRACT 1
-#define UART0_SDR cntrl0
+#define UART0_SDR CPC0_CR0
#define MFREG(a, d) d = mfdcr(a)
#define MTREG(a, d) mtdcr(a, d)
#else /* #if defined(CONFIG_440GP) */
@@ -99,18 +99,18 @@ DECLARE_GLOBAL_DATA_PTR;
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#define UDIV_SUBTRACT 0
-#define UART0_SDR sdr_uart0
-#define UART1_SDR sdr_uart1
+#define UART0_SDR SDR0_UART0
+#define UART1_SDR SDR0_UART1
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART2_SDR sdr_uart2
+#define UART2_SDR SDR0_UART2
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define UART3_SDR sdr_uart3
+#define UART3_SDR SDR0_UART3
#endif
#define MFREG(a, d) mfsdr(a, d)
#define MTREG(a, d) mtsdr(a, d)
@@ -130,8 +130,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#define UDIV_SUBTRACT 0
-#define UART0_SDR sdr_uart0
-#define UART1_SDR sdr_uart1
+#define UART0_SDR SDR0_UART0
+#define UART1_SDR SDR0_UART1
#else /* CONFIG_405GP || CONFIG_405CR */
#define UART0_BASE 0xef600300
#define UART1_BASE 0xef600400
@@ -282,7 +282,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
u32 reg;
/* check the pll feedback source */
- mfcpr(cprpllc, cpr_pllc);
+ mfcpr(CPR0_PLLC, cpr_pllc);
get_sys_info(&sysinfo);
@@ -312,10 +312,10 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
}
*pudiv = udiv;
- mfcpr(cprperd0, reg);
+ mfcpr(CPC0_PERD0, reg);
reg &= ~0x0000ffff;
reg |= ((udiv - 0) << 8) | (udiv - 0);
- mtcpr(cprperd0, reg);
+ mtcpr(CPC0_PERD0, reg);
*pbdiv = div / udiv;
}
#endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */
@@ -412,7 +412,7 @@ int serial_init_dev (unsigned long base)
clk = tmp = reg = 0;
#else
#ifdef CONFIG_405EP
- reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
+ reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
clk = gd->cpu_clk;
tmp = CONFIG_SYS_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
@@ -420,9 +420,9 @@ int serial_init_dev (unsigned long base)
udiv = UDIV_MAX;
reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
- mtdcr (cpc0_ucr, reg);
+ mtdcr (CPC0_UCR, reg);
#else /* CONFIG_405EP */
- reg = mfdcr(cntrl0) & ~CR0_MASK;
+ reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
udiv = 1;
@@ -439,7 +439,7 @@ int serial_init_dev (unsigned long base)
#endif
#endif
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
- mtdcr (cntrl0, reg);
+ mtdcr (CPC0_CR0, reg);
#endif /* CONFIG_405EP */
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index e9861abe76..2287904669 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -64,7 +64,7 @@ int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
static int pci_async_enabled(void)
{
#if defined(CONFIG_405GP)
- return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
+ return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@@ -72,7 +72,7 @@ static int pci_async_enabled(void)
defined(CONFIG_460EX) || defined(CONFIG_460GT)
unsigned long val;
- mfsdr(sdr_sdstp1, val);
+ mfsdr(SDR0_SDSTP1, val);
return (val & SDR0_SDSTP1_PAME_MASK);
#endif
}
@@ -84,21 +84,21 @@ static int pci_async_enabled(void)
static int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
- return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
+ return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
#endif
#if defined(CONFIG_405EP)
- return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
+ return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
#endif
#if defined(CONFIG_440GP)
- return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
+ return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
#endif
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long val;
- mfsdr(sdr_xcr, val);
+ mfsdr(SDR0_XCR, val);
return (val & 0x80000000);
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@@ -106,7 +106,7 @@ static int pci_arbiter_enabled(void)
defined(CONFIG_460EX) || defined(CONFIG_460GT)
unsigned long val;
- mfsdr(sdr_pci0, val);
+ mfsdr(SDR0_PCI0, val);
return (val & 0x80000000);
#endif
}
@@ -118,11 +118,11 @@ static int pci_arbiter_enabled(void)
static int i2c_bootrom_enabled(void)
{
#if defined(CONFIG_405EP)
- return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
+ return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
#else
unsigned long val;
- mfsdr(sdr_sdcs, val);
+ mfsdr(SDR0_SDCS0, val);
return (val & SDR0_SDCS_SDD);
#endif
}
@@ -256,7 +256,7 @@ static int bootstrap_option(void)
{
unsigned long val;
- mfsdr(SDR_PINSTP, val);
+ mfsdr(SDR0_PINSTP, val);
return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
}
#endif /* SDR0_PINSTP_SHIFT */
@@ -265,13 +265,13 @@ static int bootstrap_option(void)
#if defined(CONFIG_440)
static int do_chip_reset (unsigned long sys0, unsigned long sys1)
{
- /* Changes to cpc0_sys0 and cpc0_sys1 require chip
+ /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
* reset.
*/
- mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
- mtdcr (cpc0_sys0, sys0);
- mtdcr (cpc0_sys1, sys1);
- mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
+ mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */
+ mtdcr (CPC0_SYS0, sys0);
+ mtdcr (CPC0_SYS1, sys1);
+ mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */
mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
return 1;
@@ -410,13 +410,13 @@ int checkcpu (void)
case PVR_440GP_RB:
puts("GP Rev. B");
/* See errata 1.12: CHIP_4 */
- if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
- (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
+ if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
+ (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
puts ( "\n\t CPC0_SYSx DCRs corrupted. "
"Resetting chip ...\n");
udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
- do_chip_reset ( mfdcr(cpc0_strp0),
- mfdcr(cpc0_strp1) );
+ do_chip_reset ( mfdcr(CPC0_STRP0),
+ mfdcr(CPC0_STRP1) );
}
break;
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 65092fb8e4..bd06b9bc22 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -58,17 +58,17 @@ void reconfigure_pll(u32 new_cpu_freq)
target_perdv0 = 4;
target_spcid0 = 4;
- mfcpr(clk_primbd, reg);
+ mfcpr(CPR0_PRIMBD, reg);
temp = (reg & PRBDV_MASK) >> 24;
prbdv0 = temp ? temp : 8;
if (prbdv0 != target_prbdv0) {
reg &= ~PRBDV_MASK;
reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
- mtcpr(clk_primbd, reg);
+ mtcpr(CPR0_PRIMBD, reg);
reset_needed = 1;
}
- mfcpr(clk_plld, reg);
+ mfcpr(CPR0_PLLD, reg);
temp = (reg & PLLD_FWDVA_MASK) >> 16;
fwdva = temp ? temp : 16;
@@ -89,35 +89,35 @@ void reconfigure_pll(u32 new_cpu_freq)
((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
(target_lfbdv == 64 ? 0 : target_lfbdv);
- mtcpr(clk_plld, reg);
+ mtcpr(CPR0_PLLD, reg);
reset_needed = 1;
}
- mfcpr(clk_perd, reg);
+ mfcpr(CPR0_PERD, reg);
perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
if (perdv0 != target_perdv0) {
reg &= ~CPR0_PERD_PERDV0_MASK;
reg |= (target_perdv0 << 24);
- mtcpr(clk_perd, reg);
+ mtcpr(CPR0_PERD, reg);
reset_needed = 1;
}
- mfcpr(clk_spcid, reg);
+ mfcpr(CPR0_SPCID, reg);
temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
spcid0 = temp ? temp : 4;
if (spcid0 != target_spcid0) {
reg &= ~CPR0_SPCID_SPCIDV0_MASK;
reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
- mtcpr(clk_spcid, reg);
+ mtcpr(CPR0_SPCID, reg);
reset_needed = 1;
}
/* Set reload inhibit so configuration will persist across
* processor resets */
- mfcpr(clk_icfg, reg);
+ mfcpr(CPR0_ICFG, reg);
reg &= ~CPR0_ICFG_RLI_MASK;
reg |= 1 << 31;
- mtcpr(clk_icfg, reg);
+ mtcpr(CPR0_ICFG, reg);
}
/* Reset processor if configuration changed */
@@ -173,7 +173,7 @@ cpu_init_f (void)
/*
* Set EMAC noise filter bits
*/
- mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
+ mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
#endif /* CONFIG_405EP */
#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
@@ -204,43 +204,43 @@ cpu_init_f (void)
asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
#endif
- mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);
- mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
+ mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
+ mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
#endif
#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
- mtebc(pb1ap, CONFIG_SYS_EBC_PB1AP);
- mtebc(pb1cr, CONFIG_SYS_EBC_PB1CR);
+ mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP);
+ mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR);
#endif
#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
- mtebc(pb2ap, CONFIG_SYS_EBC_PB2AP);
- mtebc(pb2cr, CONFIG_SYS_EBC_PB2CR);
+ mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP);
+ mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR);
#endif
#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
- mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP);
- mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR);
+ mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);
+ mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
#endif
#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
- mtebc(pb4ap, CONFIG_SYS_EBC_PB4AP);
- mtebc(pb4cr, CONFIG_SYS_EBC_PB4CR);
+ mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP);
+ mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR);
#endif
#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
- mtebc(pb5ap, CONFIG_SYS_EBC_PB5AP);
- mtebc(pb5cr, CONFIG_SYS_EBC_PB5CR);
+ mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP);
+ mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR);
#endif
#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
- mtebc(pb6ap, CONFIG_SYS_EBC_PB6AP);
- mtebc(pb6cr, CONFIG_SYS_EBC_PB6CR);
+ mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP);
+ mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR);
#endif
#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
- mtebc(pb7ap, CONFIG_SYS_EBC_PB7AP);
- mtebc(pb7cr, CONFIG_SYS_EBC_PB7CR);
+ mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP);
+ mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR);
#endif
#if defined (CONFIG_SYS_EBC_CFG)
@@ -276,9 +276,9 @@ cpu_init_f (void)
* Compatibility mode and Ethernet Clock select are not
* correct in the manual
*/
- mfsdr(sdr_mfr, val);
+ mfsdr(SDR0_MFR, val);
val &= ~0x10000000;
- mtsdr(sdr_mfr,val);
+ mtsdr(SDR0_MFR,val);
#endif /* CONFIG_440GX */
#if defined(CONFIG_460EX)
@@ -304,10 +304,10 @@ cpu_init_f (void)
/*
* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
*/
- mtdcr(plb0_acr, (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) |
- plb0_acr_rdp_4deep);
- mtdcr(plb1_acr, (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) |
- plb1_acr_rdp_4deep);
+ mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) |
+ PLB0_ACR_RDP_4DEEP);
+ mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) |
+ PLB1_ACR_RDP_4DEEP);
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
}
@@ -324,7 +324,7 @@ int cpu_init_r (void)
* for compatibility to existing PPC405GP designs.
*/
if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
- mtdcr(ecr, 0x60606000);
+ mtdcr(CPC0_ECR, 0x60606000);
}
#endif /* defined(CONFIG_405GP) */
diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index ba5c120ad7..496e0285b5 100644
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -51,8 +51,8 @@ void __ft_board_setup(void *blob, bd_t *bd)
* peripheral banks into the OPB/PLB address space
*/
for (i = 0; i < EBC_NUM_BANKS; i++) {
- mtdcr(ebccfga, EBC_BXCR(i));
- bxcr = mfdcr(ebccfgd);
+ mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
+ bxcr = mfdcr(EBC0_CFGDATA);
if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
*p++ = i;
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index 4365df9879..5a3336e3c8 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -375,8 +375,8 @@ phys_size_t initdram(int board_type)
/*
* Soft-reset SDRAM controller.
*/
- mtsdr(sdr_srst, SDR0_SRST_DMC);
- mtsdr(sdr_srst, 0x00000000);
+ mtsdr(SDR0_SRST, SDR0_SRST_DMC);
+ mtsdr(SDR0_SRST, 0x00000000);
#endif
for (i=0; i<N_MB0CF; i++) {
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index c0a5824a63..988ba9742d 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -50,12 +50,12 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
/*
* Read PLL Mode register
*/
- pllmr = mfdcr (pllmd);
+ pllmr = mfdcr (CPC0_PLLMR);
/*
* Read Pin Strapping register
*/
- psr = mfdcr (strap);
+ psr = mfdcr (CPC0_PSR);
/*
* Determine FWD_DIV.
@@ -165,30 +165,13 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
}
}
+ sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv;
-
sysInfo->freqUART = sysInfo->freqProcessor;
}
/********************************************
- * get_OPB_freq
- * return OPB bus freq in Hz
- *********************************************/
-ulong get_OPB_freq (void)
-{
- ulong val = 0;
-
- PPC4xx_SYS_INFO sys_info;
-
- get_sys_info (&sys_info);
- val = sys_info.freqPLB / sys_info.pllOpbDiv;
-
- return val;
-}
-
-
-/********************************************
* get_PCI_freq
* return PCI bus freq in Hz
*********************************************/
@@ -280,8 +263,8 @@ void get_sys_info (sys_info_t * sysInfo)
unsigned long plbedv0;
/* Extract configured divisors */
- mfsdr(sdr_sdstp0, strp0);
- mfsdr(sdr_sdstp1, strp1);
+ mfsdr(SDR0_SDSTP0, strp0);
+ mfsdr(SDR0_SDSTP1, strp1);
temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 4);
sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
@@ -342,7 +325,7 @@ void get_sys_info (sys_info_t *sysInfo)
*/
/* Decode CPR0_PLLD0 for divisors */
- mfcpr(clk_plld, reg);
+ mfcpr(CPR0_PLLD, reg);
temp = (reg & PLLD_FWDVA_MASK) >> 16;
sysInfo->pllFwdDivA = temp ? temp : 16;
temp = (reg & PLLD_FWDVB_MASK) >> 8;
@@ -351,28 +334,28 @@ void get_sys_info (sys_info_t *sysInfo)
sysInfo->pllFbkDiv = temp ? temp : 32;
lfdiv = reg & PLLD_LFBDV_MASK;
- mfcpr(clk_opbd, reg);
+ mfcpr(CPR0_OPBD, reg);
temp = (reg & OPBDDV_MASK) >> 24;
sysInfo->pllOpbDiv = temp ? temp : 4;
- mfcpr(clk_perd, reg);
+ mfcpr(CPR0_PERD, reg);
temp = (reg & PERDV_MASK) >> 24;
sysInfo->pllExtBusDiv = temp ? temp : 8;
- mfcpr(clk_primbd, reg);
+ mfcpr(CPR0_PRIMBD, reg);
temp = (reg & PRBDV_MASK) >> 24;
prbdv0 = temp ? temp : 8;
- mfcpr(clk_spcid, reg);
+ mfcpr(CPR0_SPCID, reg);
temp = (reg & SPCID_MASK) >> 24;
sysInfo->pllPciDiv = temp ? temp : 4;
/* Calculate 'M' based on feedback source */
- mfsdr(sdr_sdstp0, reg);
+ mfsdr(SDR0_SDSTP0, reg);
temp = (reg & PLLSYS0_SEL_MASK) >> 27;
if (temp == 0) { /* PLL output */
/* Figure which pll to use */
- mfcpr(clk_pllc, reg);
+ mfcpr(CPR0_PLLC, reg);
temp = (reg & PLLC_SRC_MASK) >> 29;
if (!temp) /* PLLOUTA */
m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
@@ -426,7 +409,7 @@ void get_sys_info (sys_info_t * sysInfo)
unsigned long m;
/* Extract configured divisors */
- strp0 = mfdcr( cpc0_strp0 );
+ strp0 = mfdcr( CPC0_STRP0 );
sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
@@ -484,8 +467,8 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
/* Extract configured divisors */
- mfsdr( sdr_sdstp0,strp0 );
- mfsdr( sdr_sdstp1,strp1 );
+ mfsdr( SDR0_SDSTP0,strp0 );
+ mfsdr( SDR0_SDSTP1,strp1 );
temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
sysInfo->pllFwdDivA = temp ? temp : 16 ;
@@ -531,7 +514,7 @@ void get_sys_info (sys_info_t * sysInfo)
/* Determine PCI Clock Period */
pci_clock_per = determine_pci_clock_per();
sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000;
- mfsdr(sdr_ddr0, sdr_ddrpll);
+ mfsdr(SDR0_DDR0, sdr_ddrpll);
sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
#endif
@@ -752,14 +735,6 @@ unsigned long determine_pci_clock_per(void)
}
#endif
-ulong get_OPB_freq (void)
-{
-
- sys_info_t sys_info;
- get_sys_info (&sys_info);
- return sys_info.freqOPB;
-}
-
#elif defined(CONFIG_XILINX_405)
extern void get_sys_info (sys_info_t * sysInfo);
extern ulong get_PCI_freq (void);
@@ -794,8 +769,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
/*
* Read PLL Mode registers
*/
- pllmr0 = mfdcr (cpc0_pllmr0);
- pllmr1 = mfdcr (cpc0_pllmr1);
+ pllmr0 = mfdcr (CPC0_PLLMR0);
+ pllmr1 = mfdcr (CPC0_PLLMR1);
/*
* Determine forward divider A
@@ -875,23 +850,6 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
/********************************************
- * get_OPB_freq
- * return OPB bus freq in Hz
- *********************************************/
-ulong get_OPB_freq (void)
-{
- ulong val = 0;
-
- PPC4xx_SYS_INFO sys_info;
-
- get_sys_info (&sys_info);
- val = sys_info.freqPLB / sys_info.pllOpbDiv;
-
- return val;
-}
-
-
-/********************************************
* get_PCI_freq
* return PCI bus freq in Hz
*********************************************/
@@ -914,12 +872,13 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000);
unsigned long primad_cpudv;
unsigned long m;
+ unsigned long plloutb;
/*
* Read PLL Mode registers
*/
- mfcpr(cprplld, cpr_plld);
- mfcpr(cprpllc, cpr_pllc);
+ mfcpr(CPR0_PLLD, cpr_plld);
+ mfcpr(CPR0_PLLC, cpr_pllc);
/*
* Determine forward divider A
@@ -943,7 +902,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
/*
* Read CPR_PRIMAD register
*/
- mfcpr(cprprimad, cpr_primad);
+ mfcpr(CPC0_PRIMAD, cpr_primad);
/*
* Determine PLB_DIV.
@@ -996,26 +955,16 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) /
sysInfo->pllFwdDiv / sysInfo->pllPlbDiv;
+ sysInfo->freqOPB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) /
+ sysInfo->pllOpbDiv;
+
sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) /
sysInfo->pllExtBusDiv;
- sysInfo->freqUART = sysInfo->freqVCOHz;
-}
-
-/********************************************
- * get_OPB_freq
- * return OPB bus freq in Hz
- *********************************************/
-ulong get_OPB_freq (void)
-{
- ulong val = 0;
-
- PPC4xx_SYS_INFO sys_info;
-
- get_sys_info (&sys_info);
- val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv;
-
- return val;
+ plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
+ sysInfo->pllFwdDivB : sysInfo->pllFwdDiv) * sysInfo->pllFbkDiv) /
+ sysInfo->pllFwdDivB);
+ sysInfo->freqUART = plloutb;
}
#elif defined(CONFIG_405EX)
@@ -1074,7 +1023,7 @@ void get_sys_info (sys_info_t * sysInfo)
};
unsigned char sel, cpudv0, plb2xDiv;
- mfcpr(cpr0_plld, tmp);
+ mfcpr(CPR0_PLLD, tmp);
/*
* Determine forward divider A
@@ -1094,29 +1043,29 @@ void get_sys_info (sys_info_t * sysInfo)
/*
* Determine PERDV0
*/
- mfcpr(cpr0_perd, tmp);
+ mfcpr(CPR0_PERD, tmp);
tmp = (tmp >> 24) & 0x03;
sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp;
/*
* Determine OPBDV0
*/
- mfcpr(cpr0_opbd, tmp);
+ mfcpr(CPR0_OPBD, tmp);
tmp = (tmp >> 24) & 0x03;
sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp;
/* Determine PLB2XDV0 */
- mfcpr(cpr0_plbd, tmp);
+ mfcpr(CPR0_PLBD, tmp);
tmp = (tmp >> 16) & 0x07;
plb2xDiv = (tmp == 0) ? 8 : tmp;
/* Determine CPUDV0 */
- mfcpr(cpr0_cpud, tmp);
+ mfcpr(CPR0_CPUD, tmp);
tmp = (tmp >> 24) & 0x07;
cpudv0 = (tmp == 0) ? 8 : tmp;
/* Determine SEL(5:7) in CPR0_PLLC */
- mfcpr(cpr0_pllc, tmp);
+ mfcpr(CPR0_PLLC, tmp);
sel = (tmp >> 24) & 0x07;
/*
@@ -1164,22 +1113,6 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqUART = sysInfo->freqPLB;
}
-/********************************************
- * get_OPB_freq
- * return OPB bus freq in Hz
- *********************************************/
-ulong get_OPB_freq (void)
-{
- ulong val = 0;
-
- PPC4xx_SYS_INFO sys_info;
-
- get_sys_info (&sys_info);
- val = sys_info.freqPLB / sys_info.pllOpbDiv;
-
- return val;
-}
-
#endif
int get_clocks (void)
@@ -1231,3 +1164,14 @@ ulong get_bus_freq (ulong dummy)
return val;
}
+
+#if !defined(CONFIG_IOP480)
+ulong get_OPB_freq (void)
+{
+ PPC4xx_SYS_INFO sys_info;
+
+ get_sys_info (&sys_info);
+
+ return sys_info.freqOPB;
+}
+#endif
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index f967d8464c..287a912246 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -83,64 +83,64 @@
#ifdef CONFIG_SYS_INIT_DCACHE_CS
# if (CONFIG_SYS_INIT_DCACHE_CS == 0)
-# define PBxAP pb0ap
-# define PBxCR pb0cr
+# define PBxAP PB1AP
+# define PBxCR PB0CR
# if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
# define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
# define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
# endif
# endif
# if (CONFIG_SYS_INIT_DCACHE_CS == 1)
-# define PBxAP pb1ap
-# define PBxCR pb1cr
+# define PBxAP PB1AP
+# define PBxCR PB1CR
# if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
# define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
# define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
# endif
# endif
# if (CONFIG_SYS_INIT_DCACHE_CS == 2)
-# define PBxAP pb2ap
-# define PBxCR pb2cr
+# define PBxAP PB2AP
+# define PBxCR PB2CR
# if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
# define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
# define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
# endif
# endif
# if (CONFIG_SYS_INIT_DCACHE_CS == 3)
-# define PBxAP pb3ap
-# define PBxCR pb3cr
+# define PBxAP PB3AP
+# define PBxCR PB3CR
# if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
# define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
# define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
# endif
# endif
# if (CONFIG_SYS_INIT_DCACHE_CS == 4)
-# define PBxAP pb4ap
-# define PBxCR pb4cr
+# define PBxAP PB4AP
+# define PBxCR PB4CR
# if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
# define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
# define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
# endif
# endif
# if (CONFIG_SYS_INIT_DCACHE_CS == 5)
-# define PBxAP pb5ap
-# define PBxCR pb5cr
+# define PBxAP PB5AP
+# define PBxCR PB5CR
# if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
# define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
# define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
# endif
# endif
# if (CONFIG_SYS_INIT_DCACHE_CS == 6)
-# define PBxAP pb6ap
-# define PBxCR pb6cr
+# define PBxAP PB6AP
+# define PBxCR PB6CR
# if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
# define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
# define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
# endif
# endif
# if (CONFIG_SYS_INIT_DCACHE_CS == 7)
-# define PBxAP pb7ap
-# define PBxCR pb7cr
+# define PBxAP PB7AP
+# define PBxCR PB7CR
# if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
# define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
# define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
@@ -998,7 +998,7 @@ _start:
/*----------------------------------------------------------------------- */
addis r3,r0, 0xFFFF /* Clear all existing DMA status */
ori r3,r3, 0xFFFF
- mtdcr dmasr, r3
+ mtdcr DMASR, r3
bl ppc405ep_init /* do ppc405ep specific init */
#endif /* CONFIG_405EP */
@@ -1015,21 +1015,21 @@ _start:
lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
- mtdcr ocmplb3cr1,r3 /* Set PLB Access */
+ mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
- mtdcr ocmplb3cr2,r3 /* Set PLB Access */
+ mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
isync
lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
- mtdcr ocmdscr1, r3 /* Set Data Side */
- mtdcr ocmiscr1, r3 /* Set Instruction Side */
+ mtdcr OCM0_DSRC1, r3 /* Set Data Side */
+ mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
- mtdcr ocmdscr2, r3 /* Set Data Side */
- mtdcr ocmiscr2, r3 /* Set Instruction Side */
+ mtdcr OCM0_DSRC2, r3 /* Set Data Side */
+ mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
- mtdcr ocmdsisdpc,r3
+ mtdcr OCM0_DISDPC,r3
isync
#else /* CONFIG_405EZ */
@@ -1039,19 +1039,19 @@ _start:
/* Setup OCM */
lis r0, 0x7FFF
ori r0, r0, 0xFFFF
- mfdcr r3, ocmiscntl /* get instr-side IRAM config */
- mfdcr r4, ocmdscntl /* get data-side IRAM config */
+ mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
+ mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
and r3, r3, r0 /* disable data-side IRAM */
and r4, r4, r0 /* disable data-side IRAM */
- mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
- mtdcr ocmdscntl, r4 /* set data-side IRAM config */
+ mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
+ mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
isync
lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
- mtdcr ocmdsarc, r3
+ mtdcr OCM0_DSARC, r3
addis r4, 0, 0xC000 /* OCM data area enabled */
- mtdcr ocmdscntl, r4
+ mtdcr OCM0_DSCNTL, r4
isync
#endif /* CONFIG_405EZ */
#endif
@@ -1061,16 +1061,16 @@ _start:
/*----------------------------------------------------------------------- */
#ifdef CONFIG_SYS_INIT_DCACHE_CS
li r4, PBxAP
- mtdcr ebccfga, r4
+ mtdcr EBC0_CFGADDR, r4
lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
- mtdcr ebccfgd, r4
+ mtdcr EBC0_CFGDATA, r4
addi r4, 0, PBxCR
- mtdcr ebccfga, r4
+ mtdcr EBC0_CFGADDR, r4
lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
- mtdcr ebccfgd, r4
+ mtdcr EBC0_CFGDATA, r4
/*
* Enable the data cache for the 128MB storage access control region
@@ -1428,16 +1428,16 @@ relocate_code:
/* Restore the EBC parameters */
li r3, PBxAP
- mtdcr ebccfga, r3
+ mtdcr EBC0_CFGADDR, r3
lis r3, PBxAP_VAL@h
ori r3, r3, PBxAP_VAL@l
- mtdcr ebccfgd, r3
+ mtdcr EBC0_CFGDATA, r3
li r3, PBxCR
- mtdcr ebccfga, r3
+ mtdcr EBC0_CFGADDR, r3
lis r3, PBxCR_VAL@h
ori r3, r3, PBxCR_VAL@l
- mtdcr ebccfgd, r3
+ mtdcr EBC0_CFGDATA, r3
#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
/* Restore registers */
@@ -1860,38 +1860,38 @@ ppc405ep_init:
ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
stw r4,0(r3)
- li r3,pb1ap /* program EBC bank 1 for RTC access */
- mtdcr ebccfga,r3
+ li r3,PB1AP /* program EBC bank 1 for RTC access */
+ mtdcr EBC0_CFGADDR,r3
lis r3,CONFIG_SYS_EBC_PB1AP@h
ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
- mtdcr ebccfgd,r3
- li r3,pb1cr
- mtdcr ebccfga,r3
+ mtdcr EBC0_CFGDATA,r3
+ li r3,PB1CR
+ mtdcr EBC0_CFGADDR,r3
lis r3,CONFIG_SYS_EBC_PB1CR@h
ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
- mtdcr ebccfgd,r3
+ mtdcr EBC0_CFGDATA,r3
- li r3,pb1ap /* program EBC bank 1 for RTC access */
- mtdcr ebccfga,r3
+ li r3,PB1AP /* program EBC bank 1 for RTC access */
+ mtdcr EBC0_CFGADDR,r3
lis r3,CONFIG_SYS_EBC_PB1AP@h
ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
- mtdcr ebccfgd,r3
- li r3,pb1cr
- mtdcr ebccfga,r3
+ mtdcr EBC0_CFGDATA,r3
+ li r3,PB1CR
+ mtdcr EBC0_CFGADDR,r3
lis r3,CONFIG_SYS_EBC_PB1CR@h
ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
- mtdcr ebccfgd,r3
+ mtdcr EBC0_CFGDATA,r3
- li r3,pb4ap /* program EBC bank 4 for FPGA access */
- mtdcr ebccfga,r3
+ li r3,PB4AP /* program EBC bank 4 for FPGA access */
+ mtdcr EBC0_CFGADDR,r3
lis r3,CONFIG_SYS_EBC_PB4AP@h
ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
- mtdcr ebccfgd,r3
- li r3,pb4cr
- mtdcr ebccfga,r3
+ mtdcr EBC0_CFGDATA,r3
+ li r3,PB4CR
+ mtdcr EBC0_CFGADDR,r3
lis r3,CONFIG_SYS_EBC_PB4CR@h
ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
- mtdcr ebccfgd,r3
+ mtdcr EBC0_CFGDATA,r3
#endif
/*
diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c
index faf7f0878f..5bb4f3ce63 100644
--- a/cpu/ppc4xx/usbdev.c
+++ b/cpu/ppc4xx/usbdev.c
@@ -206,14 +206,14 @@ void usb_dev_init()
#ifdef USB_2_0_DEVICE
printf("USB 2.0 Device init\n");
/*select 2.0 device */
- mtsdr(sdr_usb0, 0x0); /* 2.0 */
+ mtsdr(SDR0_USB0, 0x0); /* 2.0 */
/*usb dev init */
*(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */
#else
printf("USB 1.1 Device init\n");
/*select 1.1 device */
- mtsdr(sdr_usb0, 0x2); /* 1.1 */
+ mtsdr(SDR0_USB0, 0x2); /* 1.1 */
/*usb dev init */
*(unsigned char *)USB2D0_POWER_8 = 0xc0; /* 1.1 */
generated by cgit (git 2.34.1) at 2025-02-11 09:17:10 +0000