diff options
Diffstat (limited to 'cpu')
164 files changed, 11064 insertions, 9220 deletions
diff --git a/cpu/arm1136/Makefile b/cpu/arm1136/Makefile index d5ac7d3fd9..7701b03bbe 100644 --- a/cpu/arm1136/Makefile +++ b/cpu/arm1136/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o +COBJS = cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c index fa78eaa7f0..c27f8cd58c 100644 --- a/cpu/arm1136/cpu.c +++ b/cpu/arm1136/cpu.c @@ -33,9 +33,6 @@ #include <common.h> #include <command.h> -#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) -#include <asm/arch/omap2420.h> -#endif #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; @@ -47,10 +44,10 @@ static unsigned long read_p15_c1 (void) unsigned long value; __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); return value; } diff --git a/cpu/bf533/Makefile b/cpu/arm1136/mx31/Makefile index ad48f1c5c1..b648ffd6ff 100644 --- a/cpu/bf533/Makefile +++ b/cpu/arm1136/mx31/Makefile @@ -1,6 +1,3 @@ -# U-boot - Makefile -# -# Copyright (c) 2005-2007 Analog Devices Inc. # # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -20,24 +17,20 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -# MA 02110-1301 USA +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA # include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a - -SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o -COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o +LIB = $(obj)lib$(SOC).a -EXTRA = init_sdram_bootrom_initblock.o +COBJS = interrupts.o serial.o generic.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA) +all: $(obj).depend $(LIB) $(LIB): $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c new file mode 100644 index 0000000000..16b2cf1364 --- /dev/null +++ b/cpu/arm1136/mx31/generic.c @@ -0,0 +1,100 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/mx31-regs.h> + +static u32 mx31_decode_pll(u32 reg, u32 infreq) +{ + u32 mfi = (reg >> 10) & 0xf; + u32 mfn = reg & 0x3f; + u32 mfd = (reg >> 16) & 0x3f; + u32 pd = (reg >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + mfd += 1; + pd += 1; + + return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) / + (mfd * pd)) << 10; +} + +u32 mx31_get_mpl_dpdgck_clk(void) +{ + u32 infreq; + + if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) + infreq = CONFIG_MX31_CLK32 * 1024; + else + infreq = CONFIG_MX31_HCLK_FREQ; + + return mx31_decode_pll(__REG(CCM_MPCTL), infreq); +} + +u32 mx31_get_mcu_main_clk(void) +{ + /* For now we assume mpl_dpdgck_clk == mcu_main_clk + * which should be correct for most boards + */ + return mx31_get_mpl_dpdgck_clk(); +} + +u32 mx31_get_ipg_clk(void) +{ + u32 freq = mx31_get_mcu_main_clk(); + u32 pdr0 = __REG(CCM_PDR0); + + freq /= ((pdr0 >> 3) & 0x7) + 1; + freq /= ((pdr0 >> 6) & 0x3) + 1; + + return freq; +} + +void mx31_dump_clocks(void) +{ + u32 cpufreq = mx31_get_mcu_main_clk(); + printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000); + printf("ipg clock : %dHz\n", mx31_get_ipg_clk()); +} + +void mx31_gpio_mux(unsigned long mode) +{ + unsigned long reg, shift, tmp; + + reg = IOMUXC_BASE + (mode & 0xfc); + shift = (~mode & 0x3) * 8; + + tmp = __REG(reg); + tmp &= ~(0xff << shift); + tmp |= ((mode >> 8) & 0xff) << shift; + __REG(reg) = tmp; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo (void) +{ + printf("CPU: Freescale i.MX31 at %d MHz\n", + mx31_get_mcu_main_clk() / 1000000); + return 0; +} +#endif diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c new file mode 100644 index 0000000000..21b77a544a --- /dev/null +++ b/cpu/arm1136/mx31/interrupts.c @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/mx31-regs.h> + +#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ + +/* General purpose timers registers */ +#define GPTCR __REG(TIMER_BASE) /* Control register */ +#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ +#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ +#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1<<15) /* Software reset */ +#define GPTCR_FRR (1<<9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ +#define GPTCR_TEN (1) /* Timer enable */ + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init (void) +{ + int i; + + /* setup GP Timer 1 */ + GPTCR = GPTCR_SWR; + for ( i=0; i<100; i++) GPTCR = 0; /* We have no udelay by now */ + GPTPR = 0; /* 32Khz */ + GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */ + + return 0; +} + +void reset_timer_masked (void) +{ + GPTCR = 0; + GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */ +} + +ulong get_timer_masked (void) +{ + ulong val = GPTCNT; + return val; +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + +void reset_cpu (ulong addr) +{ + __REG16(WDOG_BASE) = 4; +} diff --git a/cpu/arm1136/mx31/serial.c b/cpu/arm1136/mx31/serial.c new file mode 100644 index 0000000000..a829ba7dac --- /dev/null +++ b/cpu/arm1136/mx31/serial.c @@ -0,0 +1,231 @@ +/* + * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> + +#if defined CONFIG_MX31_UART + +#include <asm/arch/mx31.h> + +#define __REG(x) (*((volatile u32 *)(x))) + +#ifdef CFG_MX31_UART1 +#define UART_PHYS 0x43f90000 +#elif defined(CFG_MX31_UART2) +#define UART_PHYS 0x43f94000 +#elif defined(CFG_MX31_UART3) +#define UART_PHYS 0x5000c000 +#elif defined(CFG_MX31_UART4) +#define UART_PHYS 0x43fb0000 +#elif defined(CFG_MX31_UART5) +#define UART_PHYS 0x43fb4000 +#else +#error "define CFG_MX31_UARTx to use the mx31 UART driver" +#endif + +/* Register definitions */ +#define URXD 0x0 /* Receiver Register */ +#define UTXD 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define UCR3 0x88 /* Control Register 3 */ +#define UCR4 0x8c /* Control Register 4 */ +#define UFCR 0x90 /* FIFO Control Register */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UESC 0x9c /* Escape Character Register */ +#define UTIM 0xa0 /* Escape Timer Register */ +#define UBIR 0xa4 /* BRM Incremental Register */ +#define UBMR 0xa8 /* BRM Modulator Register */ +#define UBRC 0xac /* Baud Rate Count Register */ +#define UTS 0xb4 /* UART Test Register (mx31) */ + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +DECLARE_GLOBAL_DATA_PTR; + +void serial_setbrg (void) +{ + u32 clk = mx31_get_ipg_clk(); + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + + __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UBIR) = 0xf; + __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); + +} + +int serial_getc (void) +{ + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); + return __REG(UART_PHYS + URXD); +} + +void serial_putc (const char c) +{ + __REG(UART_PHYS + UTXD) = c; + + /* wait for transmitter to be ready */ + while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc (void) +{ + /* If receive fifo is empty, return false */ + if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + return 0; + return 1; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + __REG(UART_PHYS + UCR1) = 0x0; + __REG(UART_PHYS + UCR2) = 0x0; + + while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); + + __REG(UART_PHYS + UCR3) = 0x0704; + __REG(UART_PHYS + UCR4) = 0x8000; + __REG(UART_PHYS + UESC) = 0x002b; + __REG(UART_PHYS + UTIM) = 0x0; + + __REG(UART_PHYS + UTS) = 0x0; + + serial_setbrg(); + + __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; + + __REG(UART_PHYS + UCR1) = UCR1_UARTEN; + + return 0; +} + + +#endif /* CONFIG_MX31 */ diff --git a/cpu/bf561/Makefile b/cpu/arm1136/omap24xx/Makefile index 418a4370eb..f9afed72f6 100644 --- a/cpu/bf561/Makefile +++ b/cpu/arm1136/omap24xx/Makefile @@ -1,8 +1,5 @@ -# U-boot - Makefile # -# Copyright (c) 2005-2007 Analog Devices Inc. -# -# (C) Copyright 2000-2004 +# (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -20,24 +17,21 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -# MA 02110-1301 USA +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA # include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a - -SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o -COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o +LIB = $(obj)lib$(SOC).a -EXTRA = init_sdram_bootrom_initblock.o +COBJS = interrupts.o +SOBJS = start.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA) +all: $(obj).depend $(LIB) $(LIB): $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) diff --git a/cpu/arm1136/interrupts.c b/cpu/arm1136/omap24xx/interrupts.c index 491c902ace..b9a8b93521 100644 --- a/cpu/arm1136/interrupts.c +++ b/cpu/arm1136/omap24xx/interrupts.c @@ -32,19 +32,12 @@ #include <common.h> #include <asm/arch/bits.h> - -#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) -# include <asm/arch/omap2420.h> -#endif +#include <asm/arch/omap2420.h> #define TIMER_LOAD_VAL 0 /* macro to read the 32 bit timer */ -#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR)) - -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) -/* Use the IntegratorCP function from board/integratorcp.c */ -#else +#define READ_TIMER (*((volatile ulong *)(CFG_TIMERBASE+TCRR))) static ulong timestamp; static ulong lastinc; @@ -164,4 +157,3 @@ ulong get_tbclk (void) tbclk = CFG_HZ; return tbclk; } -#endif /* !Integrator/CP */ diff --git a/cpu/arm1136/omap24xx/start.S b/cpu/arm1136/omap24xx/start.S new file mode 100644 index 0000000000..d6cefbd445 --- /dev/null +++ b/cpu/arm1136/omap24xx/start.S @@ -0,0 +1,42 @@ +/* + * armboot - Startup Code for OMP2420/ARM1136 CPU-core + * + * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> + * + * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <gj@denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> + * Copyright (c) 2003 Kshitij <kshitij@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/omap2420.h> + +.globl reset_cpu +reset_cpu: + ldr r1, rstctl /* get addr for global reset reg */ + mov r3, #0x2 /* full reset pll+mpu */ + str r3, [r1] /* force reset */ + mov r0, r0 +_loop_forever: + b _loop_forever +rstctl: + .word PM_RSTCTRL_WKUP diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 8b765f1e80..56009d0fb3 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -30,9 +30,6 @@ #include <config.h> #include <version.h> -#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) -#include <asm/arch/omap2420.h> -#endif .globl _start _start: b reset #ifdef CONFIG_ONENAND_IPL @@ -438,22 +435,4 @@ fiq: arm1136_cache_flush: mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache mov pc, lr @ back to caller - -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) -/* Use the IntegratorCP function from board/integratorcp/platform.S */ -#else - - .align 5 -.globl reset_cpu -reset_cpu: - ldr r1, rstctl /* get addr for global reset reg */ - mov r3, #0x2 /* full reset pll+mpu */ - str r3, [r1] /* force reset */ - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PM_RSTCTRL_WKUP - -#endif #endif /* CONFIG_ONENAND_IPL */ diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S index 1902bd02c5..98363eb400 100644 --- a/cpu/arm920t/at91rm9200/lowlevel_init.S +++ b/cpu/arm920t/at91rm9200/lowlevel_init.S @@ -46,7 +46,7 @@ #define MC_ASR 0xFFFFFF04 #define MC_AASR 0xFFFFFF08 #define EBI_CFGR 0xFFFFFF64 -#define SMC2_CSR 0xFFFFFF70 +#define SMC_CSR0 0xFFFFFF70 /* clocks */ #define PLLAR 0xFFFFFC28 @@ -146,8 +146,8 @@ SMRDATA: .word MC_AASR_VAL .word EBI_CFGR .word EBI_CFGR_VAL - .word SMC2_CSR - .word SMC2_CSR_VAL + .word SMC_CSR0 + .word SMC_CSR0_VAL .word PLLAR .word PLLAR_VAL .word PLLBR diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index ae86002a8f..acc00ad970 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -178,7 +178,7 @@ copyex: bl cpu_init_crit #endif -#ifdef CONFIG_AT91RM9200 +#ifndef CONFIG_AT91RM9200 #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ diff --git a/cpu/arm926ejs/at91cap9/spi.c b/cpu/arm926ejs/at91cap9/spi.c deleted file mode 100644 index 0953820bdf..0000000000 --- a/cpu/arm926ejs/at91cap9/spi.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Driver for ATMEL DataFlash support - * Author : Hamid Ikdoumi (Atmel) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include <config.h> -#include <common.h> -#include <asm/hardware.h> - -#ifdef CONFIG_HAS_DATAFLASH -#include <dataflash.h> - -/* Max Value = 10MHz to be compliant to the Continuous Array Read function */ -#define AT91C_SPI_CLK 10000000 - -/* AC Characteristics: DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -#define DATAFLASH_TCSS (0xFA << 16) -#define DATAFLASH_TCHS (0x8 << 24) - -#define AT91C_TIMEOUT_WRDY 200000 -#define AT91C_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */ -#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ - -void AT91F_SpiInit(void) -{ - /* Reset the SPI */ - AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SWRST; - - /* Configure SPI in Master Mode with No CS selected !!! */ - AT91C_BASE_SPI0->SPI_MR = - AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; - - /* Configure CS0 */ - AT91C_BASE_SPI0->SPI_CSR[0] = - AT91C_SPI_CPOL | - (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | - (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); -} - -void AT91F_SpiEnable(int cs) -{ - switch (cs) { - case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI0->SPI_MR |= - ((AT91C_SPI_PCS0_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - case 3: - AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF; - AT91C_BASE_SPI0->SPI_MR |= - ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); - break; - } - - /* SPI_Enable */ - AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SPIEN; -} - -unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) -{ - unsigned int timeout; - - pDesc->state = BUSY; - - AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - - /* Initialize the Transmit and Receive Pointer */ - AT91C_BASE_SPI0->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt; - AT91C_BASE_SPI0->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt; - - /* Intialize the Transmit and Receive Counters */ - AT91C_BASE_SPI0->SPI_RCR = pDesc->rx_cmd_size; - AT91C_BASE_SPI0->SPI_TCR = pDesc->tx_cmd_size; - - if (pDesc->tx_data_size != 0) { - /* Initialize the Next Transmit and Next Receive Pointer */ - AT91C_BASE_SPI0->SPI_RNPR = (unsigned int)pDesc->rx_data_pt; - AT91C_BASE_SPI0->SPI_TNPR = (unsigned int)pDesc->tx_data_pt; - - /* Intialize the Next Transmit and Next Receive Counters */ - AT91C_BASE_SPI0->SPI_RNCR = pDesc->rx_data_size; - AT91C_BASE_SPI0->SPI_TNCR = pDesc->tx_data_size; - } - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - timeout = 0; - - AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; - while (!(AT91C_BASE_SPI0->SPI_SR & AT91C_SPI_RXBUFF) && - ((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT)); - AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; - pDesc->state = IDLE; - - if (timeout >= CFG_SPI_WRITE_TOUT) { - printf("Error Timeout\n\r"); - return DATAFLASH_ERROR; - } - - return DATAFLASH_OK; -} -#endif diff --git a/cpu/arm926ejs/at91cap9/Makefile b/cpu/arm926ejs/at91sam9/Makefile index bf15e1edb3..203abc28e1 100644 --- a/cpu/arm926ejs/at91cap9/Makefile +++ b/cpu/arm926ejs/at91sam9/Makefile @@ -25,11 +25,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = ether.o timer.o spi.o usb.o +COBJS-y += ether.o +COBJS-y += timer.o +COBJS-$(CONFIG_HAS_DATAFLASH) +=spi.o +COBJS-y += usb.o SOBJS = lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) all: $(obj).depend $(LIB) diff --git a/cpu/arm926ejs/at91cap9/config.mk b/cpu/arm926ejs/at91sam9/config.mk index ca2cae181b..ca2cae181b 100644 --- a/cpu/arm926ejs/at91cap9/config.mk +++ b/cpu/arm926ejs/at91sam9/config.mk diff --git a/cpu/arm926ejs/at91cap9/ether.c b/cpu/arm926ejs/at91sam9/ether.c index b7958d5aba..e4f56012aa 100644 --- a/cpu/arm926ejs/at91cap9/ether.c +++ b/cpu/arm926ejs/at91sam9/ether.c @@ -23,13 +23,13 @@ */ #include <common.h> -#include <asm/arch/AT91CAP9.h> +#include <asm/arch/hardware.h> extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); #if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) -void at91cap9_eth_initialize(bd_t *bi) +void at91sam9_eth_initialize(bd_t *bi) { - macb_eth_initialize(0, (void *)AT91C_BASE_MACB, 0x00); + macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00); } #endif diff --git a/cpu/arm926ejs/at91cap9/lowlevel_init.S b/cpu/arm926ejs/at91sam9/lowlevel_init.S index 24d950cf74..40a3f6aaef 100644 --- a/cpu/arm926ejs/at91cap9/lowlevel_init.S +++ b/cpu/arm926ejs/at91sam9/lowlevel_init.S @@ -1,5 +1,5 @@ /* - * AT91CAP9 setup stuff + * AT91CAP9/SAM9 setup stuff * * (C) Copyright 2007-2008 * Stelian Pop <stelian.pop <at> leadtechdesign.com> diff --git a/cpu/arm926ejs/at91sam9/spi.c b/cpu/arm926ejs/at91sam9/spi.c new file mode 100644 index 0000000000..c9fe6d8a3f --- /dev/null +++ b/cpu/arm926ejs/at91sam9/spi.c @@ -0,0 +1,157 @@ +/* + * Driver for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_spi.h> + +#include <dataflash.h> + +#define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */ +#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 0: NPCS0%1101 */ +#define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ + +void AT91F_SpiInit(void) +{ + /* Reset the SPI */ + writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR); + + /* Configure SPI in Master Mode with No CS selected !!! */ + writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS, + AT91_BASE_SPI + AT91_SPI_MR); + + /* Configure CS0 */ + writel(AT91_SPI_NCPHA | + (AT91_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), + AT91_BASE_SPI + AT91_SPI_CSR(0)); + +#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS1 + /* Configure CS1 */ + writel(AT91_SPI_NCPHA | + (AT91_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), + AT91_BASE_SPI + AT91_SPI_CSR(1)); +#endif + +#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS3 + /* Configure CS3 */ + writel(AT91_SPI_NCPHA | + (AT91_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), + AT91_BASE_SPI + AT91_SPI_CSR(3)); +#endif + + /* SPI_Enable */ + writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR); + + while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS)); + + /* + * Add tempo to get SPI in a safe state. + * Should not be needed for new silicon (Rev B) + */ + udelay(500000); + readl(AT91_BASE_SPI + AT91_SPI_SR); + readl(AT91_BASE_SPI + AT91_SPI_RDR); + +} + +void AT91F_SpiEnable(int cs) +{ + unsigned long mode; + + switch (cs) { + case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ + mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode &= 0xFFF0FFFF; + writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS), + AT91_BASE_SPI + AT91_SPI_MR); + break; + case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */ + mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode &= 0xFFF0FFFF; + writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS), + AT91_BASE_SPI + AT91_SPI_MR); + break; + case 3: + mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode &= 0xFFF0FFFF; + writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS), + AT91_BASE_SPI + AT91_SPI_MR); + break; + } + + /* SPI_Enable */ + writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR); +} + +unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc); + +unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) +{ + unsigned int timeout; + + pDesc->state = BUSY; + + writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR); + + /* Initialize the Transmit and Receive Pointer */ + writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR); + writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR); + + /* Intialize the Transmit and Receive Counters */ + writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR); + writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR); + + if (pDesc->tx_data_size != 0) { + /* Initialize the Next Transmit and Next Receive Pointer */ + writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR); + writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR); + + /* Intialize the Next Transmit and Next Receive Counters */ + writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR); + writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR); + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + timeout = 0; + + writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR); + while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) && + ((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT)); + writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR); + pDesc->state = IDLE; + + if (timeout >= CFG_SPI_WRITE_TOUT) { + printf("Error Timeout\n\r"); + return DATAFLASH_ERROR; + } + + return DATAFLASH_OK; +} diff --git a/cpu/arm926ejs/at91cap9/timer.c b/cpu/arm926ejs/at91sam9/timer.c index 4110e15b5c..4e79466286 100644 --- a/cpu/arm926ejs/at91cap9/timer.c +++ b/cpu/arm926ejs/at91sam9/timer.c @@ -24,36 +24,35 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch/at91_pit.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/io.h> /* - * We're using the AT91CAP9 PITC in 32 bit mode, by + * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by * setting the 20 bit counter period to its maximum (0xfffff). */ #define TIMER_LOAD_VAL 0xfffff -#define READ_RESET_TIMER (AT91C_BASE_PITC->PITC_PIVR) -#define READ_TIMER (AT91C_BASE_PITC->PITC_PIIR) +#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR) +#define READ_TIMER at91_sys_read(AT91_PIT_PIIR) #define TIMER_FREQ (AT91C_MASTER_CLOCK << 4) #define TICKS_TO_USEC(ticks) ((ticks) / 6) ulong get_timer_masked(void); ulong resettime; -AT91PS_PITC p_pitc; - /* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init(void) +int timer_init(void) { /* * Enable PITC Clock * The clock is already enabled for system controller in boot */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS; + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); /* Enable PITC */ - AT91C_BASE_PITC->PITC_PIMR = AT91C_PITC_PITEN; - - /* Load PITC_PIMR with the right timer value */ - AT91C_BASE_PITC->PITC_PIMR |= TIMER_LOAD_VAL; + at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN); reset_timer_masked(); @@ -67,6 +66,7 @@ int interrupt_init(void) static inline ulong get_timer_raw(void) { ulong now = READ_TIMER; + if (now >= resettime) return now - resettime; else @@ -129,20 +129,20 @@ unsigned long long get_ticks(void) ulong get_tbclk(void) { ulong tbclk; + tbclk = CFG_HZ; return tbclk; } /* - * Reset the cpu by setting up the watchdog timer and let him time out - * on the AT91CAP9ADK board + * Reset the cpu by setting up the watchdog timer and let him time out. */ void reset_cpu(ulong ignored) { /* this is the way Linux does it */ - AT91C_BASE_RSTC->RSTC_RCR = (0xA5 << 24) | - AT91C_RSTC_PROCRST | - AT91C_RSTC_PERRST; + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | + AT91_RSTC_PROCRST | + AT91_RSTC_PERRST); while (1); /* Never reached */ diff --git a/cpu/arm926ejs/at91cap9/usb.c b/cpu/arm926ejs/at91sam9/usb.c index 69da5f3a92..d678897dc7 100644 --- a/cpu/arm926ejs/at91cap9/usb.c +++ b/cpu/arm926ejs/at91sam9/usb.c @@ -24,15 +24,16 @@ #include <common.h> #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) -#ifdef CONFIG_AT91CAP9 #include <asm/arch/hardware.h> +#include <asm/arch/io.h> +#include <asm/arch/at91_pmc.h> int usb_cpu_init(void) { /* Enable USB host clock. */ - AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UHP; - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_UHP; + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP); + at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP); return 0; } @@ -40,8 +41,8 @@ int usb_cpu_init(void) int usb_cpu_stop(void) { /* Disable USB host clock. */ - AT91C_BASE_PMC->PMC_PCDR = 1 << AT91C_ID_UHP; - AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_UHP; + at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP); + at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP); return 0; } @@ -50,5 +51,4 @@ int usb_cpu_init_fail(void) return usb_cpu_stop(); } -#endif /* CONFIG_AT91CAP9 */ #endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */ diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c index 8bb8b45713..6c670f0b75 100644 --- a/cpu/arm926ejs/davinci/timer.c +++ b/cpu/arm926ejs/davinci/timer.c @@ -42,9 +42,9 @@ typedef volatile struct { u_int32_t pid12; - u_int32_t emumgt_clksped; - u_int32_t gpint_en; - u_int32_t gpdir_dat; + u_int32_t emumgt; + u_int32_t na1; + u_int32_t na2; u_int32_t tim12; u_int32_t tim34; u_int32_t prd12; @@ -52,21 +52,12 @@ typedef volatile struct { u_int32_t tcr; u_int32_t tgcr; u_int32_t wdtcr; - u_int32_t tlgc; - u_int32_t tlmr; } davinci_timer; davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE; #define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ) -#define READ_TIMER timer->tim34 - -/* - * Timer runs with CFG_HZ_CLOCK, currently 27MHz. To avoid wrap - * around of timestamp already after min ~159s, divide it, e.g. by 16. - * timestamp will then wrap around all min ~42min - */ -#define DIV(x) ((x) >> 4) +#define TIM_CLK_DIV 16 static ulong timestamp; static ulong lastinc; @@ -76,63 +67,51 @@ int timer_init(void) /* We are using timer34 in unchained 32-bit mode, full speed */ timer->tcr = 0x0; timer->tgcr = 0x0; - timer->tgcr = 0x06; + timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8); timer->tim34 = 0x0; timer->prd34 = TIMER_LOAD_VAL; lastinc = 0; - timer->tcr = 0x80 << 16; timestamp = 0; + timer->tcr = 2 << 22; return(0); } void reset_timer(void) { - reset_timer_masked(); -} - -ulong get_timer(ulong base) -{ - return(get_timer_masked() - base); -} - -void set_timer(ulong t) -{ - timestamp = t; -} - -void udelay(unsigned long usec) -{ - udelay_masked(usec); -} - -void reset_timer_masked(void) -{ - lastinc = DIV(READ_TIMER); + timer->tcr = 0x0; + timer->tim34 = 0; + lastinc = 0; timestamp = 0; + timer->tcr = 2 << 22; } -ulong get_timer_raw(void) +static ulong get_timer_raw(void) { - ulong now = DIV(READ_TIMER); + ulong now = timer->tim34; if (now >= lastinc) { /* normal mode */ timestamp += now - lastinc; } else { /* overflow ... */ - timestamp += now + DIV(TIMER_LOAD_VAL) - lastinc; + timestamp += now + TIMER_LOAD_VAL - lastinc; } lastinc = now; return timestamp; } -ulong get_timer_masked(void) +ulong get_timer(ulong base) +{ + return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base); +} + +void set_timer(ulong t) { - return(get_timer_raw() / DIV(TIMER_LOAD_VAL)); + timestamp = t; } -void udelay_masked(unsigned long usec) +void udelay(unsigned long usec) { ulong tmo; ulong endtime; @@ -140,7 +119,7 @@ void udelay_masked(unsigned long usec) tmo = CFG_HZ_CLOCK / 1000; tmo *= usec; - tmo /= 1000; + tmo /= (1000 * TIM_CLK_DIV); endtime = get_timer_raw() + tmo; @@ -165,8 +144,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - ulong tbclk; - - tbclk = CFG_HZ; - return(tbclk); + return CFG_HZ; } diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c index 0971fea814..1819f6b078 100644 --- a/cpu/arm926ejs/interrupts.c +++ b/cpu/arm926ejs/interrupts.c @@ -38,7 +38,7 @@ #include <common.h> #include <arm926ejs.h> -#if defined(CONFIG_INTEGRATOR) || defined(CONFIG_AT91CAP9ADK) +#ifdef CONFIG_INTEGRATOR /* Timer functionality supplied by Integrator board (AP or CP) */ diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h deleted file mode 100644 index 9970b723d5..0000000000 --- a/cpu/bf533/bf533_serial.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * U-boot - bf533_serial.h Serial Driver defines - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver. - * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl> - * BuyWays B.V. (www.buyways.nl) - * - * Based heavily on: - * blkfinserial.h: Definitions for the BlackFin DSP serial driver. - * - * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com - * Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com> - * - * Based on code from 68328serial.c which was: - * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu> - * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com> - * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org> - * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _Bf533_SERIAL_H -#define _Bf533_SERIAL_H - -#include <linux/config.h> -#include <asm/blackfin.h> - -#define SYNC_ALL __asm__ __volatile__ ("ssync;\n") -#define ACCESS_LATCH *pUART_LCR |= DLAB; -#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB); - -void serial_setbrg(void); -static void local_put_char(char ch); -void calc_baud(void); -void serial_setbrg(void); -int serial_init(void); -void serial_putc(const char c); -int serial_tstc(void); -int serial_getc(void); -void serial_puts(const char *s); -static void local_put_char(char ch); - -int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 }; - -struct { - unsigned char dl_high; - unsigned char dl_low; -} hw_baud_table[5]; - -#ifdef CONFIG_STAMP -extern unsigned long pll_div_fact; -#endif - -#endif diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S deleted file mode 100644 index d9015c6d1a..0000000000 --- a/cpu/bf533/cache.S +++ /dev/null @@ -1,129 +0,0 @@ -#define ASSEMBLY -#include <asm/linkage.h> -#include <config.h> -#include <asm/blackfin.h> -#include <asm/mach-common/bits/mpu.h> - -.text -.align 2 -ENTRY(_blackfin_icache_flush_range) - R2 = -32; - R2 = R0 & R2; - P0 = R2; - P1 = R1; - CSYNC; - 1: - IFLUSH[P0++]; - CC = P0 < P1(iu); - IF CC JUMP 1b(bp); - IFLUSH[P0]; - SSYNC; - RTS; - -ENTRY(_blackfin_dcache_flush_range) - R2 = -32; - R2 = R0 & R2; - P0 = R2; - P1 = R1; - CSYNC; -1: - FLUSH[P0++]; - CC = P0 < P1(iu); - IF CC JUMP 1b(bp); - FLUSH[P0]; - SSYNC; - RTS; - -ENTRY(_icache_invalidate) -ENTRY(_invalidate_entire_icache) - [--SP] = (R7:5); - - P0.L = (IMEM_CONTROL & 0xFFFF); - P0.H = (IMEM_CONTROL >> 16); - R7 =[P0]; - - /* - * Clear the IMC bit , All valid bits in the instruction - * cache are set to the invalid state - */ - BITCLR(R7, IMC_P); - CLI R6; - /* SSYNC required before invalidating cache. */ - SSYNC; - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - /* Configures the instruction cache agian */ - R6 = (IMC | ENICPLB); - R7 = R7 | R6; - - CLI R6; - SSYNC; - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - (R7:5) =[SP++]; - RTS; - -/* - * Invalidate the Entire Data cache by - * clearing DMC[1:0] bits - */ -ENTRY(_invalidate_entire_dcache) -ENTRY(_dcache_invalidate) - [--SP] = (R7:6); - - P0.L = (DMEM_CONTROL & 0xFFFF); - P0.H = (DMEM_CONTROL >> 16); - R7 =[P0]; - - /* - * Clear the DMC[1:0] bits, All valid bits in the data - * cache are set to the invalid state - */ - BITCLR(R7, DMC0_P); - BITCLR(R7, DMC1_P); - CLI R6; - SSYNC; - .align 8; - [P0] = R7; - SSYNC; - STI R6; - /* Configures the data cache again */ - - R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - R7 = R7 | R6; - - CLI R6; - SSYNC; - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - (R7:6) =[SP++]; - RTS; - -ENTRY(_blackfin_dcache_invalidate_range) - R2 = -32; - R2 = R0 & R2; - P0 = R2; - P1 = R1; - CSYNC; -1: - FLUSHINV[P0++]; - CC = P0 < P1(iu); - IF CC JUMP 1b(bp); - - /* - * If the data crosses a cache line, then we'll be pointing to - * the last cache line, but won't have flushed/invalidated it yet, so do - * one more. - */ - FLUSHINV[P0]; - SSYNC; - RTS; diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c deleted file mode 100644 index edb771e33c..0000000000 --- a/cpu/bf533/cpu.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * U-boot - cpu.c CPU specific functions - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <asm/blackfin.h> -#include <command.h> -#include <asm/entry.h> -#include <asm/cplb.h> -#include <asm/io.h> - -#define CACHE_ON 1 -#define CACHE_OFF 0 - -extern unsigned int icplb_table[page_descriptor_table_size][2]; -extern unsigned int dcplb_table[page_descriptor_table_size][2]; - -int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) - ); - - return 0; -} - -/* These functions are just used to satisfy the linker */ -int cpu_init(void) -{ - return 0; -} - -int cleanup_before_linux(void) -{ - return 0; -} - -void icache_enable(void) -{ - unsigned int *I0, *I1; - int i, j = 0; - - /* Before enable icache, disable it first */ - icache_disable(); - I0 = (unsigned int *)ICPLB_ADDR0; - I1 = (unsigned int *)ICPLB_DATA0; - - /* make sure the locked ones go in first */ - for (i = 0; i < page_descriptor_table_size; i++) { - if (CPLB_LOCK & icplb_table[i][1]) { - debug("adding %02i %02i 0x%08x 0x%08x\n", i, j, - icplb_table[i][0], icplb_table[i][1]); - *I0++ = icplb_table[i][0]; - *I1++ = icplb_table[i][1]; - j++; - } - } - - for (i = 0; i < page_descriptor_table_size; i++) { - if (!(CPLB_LOCK & icplb_table[i][1])) { - debug("adding %02i %02i 0x%08x 0x%08x\n", i, j, - icplb_table[i][0], icplb_table[i][1]); - *I0++ = icplb_table[i][0]; - *I1++ = icplb_table[i][1]; - j++; - if (j == 16) { - break; - } - } - } - - /* Fill the rest with invalid entry */ - if (j <= 15) { - for (; j < 16; j++) { - debug("filling %i with 0", j); - *I1++ = 0x0; - } - - } - - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - SSYNC(); -} - -void icache_disable(void) -{ - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - SSYNC(); -} - -int icache_status(void) -{ - unsigned int value; - value = *(unsigned int *)IMEM_CONTROL; - - if (value & (IMC | ENICPLB)) - return CACHE_ON; - else - return CACHE_OFF; -} - -void dcache_enable(void) -{ - unsigned int *I0, *I1; - unsigned int temp; - int i, j = 0; - - /* Before enable dcache, disable it first */ - dcache_disable(); - I0 = (unsigned int *)DCPLB_ADDR0; - I1 = (unsigned int *)DCPLB_DATA0; - - /* make sure the locked ones go in first */ - for (i = 0; i < page_descriptor_table_size; i++) { - if (CPLB_LOCK & dcplb_table[i][1]) { - debug("adding %02i %02i 0x%08x 0x%08x\n", i, j, - dcplb_table[i][0], dcplb_table[i][1]); - *I0++ = dcplb_table[i][0]; - *I1++ = dcplb_table[i][1]; - j++; - } else { - debug("skip %02i %02i 0x%08x 0x%08x\n", i, j, - dcplb_table[i][0], dcplb_table[i][1]); - } - } - - for (i = 0; i < page_descriptor_table_size; i++) { - if (!(CPLB_LOCK & dcplb_table[i][1])) { - debug("adding %02i %02i 0x%08x 0x%08x\n", i, j, - dcplb_table[i][0], dcplb_table[i][1]); - *I0++ = dcplb_table[i][0]; - *I1++ = dcplb_table[i][1]; - j++; - if (j == 16) { - break; - } - } - } - - /* Fill the rest with invalid entry */ - if (j <= 15) { - for (; j < 16; j++) { - debug("filling %i with 0", j); - *I1++ = 0x0; - } - } - - temp = *(unsigned int *)DMEM_CONTROL; - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)DMEM_CONTROL = - ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - SSYNC(); -} - -void dcache_disable(void) -{ - unsigned int *I0, *I1; - int i; - - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)DMEM_CONTROL &= - ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - SSYNC(); - - /* after disable dcache, - * clear it so we don't confuse the next application - */ - I0 = (unsigned int *)DCPLB_ADDR0; - I1 = (unsigned int *)DCPLB_DATA0; - - for (i = 0; i < 16; i++) { - *I0++ = 0x0; - *I1++ = 0x0; - } -} - -int dcache_status(void) -{ - unsigned int value; - value = *(unsigned int *)DMEM_CONTROL; - if (value & (ENDCPLB)) - return CACHE_ON; - else - return CACHE_OFF; -} diff --git a/cpu/bf533/cpu.h b/cpu/bf533/cpu.h deleted file mode 100644 index b6b73b1d8f..0000000000 --- a/cpu/bf533/cpu.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * U-boot - cpu.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _CPU_H_ -#define _CPU_H_ - -#include <command.h> - -#define INTERNAL_IRQS (32) -#define NUM_IRQ_NODES 16 -#define DEF_INTERRUPT_FLAGS 1 -#define MAX_TIM_LOAD 0xFFFFFFFF - -void blackfin_irq_panic(int reason, struct pt_regs *reg); -extern void dump(struct pt_regs *regs); -void display_excp(void); -asmlinkage void evt_nmi(void); -asmlinkage void evt_exception(void); -asmlinkage void trap(void); -asmlinkage void evt_ivhw(void); -asmlinkage void evt_rst(void); -asmlinkage void evt_timer(void); -asmlinkage void evt_evt7(void); -asmlinkage void evt_evt8(void); -asmlinkage void evt_evt9(void); -asmlinkage void evt_evt10(void); -asmlinkage void evt_evt11(void); -asmlinkage void evt_evt12(void); -asmlinkage void evt_evt13(void); -asmlinkage void evt_soft_int1(void); -asmlinkage void evt_system_call(void); -void blackfin_irq_panic(int reason, struct pt_regs *regs); -void blackfin_free_irq(unsigned int irq, void *dev_id); -void call_isr(int irq, struct pt_regs *fp); -void blackfin_do_irq(int vec, struct pt_regs *fp); -void blackfin_init_IRQ(void); -void blackfin_enable_irq(unsigned int irq); -void blackfin_disable_irq(unsigned int irq); -extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); -int blackfin_request_irq(unsigned int irq, - void (*handler) (int, void *, struct pt_regs *), - unsigned long flags, const char *devname, - void *dev_id); -void timer_init(void); -#endif diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S deleted file mode 100644 index 62e3d65ae7..0000000000 --- a/cpu/bf533/flush.S +++ /dev/null @@ -1,405 +0,0 @@ -/* Copyright (C) 2003-2007 Analog Devices Inc. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. - */ - -#define ASSEMBLY - -#include <asm/linkage.h> -#include <asm/cplb.h> -#include <config.h> -#include <asm/blackfin.h> - -.text - -/* This is an external function being called by the user - * application through __flush_cache_all. Currently this function - * serves the purpose of flushing all the pending writes in - * in the instruction cache. - */ - -ENTRY(_flush_instruction_cache) - [--SP] = ( R7:6, P5:4 ); - LINK 12; - SP += -12; - P5.H = (ICPLB_ADDR0 >> 16); - P5.L = (ICPLB_ADDR0 & 0xFFFF); - P4.H = (ICPLB_DATA0 >> 16); - P4.L = (ICPLB_DATA0 & 0xFFFF); - R7 = CPLB_VALID | CPLB_L1_CHBL; - R6 = 16; -inext: R0 = [P5++]; - R1 = [P4++]; - [--SP] = RETS; - CALL _icplb_flush; /* R0 = page, R1 = data*/ - RETS = [SP++]; -iskip: R6 += -1; - CC = R6; - IF CC JUMP inext; - SSYNC; - SP += 12; - UNLINK; - ( R7:6, P5:4 ) = [SP++]; - RTS; - -/* This is an internal function to flush all pending - * writes in the cache associated with a particular ICPLB. - * - * R0 - page's start address - * R1 - CPLB's data field. - */ - -.align 2 -ENTRY(_icplb_flush) - [--SP] = ( R7:0, P5:0 ); - [--SP] = LC0; - [--SP] = LT0; - [--SP] = LB0; - [--SP] = LC1; - [--SP] = LT1; - [--SP] = LB1; - - /* If it's a 1K or 4K page, then it's quickest to - * just systematically flush all the addresses in - * the page, regardless of whether they're in the - * cache, or dirty. If it's a 1M or 4M page, there - * are too many addresses, and we have to search the - * cache for lines corresponding to the page. - */ - - CC = BITTST(R1, 17); /* 1MB or 4MB */ - IF !CC JUMP iflush_whole_page; - - /* We're only interested in the page's size, so extract - * this from the CPLB (bits 17:16), and scale to give an - * offset into the page_size and page_prefix tables. - */ - - R1 <<= 14; - R1 >>= 30; - R1 <<= 2; - - /* We can also determine the sub-bank used, because this is - * taken from bits 13:12 of the address. - */ - - R3 = ((12<<8)|2); /* Extraction pattern */ - nop; /* Anamoly 05000209 */ - R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */ - - /* Save in extraction pattern for later deposit. */ - R3.H = R4.L << 0; - - /* So: - * R0 = Page start - * R1 = Page length (actually, offset into size/prefix tables) - * R3 = sub-bank deposit values - * - * The cache has 2 Ways, and 64 sets, so we iterate through - * the sets, accessing the tag for each Way, for our Bank and - * sub-bank, looking for dirty, valid tags that match our - * address prefix. - */ - - P5.L = (ITEST_COMMAND & 0xFFFF); - P5.H = (ITEST_COMMAND >> 16); - P4.L = (ITEST_DATA0 & 0xFFFF); - P4.H = (ITEST_DATA0 >> 16); - - P0.L = page_prefix_table; - P0.H = page_prefix_table; - P1 = R1; - R5 = 0; /* Set counter*/ - P0 = P1 + P0; - R4 = [P0]; /* This is the address prefix*/ - - /* We're reading (bit 1==0) the tag (bit 2==0), and we - * don't care about which double-word, since we're only - * fetching tags, so we only have to set Set, Bank, - * Sub-bank and Way. - */ - - P2 = 4; - LSETUP (ifs1, ife1) LC1 = P2; -ifs1: P0 = 32; /* iterate over all sets*/ - LSETUP (ifs0, ife0) LC0 = P0; -ifs0: R6 = R5 << 5; /* Combine set*/ - R6.H = R3.H << 0 ; /* and sub-bank*/ - [P5] = R6; /* Issue Command*/ - SSYNC; /* CSYNC will not work here :(*/ - R7 = [P4]; /* and read Tag.*/ - CC = BITTST(R7, 0); /* Check if valid*/ - IF !CC JUMP ifskip; /* and skip if not.*/ - - /* Compare against the page address. First, plant bits 13:12 - * into the tag, since those aren't part of the returned data. - */ - - R7 = DEPOSIT(R7, R3); /* set 13:12*/ - R1 = R7 & R4; /* Mask off lower bits*/ - CC = R1 == R0; /* Compare against page start.*/ - IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/ - - /* Tag address matches against page, so this is an entry - * we must flush. - */ - - R7 >>= 10; /* Mask off the non-address bits*/ - R7 <<= 10; - P3 = R7; - IFLUSH [P3]; /* And flush the entry*/ -ifskip: -ife0: R5 += 1; /* Advance to next Set*/ -ife1: NOP; - -ifinished: - SSYNC; /* Ensure the data gets out to mem.*/ - - /*Finished. Restore context.*/ - LB1 = [SP++]; - LT1 = [SP++]; - LC1 = [SP++]; - LB0 = [SP++]; - LT0 = [SP++]; - LC0 = [SP++]; - ( R7:0, P5:0 ) = [SP++]; - RTS; - -iflush_whole_page: - /* It's a 1K or 4K page, so quicker to just flush the - * entire page. - */ - - P1 = 32; /* For 1K pages*/ - P2 = P1 << 2; /* For 4K pages*/ - P0 = R0; /* Start of page*/ - CC = BITTST(R1, 16); /* Whether 1K or 4K*/ - IF CC P1 = P2; - P1 += -1; /* Unroll one iteration*/ - SSYNC; - IFLUSH [P0++]; /* because CSYNC can't end loops.*/ - LSETUP (isall, ieall) LC0 = P1; -isall: - IFLUSH [P0++]; -ieall: - NOP; - SSYNC; - JUMP ifinished; - -/* This is an external function being called by the user - * application through __flush_cache_all. Currently this function - * serves the purpose of flushing all the pending writes in - * in the data cache. - */ - -ENTRY(_flush_data_cache) - [--SP] = ( R7:6, P5:4 ); - LINK 12; - SP += -12; - P5.H = (DCPLB_ADDR0 >> 16); - P5.L = (DCPLB_ADDR0 & 0xFFFF); - P4.H = (DCPLB_DATA0 >> 16); - P4.L = (DCPLB_DATA0 & 0xFFFF); - R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z); - R6 = 16; -next: R0 = [P5++]; - R1 = [P4++]; - CC = BITTST(R1, 14); /* Is it write-through?*/ - IF CC JUMP skip; /* If so, ignore it.*/ - R2 = R1 & R7; /* Is it a dirty, cached page?*/ - CC = R2; - IF !CC JUMP skip; /* If not, ignore it.*/ - [--SP] = RETS; - CALL _dcplb_flush; /* R0 = page, R1 = data*/ - RETS = [SP++]; -skip: R6 += -1; - CC = R6; - IF CC JUMP next; - SSYNC; - SP += 12; - UNLINK; - ( R7:6, P5:4 ) = [SP++]; - RTS; - -/* This is an internal function to flush all pending - * writes in the cache associated with a particular DCPLB. - * - * R0 - page's start address - * R1 - CPLB's data field. - */ - -.align 2 -ENTRY(_dcplb_flush) - [--SP] = ( R7:0, P5:0 ); - [--SP] = LC0; - [--SP] = LT0; - [--SP] = LB0; - [--SP] = LC1; - [--SP] = LT1; - [--SP] = LB1; - - /* If it's a 1K or 4K page, then it's quickest to - * just systematically flush all the addresses in - * the page, regardless of whether they're in the - * cache, or dirty. If it's a 1M or 4M page, there - * are too many addresses, and we have to search the - * cache for lines corresponding to the page. - */ - - CC = BITTST(R1, 17); /* 1MB or 4MB */ - IF !CC JUMP dflush_whole_page; - - /* We're only interested in the page's size, so extract - * this from the CPLB (bits 17:16), and scale to give an - * offset into the page_size and page_prefix tables. - */ - - R1 <<= 14; - R1 >>= 30; - R1 <<= 2; - - /* The page could be mapped into Bank A or Bank B, depending - * on (a) whether both banks are configured as cache, and - * (b) on whether address bit A[x] is set. x is determined - * by DCBS in DMEM_CONTROL - */ - - R2 = 0; /* Default to Bank A (Bank B would be 1)*/ - - P0.L = (DMEM_CONTROL & 0xFFFF); - P0.H = (DMEM_CONTROL >> 16); - - R3 = [P0]; /* If Bank B is not enabled as cache*/ - CC = BITTST(R3, 2); /* then Bank A is our only option.*/ - IF CC JUMP bank_chosen; - - R4 = 1<<14; /* If DCBS==0, use A[14].*/ - R5 = R4 << 7; /* If DCBS==1, use A[23];*/ - CC = BITTST(R3, 4); - IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/ - R5 = R0 & R4; /* Use it to test the Page address*/ - CC = R5; /* and if that bit is set, we use Bank B,*/ - R2 = CC; /* else we use Bank A.*/ - R2 <<= 23; /* The Bank selection's at posn 23.*/ - -bank_chosen: - - /* We can also determine the sub-bank used, because this is - * taken from bits 13:12 of the address. - */ - - R3 = ((12<<8)|2); /* Extraction pattern */ - nop; /*Anamoly 05000209*/ - R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/ - /* Save in extraction pattern for later deposit.*/ - R3.H = R4.L << 0; - - /* So: - * R0 = Page start - * R1 = Page length (actually, offset into size/prefix tables) - * R2 = Bank select mask - * R3 = sub-bank deposit values - * - * The cache has 2 Ways, and 64 sets, so we iterate through - * the sets, accessing the tag for each Way, for our Bank and - * sub-bank, looking for dirty, valid tags that match our - * address prefix. - */ - - P5.L = (DTEST_COMMAND & 0xFFFF); - P5.H = (DTEST_COMMAND >> 16); - P4.L = (DTEST_DATA0 & 0xFFFF); - P4.H = (DTEST_DATA0 >> 16); - - P0.L = page_prefix_table; - P0.H = page_prefix_table; - P1 = R1; - R5 = 0; /* Set counter*/ - P0 = P1 + P0; - R4 = [P0]; /* This is the address prefix*/ - - - /* We're reading (bit 1==0) the tag (bit 2==0), and we - * don't care about which double-word, since we're only - * fetching tags, so we only have to set Set, Bank, - * Sub-bank and Way. - */ - - P2 = 2; - LSETUP (fs1, fe1) LC1 = P2; -fs1: P0 = 64; /* iterate over all sets*/ - LSETUP (fs0, fe0) LC0 = P0; -fs0: R6 = R5 << 5; /* Combine set*/ - R6.H = R3.H << 0 ; /* and sub-bank*/ - R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/ - BITSET(R6,14); - [P5] = R6; /* Issue Command*/ - SSYNC; - R7 = [P4]; /* and read Tag.*/ - CC = BITTST(R7, 0); /* Check if valid*/ - IF !CC JUMP fskip; /* and skip if not.*/ - CC = BITTST(R7, 1); /* Check if dirty*/ - IF !CC JUMP fskip; /* and skip if not.*/ - - /* Compare against the page address. First, plant bits 13:12 - * into the tag, since those aren't part of the returned data. - */ - - R7 = DEPOSIT(R7, R3); /* set 13:12*/ - R1 = R7 & R4; /* Mask off lower bits*/ - CC = R1 == R0; /* Compare against page start.*/ - IF !CC JUMP fskip; /* Skip it if it doesn't match.*/ - - /* Tag address matches against page, so this is an entry - * we must flush. - */ - - R7 >>= 10; /* Mask off the non-address bits*/ - R7 <<= 10; - P3 = R7; - SSYNC; - FLUSHINV [P3]; /* And flush the entry*/ -fskip: -fe0: R5 += 1; /* Advance to next Set*/ -fe1: BITSET(R2, 26); /* Go to next Way.*/ - -dfinished: - SSYNC; /* Ensure the data gets out to mem.*/ - - /*Finished. Restore context.*/ - LB1 = [SP++]; - LT1 = [SP++]; - LC1 = [SP++]; - LB0 = [SP++]; - LT0 = [SP++]; - LC0 = [SP++]; - ( R7:0, P5:0 ) = [SP++]; - RTS; - -dflush_whole_page: - - /* It's a 1K or 4K page, so quicker to just flush the - * entire page. - */ - - P1 = 32; /* For 1K pages*/ - P2 = P1 << 2; /* For 4K pages*/ - P0 = R0; /* Start of page*/ - CC = BITTST(R1, 16); /* Whether 1K or 4K*/ - IF CC P1 = P2; - P1 += -1; /* Unroll one iteration*/ - SSYNC; - FLUSHINV [P0++]; /* because CSYNC can't end loops.*/ - LSETUP (eall, eall) LC0 = P1; -eall: FLUSHINV [P0++]; - SSYNC; - JUMP dfinished; - -.align 4; -page_prefix_table: -.byte4 0xFFFFFC00; /* 1K */ -.byte4 0xFFFFF000; /* 4K */ -.byte4 0xFFF00000; /* 1M */ -.byte4 0xFFC00000; /* 4M */ -.page_prefix_table.end: diff --git a/cpu/bf533/init_sdram.S b/cpu/bf533/init_sdram.S deleted file mode 100644 index 67a99e46bd..0000000000 --- a/cpu/bf533/init_sdram.S +++ /dev/null @@ -1,183 +0,0 @@ -#define ASSEMBLY - -#include <linux/config.h> -#include <config.h> -#include <asm/blackfin.h> -#include <asm/mem_init.h> -#include <asm/mach-common/bits/bootrom.h> -#include <asm/mach-common/bits/ebiu.h> -#include <asm/mach-common/bits/pll.h> -#include <asm/mach-common/bits/uart.h> -.global init_sdram; - -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif - -init_sdram: - [--SP] = ASTAT; - [--SP] = RETS; - [--SP] = (R7:0); - [--SP] = (P5:0); - -#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) - p0.h = hi(SPI_BAUD); - p0.l = lo(SPI_BAUD); - r0.l = CONFIG_SPI_BAUD; - w[p0] = r0.l; - SSYNC; -#endif - - /* - * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable - */ - p0.h = hi(PLL_LOCKCNT); - p0.l = lo(PLL_LOCKCNT); - r0 = 0x300(Z); - w[p0] = r0.l; - ssync; - - /* - * Put SDRAM in self-refresh, incase anything is running - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITSET (R0, 24); - [P2] = R0; - SSYNC; - - /* - * Set PLL_CTL with the value that we calculate in R0 - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK - * - [7] = output delay (add 200ps of delay to mem signals) - * - [6] = input delay (add 200ps of input delay to mem signals) - * - [5] = PDWN : 1=All Clocks off - * - [3] = STOPCK : 1=Core Clock off - * - [1] = PLL_OFF : 1=Disable Power to PLL - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL - * all other bits set to zero - */ - - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ - r0 = r0 << 9; /* Shift it over, */ - r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ - r0 = r1 | r0; - r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ - r1 = r1 << 8; /* Shift it over */ - r0 = r1 | r0; /* add them all together */ - - p0.h = hi(PLL_CTL); - p0.l = lo(PLL_CTL); /* Load the address */ - cli r2; /* Disable interrupts */ - ssync; - w[p0] = r0.l; /* Set the value */ - idle; /* Wait for the PLL to stablize */ - sti r2; /* Enable interrupts */ - -check_again: - p0.h = hi(PLL_STAT); - p0.l = lo(PLL_STAT); - R0 = W[P0](Z); - CC = BITTST(R0,5); - if ! CC jump check_again; - - /* Configure SCLK & CCLK Dividers */ - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); - p0.h = hi(PLL_DIV); - p0.l = lo(PLL_DIV); - w[p0] = r0.l; - ssync; - - /* - * We now are running at speed, time to set the Async mem bank wait states - * This will speed up execution, since we are normally running from FLASH. - */ - - p2.h = (EBIU_AMBCTL1 >> 16); - p2.l = (EBIU_AMBCTL1 & 0xFFFF); - r0.h = (AMBCTL1VAL >> 16); - r0.l = (AMBCTL1VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMBCTL0 >> 16); - p2.l = (EBIU_AMBCTL0 & 0xFFFF); - r0.h = (AMBCTL0VAL >> 16); - r0.l = (AMBCTL0VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMGCTL >> 16); - p2.l = (EBIU_AMGCTL & 0xffff); - r0 = AMGCTLVAL; - w[p2] = r0; - ssync; - - /* - * Now, Initialize the SDRAM, - * start with the SDRAM Refresh Rate Control Register - */ - p0.l = lo(EBIU_SDRRC); - p0.h = hi(EBIU_SDRRC); - r0 = mem_SDRRC; - w[p0] = r0.l; - ssync; - - /* - * SDRAM Memory Bank Control Register - bank specific parameters - */ - p0.l = (EBIU_SDBCTL & 0xFFFF); - p0.h = (EBIU_SDBCTL >> 16); - r0 = mem_SDBCTL; - w[p0] = r0.l; - ssync; - - /* - * SDRAM Global Control Register - global programmable parameters - * Disable self-refresh - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITCLR (R0, 24); - - /* - * Check if SDRAM is already powered up, if it is, enable self-refresh - */ - p0.h = hi(EBIU_SDSTAT); - p0.l = lo(EBIU_SDSTAT); - r2.l = w[p0]; - cc = bittst(r2,3); - if !cc jump skip; - NOP; - BITSET (R0, 23); -skip: - [P2] = R0; - SSYNC; - - /* Write in the new value in the register */ - R0.L = lo(mem_SDGCTL); - R0.H = hi(mem_SDGCTL); - [P2] = R0; - SSYNC; - nop; - - (P5:0) = [SP++]; - (R7:0) = [SP++]; - RETS = [SP++]; - ASTAT = [SP++]; - RTS; diff --git a/cpu/bf533/init_sdram_bootrom_initblock.S b/cpu/bf533/init_sdram_bootrom_initblock.S deleted file mode 100644 index 8694ca2c2c..0000000000 --- a/cpu/bf533/init_sdram_bootrom_initblock.S +++ /dev/null @@ -1,183 +0,0 @@ -#define ASSEMBLY - -#include <linux/config.h> -#include <config.h> -#include <asm/blackfin.h> -#include <asm/mem_init.h> -#include <asm/mach-common/bits/bootrom.h> -#include <asm/mach-common/bits/ebiu.h> -#include <asm/mach-common/bits/pll.h> -#include <asm/mach-common/bits/uart.h> -.global init_sdram; - -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif - -init_sdram: - [--SP] = ASTAT; - [--SP] = RETS; - [--SP] = (R7:0); - [--SP] = (P5:0); - -#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) - p0.h = hi(SPI_BAUD); - p0.l = lo(SPI_BAUD); - r0.l = CONFIG_SPI_BAUD_INITBLOCK; - w[p0] = r0.l; - SSYNC; -#endif - - /* - * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable - */ - p0.h = hi(PLL_LOCKCNT); - p0.l = lo(PLL_LOCKCNT); - r0 = 0x300(Z); - w[p0] = r0.l; - ssync; - - /* - * Put SDRAM in self-refresh, incase anything is running - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITSET (R0, 24); - [P2] = R0; - SSYNC; - - /* - * Set PLL_CTL with the value that we calculate in R0 - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK - * - [7] = output delay (add 200ps of delay to mem signals) - * - [6] = input delay (add 200ps of input delay to mem signals) - * - [5] = PDWN : 1=All Clocks off - * - [3] = STOPCK : 1=Core Clock off - * - [1] = PLL_OFF : 1=Disable Power to PLL - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL - * all other bits set to zero - */ - - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ - r0 = r0 << 9; /* Shift it over, */ - r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ - r0 = r1 | r0; - r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ - r1 = r1 << 8; /* Shift it over */ - r0 = r1 | r0; /* add them all together */ - - p0.h = hi(PLL_CTL); - p0.l = lo(PLL_CTL); /* Load the address */ - cli r2; /* Disable interrupts */ - ssync; - w[p0] = r0.l; /* Set the value */ - idle; /* Wait for the PLL to stablize */ - sti r2; /* Enable interrupts */ - -check_again: - p0.h = hi(PLL_STAT); - p0.l = lo(PLL_STAT); - R0 = W[P0](Z); - CC = BITTST(R0,5); - if ! CC jump check_again; - - /* Configure SCLK & CCLK Dividers */ - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); - p0.h = hi(PLL_DIV); - p0.l = lo(PLL_DIV); - w[p0] = r0.l; - ssync; - - /* - * We now are running at speed, time to set the Async mem bank wait states - * This will speed up execution, since we are normally running from FLASH. - */ - - p2.h = (EBIU_AMBCTL1 >> 16); - p2.l = (EBIU_AMBCTL1 & 0xFFFF); - r0.h = (AMBCTL1VAL >> 16); - r0.l = (AMBCTL1VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMBCTL0 >> 16); - p2.l = (EBIU_AMBCTL0 & 0xFFFF); - r0.h = (AMBCTL0VAL >> 16); - r0.l = (AMBCTL0VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMGCTL >> 16); - p2.l = (EBIU_AMGCTL & 0xffff); - r0 = AMGCTLVAL; - w[p2] = r0; - ssync; - - /* - * Now, Initialize the SDRAM, - * start with the SDRAM Refresh Rate Control Register - */ - p0.l = lo(EBIU_SDRRC); - p0.h = hi(EBIU_SDRRC); - r0 = mem_SDRRC; - w[p0] = r0.l; - ssync; - - /* - * SDRAM Memory Bank Control Register - bank specific parameters - */ - p0.l = (EBIU_SDBCTL & 0xFFFF); - p0.h = (EBIU_SDBCTL >> 16); - r0 = mem_SDBCTL; - w[p0] = r0.l; - ssync; - - /* - * SDRAM Global Control Register - global programmable parameters - * Disable self-refresh - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITCLR (R0, 24); - - /* - * Check if SDRAM is already powered up, if it is, enable self-refresh - */ - p0.h = hi(EBIU_SDSTAT); - p0.l = lo(EBIU_SDSTAT); - r2.l = w[p0]; - cc = bittst(r2,3); - if !cc jump skip; - NOP; - BITSET (R0, 23); -skip: - [P2] = R0; - SSYNC; - - /* Write in the new value in the register */ - R0.L = lo(mem_SDGCTL); - R0.H = hi(mem_SDGCTL); - [P2] = R0; - SSYNC; - nop; - - (P5:0) = [SP++]; - (R7:0) = [SP++]; - RETS = [SP++]; - ASTAT = [SP++]; - RTS; diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S deleted file mode 100644 index 7556ec9fbd..0000000000 --- a/cpu/bf533/interrupt.S +++ /dev/null @@ -1,244 +0,0 @@ -/* - * U-boot - interrupt.S Processing of interrupts and exception handling - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on interrupt.S - * - * Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com> - * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca> - * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, - * Kenneth Albanowski <kjahds@kjahds.com>, - * The Silver Hammer Group, Ltd. - * - * (c) 1995, Dionne & Associates - * (c) 1995, DKG Display Tech. - * - * This file is also based on exception.asm - * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#define ASSEMBLY -#include <config.h> -#include <asm/blackfin.h> -#include <asm/entry.h> - -.global _blackfin_irq_panic; - -.text -.align 2 - -#ifndef CONFIG_KGDB -.global _evt_emulation -_evt_emulation: - SAVE_CONTEXT - r0 = 0; - r1 = seqstat; - sp += -12; - call _blackfin_irq_panic; - sp += 12; - rte; -#endif - -.global _evt_nmi -_evt_nmi: - SAVE_CONTEXT - r0 = 2; - r1 = RETN; - sp += -12; - call _blackfin_irq_panic; - sp += 12; - -_evt_nmi_exit: - rtn; - -.global _trap -_trap: - SAVE_ALL_SYS - r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ - sp += -12; - call _trap_c - sp += 12; - RESTORE_ALL_SYS - rtx; - -.global _evt_rst -_evt_rst: - SAVE_CONTEXT - r0 = 1; - r1 = RETN; - sp += -12; - call _do_reset; - sp += 12; - -_evt_rst_exit: - rtn; - -irq_panic: - r0 = 3; - r1 = sp; - sp += -12; - call _blackfin_irq_panic; - sp += 12; - -.global _evt_ivhw -_evt_ivhw: - SAVE_CONTEXT - RAISE 14; - -_evt_ivhw_exit: - rti; - -.global _evt_timer -_evt_timer: - SAVE_CONTEXT - r0 = 6; - sp += -12; - /* Polling method used now. */ - /* call timer_int; */ - sp += 12; - RESTORE_CONTEXT - rti; - nop; - -.global _evt_evt7 -_evt_evt7: - SAVE_CONTEXT - r0 = 7; - sp += -12; - call _process_int; - sp += 12; - -evt_evt7_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt8 -_evt_evt8: - SAVE_CONTEXT - r0 = 8; - sp += -12; - call _process_int; - sp += 12; - -evt_evt8_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt9 -_evt_evt9: - SAVE_CONTEXT - r0 = 9; - sp += -12; - call _process_int; - sp += 12; - -evt_evt9_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt10 -_evt_evt10: - SAVE_CONTEXT - r0 = 10; - sp += -12; - call _process_int; - sp += 12; - -evt_evt10_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt11 -_evt_evt11: - SAVE_CONTEXT - r0 = 11; - sp += -12; - call _process_int; - sp += 12; - -evt_evt11_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt12 -_evt_evt12: - SAVE_CONTEXT - r0 = 12; - sp += -12; - call _process_int; - sp += 12; -evt_evt12_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt13 -_evt_evt13: - SAVE_CONTEXT - r0 = 13; - sp += -12; - call _process_int; - sp += 12; - -evt_evt13_exit: - RESTORE_CONTEXT - rti; - -.global _evt_system_call -_evt_system_call: - [--sp] = r0; - [--SP] = RETI; - r0 = [sp++]; - r0 += 2; - [--sp] = r0; - RETI = [SP++]; - r0 = [SP++]; - SAVE_CONTEXT - sp += -12; - call _exception_handle; - sp += 12; - RESTORE_CONTEXT - RTI; - -evt_system_call_exit: - rti; - -.global _evt_soft_int1 -_evt_soft_int1: - [--sp] = r0; - [--SP] = RETI; - r0 = [sp++]; - r0 += 2; - [--sp] = r0; - RETI = [SP++]; - r0 = [SP++]; - SAVE_CONTEXT - sp += -12; - call _exception_handle; - sp += 12; - RESTORE_CONTEXT - RTI; - -evt_soft_int1_exit: - rti; diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c deleted file mode 100644 index 3d1c3bc8c2..0000000000 --- a/cpu/bf533/interrupts.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * U-boot - interrupts.c Interrupt related routines - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on interrupts.c - * Copyright 1996 Roman Zippel - * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org> - * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> - * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> - * Copyright 2003 Metrowerks/Motorola - * Copyright 2003 Bas Vermeulen <bas@buyways.nl>, - * BuyWays B.V. (www.buyways.nl) - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <config.h> -#include <asm/blackfin.h> -#include "cpu.h" - -static ulong timestamp; -static ulong last_time; -static int int_flag; - -int irq_flags; /* needed by asm-blackfin/system.h */ - -/* Functions just to satisfy the linker */ - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On BF533 it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On BF533 it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - ulong tbclk; - - tbclk = CFG_HZ; - return tbclk; -} - -void enable_interrupts(void) -{ -} - -int disable_interrupts(void) -{ - return 1; -} - -int interrupt_init(void) -{ - return (0); -} - -void udelay(unsigned long usec) -{ - unsigned long delay, start, stop; - unsigned long cclk; - cclk = (CONFIG_CCLK_HZ); - - while (usec > 1) { - /* - * how many clock ticks to delay? - * - request(in useconds) * clock_ticks(Hz) / useconds/second - */ - if (usec < 1000) { - delay = (usec * (cclk / 244)) >> 12; - usec = 0; - } else { - delay = (1000 * (cclk / 244)) >> 12; - usec -= 1000; - } - - asm volatile (" %0 = CYCLES;":"=r" (start)); - do { - asm volatile (" %0 = CYCLES; ":"=r" (stop)); - } while (stop - start < delay); - } - - return; -} - -void timer_init(void) -{ - *pTCNTL = 0x1; - *pTSCALE = 0x0; - *pTCOUNT = MAX_TIM_LOAD; - *pTPERIOD = MAX_TIM_LOAD; - *pTCNTL = 0x7; - asm("CSYNC;"); - - timestamp = 0; - last_time = 0; -} - -/* Any network command or flash - * command is started get_timer shall - * be called before TCOUNT gets reset, - * to implement the accurate timeouts. - * - * How ever milliconds doesn't return - * the number that has been elapsed from - * the last reset. - * - * As get_timer is used in the u-boot - * only for timeouts this should be - * sufficient - */ -ulong get_timer(ulong base) -{ - ulong milisec; - - /* Number of clocks elapsed */ - ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT)); - - /** - * Find if the TCOUNT is reset - * timestamp gives the number of times - * TCOUNT got reset - */ - if (clocks < last_time) - timestamp++; - last_time = clocks; - - /* Get the number of milliseconds */ - milisec = clocks / (CONFIG_CCLK_HZ / 1000); - - /** - * Find the number of millisonds - * that got elapsed before this TCOUNT cycle - */ - milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000)); - - return (milisec - base); -} diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c deleted file mode 100644 index 05d9a1b67e..0000000000 --- a/cpu/bf533/ints.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * U-boot - ints.c Interrupt related routines - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on ints.c - * - * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin - * drivers - * - * Copyright 1996 Roman Zippel - * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org> - * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> - * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> - * Copyright 2003 Metrowerks/Motorola - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <linux/stddef.h> -#include <asm/system.h> -#include <asm/traps.h> -#include <asm/io.h> -#include <asm/errno.h> -#include <asm/blackfin.h> -#include "cpu.h" - -void blackfin_irq_panic(int reason, struct pt_regs *regs) -{ - printf("\n\nException: IRQ 0x%x entered\n", reason); - printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f)); - printf("stack frame=0x%x, ", (unsigned int)regs); - printf("bad PC=0x%04x\n", (unsigned int)regs->pc); - dump(regs); - printf("Unhandled IRQ or exceptions!\n"); - printf("Please reset the board \n"); -} - -void blackfin_init_IRQ(void) -{ - *(unsigned volatile long *)(SIC_IMASK) = 0; -#ifndef CONFIG_KGDB - *(unsigned volatile long *)(EVT1) = 0x0; -#endif - *(unsigned volatile long *)(EVT2) = - (unsigned volatile long)evt_nmi; - *(unsigned volatile long *)(EVT3) = - (unsigned volatile long)trap; - *(unsigned volatile long *)(EVT5) = - (unsigned volatile long)evt_ivhw; - *(unsigned volatile long *)(EVT0) = - (unsigned volatile long)evt_rst; - *(unsigned volatile long *)(EVT6) = - (unsigned volatile long)evt_timer; - *(unsigned volatile long *)(EVT7) = - (unsigned volatile long)evt_evt7; - *(unsigned volatile long *)(EVT8) = - (unsigned volatile long)evt_evt8; - *(unsigned volatile long *)(EVT9) = - (unsigned volatile long)evt_evt9; - *(unsigned volatile long *)(EVT10) = - (unsigned volatile long)evt_evt10; - *(unsigned volatile long *)(EVT11) = - (unsigned volatile long)evt_evt11; - *(unsigned volatile long *)(EVT12) = - (unsigned volatile long)evt_evt12; - *(unsigned volatile long *)(EVT13) = - (unsigned volatile long)evt_evt13; - *(unsigned volatile long *)(EVT14) = - (unsigned volatile long)evt_system_call; - *(unsigned volatile long *)(EVT15) = - (unsigned volatile long)evt_soft_int1; - *(volatile unsigned long *)ILAT = 0; - asm("csync;"); - *(volatile unsigned long *)IMASK = 0xffbf; - asm("csync;"); -} - -void exception_handle(void) -{ -#if defined (CONFIG_PANIC_HANG) - display_excp(); -#else - udelay(100000); /* allow messages to go out */ - do_reset(NULL, 0, 0, NULL); -#endif -} - -void display_excp(void) -{ - printf("Exception!\n"); -} diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c deleted file mode 100644 index 05fcfcccce..0000000000 --- a/cpu/bf533/serial.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * U-boot - serial.c Serial driver for BF533 - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART. - * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>, - * BuyWays B.V. (www.buyways.nl) - * - * Based heavily on blkfinserial.c - * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs. - * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com> - * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com> - * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com> - * - * Based on code from 68328 version serial driver imlpementation which was: - * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu> - * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com> - * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org> - * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <asm/system.h> -#include <asm/bitops.h> -#include <asm/delay.h> -#include <asm/io.h> -#include "bf533_serial.h" -#include <asm/mach-common/bits/uart.h> - -DECLARE_GLOBAL_DATA_PTR; - -unsigned long pll_div_fact; - -void calc_baud(void) -{ - unsigned char i; - int temp; - u_long sclk = get_sclk(); - - for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) { - temp = sclk / (baud_table[i] * 8); - if ((temp & 0x1) == 1) { - temp++; - } - temp = temp / 2; - hw_baud_table[i].dl_high = (temp >> 8) & 0xFF; - hw_baud_table[i].dl_low = (temp) & 0xFF; - } -} - -void serial_setbrg(void) -{ - int i; - - calc_baud(); - - for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) { - if (gd->baudrate == baud_table[i]) - break; - } - - /* Enable UART */ - *pUART_GCTL |= UCEN; - SSYNC(); - - /* Set DLAB in LCR to Access DLL and DLH */ - ACCESS_LATCH; - SSYNC(); - - *pUART_DLL = hw_baud_table[i].dl_low; - SSYNC(); - *pUART_DLH = hw_baud_table[i].dl_high; - SSYNC(); - - /* Clear DLAB in LCR to Access THR RBR IER */ - ACCESS_PORT_IER; - SSYNC(); - - /* Enable ERBFI and ELSI interrupts - * to poll SIC_ISR register*/ - *pUART_IER = ELSI | ERBFI | ETBEI; - SSYNC(); - - /* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = WLS_8; - SSYNC(); - - return; -} - -int serial_init(void) -{ - serial_setbrg(); - return (0); -} - -void serial_putc(const char c) -{ - if ((*pUART_LSR) & TEMT) { - if (c == '\n') - serial_putc('\r'); - - local_put_char(c); - } - - while (!((*pUART_LSR) & TEMT)) - SYNC_ALL; - - return; -} - -int serial_tstc(void) -{ - if (*pUART_LSR & DR) - return 1; - else - return 0; -} - -int serial_getc(void) -{ - unsigned short uart_lsr_val, uart_rbr_val; - unsigned long isr_val; - int ret; - - /* Poll for RX Interrupt */ - while (!serial_tstc()) - continue; - asm("csync;"); - - uart_lsr_val = *pUART_LSR; /* Clear status bit */ - uart_rbr_val = *pUART_RBR; /* getc() */ - - if (uart_lsr_val & (OE|PE|FE|BI)) { - ret = -1; - } else { - ret = uart_rbr_val & 0xff; - } - - return ret; -} - -void serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - -static void local_put_char(char ch) -{ - int flags = 0; - unsigned long isr_val; - - /* Poll for TX Interruput */ - while (!(*pUART_LSR & THRE)) - continue; - asm("csync;"); - - *pUART_THR = ch; /* putc() */ - - return; -} diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S deleted file mode 100644 index c32fef6163..0000000000 --- a/cpu/bf533/start.S +++ /dev/null @@ -1,313 +0,0 @@ -/* - * U-boot - start.S Startup file of u-boot for BF533/BF561 - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on head.S - * Copyright (c) 2003 Metrowerks/Motorola - * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, - * Kenneth Albanowski <kjahds@kjahds.com>, - * The Silver Hammer Group, Ltd. - * (c) 1995, Dionne & Associates - * (c) 1995, DKG Display Tech. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* - * Note: A change in this file subsequently requires a change in - * board/$(board_name)/config.mk for a valid u-boot.bin - */ - -#define ASSEMBLY - -#include <linux/config.h> -#include <config.h> -#include <asm/blackfin.h> - -#include <asm/mach-common/bits/core.h> -#include <asm/mach-common/bits/dma.h> -#include <asm/mach-common/bits/pll.h> - -.global _stext; -.global __bss_start; -.global start; -.global _start; -.global edata; -.global _exit; -.global init_sdram; - -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif - -.text -_start: -start: -_stext: - - R0 = 0x32; - SYSCFG = R0; - SSYNC; - - /* As per HW reference manual DAG registers, - * DATA and Address resgister shall be zero'd - * in initialization, after a reset state - */ - r1 = 0; /* Data registers zero'd */ - r2 = 0; - r3 = 0; - r4 = 0; - r5 = 0; - r6 = 0; - r7 = 0; - - p0 = 0; /* Address registers zero'd */ - p1 = 0; - p2 = 0; - p3 = 0; - p4 = 0; - p5 = 0; - - i0 = 0; /* DAG Registers zero'd */ - i1 = 0; - i2 = 0; - i3 = 0; - m0 = 0; - m1 = 0; - m3 = 0; - m3 = 0; - l0 = 0; - l1 = 0; - l2 = 0; - l3 = 0; - b0 = 0; - b1 = 0; - b2 = 0; - b3 = 0; - - /* Set loop counters to zero, to make sure that - * hw loops are disabled. - */ - r0 = 0; - lc0 = r0; - lc1 = r0; - - SSYNC; - - /* Check soft reset status */ - p0.h = SWRST >> 16; - p0.l = SWRST & 0xFFFF; - r0.l = w[p0]; - - cc = bittst(r0, 15); - if !cc jump no_soft_reset; - - /* Clear Soft reset */ - r0 = 0x0000; - w[p0] = r0; - ssync; - -no_soft_reset: - nop; - - /* Clear EVT registers */ - p0.h = (EVT0 >> 16); - p0.l = (EVT0 & 0xFFFF); - p0 += 8; - p1 = 14; - r1 = 0; - LSETUP(4,4) lc0 = p1; - [ p0 ++ ] = r1; - - p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); - r0.l = 0x1; - w[p0] = r0.l; - SSYNC; - - sp.l = (0xffb01000 & 0xFFFF); - sp.h = (0xffb01000 >> 16); - - call init_sdram; - - /* relocate into to RAM */ - call get_pc; -offset: - r2.l = offset; - r2.h = offset; - r3.l = start; - r3.h = start; - r1 = r2 - r3; - - r0 = r0 - r1; - p1 = r0; - - p2.l = (CFG_MONITOR_BASE & 0xffff); - p2.h = (CFG_MONITOR_BASE >> 16); - - p3 = 0x04; - p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff); - p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16); -loop1: - r1 = [p1 ++ p3]; - [p2 ++ p3] = r1; - cc=p2==p4; - if !cc jump loop1; - /* - * configure STACK - */ - r0.h = (CONFIG_STACKBASE >> 16); - r0.l = (CONFIG_STACKBASE & 0xFFFF); - sp = r0; - fp = sp; - - /* - * This next section keeps the processor in supervisor mode - * during kernel boot. Switches to user mode at end of boot. - * See page 3-9 of Hardware Reference manual for documentation. - */ - - /* To keep ourselves in the supervisor mode */ - p0.l = (EVT15 & 0xFFFF); - p0.h = (EVT15 >> 16); - - p1.l = _real_start; - p1.h = _real_start; - [p0] = p1; - - p0.l = (IMASK & 0xFFFF); - p0.h = (IMASK >> 16); - r0.l = LO(EVT_IVG15); - r0.h = HI(EVT_IVG15); - [p0] = r0; - raise 15; - p0.l = WAIT_HERE; - p0.h = WAIT_HERE; - reti = p0; - rti; - -WAIT_HERE: - jump WAIT_HERE; - -.global _real_start; -_real_start: - [ -- sp ] = reti; - - /* DMA reset code to Hi of L1 SRAM */ -copy: - /* P1 Points to the beginning of SYSTEM MMR Space */ - P1.H = hi(SYSMMR_BASE); - P1.L = lo(SYSMMR_BASE); - - R0.H = reset_start; /* Source Address (high) */ - R0.L = reset_start; /* Source Address (low) */ - R1.H = reset_end; - R1.L = reset_end; - R2 = R1 - R0; /* Count */ - R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ - R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ - R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ - /* Destination DMAConfig Value (8-bit words) */ - R4.L = (DI_EN | WNR | DMAEN); - -DMA: - R6 = 0x1 (Z); - W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ - W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ - - [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ - W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ - /* Set Source DMAConfig = DMA Enable, - Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ - W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; - - /* Set Destination Base Address */ - [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; - W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ - /* Set Destination DMAConfig = DMA Enable, - Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ - W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; - -WAIT_DMA_DONE: - p0.h = hi(MDMA_D0_IRQ_STATUS); - p0.l = lo(MDMA_D0_IRQ_STATUS); - R0 = W[P0](Z); - CC = BITTST(R0, 0); - if ! CC jump WAIT_DMA_DONE - - R0 = 0x1; - - /* Write 1 to clear DMA interrupt */ - W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; - - /* Initialize BSS Section with 0 s */ - p1.l = __bss_start; - p1.h = __bss_start; - p2.l = _end; - p2.h = _end; - r1 = p1; - r2 = p2; - r3 = r2 - r1; - r3 = r3 >> 2; - p3 = r3; - lsetup (_clear_bss, _clear_bss_end ) lc1 = p3; - CC = p2<=p1; - if CC jump _clear_bss_skip; - r0 = 0; -_clear_bss: -_clear_bss_end: - [p1++] = r0; -_clear_bss_skip: - - p0.l = _start1; - p0.h = _start1; - jump (p0); - -reset_start: - p0.h = WDOG_CNT >> 16; - p0.l = WDOG_CNT & 0xffff; - r0 = 0x0010; - w[p0] = r0; - p0.h = WDOG_CTL >> 16; - p0.l = WDOG_CTL & 0xffff; - r0 = 0x0000; - w[p0] = r0; -reset_wait: - jump reset_wait; - -reset_end: nop; - -_exit: - jump.s _exit; -get_pc: - r0 = rets; - rts; diff --git a/cpu/bf533/start1.S b/cpu/bf533/start1.S deleted file mode 100644 index 6d4731b696..0000000000 --- a/cpu/bf533/start1.S +++ /dev/null @@ -1,38 +0,0 @@ -/* - * U-boot - start1.S Code running out of RAM after relocation - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#define ASSEMBLY -#include <linux/config.h> -#include <config.h> -#include <asm/blackfin.h> - -.global start1; -.global _start1; - -.text -_start1: -start1: - sp += -12; - call _board_init_f; - sp += 12; diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c deleted file mode 100644 index 7e156d5110..0000000000 --- a/cpu/bf533/traps.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * U-boot - traps.c Routines related to interrupts and exceptions - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * No original Copyright holder listed, - * Probabily original (C) Roman Zippel (assigned DJD, 1999) - * - * Copyright 2003 Metrowerks - for Blackfin - * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca> - * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org> - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <linux/types.h> -#include <asm/errno.h> -#include <asm/system.h> -#include <asm/traps.h> -#include "cpu.h" -#include <asm/cplb.h> -#include <asm/io.h> -#include <asm/mach-common/bits/core.h> -#include <asm/mach-common/bits/mpu.h> - -void init_IRQ(void) -{ - blackfin_init_IRQ(); - return; -} - -void process_int(unsigned long vec, struct pt_regs *fp) -{ - printf("interrupt\n"); - return; -} - -extern unsigned int icplb_table[page_descriptor_table_size][2]; -extern unsigned int dcplb_table[page_descriptor_table_size][2]; - -unsigned long last_cplb_fault_retx; - -static unsigned int cplb_sizes[4] = - { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 }; - -void trap_c(struct pt_regs *regs) -{ - unsigned int addr; - unsigned long trapnr = (regs->seqstat) & EXCAUSE; - unsigned int i, j, size, *I0, *I1; - unsigned short data = 0; - - switch (trapnr) { - /* 0x26 - Data CPLB Miss */ - case VEC_CPLB_M: - -#if ANOMALY_05000261 - /* - * Work around an anomaly: if we see a new DCPLB fault, - * return without doing anything. Then, - * if we get the same fault again, handle it. - */ - addr = last_cplb_fault_retx; - last_cplb_fault_retx = regs->retx; - printf("this time, curr = 0x%08x last = 0x%08x\n", - addr, last_cplb_fault_retx); - if (addr != last_cplb_fault_retx) - goto trap_c_return; -#endif - data = 1; - - case VEC_CPLB_I_M: - - if (data) { - addr = *(unsigned int *)pDCPLB_FAULT_ADDR; - } else { - addr = *(unsigned int *)pICPLB_FAULT_ADDR; - } - for (i = 0; i < page_descriptor_table_size; i++) { - if (data) { - size = cplb_sizes[dcplb_table[i][1] >> 16]; - j = dcplb_table[i][0]; - } else { - size = cplb_sizes[icplb_table[i][1] >> 16]; - j = icplb_table[i][0]; - } - if ((j <= addr) && ((j + size) > addr)) { - debug("found %i 0x%08x\n", i, j); - break; - } - } - if (i == page_descriptor_table_size) { - printf("something is really wrong\n"); - do_reset(NULL, 0, 0, NULL); - } - - /* Turn the cache off */ - if (data) { - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)DMEM_CONTROL &= - ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - SSYNC(); - } else { - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - SSYNC(); - } - - if (data) { - I0 = (unsigned int *)DCPLB_ADDR0; - I1 = (unsigned int *)DCPLB_DATA0; - } else { - I0 = (unsigned int *)ICPLB_ADDR0; - I1 = (unsigned int *)ICPLB_DATA0; - } - - j = 0; - while (*I1 & CPLB_LOCK) { - debug("skipping %i %08p - %08x\n", j, I1, *I1); - *I0++; - *I1++; - j++; - } - - debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1); - - for (; j < 15; j++) { - debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1); - *I0++ = *(I0 + 1); - *I1++ = *(I1 + 1); - } - - if (data) { - *I0 = dcplb_table[i][0]; - *I1 = dcplb_table[i][1]; - I0 = (unsigned int *)DCPLB_ADDR0; - I1 = (unsigned int *)DCPLB_DATA0; - } else { - *I0 = icplb_table[i][0]; - *I1 = icplb_table[i][1]; - I0 = (unsigned int *)ICPLB_ADDR0; - I1 = (unsigned int *)ICPLB_DATA0; - } - - for (j = 0; j < 16; j++) { - debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++); - } - - /* Turn the cache back on */ - if (data) { - j = *(unsigned int *)DMEM_CONTROL; - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)DMEM_CONTROL = - ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; - SSYNC(); - } else { - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - SSYNC(); - } - - break; - default: - /* All traps come here */ - printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f)); - printf("stack frame=0x%x, ", (unsigned int)regs); - printf("bad PC=0x%04x\n", (unsigned int)regs->pc); - dump(regs); - printf("\n\n"); - - printf("Unhandled IRQ or exceptions!\n"); - printf("Please reset the board \n"); - do_reset(NULL, 0, 0, NULL); - } - - return; - -} - -void dump(struct pt_regs *fp) -{ - debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n", - fp->rete, fp->retn, fp->retx, fp->rets); - debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg); - debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp); - debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n", - fp->r0, fp->r1, fp->r2, fp->r3); - debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", - fp->r4, fp->r5, fp->r6, fp->r7); - debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n", - fp->p0, fp->p1, fp->p2, fp->p3); - debug("P4: %08lx P5: %08lx FP: %08lx\n", - fp->p4, fp->p5, fp->fp); - debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", - fp->a0w, fp->a0x, fp->a1w, fp->a1x); - - debug("LB0: %08lx LT0: %08lx LC0: %08lx\n", - fp->lb0, fp->lt0, fp->lc0); - debug("LB1: %08lx LT1: %08lx LC1: %08lx\n", - fp->lb1, fp->lt1, fp->lc1); - debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n", - fp->b0, fp->l0, fp->m0, fp->i0); - debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n", - fp->b1, fp->l1, fp->m1, fp->i1); - debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n", - fp->b2, fp->l2, fp->m2, fp->i2); - debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n", - fp->b3, fp->l3, fp->m3, fp->i3); - - debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR); - debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR); - -} diff --git a/cpu/bf533/video.c b/cpu/bf533/video.c deleted file mode 100644 index 3ff0151d48..0000000000 --- a/cpu/bf533/video.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * (C) Copyright 2002 - * Wolfgang Denk, wd@denx.de - * (C) Copyright 2006 - * Aubrey Li, aubrey.li@analog.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <stdarg.h> -#include <common.h> -#include <config.h> -#include <asm/blackfin.h> -#include <i2c.h> -#include <linux/types.h> -#include <devices.h> - -#ifdef CONFIG_VIDEO -#define NTSC_FRAME_ADDR 0x06000000 -#include "video.h" - -/* NTSC OUTPUT SIZE 720 * 240 */ -#define VERTICAL 2 -#define HORIZONTAL 4 - -int is_vblank_line(const int line) -{ - /* - * This array contains a single bit for each line in - * an NTSC frame. - */ - if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528)) - return true; - - return false; -} - -int NTSC_framebuffer_init(char *base_address) -{ - const int NTSC_frames = 1; - const int NTSC_lines = 525; - char *dest = base_address; - int frame_num, line_num; - - for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) { - for (line_num = 1; line_num <= NTSC_lines; ++line_num) { - unsigned int code; - int offset = 0; - int i; - - if (is_vblank_line(line_num)) - offset++; - - if (line_num > 266 || line_num < 3) - offset += 2; - - /* Output EAV code */ - code = SystemCodeMap[offset].EAV; - write_dest_byte((char)(code >> 24) & 0xff); - write_dest_byte((char)(code >> 16) & 0xff); - write_dest_byte((char)(code >> 8) & 0xff); - write_dest_byte((char)(code) & 0xff); - - /* Output horizontal blanking */ - for (i = 0; i < 67 * 2; ++i) { - write_dest_byte(0x80); - write_dest_byte(0x10); - } - - /* Output SAV */ - code = SystemCodeMap[offset].SAV; - write_dest_byte((char)(code >> 24) & 0xff); - write_dest_byte((char)(code >> 16) & 0xff); - write_dest_byte((char)(code >> 8) & 0xff); - write_dest_byte((char)(code) & 0xff); - - /* Output empty horizontal data */ - for (i = 0; i < 360 * 2; ++i) { - write_dest_byte(0x80); - write_dest_byte(0x10); - } - } - } - - return dest - base_address; -} - -void fill_frame(char *Frame, int Value) -{ - int *OddPtr32; - int OddLine; - int *EvenPtr32; - int EvenLine; - int i; - int *data; - int m, n; - - /* fill odd and even frames */ - for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) { - OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276); - EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276); - for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) { - *OddPtr32 = Value; - *EvenPtr32 = Value; - } - } - - for (m = 0; m < VERTICAL; m++) { - data = (int *)u_boot_logo.data; - for (OddLine = (22 + m), EvenLine = (285 + m); - OddLine < (u_boot_logo.height * VERTICAL) + (22 + m); - OddLine += VERTICAL, EvenLine += VERTICAL) { - OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276); - EvenPtr32 = - (int *)((Frame + ((EvenLine) * 1716)) + 276); - for (i = 0; i < u_boot_logo.width / 2; i++) { - /* enlarge one pixel to m x n */ - for (n = 0; n < HORIZONTAL; n++) { - *OddPtr32++ = *data; - *EvenPtr32++ = *data; - } - data++; - } - } - } -} - -void video_putc(const char c) -{ -} - -void video_puts(const char *s) -{ -} - -static int video_init(void) -{ - char *NTSCFrame; - NTSCFrame = (char *)NTSC_FRAME_ADDR; - NTSC_framebuffer_init(NTSCFrame); - fill_frame(NTSCFrame, BLUE); - - *pPPI_CONTROL = 0x0082; - *pPPI_FRAME = 0x020D; - - *pDMA0_START_ADDR = NTSCFrame; - *pDMA0_X_COUNT = 0x035A; - *pDMA0_X_MODIFY = 0x0002; - *pDMA0_Y_COUNT = 0x020D; - *pDMA0_Y_MODIFY = 0x0002; - *pDMA0_CONFIG = 0x1015; - *pPPI_CONTROL = 0x0083; - return 0; -} - -int drv_video_init(void) -{ - int error, devices = 1; - - device_t videodev; - - video_init(); /* Video initialization */ - - memset(&videodev, 0, sizeof(videodev)); - - strcpy(videodev.name, "video"); - videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ - videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */ - videodev.putc = video_putc; /* 'putc' function */ - videodev.puts = video_puts; /* 'puts' function */ - - error = device_register(&videodev); - - return (error == 0) ? devices : error; -} -#endif diff --git a/cpu/bf533/video.h b/cpu/bf533/video.h deleted file mode 100644 index d237f6a3c7..0000000000 --- a/cpu/bf533/video.h +++ /dev/null @@ -1,25 +0,0 @@ -#include <video_logo.h> -#define write_dest_byte(val) {*dest++=val;} -#define BLACK (0x01800180) /* black pixel pattern */ -#define BLUE (0x296E29F0) /* blue pixel pattern */ -#define RED (0x51F0515A) /* red pixel pattern */ -#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */ -#define GREEN (0x91229136) /* green pixel pattern */ -#define CYAN (0xAA10AAA6) /* cyan pixel pattern */ -#define YELLOW (0xD292D210) /* yellow pixel pattern */ -#define WHITE (0xFE80FE80) /* white pixel pattern */ - -#define true 1 -#define false 0 - -typedef struct { - unsigned int SAV; - unsigned int EAV; -} SystemCodeType; - -const SystemCodeType SystemCodeMap[4] = { - {0xFF000080, 0xFF00009D}, - {0xFF0000AB, 0xFF0000B6}, - {0xFF0000C7, 0xFF0000DA}, - {0xFF0000EC, 0xFF0000F1} -}; diff --git a/cpu/bf537/cache.S b/cpu/bf537/cache.S deleted file mode 100644 index d9015c6d1a..0000000000 --- a/cpu/bf537/cache.S +++ /dev/null @@ -1,129 +0,0 @@ -#define ASSEMBLY -#include <asm/linkage.h> -#include <config.h> -#include <asm/blackfin.h> -#include <asm/mach-common/bits/mpu.h> - -.text -.align 2 -ENTRY(_blackfin_icache_flush_range) - R2 = -32; - R2 = R0 & R2; - P0 = R2; - P1 = R1; - CSYNC; - 1: - IFLUSH[P0++]; - CC = P0 < P1(iu); - IF CC JUMP 1b(bp); - IFLUSH[P0]; - SSYNC; - RTS; - -ENTRY(_blackfin_dcache_flush_range) - R2 = -32; - R2 = R0 & R2; - P0 = R2; - P1 = R1; - CSYNC; -1: - FLUSH[P0++]; - CC = P0 < P1(iu); - IF CC JUMP 1b(bp); - FLUSH[P0]; - SSYNC; - RTS; - -ENTRY(_icache_invalidate) -ENTRY(_invalidate_entire_icache) - [--SP] = (R7:5); - - P0.L = (IMEM_CONTROL & 0xFFFF); - P0.H = (IMEM_CONTROL >> 16); - R7 =[P0]; - - /* - * Clear the IMC bit , All valid bits in the instruction - * cache are set to the invalid state - */ - BITCLR(R7, IMC_P); - CLI R6; - /* SSYNC required before invalidating cache. */ - SSYNC; - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - /* Configures the instruction cache agian */ - R6 = (IMC | ENICPLB); - R7 = R7 | R6; - - CLI R6; - SSYNC; - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - (R7:5) =[SP++]; - RTS; - -/* - * Invalidate the Entire Data cache by - * clearing DMC[1:0] bits - */ -ENTRY(_invalidate_entire_dcache) -ENTRY(_dcache_invalidate) - [--SP] = (R7:6); - - P0.L = (DMEM_CONTROL & 0xFFFF); - P0.H = (DMEM_CONTROL >> 16); - R7 =[P0]; - - /* - * Clear the DMC[1:0] bits, All valid bits in the data - * cache are set to the invalid state - */ - BITCLR(R7, DMC0_P); - BITCLR(R7, DMC1_P); - CLI R6; - SSYNC; - .align 8; - [P0] = R7; - SSYNC; - STI R6; - /* Configures the data cache again */ - - R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - R7 = R7 | R6; - - CLI R6; - SSYNC; - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - (R7:6) =[SP++]; - RTS; - -ENTRY(_blackfin_dcache_invalidate_range) - R2 = -32; - R2 = R0 & R2; - P0 = R2; - P1 = R1; - CSYNC; -1: - FLUSHINV[P0++]; - CC = P0 < P1(iu); - IF CC JUMP 1b(bp); - - /* - * If the data crosses a cache line, then we'll be pointing to - * the last cache line, but won't have flushed/invalidated it yet, so do - * one more. - */ - FLUSHINV[P0]; - SSYNC; - RTS; diff --git a/cpu/bf537/cpu.c b/cpu/bf537/cpu.c deleted file mode 100644 index 7233908a07..0000000000 --- a/cpu/bf537/cpu.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * U-boot - cpu.c CPU specific functions - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <asm/blackfin.h> -#include <command.h> -#include <asm/entry.h> -#include <asm/cplb.h> -#include <asm/io.h> - -#define CACHE_ON 1 -#define CACHE_OFF 0 - -extern unsigned int icplb_table[page_descriptor_table_size][2]; -extern unsigned int dcplb_table[page_descriptor_table_size][2]; - -int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) - ); - - return 0; -} - -/* These functions are just used to satisfy the linker */ -int cpu_init(void) -{ - return 0; -} - -int cleanup_before_linux(void) -{ - return 0; -} - -void icache_enable(void) -{ - unsigned int *I0, *I1; - int i, j = 0; - - if ((*pCHIPID >> 28) < 2) - return; - - /* Before enable icache, disable it first */ - icache_disable(); - I0 = (unsigned int *)ICPLB_ADDR0; - I1 = (unsigned int *)ICPLB_DATA0; - - /* make sure the locked ones go in first */ - for (i = 0; i < page_descriptor_table_size; i++) { - if (CPLB_LOCK & icplb_table[i][1]) { - debug("adding %02i %02i 0x%08x 0x%08x\n", i, j, - icplb_table[i][0], icplb_table[i][1]); - *I0++ = icplb_table[i][0]; - *I1++ = icplb_table[i][1]; - j++; - } - } - - for (i = 0; i < page_descriptor_table_size; i++) { - if (!(CPLB_LOCK & icplb_table[i][1])) { - debug("adding %02i %02i 0x%08x 0x%08x\n", i, j, - icplb_table[i][0], icplb_table[i][1]); - *I0++ = icplb_table[i][0]; - *I1++ = icplb_table[i][1]; - j++; - if (j == 16) { - break; - } - } - } - - /* Fill the rest with invalid entry */ - if (j <= 15) { - for (; j < 16; j++) { - debug("filling %i with 0", j); - *I1++ = 0x0; - } - - } - - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - SSYNC(); -} - -void icache_disable(void) -{ - if ((*pCHIPID >> 28) < 2) - return; - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - SSYNC(); -} - -int icache_status(void) -{ - unsigned int value; - value = *(unsigned int *)IMEM_CONTROL; - - if (value & (IMC | ENICPLB)) - return CACHE_ON; - else - return CACHE_OFF; -} - -void dcache_enable(void) -{ - unsigned int *I0, *I1; - unsigned int temp; - int i, j = 0; - - /* Before enable dcache, disable it first */ - dcache_disable(); - I0 = (unsigned int *)DCPLB_ADDR0; - I1 = (unsigned int *)DCPLB_DATA0; - - /* make sure the locked ones go in first */ - for (i = 0; i < page_descriptor_table_size; i++) { - if (CPLB_LOCK & dcplb_table[i][1]) { - debug("adding %02i %02i 0x%08x 0x%08x\n", i, j, - dcplb_table[i][0], dcplb_table[i][1]); - *I0++ = dcplb_table[i][0]; - *I1++ = dcplb_table[i][1]; - j++; - } else { - debug("skip %02i %02i 0x%08x 0x%08x\n", i, j, - dcplb_table[i][0], dcplb_table[i][1]); - } - } - - for (i = 0; i < page_descriptor_table_size; i++) { - if (!(CPLB_LOCK & dcplb_table[i][1])) { - debug("adding %02i %02i 0x%08x 0x%08x\n", i, j, - dcplb_table[i][0], dcplb_table[i][1]); - *I0++ = dcplb_table[i][0]; - *I1++ = dcplb_table[i][1]; - j++; - if (j == 16) { - break; - } - } - } - - /* Fill the rest with invalid entry */ - if (j <= 15) { - for (; j < 16; j++) { - debug("filling %i with 0", j); - *I1++ = 0x0; - } - } - - temp = *(unsigned int *)DMEM_CONTROL; - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)DMEM_CONTROL = - ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - SSYNC(); -} - -void dcache_disable(void) -{ - unsigned int *I0, *I1; - int i; - - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)DMEM_CONTROL &= - ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - SSYNC(); - - /* after disable dcache, - * clear it so we don't confuse the next application - */ - I0 = (unsigned int *)DCPLB_ADDR0; - I1 = (unsigned int *)DCPLB_DATA0; - - for (i = 0; i < 16; i++) { - *I0++ = 0x0; - *I1++ = 0x0; - } -} - -int dcache_status(void) -{ - unsigned int value; - value = *(unsigned int *)DMEM_CONTROL; - - if (value & (ENDCPLB)) - return CACHE_ON; - else - return CACHE_OFF; -} diff --git a/cpu/bf537/cpu.h b/cpu/bf537/cpu.h deleted file mode 100644 index b6b73b1d8f..0000000000 --- a/cpu/bf537/cpu.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * U-boot - cpu.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _CPU_H_ -#define _CPU_H_ - -#include <command.h> - -#define INTERNAL_IRQS (32) -#define NUM_IRQ_NODES 16 -#define DEF_INTERRUPT_FLAGS 1 -#define MAX_TIM_LOAD 0xFFFFFFFF - -void blackfin_irq_panic(int reason, struct pt_regs *reg); -extern void dump(struct pt_regs *regs); -void display_excp(void); -asmlinkage void evt_nmi(void); -asmlinkage void evt_exception(void); -asmlinkage void trap(void); -asmlinkage void evt_ivhw(void); -asmlinkage void evt_rst(void); -asmlinkage void evt_timer(void); -asmlinkage void evt_evt7(void); -asmlinkage void evt_evt8(void); -asmlinkage void evt_evt9(void); -asmlinkage void evt_evt10(void); -asmlinkage void evt_evt11(void); -asmlinkage void evt_evt12(void); -asmlinkage void evt_evt13(void); -asmlinkage void evt_soft_int1(void); -asmlinkage void evt_system_call(void); -void blackfin_irq_panic(int reason, struct pt_regs *regs); -void blackfin_free_irq(unsigned int irq, void *dev_id); -void call_isr(int irq, struct pt_regs *fp); -void blackfin_do_irq(int vec, struct pt_regs *fp); -void blackfin_init_IRQ(void); -void blackfin_enable_irq(unsigned int irq); -void blackfin_disable_irq(unsigned int irq); -extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); -int blackfin_request_irq(unsigned int irq, - void (*handler) (int, void *, struct pt_regs *), - unsigned long flags, const char *devname, - void *dev_id); -void timer_init(void); -#endif diff --git a/cpu/bf537/flush.S b/cpu/bf537/flush.S deleted file mode 100644 index fbd26cc92b..0000000000 --- a/cpu/bf537/flush.S +++ /dev/null @@ -1,403 +0,0 @@ -/* Copyright (C) 2003-2007 Analog Devices Inc. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. - */ - -#define ASSEMBLY - -#include <asm/linkage.h> -#include <asm/cplb.h> -#include <config.h> -#include <asm/blackfin.h> - -.text - -/* This is an external function being called by the user - * application through __flush_cache_all. Currently this function - * serves the purpose of flushing all the pending writes in - * in the instruction cache. - */ - -ENTRY(_flush_instruction_cache) - [--SP] = ( R7:6, P5:4 ); - LINK 12; - SP += -12; - P5.H = (ICPLB_ADDR0 >> 16); - P5.L = (ICPLB_ADDR0 & 0xFFFF); - P4.H = (ICPLB_DATA0 >> 16); - P4.L = (ICPLB_DATA0 & 0xFFFF); - R7 = CPLB_VALID | CPLB_L1_CHBL; - R6 = 16; -inext: R0 = [P5++]; - R1 = [P4++]; - [--SP] = RETS; - CALL _icplb_flush; /* R0 = page, R1 = data*/ - RETS = [SP++]; -iskip: R6 += -1; - CC = R6; - IF CC JUMP inext; - SSYNC; - SP += 12; - UNLINK; - ( R7:6, P5:4 ) = [SP++]; - RTS; - -/* This is an internal function to flush all pending - * writes in the cache associated with a particular ICPLB. - * - * R0 - page's start address - * R1 - CPLB's data field. - */ - -.align 2 -ENTRY(_icplb_flush) - [--SP] = ( R7:0, P5:0 ); - [--SP] = LC0; - [--SP] = LT0; - [--SP] = LB0; - [--SP] = LC1; - [--SP] = LT1; - [--SP] = LB1; - - /* If it's a 1K or 4K page, then it's quickest to - * just systematically flush all the addresses in - * the page, regardless of whether they're in the - * cache, or dirty. If it's a 1M or 4M page, there - * are too many addresses, and we have to search the - * cache for lines corresponding to the page. - */ - - CC = BITTST(R1, 17); /* 1MB or 4MB */ - IF !CC JUMP iflush_whole_page; - - /* We're only interested in the page's size, so extract - * this from the CPLB (bits 17:16), and scale to give an - * offset into the page_size and page_prefix tables. - */ - - R1 <<= 14; - R1 >>= 30; - R1 <<= 2; - - /* We can also determine the sub-bank used, because this is - * taken from bits 13:12 of the address. - */ - - R3 = ((12<<8)|2); /* Extraction pattern */ - nop; /* Anamoly 05000209 */ - R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */ - - /* Save in extraction pattern for later deposit. */ - R3.H = R4.L << 0; - - /* So: - * R0 = Page start - * R1 = Page length (actually, offset into size/prefix tables) - * R3 = sub-bank deposit values - * - * The cache has 2 Ways, and 64 sets, so we iterate through - * the sets, accessing the tag for each Way, for our Bank and - * sub-bank, looking for dirty, valid tags that match our - * address prefix. - */ - - P5.L = (ITEST_COMMAND & 0xFFFF); - P5.H = (ITEST_COMMAND >> 16); - P4.L = (ITEST_DATA0 & 0xFFFF); - P4.H = (ITEST_DATA0 >> 16); - - P0.L = page_prefix_table; - P0.H = page_prefix_table; - P1 = R1; - R5 = 0; /* Set counter*/ - P0 = P1 + P0; - R4 = [P0]; /* This is the address prefix*/ - - /* We're reading (bit 1==0) the tag (bit 2==0), and we - * don't care about which double-word, since we're only - * fetching tags, so we only have to set Set, Bank, - * Sub-bank and Way. - */ - - P2 = 4; - LSETUP (ifs1, ife1) LC1 = P2; -ifs1: P0 = 32; /* iterate over all sets*/ - LSETUP (ifs0, ife0) LC0 = P0; -ifs0: R6 = R5 << 5; /* Combine set*/ - R6.H = R3.H << 0 ; /* and sub-bank*/ - [P5] = R6; /* Issue Command*/ - SSYNC; /* CSYNC will not work here :(*/ - R7 = [P4]; /* and read Tag.*/ - CC = BITTST(R7, 0); /* Check if valid*/ - IF !CC JUMP ifskip; /* and skip if not.*/ - - /* Compare against the page address. First, plant bits 13:12 - * into the tag, since those aren't part of the returned data. - */ - - R7 = DEPOSIT(R7, R3); /* set 13:12*/ - R1 = R7 & R4; /* Mask off lower bits*/ - CC = R1 == R0; /* Compare against page start.*/ - IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/ - - /* Tag address matches against page, so this is an entry - * we must flush. - */ - - R7 >>= 10; /* Mask off the non-address bits*/ - R7 <<= 10; - P3 = R7; - IFLUSH [P3]; /* And flush the entry*/ -ifskip: -ife0: R5 += 1; /* Advance to next Set*/ -ife1: NOP; - -ifinished: - SSYNC; /* Ensure the data gets out to mem.*/ - - /*Finished. Restore context.*/ - LB1 = [SP++]; - LT1 = [SP++]; - LC1 = [SP++]; - LB0 = [SP++]; - LT0 = [SP++]; - LC0 = [SP++]; - ( R7:0, P5:0 ) = [SP++]; - RTS; - -iflush_whole_page: - /* It's a 1K or 4K page, so quicker to just flush the - * entire page. - */ - - P1 = 32; /* For 1K pages*/ - P2 = P1 << 2; /* For 4K pages*/ - P0 = R0; /* Start of page*/ - CC = BITTST(R1, 16); /* Whether 1K or 4K*/ - IF CC P1 = P2; - P1 += -1; /* Unroll one iteration*/ - SSYNC; - IFLUSH [P0++]; /* because CSYNC can't end loops.*/ - LSETUP (isall, ieall) LC0 = P1; -isall:IFLUSH [P0++]; -ieall: NOP; - SSYNC; - JUMP ifinished; - -/* This is an external function being called by the user - * application through __flush_cache_all. Currently this function - * serves the purpose of flushing all the pending writes in - * in the data cache. - */ - -ENTRY(_flush_data_cache) - [--SP] = ( R7:6, P5:4 ); - LINK 12; - SP += -12; - P5.H = (DCPLB_ADDR0 >> 16); - P5.L = (DCPLB_ADDR0 & 0xFFFF); - P4.H = (DCPLB_DATA0 >> 16); - P4.L = (DCPLB_DATA0 & 0xFFFF); - R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z); - R6 = 16; -next: R0 = [P5++]; - R1 = [P4++]; - CC = BITTST(R1, 14); /* Is it write-through?*/ - IF CC JUMP skip; /* If so, ignore it.*/ - R2 = R1 & R7; /* Is it a dirty, cached page?*/ - CC = R2; - IF !CC JUMP skip; /* If not, ignore it.*/ - [--SP] = RETS; - CALL _dcplb_flush; /* R0 = page, R1 = data*/ - RETS = [SP++]; -skip: R6 += -1; - CC = R6; - IF CC JUMP next; - SSYNC; - SP += 12; - UNLINK; - ( R7:6, P5:4 ) = [SP++]; - RTS; - -/* This is an internal function to flush all pending - * writes in the cache associated with a particular DCPLB. - * - * R0 - page's start address - * R1 - CPLB's data field. - */ - -.align 2 -ENTRY(_dcplb_flush) - [--SP] = ( R7:0, P5:0 ); - [--SP] = LC0; - [--SP] = LT0; - [--SP] = LB0; - [--SP] = LC1; - [--SP] = LT1; - [--SP] = LB1; - - /* If it's a 1K or 4K page, then it's quickest to - * just systematically flush all the addresses in - * the page, regardless of whether they're in the - * cache, or dirty. If it's a 1M or 4M page, there - * are too many addresses, and we have to search the - * cache for lines corresponding to the page. - */ - - CC = BITTST(R1, 17); /* 1MB or 4MB */ - IF !CC JUMP dflush_whole_page; - - /* We're only interested in the page's size, so extract - * this from the CPLB (bits 17:16), and scale to give an - * offset into the page_size and page_prefix tables. - */ - - R1 <<= 14; - R1 >>= 30; - R1 <<= 2; - - /* The page could be mapped into Bank A or Bank B, depending - * on (a) whether both banks are configured as cache, and - * (b) on whether address bit A[x] is set. x is determined - * by DCBS in DMEM_CONTROL - */ - - R2 = 0; /* Default to Bank A (Bank B would be 1)*/ - - P0.L = (DMEM_CONTROL & 0xFFFF); - P0.H = (DMEM_CONTROL >> 16); - - R3 = [P0]; /* If Bank B is not enabled as cache*/ - CC = BITTST(R3, 2); /* then Bank A is our only option.*/ - IF CC JUMP bank_chosen; - - R4 = 1<<14; /* If DCBS==0, use A[14].*/ - R5 = R4 << 7; /* If DCBS==1, use A[23];*/ - CC = BITTST(R3, 4); - IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/ - R5 = R0 & R4; /* Use it to test the Page address*/ - CC = R5; /* and if that bit is set, we use Bank B,*/ - R2 = CC; /* else we use Bank A.*/ - R2 <<= 23; /* The Bank selection's at posn 23.*/ - -bank_chosen: - - /* We can also determine the sub-bank used, because this is - * taken from bits 13:12 of the address. - */ - - R3 = ((12<<8)|2); /* Extraction pattern */ - nop; /*Anamoly 05000209*/ - R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/ - /* Save in extraction pattern for later deposit.*/ - R3.H = R4.L << 0; - - /* So: - * R0 = Page start - * R1 = Page length (actually, offset into size/prefix tables) - * R2 = Bank select mask - * R3 = sub-bank deposit values - * - * The cache has 2 Ways, and 64 sets, so we iterate through - * the sets, accessing the tag for each Way, for our Bank and - * sub-bank, looking for dirty, valid tags that match our - * address prefix. - */ - - P5.L = (DTEST_COMMAND & 0xFFFF); - P5.H = (DTEST_COMMAND >> 16); - P4.L = (DTEST_DATA0 & 0xFFFF); - P4.H = (DTEST_DATA0 >> 16); - - P0.L = page_prefix_table; - P0.H = page_prefix_table; - P1 = R1; - R5 = 0; /* Set counter*/ - P0 = P1 + P0; - R4 = [P0]; /* This is the address prefix*/ - - - /* We're reading (bit 1==0) the tag (bit 2==0), and we - * don't care about which double-word, since we're only - * fetching tags, so we only have to set Set, Bank, - * Sub-bank and Way. - */ - - P2 = 2; - LSETUP (fs1, fe1) LC1 = P2; -fs1: P0 = 64; /* iterate over all sets*/ - LSETUP (fs0, fe0) LC0 = P0; -fs0: R6 = R5 << 5; /* Combine set*/ - R6.H = R3.H << 0 ; /* and sub-bank*/ - R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/ - BITSET(R6,14); - [P5] = R6; /* Issue Command*/ - SSYNC; - R7 = [P4]; /* and read Tag.*/ - CC = BITTST(R7, 0); /* Check if valid*/ - IF !CC JUMP fskip; /* and skip if not.*/ - CC = BITTST(R7, 1); /* Check if dirty*/ - IF !CC JUMP fskip; /* and skip if not.*/ - - /* Compare against the page address. First, plant bits 13:12 - * into the tag, since those aren't part of the returned data. - */ - - R7 = DEPOSIT(R7, R3); /* set 13:12*/ - R1 = R7 & R4; /* Mask off lower bits*/ - CC = R1 == R0; /* Compare against page start.*/ - IF !CC JUMP fskip; /* Skip it if it doesn't match.*/ - - /* Tag address matches against page, so this is an entry - * we must flush. - */ - - R7 >>= 10; /* Mask off the non-address bits*/ - R7 <<= 10; - P3 = R7; - SSYNC; - FLUSHINV [P3]; /* And flush the entry*/ -fskip: -fe0: R5 += 1; /* Advance to next Set*/ -fe1: BITSET(R2, 26); /* Go to next Way.*/ - -dfinished: - SSYNC; /* Ensure the data gets out to mem.*/ - - /*Finished. Restore context.*/ - LB1 = [SP++]; - LT1 = [SP++]; - LC1 = [SP++]; - LB0 = [SP++]; - LT0 = [SP++]; - LC0 = [SP++]; - ( R7:0, P5:0 ) = [SP++]; - RTS; - -dflush_whole_page: - - /* It's a 1K or 4K page, so quicker to just flush the - * entire page. - */ - - P1 = 32; /* For 1K pages*/ - P2 = P1 << 2; /* For 4K pages*/ - P0 = R0; /* Start of page*/ - CC = BITTST(R1, 16); /* Whether 1K or 4K*/ - IF CC P1 = P2; - P1 += -1; /* Unroll one iteration*/ - SSYNC; - FLUSHINV [P0++]; /* because CSYNC can't end loops.*/ - LSETUP (eall, eall) LC0 = P1; -eall: FLUSHINV [P0++]; - SSYNC; - JUMP dfinished; - -.align 4; -page_prefix_table: -.byte4 0xFFFFFC00; /* 1K */ -.byte4 0xFFFFF000; /* 4K */ -.byte4 0xFFF00000; /* 1M */ -.byte4 0xFFC00000; /* 4M */ -.page_prefix_table.end: diff --git a/cpu/bf537/init_sdram.S b/cpu/bf537/init_sdram.S deleted file mode 100644 index e9975000a2..0000000000 --- a/cpu/bf537/init_sdram.S +++ /dev/null @@ -1,178 +0,0 @@ -#define ASSEMBLY - -#include <linux/config.h> -#include <config.h> -#include <asm/blackfin.h> -#include <asm/mem_init.h> -#include <asm/mach-common/bits/bootrom.h> -#include <asm/mach-common/bits/ebiu.h> -#include <asm/mach-common/bits/pll.h> -#include <asm/mach-common/bits/uart.h> -.global init_sdram; - -#if (BFIN_BOOT_MODE != BF537_UART_BOOT) -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif -#endif - -init_sdram: - [--SP] = ASTAT; - [--SP] = RETS; - [--SP] = (R7:0); - [--SP] = (P5:0); - -#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) - p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); - r0.l = 0x1; - w[p0] = r0.l; - SSYNC; - - p0.h = hi(SPI_BAUD); - p0.l = lo(SPI_BAUD); - r0.l = CONFIG_SPI_BAUD; - w[p0] = r0.l; - SSYNC; -#endif - -#if (BFIN_BOOT_MODE != BF537_UART_BOOT) - -#ifdef CONFIG_BF537 - /* Enable PHY CLK buffer output */ - p0.h = hi(VR_CTL); - p0.l = lo(VR_CTL); - r0.l = w[p0]; - bitset(r0, 14); - w[p0] = r0.l; - ssync; -#endif - /* - * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable - */ - p0.h = hi(PLL_LOCKCNT); - p0.l = lo(PLL_LOCKCNT); - r0 = 0x300(Z); - w[p0] = r0.l; - ssync; - - /* - * Put SDRAM in self-refresh, incase anything is running - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITSET (R0, 24); - [P2] = R0; - SSYNC; - - /* - * Set PLL_CTL with the value that we calculate in R0 - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK - * - [7] = output delay (add 200ps of delay to mem signals) - * - [6] = input delay (add 200ps of input delay to mem signals) - * - [5] = PDWN : 1=All Clocks off - * - [3] = STOPCK : 1=Core Clock off - * - [1] = PLL_OFF : 1=Disable Power to PLL - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL - * all other bits set to zero - */ - - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ - r0 = r0 << 9; /* Shift it over */ - r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ - r0 = r1 | r0; - r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ - r1 = r1 << 8; /* Shift it over */ - r0 = r1 | r0; /* add them all together */ - - p0.h = hi(PLL_CTL); - p0.l = lo(PLL_CTL); /* Load the address */ - cli r2; /* Disable interrupts */ - ssync; - w[p0] = r0.l; /* Set the value */ - idle; /* Wait for the PLL to stablize */ - sti r2; /* Enable interrupts */ - -check_again: - p0.h = hi(PLL_STAT); - p0.l = lo(PLL_STAT); - R0 = W[P0](Z); - CC = BITTST(R0,5); - if ! CC jump check_again; - - /* Configure SCLK & CCLK Dividers */ - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); - p0.h = hi(PLL_DIV); - p0.l = lo(PLL_DIV); - w[p0] = r0.l; - ssync; -#endif - - /* - * Now, Initialize the SDRAM, - * start with the SDRAM Refresh Rate Control Register - */ - p0.l = lo(EBIU_SDRRC); - p0.h = hi(EBIU_SDRRC); - r0 = mem_SDRRC; - w[p0] = r0.l; - ssync; - - /* - * SDRAM Memory Bank Control Register - bank specific parameters - */ - p0.l = (EBIU_SDBCTL & 0xFFFF); - p0.h = (EBIU_SDBCTL >> 16); - r0 = mem_SDBCTL; - w[p0] = r0.l; - ssync; - - /* - * SDRAM Global Control Register - global programmable parameters - * Disable self-refresh - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITCLR (R0, 24); - - /* - * Check if SDRAM is already powered up, if it is, enable self-refresh - */ - p0.h = hi(EBIU_SDSTAT); - p0.l = lo(EBIU_SDSTAT); - r2.l = w[p0]; - cc = bittst(r2,3); - if !cc jump skip; - NOP; - BITSET (R0, 23); -skip: - [P2] = R0; - SSYNC; - - /* Write in the new value in the register */ - R0.L = lo(mem_SDGCTL); - R0.H = hi(mem_SDGCTL); - [P2] = R0; - SSYNC; - nop; - - (P5:0) = [SP++]; - (R7:0) = [SP++]; - RETS = [SP++]; - ASTAT = [SP++]; - RTS; diff --git a/cpu/bf537/init_sdram_bootrom_initblock.S b/cpu/bf537/init_sdram_bootrom_initblock.S deleted file mode 100644 index 197b836067..0000000000 --- a/cpu/bf537/init_sdram_bootrom_initblock.S +++ /dev/null @@ -1,203 +0,0 @@ -#define ASSEMBLY - -#include <linux/config.h> -#include <config.h> -#include <asm/blackfin.h> -#include <asm/mem_init.h> -#include <asm/mach-common/bits/bootrom.h> -#include <asm/mach-common/bits/ebiu.h> -#include <asm/mach-common/bits/pll.h> -#include <asm/mach-common/bits/uart.h> -.global init_sdram; - -#if (BFIN_BOOT_MODE != BF537_UART_BOOT) -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif -#endif - -init_sdram: - [--SP] = ASTAT; - [--SP] = RETS; - [--SP] = (R7:0); - [--SP] = (P5:0); - -#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) - p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); - r0.l = 0x1; - w[p0] = r0.l; - SSYNC; - - p0.h = hi(SPI_BAUD); - p0.l = lo(SPI_BAUD); - r0.l = CONFIG_SPI_BAUD_INITBLOCK; - w[p0] = r0.l; - SSYNC; -#endif - -#if (BFIN_BOOT_MODE != BF537_UART_BOOT) - -#ifdef CONFIG_BF537 - /* Enable PHY CLK buffer output */ - p0.h = hi(VR_CTL); - p0.l = lo(VR_CTL); - r0.l = w[p0]; - bitset(r0, 14); - w[p0] = r0.l; - ssync; -#endif - /* - * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable - */ - p0.h = hi(PLL_LOCKCNT); - p0.l = lo(PLL_LOCKCNT); - r0 = 0x300(Z); - w[p0] = r0.l; - ssync; - - /* - * Put SDRAM in self-refresh, incase anything is running - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITSET (R0, 24); - [P2] = R0; - SSYNC; - - /* - * Set PLL_CTL with the value that we calculate in R0 - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK - * - [7] = output delay (add 200ps of delay to mem signals) - * - [6] = input delay (add 200ps of input delay to mem signals) - * - [5] = PDWN : 1=All Clocks off - * - [3] = STOPCK : 1=Core Clock off - * - [1] = PLL_OFF : 1=Disable Power to PLL - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL - * all other bits set to zero - */ - - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ - r0 = r0 << 9; /* Shift it over */ - r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ - r0 = r1 | r0; - r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ - r1 = r1 << 8; /* Shift it over */ - r0 = r1 | r0; /* add them all together */ - - p0.h = hi(PLL_CTL); - p0.l = lo(PLL_CTL); /* Load the address */ - cli r2; /* Disable interrupts */ - ssync; - w[p0] = r0.l; /* Set the value */ - idle; /* Wait for the PLL to stablize */ - sti r2; /* Enable interrupts */ - -check_again: - p0.h = hi(PLL_STAT); - p0.l = lo(PLL_STAT); - R0 = W[P0](Z); - CC = BITTST(R0,5); - if ! CC jump check_again; - - /* Configure SCLK & CCLK Dividers */ - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); - p0.h = hi(PLL_DIV); - p0.l = lo(PLL_DIV); - w[p0] = r0.l; - ssync; -#endif - - /* - * We now are running at speed, time to set the Async mem bank wait states - * This will speed up execution, since we are normally running from FLASH. - */ - - p2.h = (EBIU_AMBCTL1 >> 16); - p2.l = (EBIU_AMBCTL1 & 0xFFFF); - r0.h = (AMBCTL1VAL >> 16); - r0.l = (AMBCTL1VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMBCTL0 >> 16); - p2.l = (EBIU_AMBCTL0 & 0xFFFF); - r0.h = (AMBCTL0VAL >> 16); - r0.l = (AMBCTL0VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMGCTL >> 16); - p2.l = (EBIU_AMGCTL & 0xffff); - r0 = AMGCTLVAL; - w[p2] = r0; - ssync; - - /* - * Now, Initialize the SDRAM, - * start with the SDRAM Refresh Rate Control Register - */ - p0.l = lo(EBIU_SDRRC); - p0.h = hi(EBIU_SDRRC); - r0 = mem_SDRRC; - w[p0] = r0.l; - ssync; - - /* - * SDRAM Memory Bank Control Register - bank specific parameters - */ - p0.l = (EBIU_SDBCTL & 0xFFFF); - p0.h = (EBIU_SDBCTL >> 16); - r0 = mem_SDBCTL; - w[p0] = r0.l; - ssync; - - /* - * SDRAM Global Control Register - global programmable parameters - * Disable self-refresh - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITCLR (R0, 24); - - /* - * Check if SDRAM is already powered up, if it is, enable self-refresh - */ - p0.h = hi(EBIU_SDSTAT); - p0.l = lo(EBIU_SDSTAT); - r2.l = w[p0]; - cc = bittst(r2,3); - if !cc jump skip; - NOP; - BITSET (R0, 23); -skip: - [P2] = R0; - SSYNC; - - /* Write in the new value in the register */ - R0.L = lo(mem_SDGCTL); - R0.H = hi(mem_SDGCTL); - [P2] = R0; - SSYNC; - nop; - - (P5:0) = [SP++]; - (R7:0) = [SP++]; - RETS = [SP++]; - ASTAT = [SP++]; - RTS; diff --git a/cpu/bf537/interrupt.S b/cpu/bf537/interrupt.S deleted file mode 100644 index fe850bf2e3..0000000000 --- a/cpu/bf537/interrupt.S +++ /dev/null @@ -1,244 +0,0 @@ -/* - * U-boot - interrupt.S Processing of interrupts and exception handling - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on interrupt.S - * - * Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com> - * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca> - * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, - * Kenneth Albanowski <kjahds@kjahds.com>, - * The Silver Hammer Group, Ltd. - * - * (c) 1995, Dionne & Associates - * (c) 1995, DKG Display Tech. - * - * This file is also based on exception.asm - * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#define ASSEMBLY -#include <config.h> -#include <asm/blackfin.h> -#include <asm/entry.h> - -.global _blackfin_irq_panic; - -.text -.align 2 - -#ifndef CONFIG_KGDB -.global _evt_emulation -_evt_emulation: - SAVE_CONTEXT - r0 = 0; - r1 = seqstat; - sp += -12; - call _blackfin_irq_panic; - sp += 12; - rte; -#endif - -.global _evt_nmi -_evt_nmi: - SAVE_CONTEXT - r0 = 2; - r1 = RETN; - sp += -12; - call _blackfin_irq_panic; - sp += 12; - -_evt_nmi_exit: - rtn; - -.global _trap -_trap: - SAVE_ALL_SYS - r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ - sp += -12; - call _trap_c - sp += 12; - RESTORE_ALL_SYS - rtx; - -.global _evt_rst -_evt_rst: - SAVE_CONTEXT - r0 = 1; - r1 = RETN; - sp += -12; - call _do_reset; - sp += 12; - -_evt_rst_exit: - rtn; - -irq_panic: - r0 = 3; - r1 = sp; - sp += -12; - call _blackfin_irq_panic; - sp += 12; - -.global _evt_ivhw -_evt_ivhw: - SAVE_CONTEXT - RAISE 14; - -_evt_ivhw_exit: - rti; - -.global _evt_timer -_evt_timer: - SAVE_CONTEXT - r0 = 6; - sp += -12; - /* Polling method used now. */ - /* call timer_int; */ - sp += 12; - RESTORE_CONTEXT - rti; - nop; - -.global _evt_evt7 -_evt_evt7: - SAVE_CONTEXT - r0 = 7; - sp += -12; - call _process_int; - sp += 12; - -evt_evt7_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt8 -_evt_evt8: - SAVE_CONTEXT - r0 = 8; - sp += -12; - call _process_int; - sp += 12; - -evt_evt8_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt9 -_evt_evt9: - SAVE_CONTEXT - r0 = 9; - sp += -12; - call _process_int; - sp += 12; - -evt_evt9_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt10 -_evt_evt10: - SAVE_CONTEXT - r0 = 10; - sp += -12; - call _process_int; - sp += 12; - -evt_evt10_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt11 -_evt_evt11: - SAVE_CONTEXT - r0 = 11; - sp += -12; - call _process_int; - sp += 12; - -evt_evt11_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt12 -_evt_evt12: - SAVE_CONTEXT - r0 = 12; - sp += -12; - call _process_int; - sp += 12; -evt_evt12_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt13 -_evt_evt13: - SAVE_CONTEXT - r0 = 13; - sp += -12; - call _process_int; - sp += 12; - -evt_evt13_exit: - RESTORE_CONTEXT - rti; - -.global _evt_system_call -_evt_system_call: - [--sp] = r0; - [--SP] = RETI; - r0 = [sp++]; - r0 += 2; - [--sp] = r0; - RETI = [SP++]; - r0 = [SP++]; - SAVE_CONTEXT - sp += -12; - call _exception_handle; - sp += 12; - RESTORE_CONTEXT - RTI; - -evt_system_call_exit: - rti; - -.global _evt_soft_int1 -_evt_soft_int1: - [--sp] = r0; - [--SP] = RETI; - r0 = [sp++]; - r0 += 2; - [--sp] = r0; - RETI = [SP++]; - r0 = [SP++]; - SAVE_CONTEXT - sp += -12; - call _exception_handle; - sp += 12; - RESTORE_CONTEXT - RTI; - -evt_soft_int1_exit: - rti; diff --git a/cpu/bf537/interrupts.c b/cpu/bf537/interrupts.c deleted file mode 100644 index 853fa492c7..0000000000 --- a/cpu/bf537/interrupts.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - * U-boot - interrupts.c Interrupt related routines - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on interrupts.c - * Copyright 1996 Roman Zippel - * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org> - * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> - * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> - * Copyright 2003 Metrowerks/Motorola - * Copyright 2003 Bas Vermeulen <bas@buyways.nl>, - * BuyWays B.V. (www.buyways.nl) - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <config.h> -#include <asm/blackfin.h> -#include "cpu.h" - -static ulong timestamp; -static ulong last_time; -static int int_flag; - -int irq_flags; /* needed by asm-blackfin/system.h */ - -/* Functions just to satisfy the linker */ - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On BF533 it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On BF533 it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - - tbclk = CFG_HZ; - return tbclk; -} - -void enable_interrupts(void) -{ -} - -int disable_interrupts(void) -{ - return 1; -} - -int interrupt_init(void) -{ - return (0); -} - -void udelay(unsigned long usec) -{ - unsigned long delay, start, stop; - unsigned long cclk; - cclk = (CONFIG_CCLK_HZ); - - while (usec > 1) { - /* - * how many clock ticks to delay? - * - request(in useconds) * clock_ticks(Hz) / useconds/second - */ - if (usec < 1000) { - delay = (usec * (cclk / 244)) >> 12; - usec = 0; - } else { - delay = (1000 * (cclk / 244)) >> 12; - usec -= 1000; - } - - asm volatile (" %0 = CYCLES;":"=r" (start)); - do { - asm volatile (" %0 = CYCLES; ":"=r" (stop)); - } while (stop - start < delay); - } - - return; -} - -void timer_init(void) -{ - *pTCNTL = 0x1; - *pTSCALE = 0x0; - *pTCOUNT = MAX_TIM_LOAD; - *pTPERIOD = MAX_TIM_LOAD; - *pTCNTL = 0x7; - asm("CSYNC;"); - - timestamp = 0; - last_time = 0; -} - -/* Any network command or flash - * command is started get_timer shall - * be called before TCOUNT gets reset, - * to implement the accurate timeouts. - * - * How ever milliconds doesn't return - * the number that has been elapsed from - * the last reset. - * - * As get_timer is used in the u-boot - * only for timeouts this should be - * sufficient - */ -ulong get_timer(ulong base) -{ - ulong milisec; - - /* Number of clocks elapsed */ - ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT)); - - /** - * Find if the TCOUNT is reset - * timestamp gives the number of times - * TCOUNT got reset - */ - if (clocks < last_time) - timestamp++; - last_time = clocks; - - /* Get the number of milliseconds */ - milisec = clocks / (CONFIG_CCLK_HZ / 1000); - - /** - * Find the number of millisonds - * that got elapsed before this TCOUNT cycle - */ - milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000)); - - return (milisec - base); -} - -void reset_timer (void) -{ - timestamp = 0; -} diff --git a/cpu/bf537/ints.c b/cpu/bf537/ints.c deleted file mode 100644 index 05d9a1b67e..0000000000 --- a/cpu/bf537/ints.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * U-boot - ints.c Interrupt related routines - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on ints.c - * - * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin - * drivers - * - * Copyright 1996 Roman Zippel - * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org> - * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> - * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> - * Copyright 2003 Metrowerks/Motorola - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <linux/stddef.h> -#include <asm/system.h> -#include <asm/traps.h> -#include <asm/io.h> -#include <asm/errno.h> -#include <asm/blackfin.h> -#include "cpu.h" - -void blackfin_irq_panic(int reason, struct pt_regs *regs) -{ - printf("\n\nException: IRQ 0x%x entered\n", reason); - printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f)); - printf("stack frame=0x%x, ", (unsigned int)regs); - printf("bad PC=0x%04x\n", (unsigned int)regs->pc); - dump(regs); - printf("Unhandled IRQ or exceptions!\n"); - printf("Please reset the board \n"); -} - -void blackfin_init_IRQ(void) -{ - *(unsigned volatile long *)(SIC_IMASK) = 0; -#ifndef CONFIG_KGDB - *(unsigned volatile long *)(EVT1) = 0x0; -#endif - *(unsigned volatile long *)(EVT2) = - (unsigned volatile long)evt_nmi; - *(unsigned volatile long *)(EVT3) = - (unsigned volatile long)trap; - *(unsigned volatile long *)(EVT5) = - (unsigned volatile long)evt_ivhw; - *(unsigned volatile long *)(EVT0) = - (unsigned volatile long)evt_rst; - *(unsigned volatile long *)(EVT6) = - (unsigned volatile long)evt_timer; - *(unsigned volatile long *)(EVT7) = - (unsigned volatile long)evt_evt7; - *(unsigned volatile long *)(EVT8) = - (unsigned volatile long)evt_evt8; - *(unsigned volatile long *)(EVT9) = - (unsigned volatile long)evt_evt9; - *(unsigned volatile long *)(EVT10) = - (unsigned volatile long)evt_evt10; - *(unsigned volatile long *)(EVT11) = - (unsigned volatile long)evt_evt11; - *(unsigned volatile long *)(EVT12) = - (unsigned volatile long)evt_evt12; - *(unsigned volatile long *)(EVT13) = - (unsigned volatile long)evt_evt13; - *(unsigned volatile long *)(EVT14) = - (unsigned volatile long)evt_system_call; - *(unsigned volatile long *)(EVT15) = - (unsigned volatile long)evt_soft_int1; - *(volatile unsigned long *)ILAT = 0; - asm("csync;"); - *(volatile unsigned long *)IMASK = 0xffbf; - asm("csync;"); -} - -void exception_handle(void) -{ -#if defined (CONFIG_PANIC_HANG) - display_excp(); -#else - udelay(100000); /* allow messages to go out */ - do_reset(NULL, 0, 0, NULL); -#endif -} - -void display_excp(void) -{ - printf("Exception!\n"); -} diff --git a/cpu/bf537/serial.c b/cpu/bf537/serial.c deleted file mode 100644 index 3c6a37016d..0000000000 --- a/cpu/bf537/serial.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * U-boot - serial.c Serial driver for BF537 - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * bf537_serial.c: Serial driver for BlackFin BF537 internal UART. - * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>, - * BuyWays B.V. (www.buyways.nl) - * - * Based heavily on blkfinserial.c - * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs. - * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com> - * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com> - * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com> - * - * Based on code from 68328 version serial driver imlpementation which was: - * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu> - * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com> - * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org> - * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <asm/system.h> -#include <asm/bitops.h> -#include <asm/delay.h> -#include <asm/io.h> -#include "serial.h" -#include <asm/mach-common/bits/uart.h> - -DECLARE_GLOBAL_DATA_PTR; - -unsigned long pll_div_fact; - -void calc_baud(void) -{ - unsigned char i; - int temp; - u_long sclk = get_sclk(); - - for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) { - temp = sclk / (baud_table[i] * 8); - if ((temp & 0x1) == 1) { - temp++; - } - temp = temp / 2; - hw_baud_table[i].dl_high = (temp >> 8) & 0xFF; - hw_baud_table[i].dl_low = (temp) & 0xFF; - } -} - -void serial_setbrg(void) -{ - int i; - - calc_baud(); - - for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) { - if (gd->baudrate == baud_table[i]) - break; - } - - /* Enable UART */ - *pUART0_GCTL |= UCEN; - SSYNC(); - - /* Set DLAB in LCR to Access DLL and DLH */ - ACCESS_LATCH; - SSYNC(); - - *pUART0_DLL = hw_baud_table[i].dl_low; - SSYNC(); - *pUART0_DLH = hw_baud_table[i].dl_high; - SSYNC(); - - /* Clear DLAB in LCR to Access THR RBR IER */ - ACCESS_PORT_IER; - SSYNC(); - - /* Enable ERBFI and ELSI interrupts - * to poll SIC_ISR register*/ - *pUART0_IER = ELSI | ERBFI | ETBEI; - SSYNC(); - - /* Set LCR to Word Lengh 8-bit word select */ - *pUART0_LCR = WLS_8; - SSYNC(); - - return; -} - -int serial_init(void) -{ - serial_setbrg(); - return (0); -} - -void serial_putc(const char c) -{ - if ((*pUART0_LSR) & TEMT) { - if (c == '\n') - serial_putc('\r'); - - local_put_char(c); - } - - while (!((*pUART0_LSR) & TEMT)) - SYNC_ALL; - - return; -} - -int serial_tstc(void) -{ - if (*pUART0_LSR & DR) - return 1; - else - return 0; -} - -int serial_getc(void) -{ - unsigned short uart_lsr_val, uart_rbr_val; - unsigned long isr_val; - int ret; - - /* Poll for RX Interrupt */ - while (!serial_tstc()) - continue; - asm("csync;"); - - uart_lsr_val = *pUART0_LSR; /* Clear status bit */ - uart_rbr_val = *pUART0_RBR; /* getc() */ - - if (uart_lsr_val & (OE|PE|FE|BI)) { - ret = -1; - } else { - ret = uart_rbr_val & 0xff; - } - - return ret; -} - -void serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - -static void local_put_char(char ch) -{ - int flags = 0; - unsigned long isr_val; - - /* Poll for TX Interruput */ - while (!(*pUART0_LSR & THRE)) - continue; - asm("csync;"); - - *pUART0_THR = ch; /* putc() */ - - return; -} diff --git a/cpu/bf537/serial.h b/cpu/bf537/serial.h deleted file mode 100644 index e4e0b9aec6..0000000000 --- a/cpu/bf537/serial.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * U-boot - bf537_serial.h Serial Driver defines - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver. - * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl> - * BuyWays B.V. (www.buyways.nl) - * - * Based heavily on: - * blkfinserial.h: Definitions for the BlackFin DSP serial driver. - * - * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com - * Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com> - * - * Based on code from 68328serial.c which was: - * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu> - * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com> - * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org> - * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _Bf537_SERIAL_H -#define _Bf537_SERIAL_H - -#include <linux/config.h> -#include <asm/blackfin.h> - -#define SYNC_ALL __asm__ __volatile__ ("ssync;\n") -#define ACCESS_LATCH *pUART0_LCR |= DLAB; -#define ACCESS_PORT_IER *pUART0_LCR &= (~DLAB); - -void serial_setbrg(void); -static void local_put_char(char ch); -void calc_baud(void); -void serial_setbrg(void); -int serial_init(void); -void serial_putc(const char c); -int serial_tstc(void); -int serial_getc(void); -void serial_puts(const char *s); -static void local_put_char(char ch); - -int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 }; - -struct { - unsigned char dl_high; - unsigned char dl_low; -} hw_baud_table[5]; - -#ifdef CONFIG_STAMP -extern unsigned long pll_div_fact; -#endif - -#endif diff --git a/cpu/bf537/start.S b/cpu/bf537/start.S deleted file mode 100644 index a48f3c6c7b..0000000000 --- a/cpu/bf537/start.S +++ /dev/null @@ -1,576 +0,0 @@ -/* - * U-boot - start.S Startup file of u-boot for BF537 - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on head.S - * Copyright (c) 2003 Metrowerks/Motorola - * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, - * Kenneth Albanowski <kjahds@kjahds.com>, - * The Silver Hammer Group, Ltd. - * (c) 1995, Dionne & Associates - * (c) 1995, DKG Display Tech. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* - * Note: A change in this file subsequently requires a change in - * board/$(board_name)/config.mk for a valid u-boot.bin - */ - -#define ASSEMBLY - -#include <linux/config.h> -#include <config.h> -#include <asm/blackfin.h> - -#include <asm/mach-common/bits/core.h> -#include <asm/mach-common/bits/dma.h> -#include <asm/mach-common/bits/pll.h> - -.global _stext; -.global __bss_start; -.global start; -.global _start; -.global edata; -.global _exit; -.global init_sdram; -.global _icache_enable; -.global _dcache_enable; -#if defined(CONFIG_BF537)&&defined(CONFIG_POST) -.global _memory_post_test; -.global _post_flag; -#endif - -#if (BFIN_BOOT_MODE == BF537_UART_BOOT) -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif -#endif - -.text -_start: -start: -_stext: - - R0 = 0x32; - SYSCFG = R0; - SSYNC; - - /* As per HW reference manual DAG registers, - * DATA and Address resgister shall be zero'd - * in initialization, after a reset state - */ - r1 = 0; /* Data registers zero'd */ - r2 = 0; - r3 = 0; - r4 = 0; - r5 = 0; - r6 = 0; - r7 = 0; - - p0 = 0; /* Address registers zero'd */ - p1 = 0; - p2 = 0; - p3 = 0; - p4 = 0; - p5 = 0; - - i0 = 0; /* DAG Registers zero'd */ - i1 = 0; - i2 = 0; - i3 = 0; - m0 = 0; - m1 = 0; - m3 = 0; - m3 = 0; - l0 = 0; - l1 = 0; - l2 = 0; - l3 = 0; - b0 = 0; - b1 = 0; - b2 = 0; - b3 = 0; - - /* Set loop counters to zero, to make sure that - * hw loops are disabled. - */ - r0 = 0; - lc0 = r0; - lc1 = r0; - - SSYNC; - - /* Check soft reset status */ - p0.h = SWRST >> 16; - p0.l = SWRST & 0xFFFF; - r0.l = w[p0]; - - cc = bittst(r0, 15); - if !cc jump no_soft_reset; - - /* Clear Soft reset */ - r0 = 0x0000; - w[p0] = r0; - ssync; - -no_soft_reset: - nop; - - /* Clear EVT registers */ - p0.h = (EVT0 >> 16); - p0.l = (EVT0 & 0xFFFF); - p0 += 8; - p1 = 14; - r1 = 0; - LSETUP(4,4) lc0 = p1; - [ p0 ++ ] = r1; - -#if (BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT) - p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); - r0.l = 0x1; - w[p0] = r0.l; - SSYNC; -#endif - -#if (BFIN_BOOT_MODE == BF537_UART_BOOT) - - p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); - r0.l = 0x1; - w[p0] = r0.l; - SSYNC; - - /* - * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable - */ - p0.h = hi(PLL_LOCKCNT); - p0.l = lo(PLL_LOCKCNT); - r0 = 0x300(Z); - w[p0] = r0.l; - ssync; - - /* - * Put SDRAM in self-refresh, incase anything is running - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITSET (R0, 24); - [P2] = R0; - SSYNC; - - /* - * Set PLL_CTL with the value that we calculate in R0 - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK - * - [7] = output delay (add 200ps of delay to mem signals) - * - [6] = input delay (add 200ps of input delay to mem signals) - * - [5] = PDWN : 1=All Clocks off - * - [3] = STOPCK : 1=Core Clock off - * - [1] = PLL_OFF : 1=Disable Power to PLL - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL - * all other bits set to zero - */ - - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ - r0 = r0 << 9; /* Shift it over, */ - r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ - r0 = r1 | r0; - r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ - r1 = r1 << 8; /* Shift it over */ - r0 = r1 | r0; /* add them all together */ - - p0.h = hi(PLL_CTL); - p0.l = lo(PLL_CTL); /* Load the address */ - cli r2; /* Disable interrupts */ - ssync; - w[p0] = r0.l; /* Set the value */ - idle; /* Wait for the PLL to stablize */ - sti r2; /* Enable interrupts */ - -check_again: - p0.h = hi(PLL_STAT); - p0.l = lo(PLL_STAT); - R0 = W[P0](Z); - CC = BITTST(R0,5); - if ! CC jump check_again; - - /* Configure SCLK & CCLK Dividers */ - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); - p0.h = hi(PLL_DIV); - p0.l = lo(PLL_DIV); - w[p0] = r0.l; - ssync; -#endif - - /* - * We now are running at speed, time to set the Async mem bank wait states - * This will speed up execution, since we are normally running from FLASH. - * we need to read MAC address from FLASH - */ - p2.h = (EBIU_AMBCTL1 >> 16); - p2.l = (EBIU_AMBCTL1 & 0xFFFF); - r0.h = (AMBCTL1VAL >> 16); - r0.l = (AMBCTL1VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMBCTL0 >> 16); - p2.l = (EBIU_AMBCTL0 & 0xFFFF); - r0.h = (AMBCTL0VAL >> 16); - r0.l = (AMBCTL0VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMGCTL >> 16); - p2.l = (EBIU_AMGCTL & 0xffff); - r0 = AMGCTLVAL; - w[p2] = r0; - ssync; - -#if ((BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT) && (BFIN_BOOT_MODE != BF537_UART_BOOT)) - sp.l = (0xffb01000 & 0xFFFF); - sp.h = (0xffb01000 >> 16); - - call init_sdram; -#endif - - -#if defined(CONFIG_BF537)&&defined(CONFIG_POST) - /* DMA POST code to Hi of L1 SRAM */ -postcopy: - /* P1 Points to the beginning of SYSTEM MMR Space */ - P1.H = hi(SYSMMR_BASE); - P1.L = lo(SYSMMR_BASE); - - R0.H = _text_l1; - R0.L = _text_l1; - R1.H = _etext_l1; - R1.L = _etext_l1; - R2 = R1 - R0; /* Count */ - R0.H = _etext; - R0.L = _etext; - R1.H = (CFG_MONITOR_BASE >> 16); - R1.L = (CFG_MONITOR_BASE & 0xFFFF); - R0 = R0 - R1; - R1.H = (CFG_FLASH_BASE >> 16); - R1.L = (CFG_FLASH_BASE & 0xFFFF); - R0 = R0 + R1; /* Source Address */ - R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ - R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ - R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ - /* Destination DMAConfig Value (8-bit words) */ - R4.L = (DI_EN | WNR | DMAEN); - - R6 = 0x1 (Z); - W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ - W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ - - [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ - W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ - /* Set Source DMAConfig = DMA Enable, - Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ - W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; - - [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ - W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ - /* Set Destination DMAConfig = DMA Enable, - Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ - W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; - -POST_DMA_DONE: - p0.h = hi(MDMA_D0_IRQ_STATUS); - p0.l = lo(MDMA_D0_IRQ_STATUS); - R0 = W[P0](Z); - CC = BITTST(R0, 0); - if ! CC jump POST_DMA_DONE - - R0 = 0x1; - W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ - - /* DMA POST data to Hi of L1 SRAM */ - R0.H = _rodata_l1; - R0.L = _rodata_l1; - R1.H = _erodata_l1; - R1.L = _erodata_l1; - R2 = R1 - R0; /* Count */ - R0.H = _erodata; - R0.L = _erodata; - R1.H = (CFG_MONITOR_BASE >> 16); - R1.L = (CFG_MONITOR_BASE & 0xFFFF); - R0 = R0 - R1; - R1.H = (CFG_FLASH_BASE >> 16); - R1.L = (CFG_FLASH_BASE & 0xFFFF); - R0 = R0 + R1; /* Source Address */ - R1.H = hi(DATA_BANKB_SRAM); /* Destination Address (high) */ - R1.L = lo(DATA_BANKB_SRAM); /* Destination Address (low) */ - R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ - R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ - - R6 = 0x1 (Z); - W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ - W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ - - [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ - W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ - /* Set Source DMAConfig = DMA Enable, - Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ - W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; - - [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ - W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ - /* Set Destination DMAConfig = DMA Enable, - Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ - W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; - -POST_DATA_DMA_DONE: - p0.h = hi(MDMA_D0_IRQ_STATUS); - p0.l = lo(MDMA_D0_IRQ_STATUS); - R0 = W[P0](Z); - CC = BITTST(R0, 0); - if ! CC jump POST_DATA_DMA_DONE - - R0 = 0x1; - W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ - - p0.l = _memory_post_test; - p0.h = _memory_post_test; - r0 = 0x0; - call (p0); - r7 = r0; /* save return value */ - - call init_sdram; -#endif - - /* relocate into to RAM */ - call get_pc; -offset: - r2.l = offset; - r2.h = offset; - r3.l = start; - r3.h = start; - r1 = r2 - r3; - - r0 = r0 - r1; - p1 = r0; - - p2.l = (CFG_MONITOR_BASE & 0xffff); - p2.h = (CFG_MONITOR_BASE >> 16); - - p3 = 0x04; - p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff); - p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16); -loop1: - r1 = [p1 ++ p3]; - [p2 ++ p3] = r1; - cc=p2==p4; - if !cc jump loop1; - /* - * configure STACK - */ - r0.h = (CONFIG_STACKBASE >> 16); - r0.l = (CONFIG_STACKBASE & 0xFFFF); - sp = r0; - fp = sp; - - /* - * This next section keeps the processor in supervisor mode - * during kernel boot. Switches to user mode at end of boot. - * See page 3-9 of Hardware Reference manual for documentation. - */ - - /* To keep ourselves in the supervisor mode */ - p0.l = (EVT15 & 0xFFFF); - p0.h = (EVT15 >> 16); - - p1.l = _real_start; - p1.h = _real_start; - [p0] = p1; - - p0.l = (IMASK & 0xFFFF); - p0.h = (IMASK >> 16); - r0.l = LO(EVT_IVG15); - r0.h = HI(EVT_IVG15); - [p0] = r0; - raise 15; - p0.l = WAIT_HERE; - p0.h = WAIT_HERE; - reti = p0; - rti; - -WAIT_HERE: - jump WAIT_HERE; - -.global _real_start; -_real_start: - [ -- sp ] = reti; - -#ifdef CONFIG_BF537 -/* Initialise General-Purpose I/O Modules on BF537 - * Rev 0.0 Anomaly 05000212 - PORTx_FER, - * PORT_MUX Registers Do Not accept "writes" correctly - */ - p0.h = hi(PORTF_FER); - p0.l = lo(PORTF_FER); - R0.L = W[P0]; /* Read */ - nop; - nop; - nop; - ssync; - R0 = 0x000F(Z); - W[P0] = R0.L; /* Write */ - nop; - nop; - nop; - ssync; - W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */ - nop; - nop; - nop; - ssync; - - p0.h = hi(PORTH_FER); - p0.l = lo(PORTH_FER); - R0.L = W[P0]; /* Read */ - nop; - nop; - nop; - ssync; - R0 = 0xFFFF(Z); - W[P0] = R0.L; /* Write */ - nop; - nop; - nop; - ssync; - W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */ - nop; - nop; - nop; - ssync; - -#endif - - /* DMA reset code to Hi of L1 SRAM */ -copy: - P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */ - P1.L = lo(SYSMMR_BASE); - - R0.H = reset_start; /* Source Address (high) */ - R0.L = reset_start; /* Source Address (low) */ - R1.H = reset_end; - R1.L = reset_end; - R2 = R1 - R0; /* Count */ - R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ - R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ - R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ - R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ - -DMA: - R6 = 0x1 (Z); - W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ - W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ - - [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ - W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ - /* Set Source DMAConfig = DMA Enable, - Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ - W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; - - [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ - W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ - /* Set Destination DMAConfig = DMA Enable, - Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ - W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; - -WAIT_DMA_DONE: - p0.h = hi(MDMA_D0_IRQ_STATUS); - p0.l = lo(MDMA_D0_IRQ_STATUS); - R0 = W[P0](Z); - CC = BITTST(R0, 0); - if ! CC jump WAIT_DMA_DONE - - R0 = 0x1; - W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ - - /* Initialize BSS Section with 0 s */ - p1.l = __bss_start; - p1.h = __bss_start; - p2.l = _end; - p2.h = _end; - r1 = p1; - r2 = p2; - r3 = r2 - r1; - r3 = r3 >> 2; - p3 = r3; - lsetup (_clear_bss, _clear_bss_end ) lc1 = p3; - CC = p2<=p1; - if CC jump _clear_bss_skip; - r0 = 0; -_clear_bss: -_clear_bss_end: - [p1++] = r0; -_clear_bss_skip: - -#if defined(CONFIG_BF537)&&defined(CONFIG_POST) - p0.l = _post_flag; - p0.h = _post_flag; - r0 = r7; - [p0] = r0; -#endif - - p0.l = _start1; - p0.h = _start1; - jump (p0); - -reset_start: - p0.h = WDOG_CNT >> 16; - p0.l = WDOG_CNT & 0xffff; - r0 = 0x0010; - w[p0] = r0; - p0.h = WDOG_CTL >> 16; - p0.l = WDOG_CTL & 0xffff; - r0 = 0x0000; - w[p0] = r0; -reset_wait: - jump reset_wait; - -reset_end: - nop; - -_exit: - jump.s _exit; -get_pc: - r0 = rets; - rts; diff --git a/cpu/bf537/start1.S b/cpu/bf537/start1.S deleted file mode 100644 index 6d4731b696..0000000000 --- a/cpu/bf537/start1.S +++ /dev/null @@ -1,38 +0,0 @@ -/* - * U-boot - start1.S Code running out of RAM after relocation - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#define ASSEMBLY -#include <linux/config.h> -#include <config.h> -#include <asm/blackfin.h> - -.global start1; -.global _start1; - -.text -_start1: -start1: - sp += -12; - call _board_init_f; - sp += 12; diff --git a/cpu/bf537/traps.c b/cpu/bf537/traps.c deleted file mode 100644 index 51de322aed..0000000000 --- a/cpu/bf537/traps.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * U-boot - traps.c Routines related to interrupts and exceptions - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * No original Copyright holder listed, - * Probabily original (C) Roman Zippel (assigned DJD, 1999) - * - * Copyright 2003 Metrowerks - for Blackfin - * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca> - * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org> - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <linux/types.h> -#include <asm/errno.h> -#include <asm/system.h> -#include <asm/traps.h> -#include "cpu.h" -#include <asm/cplb.h> -#include <asm/io.h> -#include <asm/mach-common/bits/core.h> -#include <asm/mach-common/bits/mpu.h> - -void init_IRQ(void) -{ - blackfin_init_IRQ(); - return; -} - -void process_int(unsigned long vec, struct pt_regs *fp) -{ - printf("interrupt\n"); - return; -} - -extern unsigned int icplb_table[page_descriptor_table_size][2]; -extern unsigned int dcplb_table[page_descriptor_table_size][2]; - -unsigned long last_cplb_fault_retx; - -static unsigned int cplb_sizes[4] = - { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 }; - -void trap_c(struct pt_regs *regs) -{ - unsigned int addr; - unsigned long trapnr = (regs->seqstat) & EXCAUSE; - unsigned int i, j, size, *I0, *I1; - unsigned short data = 0; - - switch (trapnr) { - /* 0x26 - Data CPLB Miss */ - case VEC_CPLB_M: - -#if ANOMALY_05000261 - /* - * Work around an anomaly: if we see a new DCPLB fault, - * return without doing anything. Then, - * if we get the same fault again, handle it. - */ - addr = last_cplb_fault_retx; - last_cplb_fault_retx = regs->retx; - printf("this time, curr = 0x%08x last = 0x%08x\n", - addr, last_cplb_fault_retx); - if (addr != last_cplb_fault_retx) - goto trap_c_return; -#endif - data = 1; - - case VEC_CPLB_I_M: - - if (data) { - addr = *pDCPLB_FAULT_ADDR; - } else { - addr = *pICPLB_FAULT_ADDR; - } - for (i = 0; i < page_descriptor_table_size; i++) { - if (data) { - size = cplb_sizes[dcplb_table[i][1] >> 16]; - j = dcplb_table[i][0]; - } else { - size = cplb_sizes[icplb_table[i][1] >> 16]; - j = icplb_table[i][0]; - } - if ((j <= addr) && ((j + size) > addr)) { - debug("found %i 0x%08x\n", i, j); - break; - } - } - if (i == page_descriptor_table_size) { - printf("something is really wrong\n"); - do_reset(NULL, 0, 0, NULL); - } - - /* Turn the cache off */ - if (data) { - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)DMEM_CONTROL &= - ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - SSYNC(); - } else { - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - SSYNC(); - } - - if (data) { - I0 = (unsigned int *)DCPLB_ADDR0; - I1 = (unsigned int *)DCPLB_DATA0; - } else { - I0 = (unsigned int *)ICPLB_ADDR0; - I1 = (unsigned int *)ICPLB_DATA0; - } - - j = 0; - while (*I1 & CPLB_LOCK) { - debug("skipping %i %08p - %08x\n", j, I1, *I1); - *I0++; - *I1++; - j++; - } - - debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1); - - for (; j < 15; j++) { - debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1); - *I0++ = *(I0 + 1); - *I1++ = *(I1 + 1); - } - - if (data) { - *I0 = dcplb_table[i][0]; - *I1 = dcplb_table[i][1]; - I0 = (unsigned int *)DCPLB_ADDR0; - I1 = (unsigned int *)DCPLB_DATA0; - } else { - *I0 = icplb_table[i][0]; - *I1 = icplb_table[i][1]; - I0 = (unsigned int *)ICPLB_ADDR0; - I1 = (unsigned int *)ICPLB_DATA0; - } - - for (j = 0; j < 16; j++) { - debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++); - } - - /* Turn the cache back on */ - if (data) { - j = *(unsigned int *)DMEM_CONTROL; - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)DMEM_CONTROL = - ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; - SSYNC(); - } else { - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - SSYNC(); - } - - break; - default: - /* All traps come here */ - printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f)); - printf("stack frame=0x%x, ", (unsigned int)regs); - printf("bad PC=0x%04x\n", (unsigned int)regs->pc); - dump(regs); - printf("\n\n"); - - printf("Unhandled IRQ or exceptions!\n"); - printf("Please reset the board \n"); - do_reset(NULL, 0, 0, NULL); - } - -trap_c_return: - return; - -} - -void dump(struct pt_regs *fp) -{ - debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n", - fp->rete, fp->retn, fp->retx, fp->rets); - debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg); - debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp); - debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n", - fp->r0, fp->r1, fp->r2, fp->r3); - debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", - fp->r4, fp->r5, fp->r6, fp->r7); - debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n", - fp->p0, fp->p1, fp->p2, fp->p3); - debug("P4: %08lx P5: %08lx FP: %08lx\n", - fp->p4, fp->p5, fp->fp); - debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", - fp->a0w, fp->a0x, fp->a1w, fp->a1x); - - debug("LB0: %08lx LT0: %08lx LC0: %08lx\n", - fp->lb0, fp->lt0, fp->lc0); - debug("LB1: %08lx LT1: %08lx LC1: %08lx\n", - fp->lb1, fp->lt1, fp->lc1); - debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n", - fp->b0, fp->l0, fp->m0, fp->i0); - debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n", - fp->b1, fp->l1, fp->m1, fp->i1); - debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n", - fp->b2, fp->l2, fp->m2, fp->i2); - debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n", - fp->b3, fp->l3, fp->m3, fp->i3); - - debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR); - debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR); - -} diff --git a/cpu/bf537/video.c b/cpu/bf537/video.c deleted file mode 100644 index 3ff0151d48..0000000000 --- a/cpu/bf537/video.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * (C) Copyright 2002 - * Wolfgang Denk, wd@denx.de - * (C) Copyright 2006 - * Aubrey Li, aubrey.li@analog.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <stdarg.h> -#include <common.h> -#include <config.h> -#include <asm/blackfin.h> -#include <i2c.h> -#include <linux/types.h> -#include <devices.h> - -#ifdef CONFIG_VIDEO -#define NTSC_FRAME_ADDR 0x06000000 -#include "video.h" - -/* NTSC OUTPUT SIZE 720 * 240 */ -#define VERTICAL 2 -#define HORIZONTAL 4 - -int is_vblank_line(const int line) -{ - /* - * This array contains a single bit for each line in - * an NTSC frame. - */ - if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528)) - return true; - - return false; -} - -int NTSC_framebuffer_init(char *base_address) -{ - const int NTSC_frames = 1; - const int NTSC_lines = 525; - char *dest = base_address; - int frame_num, line_num; - - for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) { - for (line_num = 1; line_num <= NTSC_lines; ++line_num) { - unsigned int code; - int offset = 0; - int i; - - if (is_vblank_line(line_num)) - offset++; - - if (line_num > 266 || line_num < 3) - offset += 2; - - /* Output EAV code */ - code = SystemCodeMap[offset].EAV; - write_dest_byte((char)(code >> 24) & 0xff); - write_dest_byte((char)(code >> 16) & 0xff); - write_dest_byte((char)(code >> 8) & 0xff); - write_dest_byte((char)(code) & 0xff); - - /* Output horizontal blanking */ - for (i = 0; i < 67 * 2; ++i) { - write_dest_byte(0x80); - write_dest_byte(0x10); - } - - /* Output SAV */ - code = SystemCodeMap[offset].SAV; - write_dest_byte((char)(code >> 24) & 0xff); - write_dest_byte((char)(code >> 16) & 0xff); - write_dest_byte((char)(code >> 8) & 0xff); - write_dest_byte((char)(code) & 0xff); - - /* Output empty horizontal data */ - for (i = 0; i < 360 * 2; ++i) { - write_dest_byte(0x80); - write_dest_byte(0x10); - } - } - } - - return dest - base_address; -} - -void fill_frame(char *Frame, int Value) -{ - int *OddPtr32; - int OddLine; - int *EvenPtr32; - int EvenLine; - int i; - int *data; - int m, n; - - /* fill odd and even frames */ - for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) { - OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276); - EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276); - for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) { - *OddPtr32 = Value; - *EvenPtr32 = Value; - } - } - - for (m = 0; m < VERTICAL; m++) { - data = (int *)u_boot_logo.data; - for (OddLine = (22 + m), EvenLine = (285 + m); - OddLine < (u_boot_logo.height * VERTICAL) + (22 + m); - OddLine += VERTICAL, EvenLine += VERTICAL) { - OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276); - EvenPtr32 = - (int *)((Frame + ((EvenLine) * 1716)) + 276); - for (i = 0; i < u_boot_logo.width / 2; i++) { - /* enlarge one pixel to m x n */ - for (n = 0; n < HORIZONTAL; n++) { - *OddPtr32++ = *data; - *EvenPtr32++ = *data; - } - data++; - } - } - } -} - -void video_putc(const char c) -{ -} - -void video_puts(const char *s) -{ -} - -static int video_init(void) -{ - char *NTSCFrame; - NTSCFrame = (char *)NTSC_FRAME_ADDR; - NTSC_framebuffer_init(NTSCFrame); - fill_frame(NTSCFrame, BLUE); - - *pPPI_CONTROL = 0x0082; - *pPPI_FRAME = 0x020D; - - *pDMA0_START_ADDR = NTSCFrame; - *pDMA0_X_COUNT = 0x035A; - *pDMA0_X_MODIFY = 0x0002; - *pDMA0_Y_COUNT = 0x020D; - *pDMA0_Y_MODIFY = 0x0002; - *pDMA0_CONFIG = 0x1015; - *pPPI_CONTROL = 0x0083; - return 0; -} - -int drv_video_init(void) -{ - int error, devices = 1; - - device_t videodev; - - video_init(); /* Video initialization */ - - memset(&videodev, 0, sizeof(videodev)); - - strcpy(videodev.name, "video"); - videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ - videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */ - videodev.putc = video_putc; /* 'putc' function */ - videodev.puts = video_puts; /* 'puts' function */ - - error = device_register(&videodev); - - return (error == 0) ? devices : error; -} -#endif diff --git a/cpu/bf537/video.h b/cpu/bf537/video.h deleted file mode 100644 index a43553f420..0000000000 --- a/cpu/bf537/video.h +++ /dev/null @@ -1,25 +0,0 @@ -#include <video_logo.h> -#define write_dest_byte(val) {*dest++=val;} -#define BLACK (0x01800180) /* black pixel pattern */ -#define BLUE (0x296E29F0) /* blue pixel pattern */ -#define RED (0x51F0515A) /* red pixel pattern */ -#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern*/ -#define GREEN (0x91229136) /* green pixel pattern */ -#define CYAN (0xAA10AAA6) /* cyan pixel pattern */ -#define YELLOW (0xD292D210) /* yellow pixel pattern */ -#define WHITE (0xFE80FE80) /* white pixel pattern */ - -#define true 1 -#define false 0 - -typedef struct { - unsigned int SAV; - unsigned int EAV; -} SystemCodeType; - -const SystemCodeType SystemCodeMap[4] = { - {0xFF000080, 0xFF00009D}, - {0xFF0000AB, 0xFF0000B6}, - {0xFF0000C7, 0xFF0000DA}, - {0xFF0000EC, 0xFF0000F1} -}; diff --git a/cpu/bf561/cache.S b/cpu/bf561/cache.S deleted file mode 100644 index d9015c6d1a..0000000000 --- a/cpu/bf561/cache.S +++ /dev/null @@ -1,129 +0,0 @@ -#define ASSEMBLY -#include <asm/linkage.h> -#include <config.h> -#include <asm/blackfin.h> -#include <asm/mach-common/bits/mpu.h> - -.text -.align 2 -ENTRY(_blackfin_icache_flush_range) - R2 = -32; - R2 = R0 & R2; - P0 = R2; - P1 = R1; - CSYNC; - 1: - IFLUSH[P0++]; - CC = P0 < P1(iu); - IF CC JUMP 1b(bp); - IFLUSH[P0]; - SSYNC; - RTS; - -ENTRY(_blackfin_dcache_flush_range) - R2 = -32; - R2 = R0 & R2; - P0 = R2; - P1 = R1; - CSYNC; -1: - FLUSH[P0++]; - CC = P0 < P1(iu); - IF CC JUMP 1b(bp); - FLUSH[P0]; - SSYNC; - RTS; - -ENTRY(_icache_invalidate) -ENTRY(_invalidate_entire_icache) - [--SP] = (R7:5); - - P0.L = (IMEM_CONTROL & 0xFFFF); - P0.H = (IMEM_CONTROL >> 16); - R7 =[P0]; - - /* - * Clear the IMC bit , All valid bits in the instruction - * cache are set to the invalid state - */ - BITCLR(R7, IMC_P); - CLI R6; - /* SSYNC required before invalidating cache. */ - SSYNC; - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - /* Configures the instruction cache agian */ - R6 = (IMC | ENICPLB); - R7 = R7 | R6; - - CLI R6; - SSYNC; - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - (R7:5) =[SP++]; - RTS; - -/* - * Invalidate the Entire Data cache by - * clearing DMC[1:0] bits - */ -ENTRY(_invalidate_entire_dcache) -ENTRY(_dcache_invalidate) - [--SP] = (R7:6); - - P0.L = (DMEM_CONTROL & 0xFFFF); - P0.H = (DMEM_CONTROL >> 16); - R7 =[P0]; - - /* - * Clear the DMC[1:0] bits, All valid bits in the data - * cache are set to the invalid state - */ - BITCLR(R7, DMC0_P); - BITCLR(R7, DMC1_P); - CLI R6; - SSYNC; - .align 8; - [P0] = R7; - SSYNC; - STI R6; - /* Configures the data cache again */ - - R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - R7 = R7 | R6; - - CLI R6; - SSYNC; - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - (R7:6) =[SP++]; - RTS; - -ENTRY(_blackfin_dcache_invalidate_range) - R2 = -32; - R2 = R0 & R2; - P0 = R2; - P1 = R1; - CSYNC; -1: - FLUSHINV[P0++]; - CC = P0 < P1(iu); - IF CC JUMP 1b(bp); - - /* - * If the data crosses a cache line, then we'll be pointing to - * the last cache line, but won't have flushed/invalidated it yet, so do - * one more. - */ - FLUSHINV[P0]; - SSYNC; - RTS; diff --git a/cpu/bf561/config.mk b/cpu/bf561/config.mk deleted file mode 100644 index 3628a026b0..0000000000 --- a/cpu/bf561/config.mk +++ /dev/null @@ -1,27 +0,0 @@ -# U-boot - config.mk -# -# Copyright (c) 2005-2007 Analog Devices Inc. -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -# MA 02110-1301 USA -# - -PLATFORM_RELFLAGS += -mcpu=bf561 diff --git a/cpu/bf561/cpu.c b/cpu/bf561/cpu.c deleted file mode 100644 index e0dd2f5ea8..0000000000 --- a/cpu/bf561/cpu.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * U-boot - cpu.c CPU specific functions - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <asm/blackfin.h> -#include <command.h> -#include <asm/entry.h> -#include <asm/cplb.h> -#include <asm/io.h> - -#define CACHE_ON 1 -#define CACHE_OFF 0 - -extern unsigned int icplb_table[page_descriptor_table_size][2]; -extern unsigned int dcplb_table[page_descriptor_table_size][2]; - -int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) - ); - - return 0; -} - -/* These functions are just used to satisfy the linker */ -int cpu_init(void) -{ - return 0; -} - -int cleanup_before_linux(void) -{ - return 0; -} - -void icache_enable(void) -{ - unsigned int *I0, *I1; - int i, j = 0; - - /* Before enable icache, disable it first */ - icache_disable(); - I0 = (unsigned int *)ICPLB_ADDR0; - I1 = (unsigned int *)ICPLB_DATA0; - - /* make sure the locked ones go in first */ - for (i = 0; i < page_descriptor_table_size; i++) { - if (CPLB_LOCK & icplb_table[i][1]) { - debug("adding %02i %02i 0x%08x 0x%08x\n", i, j, - icplb_table[i][0], icplb_table[i][1]); - *I0++ = icplb_table[i][0]; - *I1++ = icplb_table[i][1]; - j++; - } - } - - for (i = 0; i < page_descriptor_table_size; i++) { - if (!(CPLB_LOCK & icplb_table[i][1])) { - debug("adding %02i %02i 0x%08x 0x%08x\n", i, j, - icplb_table[i][0], icplb_table[i][1]); - *I0++ = icplb_table[i][0]; - *I1++ = icplb_table[i][1]; - j++; - if (j == 16) { - break; - } - } - } - - /* Fill the rest with invalid entry */ - if (j <= 15) { - for (; j < 16; j++) { - debug("filling %i with 0", j); - *I1++ = 0x0; - } - - } - - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - SSYNC(); -} - -void icache_disable(void) -{ - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - SSYNC(); -} - -int icache_status(void) -{ - unsigned int value; - value = *(unsigned int *)IMEM_CONTROL; - - if (value & (IMC | ENICPLB)) - return CACHE_ON; - else - return CACHE_OFF; -} - -void dcache_enable(void) -{ - unsigned int *I0, *I1; - unsigned int temp; - int i, j = 0; - - /* Before enable dcache, disable it first */ - dcache_disable(); - I0 = (unsigned int *)DCPLB_ADDR0; - I1 = (unsigned int *)DCPLB_DATA0; - - /* make sure the locked ones go in first */ - for (i = 0; i < page_descriptor_table_size; i++) { - if (CPLB_LOCK & dcplb_table[i][1]) { - debug("adding %02i %02i 0x%08x 0x%08x\n", i, j, - dcplb_table[i][0], dcplb_table[i][1]); - *I0++ = dcplb_table[i][0]; - *I1++ = dcplb_table[i][1]; - j++; - } else { - debug("skip %02i %02i 0x%08x 0x%08x\n", i, j, - dcplb_table[i][0], dcplb_table[i][1]); - } - } - - for (i = 0; i < page_descriptor_table_size; i++) { - if (!(CPLB_LOCK & dcplb_table[i][1])) { - debug("adding %02i %02i 0x%08x 0x%08x\n", i, j, - dcplb_table[i][0], dcplb_table[i][1]); - *I0++ = dcplb_table[i][0]; - *I1++ = dcplb_table[i][1]; - j++; - if (j == 16) { - break; - } - } - } - - /* Fill the rest with invalid entry */ - if (j <= 15) { - for (; j < 16; j++) { - debug("filling %i with 0", j); - *I1++ = 0x0; - } - } - - temp = *(unsigned int *)DMEM_CONTROL; - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)DMEM_CONTROL = - ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - SSYNC(); -} - -void dcache_disable(void) -{ - - unsigned int *I0, *I1; - int i; - - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)DMEM_CONTROL &= - ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - SSYNC(); - - /* after disable dcache, clear it so we don't confuse the next application */ - I0 = (unsigned int *)DCPLB_ADDR0; - I1 = (unsigned int *)DCPLB_DATA0; - - for (i = 0; i < 16; i++) { - *I0++ = 0x0; - *I1++ = 0x0; - } -} - -int dcache_status(void) -{ - unsigned int value; - value = *(unsigned int *)DMEM_CONTROL; - if (value & (ENDCPLB)) - return CACHE_ON; - else - return CACHE_OFF; -} diff --git a/cpu/bf561/cpu.h b/cpu/bf561/cpu.h deleted file mode 100644 index b6b73b1d8f..0000000000 --- a/cpu/bf561/cpu.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * U-boot - cpu.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _CPU_H_ -#define _CPU_H_ - -#include <command.h> - -#define INTERNAL_IRQS (32) -#define NUM_IRQ_NODES 16 -#define DEF_INTERRUPT_FLAGS 1 -#define MAX_TIM_LOAD 0xFFFFFFFF - -void blackfin_irq_panic(int reason, struct pt_regs *reg); -extern void dump(struct pt_regs *regs); -void display_excp(void); -asmlinkage void evt_nmi(void); -asmlinkage void evt_exception(void); -asmlinkage void trap(void); -asmlinkage void evt_ivhw(void); -asmlinkage void evt_rst(void); -asmlinkage void evt_timer(void); -asmlinkage void evt_evt7(void); -asmlinkage void evt_evt8(void); -asmlinkage void evt_evt9(void); -asmlinkage void evt_evt10(void); -asmlinkage void evt_evt11(void); -asmlinkage void evt_evt12(void); -asmlinkage void evt_evt13(void); -asmlinkage void evt_soft_int1(void); -asmlinkage void evt_system_call(void); -void blackfin_irq_panic(int reason, struct pt_regs *regs); -void blackfin_free_irq(unsigned int irq, void *dev_id); -void call_isr(int irq, struct pt_regs *fp); -void blackfin_do_irq(int vec, struct pt_regs *fp); -void blackfin_init_IRQ(void); -void blackfin_enable_irq(unsigned int irq); -void blackfin_disable_irq(unsigned int irq); -extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); -int blackfin_request_irq(unsigned int irq, - void (*handler) (int, void *, struct pt_regs *), - unsigned long flags, const char *devname, - void *dev_id); -void timer_init(void); -#endif diff --git a/cpu/bf561/flush.S b/cpu/bf561/flush.S deleted file mode 100644 index 0140a60c49..0000000000 --- a/cpu/bf561/flush.S +++ /dev/null @@ -1,402 +0,0 @@ -/* Copyright (C) 2003-2007 Analog Devices Inc. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. - */ - -#define ASSEMBLY - -#include <asm/linkage.h> -#include <asm/cplb.h> -#include <config.h> -#include <asm/blackfin.h> - -.text - -/* This is an external function being called by the user - * application through __flush_cache_all. Currently this function - * serves the purpose of flushing all the pending writes in - * in the instruction cache. - */ - -ENTRY(_flush_instruction_cache) - [--SP] = ( R7:6, P5:4 ); - LINK 12; - SP += -12; - P5.H = (ICPLB_ADDR0 >> 16); - P5.L = (ICPLB_ADDR0 & 0xFFFF); - P4.H = (ICPLB_DATA0 >> 16); - P4.L = (ICPLB_DATA0 & 0xFFFF); - R7 = CPLB_VALID | CPLB_L1_CHBL; - R6 = 16; -inext: R0 = [P5++]; - R1 = [P4++]; - [--SP] = RETS; - CALL _icplb_flush; /* R0 = page, R1 = data*/ - RETS = [SP++]; -iskip: R6 += -1; - CC = R6; - IF CC JUMP inext; - SSYNC; - SP += 12; - UNLINK; - ( R7:6, P5:4 ) = [SP++]; - RTS; - -/* This is an internal function to flush all pending - * writes in the cache associated with a particular ICPLB. - * - * R0 - page's start address - * R1 - CPLB's data field. - */ - -.align 2 -ENTRY(_icplb_flush) - [--SP] = ( R7:0, P5:0 ); - [--SP] = LC0; - [--SP] = LT0; - [--SP] = LB0; - [--SP] = LC1; - [--SP] = LT1; - [--SP] = LB1; - - /* If it's a 1K or 4K page, then it's quickest to - * just systematically flush all the addresses in - * the page, regardless of whether they're in the - * cache, or dirty. If it's a 1M or 4M page, there - * are too many addresses, and we have to search the - * cache for lines corresponding to the page. - */ - - CC = BITTST(R1, 17); /* 1MB or 4MB */ - IF !CC JUMP iflush_whole_page; - - /* We're only interested in the page's size, so extract - * this from the CPLB (bits 17:16), and scale to give an - * offset into the page_size and page_prefix tables. - */ - - R1 <<= 14; - R1 >>= 30; - R1 <<= 2; - - /* We can also determine the sub-bank used, because this is - * taken from bits 13:12 of the address. - */ - - R3 = ((12<<8)|2); /* Extraction pattern */ - nop; /*Anamoly 05000209*/ - R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/ - R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/ - - - /* So: - * R0 = Page start - * R1 = Page length (actually, offset into size/prefix tables) - * R3 = sub-bank deposit values - * - * The cache has 2 Ways, and 64 sets, so we iterate through - * the sets, accessing the tag for each Way, for our Bank and - * sub-bank, looking for dirty, valid tags that match our - * address prefix. - */ - - P5.L = (ITEST_COMMAND & 0xFFFF); - P5.H = (ITEST_COMMAND >> 16); - P4.L = (ITEST_DATA0 & 0xFFFF); - P4.H = (ITEST_DATA0 >> 16); - - P0.L = page_prefix_table; - P0.H = page_prefix_table; - P1 = R1; - R5 = 0; /* Set counter*/ - P0 = P1 + P0; - R4 = [P0]; /* This is the address prefix*/ - - /* We're reading (bit 1==0) the tag (bit 2==0), and we - * don't care about which double-word, since we're only - * fetching tags, so we only have to set Set, Bank, - * Sub-bank and Way. - */ - - P2 = 4; - LSETUP (ifs1, ife1) LC1 = P2; -ifs1: P0 = 32; /* iterate over all sets*/ - LSETUP (ifs0, ife0) LC0 = P0; -ifs0: R6 = R5 << 5; /* Combine set*/ - R6.H = R3.H << 0 ; /* and sub-bank*/ - [P5] = R6; /* Issue Command*/ - SSYNC; /* CSYNC will not work here :(*/ - R7 = [P4]; /* and read Tag.*/ - CC = BITTST(R7, 0); /* Check if valid*/ - IF !CC JUMP ifskip; /* and skip if not.*/ - - /* Compare against the page address. First, plant bits 13:12 - * into the tag, since those aren't part of the returned data. - */ - - R7 = DEPOSIT(R7, R3); /* set 13:12*/ - R1 = R7 & R4; /* Mask off lower bits*/ - CC = R1 == R0; /* Compare against page start.*/ - IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/ - - /* Tag address matches against page, so this is an entry - * we must flush. - */ - - R7 >>= 10; /* Mask off the non-address bits*/ - R7 <<= 10; - P3 = R7; - IFLUSH [P3]; /* And flush the entry*/ -ifskip: -ife0: R5 += 1; /* Advance to next Set*/ -ife1: NOP; - -ifinished: - SSYNC; /* Ensure the data gets out to mem.*/ - - /*Finished. Restore context.*/ - LB1 = [SP++]; - LT1 = [SP++]; - LC1 = [SP++]; - LB0 = [SP++]; - LT0 = [SP++]; - LC0 = [SP++]; - ( R7:0, P5:0 ) = [SP++]; - RTS; - -iflush_whole_page: - /* It's a 1K or 4K page, so quicker to just flush the - * entire page. - */ - - P1 = 32; /* For 1K pages*/ - P2 = P1 << 2; /* For 4K pages*/ - P0 = R0; /* Start of page*/ - CC = BITTST(R1, 16); /* Whether 1K or 4K*/ - IF CC P1 = P2; - P1 += -1; /* Unroll one iteration*/ - SSYNC; - IFLUSH [P0++]; /* because CSYNC can't end loops.*/ - LSETUP (isall, ieall) LC0 = P1; -isall:IFLUSH [P0++]; -ieall: NOP; - SSYNC; - JUMP ifinished; - -/* This is an external function being called by the user - * application through __flush_cache_all. Currently this function - * serves the purpose of flushing all the pending writes in - * in the data cache. - */ - -ENTRY(_flush_data_cache) - [--SP] = ( R7:6, P5:4 ); - LINK 12; - SP += -12; - P5.H = (DCPLB_ADDR0 >> 16); - P5.L = (DCPLB_ADDR0 & 0xFFFF); - P4.H = (DCPLB_DATA0 >> 16); - P4.L = (DCPLB_DATA0 & 0xFFFF); - R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z); - R6 = 16; -next: R0 = [P5++]; - R1 = [P4++]; - CC = BITTST(R1, 14); /* Is it write-through?*/ - IF CC JUMP skip; /* If so, ignore it.*/ - R2 = R1 & R7; /* Is it a dirty, cached page?*/ - CC = R2; - IF !CC JUMP skip; /* If not, ignore it.*/ - [--SP] = RETS; - CALL _dcplb_flush; /* R0 = page, R1 = data*/ - RETS = [SP++]; -skip: R6 += -1; - CC = R6; - IF CC JUMP next; - SSYNC; - SP += 12; - UNLINK; - ( R7:6, P5:4 ) = [SP++]; - RTS; - -/* This is an internal function to flush all pending - * writes in the cache associated with a particular DCPLB. - * - * R0 - page's start address - * R1 - CPLB's data field. - */ - -.align 2 -ENTRY(_dcplb_flush) - [--SP] = ( R7:0, P5:0 ); - [--SP] = LC0; - [--SP] = LT0; - [--SP] = LB0; - [--SP] = LC1; - [--SP] = LT1; - [--SP] = LB1; - - /* If it's a 1K or 4K page, then it's quickest to - * just systematically flush all the addresses in - * the page, regardless of whether they're in the - * cache, or dirty. If it's a 1M or 4M page, there - * are too many addresses, and we have to search the - * cache for lines corresponding to the page. - */ - - CC = BITTST(R1, 17); /* 1MB or 4MB */ - IF !CC JUMP dflush_whole_page; - - /* We're only interested in the page's size, so extract - * this from the CPLB (bits 17:16), and scale to give an - * offset into the page_size and page_prefix tables. - */ - - R1 <<= 14; - R1 >>= 30; - R1 <<= 2; - - /* The page could be mapped into Bank A or Bank B, depending - * on (a) whether both banks are configured as cache, and - * (b) on whether address bit A[x] is set. x is determined - * by DCBS in DMEM_CONTROL - */ - - R2 = 0; /* Default to Bank A (Bank B would be 1)*/ - - P0.L = (DMEM_CONTROL & 0xFFFF); - P0.H = (DMEM_CONTROL >> 16); - - R3 = [P0]; /* If Bank B is not enabled as cache*/ - CC = BITTST(R3, 2); /* then Bank A is our only option.*/ - IF CC JUMP bank_chosen; - - R4 = 1<<14; /* If DCBS==0, use A[14].*/ - R5 = R4 << 7; /* If DCBS==1, use A[23];*/ - CC = BITTST(R3, 4); - IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/ - R5 = R0 & R4; /* Use it to test the Page address*/ - CC = R5; /* and if that bit is set, we use Bank B,*/ - R2 = CC; /* else we use Bank A.*/ - R2 <<= 23; /* The Bank selection's at posn 23.*/ - -bank_chosen: - - /* We can also determine the sub-bank used, because this is - * taken from bits 13:12 of the address. - */ - - R3 = ((12<<8)|2); /* Extraction pattern */ - nop; /*Anamoly 05000209*/ - R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/ - /* Save in extraction pattern for later deposit.*/ - R3.H = R4.L << 0; - - /* So: - * R0 = Page start - * R1 = Page length (actually, offset into size/prefix tables) - * R2 = Bank select mask - * R3 = sub-bank deposit values - * - * The cache has 2 Ways, and 64 sets, so we iterate through - * the sets, accessing the tag for each Way, for our Bank and - * sub-bank, looking for dirty, valid tags that match our - * address prefix. - */ - - P5.L = (DTEST_COMMAND & 0xFFFF); - P5.H = (DTEST_COMMAND >> 16); - P4.L = (DTEST_DATA0 & 0xFFFF); - P4.H = (DTEST_DATA0 >> 16); - - P0.L = page_prefix_table; - P0.H = page_prefix_table; - P1 = R1; - R5 = 0; /* Set counter*/ - P0 = P1 + P0; - R4 = [P0]; /* This is the address prefix*/ - - - /* We're reading (bit 1==0) the tag (bit 2==0), and we - * don't care about which double-word, since we're only - * fetching tags, so we only have to set Set, Bank, - * Sub-bank and Way. - */ - - P2 = 2; - LSETUP (fs1, fe1) LC1 = P2; -fs1: P0 = 64; /* iterate over all sets*/ - LSETUP (fs0, fe0) LC0 = P0; -fs0: R6 = R5 << 5; /* Combine set*/ - R6.H = R3.H << 0 ; /* and sub-bank*/ - R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/ - BITSET(R6,14); - [P5] = R6; /* Issue Command*/ - SSYNC; - R7 = [P4]; /* and read Tag.*/ - CC = BITTST(R7, 0); /* Check if valid*/ - IF !CC JUMP fskip; /* and skip if not.*/ - CC = BITTST(R7, 1); /* Check if dirty*/ - IF !CC JUMP fskip; /* and skip if not.*/ - - /* Compare against the page address. First, plant bits 13:12 - * into the tag, since those aren't part of the returned data. - */ - - R7 = DEPOSIT(R7, R3); /* set 13:12*/ - R1 = R7 & R4; /* Mask off lower bits*/ - CC = R1 == R0; /* Compare against page start.*/ - IF !CC JUMP fskip; /* Skip it if it doesn't match.*/ - - /* Tag address matches against page, so this is an entry - * we must flush. - */ - - R7 >>= 10; /* Mask off the non-address bits*/ - R7 <<= 10; - P3 = R7; - SSYNC; - FLUSHINV [P3]; /* And flush the entry*/ -fskip: -fe0: R5 += 1; /* Advance to next Set*/ -fe1: BITSET(R2, 26); /* Go to next Way.*/ - -dfinished: - SSYNC; /* Ensure the data gets out to mem.*/ - - /*Finished. Restore context.*/ - LB1 = [SP++]; - LT1 = [SP++]; - LC1 = [SP++]; - LB0 = [SP++]; - LT0 = [SP++]; - LC0 = [SP++]; - ( R7:0, P5:0 ) = [SP++]; - RTS; - -dflush_whole_page: - - /* It's a 1K or 4K page, so quicker to just flush the - * entire page. - */ - - P1 = 32; /* For 1K pages*/ - P2 = P1 << 2; /* For 4K pages*/ - P0 = R0; /* Start of page*/ - CC = BITTST(R1, 16); /* Whether 1K or 4K*/ - IF CC P1 = P2; - P1 += -1; /* Unroll one iteration*/ - SSYNC; - FLUSHINV [P0++]; /* because CSYNC can't end loops.*/ - LSETUP (eall, eall) LC0 = P1; -eall: FLUSHINV [P0++]; - SSYNC; - JUMP dfinished; - -.align 4; -page_prefix_table: -.byte4 0xFFFFFC00; /* 1K */ -.byte4 0xFFFFF000; /* 4K */ -.byte4 0xFFF00000; /* 1M */ -.byte4 0xFFC00000; /* 4M */ -.page_prefix_table.end: diff --git a/cpu/bf561/init_sdram.S b/cpu/bf561/init_sdram.S deleted file mode 100644 index f5ccf30f9a..0000000000 --- a/cpu/bf561/init_sdram.S +++ /dev/null @@ -1,175 +0,0 @@ -#define ASSEMBLY - -#include <linux/config.h> -#include <config.h> -#include <asm/blackfin.h> -#include <asm/mem_init.h> -#include <asm/mach-common/bits/bootrom.h> -#include <asm/mach-common/bits/ebiu.h> -#include <asm/mach-common/bits/pll.h> -#include <asm/mach-common/bits/uart.h> -.global init_sdram; - -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif - -init_sdram: - [--SP] = ASTAT; - [--SP] = RETS; - [--SP] = (R7:0); - [--SP] = (P5:0); - - /* - * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable - */ - p0.h = hi(PLL_LOCKCNT); - p0.l = lo(PLL_LOCKCNT); - r0 = 0x300(Z); - w[p0] = r0.l; - ssync; - - /* - * Put SDRAM in self-refresh, incase anything is running - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITSET (R0, 24); - [P2] = R0; - SSYNC; - - /* - * Set PLL_CTL with the value that we calculate in R0 - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK - * - [7] = output delay (add 200ps of delay to mem signals) - * - [6] = input delay (add 200ps of input delay to mem signals) - * - [5] = PDWN : 1=All Clocks off - * - [3] = STOPCK : 1=Core Clock off - * - [1] = PLL_OFF : 1=Disable Power to PLL - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL - * all other bits set to zero - */ - - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ - r0 = r0 << 9; /* Shift it over, */ - r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */ - r0 = r1 | r0; - r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ - r1 = r1 << 8; /* Shift it over */ - r0 = r1 | r0; /* add them all together */ - - p0.h = hi(PLL_CTL); - p0.l = lo(PLL_CTL); /* Load the address */ - cli r2; /* Disable interrupts */ - ssync; - w[p0] = r0.l; /* Set the value */ - idle; /* Wait for the PLL to stablize */ - sti r2; /* Enable interrupts */ - -check_again: - p0.h = hi(PLL_STAT); - p0.l = lo(PLL_STAT); - R0 = W[P0](Z); - CC = BITTST(R0,5); - if ! CC jump check_again; - - /* Configure SCLK & CCLK Dividers */ - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); - p0.h = hi(PLL_DIV); - p0.l = lo(PLL_DIV); - w[p0] = r0.l; - ssync; - - /* - * We now are running at speed, time to set the Async mem bank wait states - * This will speed up execution, since we are normally running from FLASH. - */ - - p2.h = (EBIU_AMBCTL1 >> 16); - p2.l = (EBIU_AMBCTL1 & 0xFFFF); - r0.h = (AMBCTL1VAL >> 16); - r0.l = (AMBCTL1VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMBCTL0 >> 16); - p2.l = (EBIU_AMBCTL0 & 0xFFFF); - r0.h = (AMBCTL0VAL >> 16); - r0.l = (AMBCTL0VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMGCTL >> 16); - p2.l = (EBIU_AMGCTL & 0xffff); - r0 = AMGCTLVAL; - w[p2] = r0; - ssync; - - /* - * Now, Initialize the SDRAM, - * start with the SDRAM Refresh Rate Control Register - */ - p0.l = lo(EBIU_SDRRC); - p0.h = hi(EBIU_SDRRC); - r0 = mem_SDRRC; - w[p0] = r0.l; - ssync; - - /* - * SDRAM Memory Bank Control Register - bank specific parameters - */ - p0.l = (EBIU_SDBCTL & 0xFFFF); - p0.h = (EBIU_SDBCTL >> 16); - r0 = mem_SDBCTL; - w[p0] = r0.l; - ssync; - - /* - * SDRAM Global Control Register - global programmable parameters - * Disable self-refresh - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITCLR (R0, 24); - - /* - * Check if SDRAM is already powered up, if it is, enable self-refresh - */ - p0.h = hi(EBIU_SDSTAT); - p0.l = lo(EBIU_SDSTAT); - r2.l = w[p0]; - cc = bittst(r2,3); - if !cc jump skip; - NOP; - BITSET (R0, 23); -skip: - [P2] = R0; - SSYNC; - - /* Write in the new value in the register */ - R0.L = lo(mem_SDGCTL); - R0.H = hi(mem_SDGCTL); - [P2] = R0; - SSYNC; - nop; - - (P5:0) = [SP++]; - (R7:0) = [SP++]; - RETS = [SP++]; - ASTAT = [SP++]; - RTS; diff --git a/cpu/bf561/init_sdram_bootrom_initblock.S b/cpu/bf561/init_sdram_bootrom_initblock.S deleted file mode 100644 index 9cc5e78b04..0000000000 --- a/cpu/bf561/init_sdram_bootrom_initblock.S +++ /dev/null @@ -1,189 +0,0 @@ -#define ASSEMBLY - -#include <linux/config.h> -#include <config.h> -#include <asm/blackfin.h> -#include <asm/mem_init.h> -#include <asm/mach-common/bits/bootrom.h> -#include <asm/mach-common/bits/ebiu.h> -#include <asm/mach-common/bits/pll.h> -#include <asm/mach-common/bits/uart.h> -.global init_sdram; - -#if (CONFIG_CCLK_DIV == 1) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 -#endif -#if (CONFIG_CCLK_DIV == 2) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 -#endif -#if (CONFIG_CCLK_DIV == 4) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 -#endif -#if (CONFIG_CCLK_DIV == 8) -#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 -#endif -#ifndef CONFIG_CCLK_ACT_DIV -#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly -#endif - -init_sdram: - [--SP] = ASTAT; - [--SP] = RETS; - [--SP] = (R7:0); - [--SP] = (P5:0); - - - p0.h = hi(SICA_IWR0); - p0.l = lo(SICA_IWR0); - r0.l = 0x1; - w[p0] = r0.l; - SSYNC; - - p0.h = hi(SPI_BAUD); - p0.l = lo(SPI_BAUD); - r0.l = CONFIG_SPI_BAUD_INITBLOCK; - w[p0] = r0.l; - SSYNC; - - /* - * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable - */ - p0.h = hi(PLL_LOCKCNT); - p0.l = lo(PLL_LOCKCNT); - r0 = 0x300(Z); - w[p0] = r0.l; - ssync; - - /* - * Put SDRAM in self-refresh, incase anything is running - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITSET (R0, 24); - [P2] = R0; - SSYNC; - - /* - * Set PLL_CTL with the value that we calculate in R0 - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK - * - [7] = output delay (add 200ps of delay to mem signals) - * - [6] = input delay (add 200ps of input delay to mem signals) - * - [5] = PDWN : 1=All Clocks off - * - [3] = STOPCK : 1=Core Clock off - * - [1] = PLL_OFF : 1=Disable Power to PLL - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL - * all other bits set to zero - */ - - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ - r0 = r0 << 9; /* Shift it over, */ - r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */ - r0 = r1 | r0; - r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ - r1 = r1 << 8; /* Shift it over */ - r0 = r1 | r0; /* add them all together */ - - p0.h = hi(PLL_CTL); - p0.l = lo(PLL_CTL); /* Load the address */ - cli r2; /* Disable interrupts */ - ssync; - w[p0] = r0.l; /* Set the value */ - idle; /* Wait for the PLL to stablize */ - sti r2; /* Enable interrupts */ - -check_again: - p0.h = hi(PLL_STAT); - p0.l = lo(PLL_STAT); - R0 = W[P0](Z); - CC = BITTST(R0,5); - if ! CC jump check_again; - - /* Configure SCLK & CCLK Dividers */ - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); - p0.h = hi(PLL_DIV); - p0.l = lo(PLL_DIV); - w[p0] = r0.l; - ssync; - - /* - * We now are running at speed, time to set the Async mem bank wait states - * This will speed up execution, since we are normally running from FLASH. - */ - - p2.h = (EBIU_AMBCTL1 >> 16); - p2.l = (EBIU_AMBCTL1 & 0xFFFF); - r0.h = (AMBCTL1VAL >> 16); - r0.l = (AMBCTL1VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMBCTL0 >> 16); - p2.l = (EBIU_AMBCTL0 & 0xFFFF); - r0.h = (AMBCTL0VAL >> 16); - r0.l = (AMBCTL0VAL & 0xFFFF); - [p2] = r0; - ssync; - - p2.h = (EBIU_AMGCTL >> 16); - p2.l = (EBIU_AMGCTL & 0xffff); - r0 = AMGCTLVAL; - w[p2] = r0; - ssync; - - /* - * Now, Initialize the SDRAM, - * start with the SDRAM Refresh Rate Control Register - */ - p0.l = lo(EBIU_SDRRC); - p0.h = hi(EBIU_SDRRC); - r0 = mem_SDRRC; - w[p0] = r0.l; - ssync; - - /* - * SDRAM Memory Bank Control Register - bank specific parameters - */ - p0.l = (EBIU_SDBCTL & 0xFFFF); - p0.h = (EBIU_SDBCTL >> 16); - r0 = mem_SDBCTL; - w[p0] = r0.l; - ssync; - - /* - * SDRAM Global Control Register - global programmable parameters - * Disable self-refresh - */ - P2.H = hi(EBIU_SDGCTL); - P2.L = lo(EBIU_SDGCTL); - R0 = [P2]; - BITCLR (R0, 24); - - /* - * Check if SDRAM is already powered up, if it is, enable self-refresh - */ - p0.h = hi(EBIU_SDSTAT); - p0.l = lo(EBIU_SDSTAT); - r2.l = w[p0]; - cc = bittst(r2,3); - if !cc jump skip; - NOP; - BITSET (R0, 23); -skip: - [P2] = R0; - SSYNC; - - /* Write in the new value in the register */ - R0.L = lo(mem_SDGCTL); - R0.H = hi(mem_SDGCTL); - [P2] = R0; - SSYNC; - nop; - - - (P5:0) = [SP++]; - (R7:0) = [SP++]; - RETS = [SP++]; - ASTAT = [SP++]; - RTS; diff --git a/cpu/bf561/interrupt.S b/cpu/bf561/interrupt.S deleted file mode 100644 index a10eaabe54..0000000000 --- a/cpu/bf561/interrupt.S +++ /dev/null @@ -1,244 +0,0 @@ -/* - * U-boot - interrupt.S Processing of interrupts and exception handling - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on interrupt.S - * - * Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com> - * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca> - * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, - * Kenneth Albanowski <kjahds@kjahds.com>, - * The Silver Hammer Group, Ltd. - * - * (c) 1995, Dionne & Associates - * (c) 1995, DKG Display Tech. - * - * This file is also based on exception.asm - * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#define ASSEMBLY -#include <config.h> -#include <asm/blackfin.h> -#include <asm/entry.h> - -.global _blackfin_irq_panic; - -.text -.align 2 - -#ifndef CONFIG_KGDB -.global _evt_emulation -_evt_emulation: - SAVE_CONTEXT - r0 = 0; - r1 = seqstat; - sp += -12; - call _blackfin_irq_panic; - sp += 12; - rte; -#endif - -.global _evt_nmi -_evt_nmi: - SAVE_CONTEXT - r0 = 2; - r1 = RETN; - sp += -12; - call _blackfin_irq_panic; - sp += 12; - -_evt_nmi_exit: - rtn; - -.global _trap -_trap: - SAVE_ALL_SYS - r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ - sp += -12; - call _trap_c - sp += 12; - RESTORE_ALL_SYS - rtx; - -.global _evt_rst -_evt_rst: - SAVE_CONTEXT - r0 = 1; - r1 = RETN; - sp += -12; - call _do_reset; - sp += 12; - -_evt_rst_exit: - rtn; - -irq_panic: - r0 = 3; - r1 = sp; - sp += -12; - call _blackfin_irq_panic; - sp += 12; - -.global _evt_ivhw -_evt_ivhw: - SAVE_CONTEXT - RAISE 14; - -_evt_ivhw_exit: - rti; - -.global _evt_timer -_evt_timer: - SAVE_CONTEXT - r0 = 6; - sp += -12; - /* Polling method used now. */ - /* call timer_int; */ - sp += 12; - RESTORE_CONTEXT - rti; - nop; - -.global _evt_evt7 -_evt_evt7: - SAVE_CONTEXT - r0 = 7; - sp += -12; - call _process_int; - sp += 12; - -evt_evt7_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt8 -_evt_evt8: - SAVE_CONTEXT - r0 = 8; - sp += -12; - call _process_int; - sp += 12; - -evt_evt8_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt9 -_evt_evt9: - SAVE_CONTEXT - r0 = 9; - sp += -12; - call _process_int; - sp += 12; - -evt_evt9_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt10 -_evt_evt10: - SAVE_CONTEXT - r0 = 10; - sp += -12; - call _process_int; - sp += 12; - -evt_evt10_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt11 -_evt_evt11: - SAVE_CONTEXT - r0 = 11; - sp += -12; - call _process_int; - sp += 12; - -evt_evt11_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt12 -_evt_evt12: - SAVE_CONTEXT - r0 = 12; - sp += -12; - call _process_int; - sp += 12; -evt_evt12_exit: - RESTORE_CONTEXT - rti; - -.global _evt_evt13 -_evt_evt13: - SAVE_CONTEXT - r0 = 13; - sp += -12; - call _process_int; - sp += 12; - -evt_evt13_exit: - RESTORE_CONTEXT - rti; - -.global _evt_system_call -_evt_system_call: - [--sp] = r0; - [--SP] = RETI; - r0 = [sp++]; - r0 += 2; - [--sp] = r0; - RETI = [SP++]; - r0 = [SP++]; - SAVE_CONTEXT - sp += -12; - call _exception_handle; - sp += 12; - RESTORE_CONTEXT - RTI; - -evt_system_call_exit: - rti; - -.global _evt_soft_int1 -_evt_soft_int1: - [--sp] = r0; - [--SP] = RETI; - r0 = [sp++]; - r0 += 2; - [--sp] = r0; - RETI = [SP++]; - r0 = [SP++]; - SAVE_CONTEXT - sp += -12; - call _exception_handle; - sp += 12; - RESTORE_CONTEXT - RTI; - -evt_soft_int1_exit: - rti; diff --git a/cpu/bf561/ints.c b/cpu/bf561/ints.c deleted file mode 100644 index d6aa393170..0000000000 --- a/cpu/bf561/ints.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * U-boot - ints.c Interrupt related routines - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on ints.c - * - * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin - * drivers - * - * Copyright 1996 Roman Zippel - * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org> - * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> - * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> - * Copyright 2003 Metrowerks/Motorola - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <linux/stddef.h> -#include <asm/system.h> -#include <asm/traps.h> -#include <asm/io.h> -#include <asm/errno.h> -#include <asm/blackfin.h> -#include "cpu.h" - -void blackfin_irq_panic(int reason, struct pt_regs *regs) -{ - printf("\n\nException: IRQ 0x%x entered\n", reason); - printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f)); - printf("stack frame=0x%x, ", (unsigned int)regs); - printf("bad PC=0x%04x\n", (unsigned int)regs->pc); - dump(regs); - printf("Unhandled IRQ or exceptions!\n"); - printf("Please reset the board \n"); -} - -void blackfin_init_IRQ(void) -{ - *(unsigned volatile long *)(SICA_IMASK0) = 0; -#ifndef CONFIG_KGDB - *(unsigned volatile long *)(EVT1) = 0x0; -#endif - *(unsigned volatile long *)(EVT2) = - (unsigned volatile long)evt_nmi; - *(unsigned volatile long *)(EVT3) = - (unsigned volatile long)trap; - *(unsigned volatile long *)(EVT5) = - (unsigned volatile long)evt_ivhw; - *(unsigned volatile long *)(EVT0) = - (unsigned volatile long)evt_rst; - *(unsigned volatile long *)(EVT6) = - (unsigned volatile long)evt_timer; - *(unsigned volatile long *)(EVT7) = - (unsigned volatile long)evt_evt7; - *(unsigned volatile long *)(EVT8) = - (unsigned volatile long)evt_evt8; - *(unsigned volatile long *)(EVT9) = - (unsigned volatile long)evt_evt9; - *(unsigned volatile long *)(EVT10) = - (unsigned volatile long)evt_evt10; - *(unsigned volatile long *)(EVT11) = - (unsigned volatile long)evt_evt11; - *(unsigned volatile long *)(EVT12) = - (unsigned volatile long)evt_evt12; - *(unsigned volatile long *)(EVT13) = - (unsigned volatile long)evt_evt13; - *(unsigned volatile long *)(EVT14) = - (unsigned volatile long)evt_system_call; - *(unsigned volatile long *)(EVT15) = - (unsigned volatile long)evt_soft_int1; - *(volatile unsigned long *)ILAT = 0; - asm("csync;"); - *(volatile unsigned long *)IMASK = 0xffbf; - asm("csync;"); -} - -void exception_handle(void) -{ -#if defined (CONFIG_PANIC_HANG) - display_excp(); -#else - udelay(100000); /* allow messages to go out */ - do_reset(NULL, 0, 0, NULL); -#endif -} - -void display_excp(void) -{ - printf("Exception!\n"); -} diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c deleted file mode 100644 index a398fd5f84..0000000000 --- a/cpu/bf561/serial.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * U-boot - serial.c Serial driver for BF561 - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART. - * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>, - * BuyWays B.V. (www.buyways.nl) - * - * Based heavily on blkfinserial.c - * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs. - * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com> - * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com> - * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com> - * - * Based on code from 68328 version serial driver imlpementation which was: - * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu> - * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com> - * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org> - * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <asm/system.h> -#include <asm/bitops.h> -#include <asm/delay.h> -#include "serial.h" -#include <asm/io.h> -#include <asm/mach-common/bits/uart.h> - -DECLARE_GLOBAL_DATA_PTR; - -unsigned long pll_div_fact; - -void calc_baud(void) -{ - unsigned char i; - int temp; - u_long sclk = get_sclk(); - - for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) { - temp = sclk / (baud_table[i] * 8); - if ((temp & 0x1) == 1) { - temp++; - } - temp = temp / 2; - hw_baud_table[i].dl_high = (temp >> 8) & 0xFF; - hw_baud_table[i].dl_low = (temp) & 0xFF; - } -} - -void serial_setbrg(void) -{ - int i; - - calc_baud(); - - for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) { - if (gd->baudrate == baud_table[i]) - break; - } - - /* Enable UART */ - *pUART_GCTL |= UCEN; - SSYNC(); - - /* Set DLAB in LCR to Access DLL and DLH */ - ACCESS_LATCH; - SSYNC(); - - *pUART_DLL = hw_baud_table[i].dl_low; - SSYNC(); - *pUART_DLH = hw_baud_table[i].dl_high; - SSYNC(); - - /* Clear DLAB in LCR to Access THR RBR IER */ - ACCESS_PORT_IER; - SSYNC(); - - /* - * Enable ERBFI and ELSI interrupts - * to poll SIC_ISR register - */ - *pUART_IER = ELSI | ERBFI | ETBEI; - SSYNC(); - - /* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = WLS_8; - SSYNC(); - - return; -} - -int serial_init(void) -{ - serial_setbrg(); - return (0); -} - -void serial_putc(const char c) -{ - if ((*pUART_LSR) & TEMT) { - if (c == '\n') - serial_putc('\r'); - - local_put_char(c); - } - - while (!((*pUART_LSR) & TEMT)) - SYNC_ALL; - - return; -} - -int serial_tstc(void) -{ - if (*pUART_LSR & DR) - return 1; - else - return 0; -} - -int serial_getc(void) -{ - unsigned short uart_lsr_val, uart_rbr_val; - unsigned long isr_val; - int ret; - - /* Poll for RX Interrupt */ - while (!serial_tstc()) - continue; - asm("csync;"); - - uart_lsr_val = *pUART_LSR; /* Clear status bit */ - uart_rbr_val = *pUART_RBR; /* getc() */ - - if (uart_lsr_val & (OE|PE|FE|BI)) { - ret = -1; - } else { - ret = uart_rbr_val & 0xff; - } - - return ret; -} - -void serial_puts(const char *s) -{ - while (*s) { - serial_putc(*s++); - } -} - -static void local_put_char(char ch) -{ - int flags = 0; - unsigned long isr_val; - - /* Poll for TX Interruput */ - while (!(*pUART_LSR & THRE)) - continue; - asm("csync;"); - - *pUART_THR = ch; /* putc() */ - - return; -} diff --git a/cpu/bf561/serial.h b/cpu/bf561/serial.h deleted file mode 100644 index 647560c35c..0000000000 --- a/cpu/bf561/serial.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * U-boot - bf561_serial.h Serial Driver defines - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver. - * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl> - * BuyWays B.V. (www.buyways.nl) - * - * Based heavily on: - * blkfinserial.h: Definitions for the BlackFin DSP serial driver. - * - * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com - * Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com> - * - * Based on code from 68328serial.c which was: - * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu> - * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com> - * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org> - * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _Bf561_SERIAL_H -#define _Bf561_SERIAL_H - -#include <linux/config.h> -#include <asm/blackfin.h> - -#define SYNC_ALL __asm__ __volatile__ ("ssync;\n") -#define ACCESS_LATCH *pUART_LCR |= DLAB; -#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB); - -void serial_setbrg(void); -static void local_put_char(char ch); -void calc_baud(void); -void serial_setbrg(void); -int serial_init(void); -void serial_putc(const char c); -int serial_tstc(void); -int serial_getc(void); -void serial_puts(const char *s); -static void local_put_char(char ch); - -int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 }; - -struct { - unsigned char dl_high; - unsigned char dl_low; -} hw_baud_table[5]; - -#ifdef CONFIG_STAMP -extern unsigned long pll_div_fact; -#endif - -#endif diff --git a/cpu/bf561/start.S b/cpu/bf561/start.S deleted file mode 100644 index 6565de8cfd..0000000000 --- a/cpu/bf561/start.S +++ /dev/null @@ -1,303 +0,0 @@ -/* - * U-boot - start.S Startup file of u-boot for BF533/BF561 - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on head.S - * Copyright (c) 2003 Metrowerks/Motorola - * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, - * Kenneth Albanowski <kjahds@kjahds.com>, - * The Silver Hammer Group, Ltd. - * (c) 1995, Dionne & Associates - * (c) 1995, DKG Display Tech. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* - * Note: A change in this file subsequently requires a change in - * board/$(board_name)/config.mk for a valid u-boot.bin - */ - -#define ASSEMBLY - -#include <linux/config.h> -#include <config.h> -#include <asm/blackfin.h> - -#include <asm/mach-common/bits/core.h> -#include <asm/mach-common/bits/dma.h> -#include <asm/mach-common/bits/pll.h> - -.global _stext; -.global __bss_start; -.global start; -.global _start; -.global edata; -.global _exit; -.global init_sdram; - -.text -_start: -start: -_stext: - - R0 = 0x32; - SYSCFG = R0; - SSYNC; - - /* - * As per HW reference manual DAG registers, - * DATA and Address resgister shall be zero'd - * in initialization, after a reset state - */ - r1 = 0; /* Data registers zero'd */ - r2 = 0; - r3 = 0; - r4 = 0; - r5 = 0; - r6 = 0; - r7 = 0; - - p0 = 0; /* Address registers zero'd */ - p1 = 0; - p2 = 0; - p3 = 0; - p4 = 0; - p5 = 0; - - i0 = 0; /* DAG Registers zero'd */ - i1 = 0; - i2 = 0; - i3 = 0; - m0 = 0; - m1 = 0; - m3 = 0; - m3 = 0; - l0 = 0; - l1 = 0; - l2 = 0; - l3 = 0; - b0 = 0; - b1 = 0; - b2 = 0; - b3 = 0; - - /* - * Set loop counters to zero, to make sure that - * hw loops are disabled. - */ - r0 = 0; - lc0 = r0; - lc1 = r0; - - SSYNC; - - /* Check soft reset status */ - p0.h = SWRST >> 16; - p0.l = SWRST & 0xFFFF; - r0.l = w[p0]; - - cc = bittst(r0, 15); - if !cc jump no_soft_reset; - - /* Clear Soft reset */ - r0 = 0x0000; - w[p0] = r0; - ssync; - -no_soft_reset: - nop; - - /* Clear EVT registers */ - p0.h = (EVT0 >> 16); - p0.l = (EVT0 & 0xFFFF); - p0 += 8; - p1 = 14; - r1 = 0; - LSETUP(4,4) lc0 = p1; - [ p0 ++ ] = r1; - - p0.h = hi(SICA_IWR0); - p0.l = lo(SICA_IWR0); - r0.l = 0x1; - w[p0] = r0.l; - SSYNC; - - sp.l = (0xffb01000 & 0xFFFF); - sp.h = (0xffb01000 >> 16); - - /* - * Check if the code is in SDRAM - * If the code is in SDRAM, skip SDRAM initializaiton - */ - call get_pc; - r3.l = 0x0; - r3.h = 0x2000; - cc = r0 < r3 (iu); - if cc jump sdram_initialized; - call init_sdram; - /* relocate into to RAM */ -sdram_initialized: - call get_pc; -offset: - r2.l = offset; - r2.h = offset; - r3.l = start; - r3.h = start; - r1 = r2 - r3; - - r0 = r0 - r1; - p1 = r0; - - p2.l = (CFG_MONITOR_BASE & 0xffff); - p2.h = (CFG_MONITOR_BASE >> 16); - - p3 = 0x04; - p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff); - p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16); -loop1: - r1 = [p1 ++ p3]; - [p2 ++ p3] = r1; - cc=p2==p4; - if !cc jump loop1; - /* - * configure STACK - */ - r0.h = (CONFIG_STACKBASE >> 16); - r0.l = (CONFIG_STACKBASE & 0xFFFF); - sp = r0; - fp = sp; - - /* - * This next section keeps the processor in supervisor mode - * during kernel boot. Switches to user mode at end of boot. - * See page 3-9 of Hardware Reference manual for documentation. - */ - - /* To keep ourselves in the supervisor mode */ - p0.l = (EVT15 & 0xFFFF); - p0.h = (EVT15 >> 16); - - p1.l = _real_start; - p1.h = _real_start; - [p0] = p1; - - p0.l = (IMASK & 0xFFFF); - p0.h = (IMASK >> 16); - r0.l = LO(EVT_IVG15); - r0.h = HI(EVT_IVG15); - [p0] = r0; - raise 15; - p0.l = WAIT_HERE; - p0.h = WAIT_HERE; - reti = p0; - rti; - -WAIT_HERE: - jump WAIT_HERE; - -.global _real_start; -_real_start: - [ -- sp ] = reti; - - /* DMA reset code to Hi of L1 SRAM */ -copy: - P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */ - P1.L = lo(SYSMMR_BASE); - - R0.H = reset_start; /* Source Address (high) */ - R0.L = reset_start; /* Source Address (low) */ - R1.H = reset_end; - R1.L = reset_end; - R2 = R1 - R0; /* Count */ - R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ - R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ - R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ - R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ - -DMA: - R6 = 0x1 (Z); - W[P1+OFFSET_(IMDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ - W[P1+OFFSET_(IMDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ - - [P1+OFFSET_(IMDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ - W[P1+OFFSET_(IMDMA_S0_X_COUNT)] = R2; /* Set Source Count */ - /* Set Source DMAConfig = DMA Enable, - Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ - W[P1+OFFSET_(IMDMA_S0_CONFIG)] = R3; - - [P1+OFFSET_(IMDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ - W[P1+OFFSET_(IMDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ - /* Set Destination DMAConfig = DMA Enable, - Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ - W[P1+OFFSET_(IMDMA_D0_CONFIG)] = R4; - -WAIT_DMA_DONE: - p0.h = hi(IMDMA_D0_IRQ_STATUS); - p0.l = lo(IMDMA_D0_IRQ_STATUS); - R0 = W[P0](Z); - CC = BITTST(R0, 0); - if ! CC jump WAIT_DMA_DONE - - R0 = 0x1; - W[P1+OFFSET_(IMDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ - - /* Initialize BSS Section with 0 s */ - p1.l = __bss_start; - p1.h = __bss_start; - p2.l = _end; - p2.h = _end; - r1 = p1; - r2 = p2; - r3 = r2 - r1; - r3 = r3 >> 2; - p3 = r3; - lsetup (_clear_bss, _clear_bss_end ) lc1 = p3; - CC = p2<=p1; - if CC jump _clear_bss_skip; - r0 = 0; -_clear_bss: -_clear_bss_end: - [p1++] = r0; -_clear_bss_skip: - - p0.l = _start1; - p0.h = _start1; - jump (p0); - -reset_start: - p0.h = WDOG_CNT >> 16; - p0.l = WDOG_CNT & 0xffff; - r0 = 0x0010; - w[p0] = r0; - p0.h = WDOG_CTL >> 16; - p0.l = WDOG_CTL & 0xffff; - r0 = 0x0000; - w[p0] = r0; -reset_wait: - jump reset_wait; - -reset_end: nop; - -_exit: - jump.s _exit; -get_pc: - r0 = rets; - rts; diff --git a/cpu/bf561/traps.c b/cpu/bf561/traps.c deleted file mode 100644 index e35620c9ae..0000000000 --- a/cpu/bf561/traps.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * U-boot - traps.c Routines related to interrupts and exceptions - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * This file is based on - * No original Copyright holder listed, - * Probabily original (C) Roman Zippel (assigned DJD, 1999) - * - * Copyright 2003 Metrowerks - for Blackfin - * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca> - * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org> - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <common.h> -#include <linux/types.h> -#include <asm/errno.h> -#include <asm/system.h> -#include <asm/traps.h> -#include "cpu.h" -#include <asm/cplb.h> -#include <asm/io.h> -#include <asm/mach-common/bits/core.h> -#include <asm/mach-common/bits/mpu.h> - -void init_IRQ(void) -{ - blackfin_init_IRQ(); - return; -} - -void process_int(unsigned long vec, struct pt_regs *fp) -{ - printf("interrupt\n"); - return; -} - -extern unsigned int icplb_table[page_descriptor_table_size][2]; -extern unsigned int dcplb_table[page_descriptor_table_size][2]; - -unsigned long last_cplb_fault_retx; - -static unsigned int cplb_sizes[4] = - { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 }; - -void trap_c(struct pt_regs *regs) -{ - unsigned int addr; - unsigned long trapnr = (regs->seqstat) & EXCAUSE; - unsigned int i, j, size, *I0, *I1; - unsigned short data = 0; - - switch (trapnr) { - /* 0x26 - Data CPLB Miss */ - case VEC_CPLB_M: - -#if ANOMALY_05000261 - /* - * Work around an anomaly: if we see a new DCPLB fault, return - * without doing anything. Then, if we get the same fault again, - * handle it. - */ - addr = last_cplb_fault_retx; - last_cplb_fault_retx = regs->retx; - printf("this time, curr = 0x%08x last = 0x%08x\n", addr, - last_cplb_fault_retx); - if (addr != last_cplb_fault_retx) - goto trap_c_return; -#endif - data = 1; - - case VEC_CPLB_I_M: - - if (data) - addr = *pDCPLB_FAULT_ADDR; - else - addr = *pICPLB_FAULT_ADDR; - - for (i = 0; i < page_descriptor_table_size; i++) { - if (data) { - size = cplb_sizes[dcplb_table[i][1] >> 16]; - j = dcplb_table[i][0]; - } else { - size = cplb_sizes[icplb_table[i][1] >> 16]; - j = icplb_table[i][0]; - } - if ((j <= addr) && ((j + size) > addr)) { - debug("found %i 0x%08x\n", i, j); - break; - } - } - if (i == page_descriptor_table_size) { - printf("something is really wrong\n"); - do_reset(NULL, 0, 0, NULL); - } - - /* Turn the cache off */ - if (data) { - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)DMEM_CONTROL &= - ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - SSYNC(); - } else { - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - SSYNC(); - } - - if (data) { - I0 = (unsigned int *)DCPLB_ADDR0; - I1 = (unsigned int *)DCPLB_DATA0; - } else { - I0 = (unsigned int *)ICPLB_ADDR0; - I1 = (unsigned int *)ICPLB_DATA0; - } - - j = 0; - while (*I1 & CPLB_LOCK) { - debug("skipping %i %08p - %08x\n", j, I1, *I1); - *I0++; - *I1++; - j++; - } - - debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1); - - for (; j < 15; j++) { - debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1); - *I0++ = *(I0 + 1); - *I1++ = *(I1 + 1); - } - - if (data) { - *I0 = dcplb_table[i][0]; - *I1 = dcplb_table[i][1]; - I0 = (unsigned int *)DCPLB_ADDR0; - I1 = (unsigned int *)DCPLB_DATA0; - } else { - *I0 = icplb_table[i][0]; - *I1 = icplb_table[i][1]; - I0 = (unsigned int *)ICPLB_ADDR0; - I1 = (unsigned int *)ICPLB_DATA0; - } - - for (j = 0; j < 16; j++) { - debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++); - } - - /* Turn the cache back on */ - if (data) { - j = *(unsigned int *)DMEM_CONTROL; - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)DMEM_CONTROL = - ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; - SSYNC(); - } else { - SSYNC(); - asm(" .align 8; "); - *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - SSYNC(); - } - - break; - default: - /* All traps come here */ - printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f)); - printf("stack frame=0x%x, ", (unsigned int)regs); - printf("bad PC=0x%04x\n", (unsigned int)regs->pc); - dump(regs); - printf("\n\n"); - - printf("Unhandled IRQ or exceptions!\n"); - printf("Please reset the board \n"); - do_reset(NULL, 0, 0, NULL); - } - -trap_c_return: - return; - -} - -void dump(struct pt_regs *fp) -{ - debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n", fp->rete, - fp->retn, fp->retx, fp->rets); - debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg); - debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp); - debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n", fp->r0, - fp->r1, fp->r2, fp->r3); - debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", fp->r4, - fp->r5, fp->r6, fp->r7); - debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n", fp->p0, - fp->p1, fp->p2, fp->p3); - debug("P4: %08lx P5: %08lx FP: %08lx\n", fp->p4, fp->p5, fp->fp); - debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", - fp->a0w, fp->a0x, fp->a1w, fp->a1x); - - debug("LB0: %08lx LT0: %08lx LC0: %08lx\n", fp->lb0, fp->lt0, - fp->lc0); - debug("LB1: %08lx LT1: %08lx LC1: %08lx\n", fp->lb1, fp->lt1, - fp->lc1); - debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n", fp->b0, fp->l0, - fp->m0, fp->i0); - debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n", fp->b1, fp->l1, - fp->m1, fp->i1); - debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n", fp->b2, fp->l2, - fp->m2, fp->i2); - debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n", fp->b3, fp->l3, - fp->m3, fp->i3); - - debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR); - debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR); - -} diff --git a/cpu/bf561/video.c b/cpu/bf561/video.c deleted file mode 100644 index 3ff0151d48..0000000000 --- a/cpu/bf561/video.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * (C) Copyright 2002 - * Wolfgang Denk, wd@denx.de - * (C) Copyright 2006 - * Aubrey Li, aubrey.li@analog.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <stdarg.h> -#include <common.h> -#include <config.h> -#include <asm/blackfin.h> -#include <i2c.h> -#include <linux/types.h> -#include <devices.h> - -#ifdef CONFIG_VIDEO -#define NTSC_FRAME_ADDR 0x06000000 -#include "video.h" - -/* NTSC OUTPUT SIZE 720 * 240 */ -#define VERTICAL 2 -#define HORIZONTAL 4 - -int is_vblank_line(const int line) -{ - /* - * This array contains a single bit for each line in - * an NTSC frame. - */ - if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528)) - return true; - - return false; -} - -int NTSC_framebuffer_init(char *base_address) -{ - const int NTSC_frames = 1; - const int NTSC_lines = 525; - char *dest = base_address; - int frame_num, line_num; - - for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) { - for (line_num = 1; line_num <= NTSC_lines; ++line_num) { - unsigned int code; - int offset = 0; - int i; - - if (is_vblank_line(line_num)) - offset++; - - if (line_num > 266 || line_num < 3) - offset += 2; - - /* Output EAV code */ - code = SystemCodeMap[offset].EAV; - write_dest_byte((char)(code >> 24) & 0xff); - write_dest_byte((char)(code >> 16) & 0xff); - write_dest_byte((char)(code >> 8) & 0xff); - write_dest_byte((char)(code) & 0xff); - - /* Output horizontal blanking */ - for (i = 0; i < 67 * 2; ++i) { - write_dest_byte(0x80); - write_dest_byte(0x10); - } - - /* Output SAV */ - code = SystemCodeMap[offset].SAV; - write_dest_byte((char)(code >> 24) & 0xff); - write_dest_byte((char)(code >> 16) & 0xff); - write_dest_byte((char)(code >> 8) & 0xff); - write_dest_byte((char)(code) & 0xff); - - /* Output empty horizontal data */ - for (i = 0; i < 360 * 2; ++i) { - write_dest_byte(0x80); - write_dest_byte(0x10); - } - } - } - - return dest - base_address; -} - -void fill_frame(char *Frame, int Value) -{ - int *OddPtr32; - int OddLine; - int *EvenPtr32; - int EvenLine; - int i; - int *data; - int m, n; - - /* fill odd and even frames */ - for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) { - OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276); - EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276); - for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) { - *OddPtr32 = Value; - *EvenPtr32 = Value; - } - } - - for (m = 0; m < VERTICAL; m++) { - data = (int *)u_boot_logo.data; - for (OddLine = (22 + m), EvenLine = (285 + m); - OddLine < (u_boot_logo.height * VERTICAL) + (22 + m); - OddLine += VERTICAL, EvenLine += VERTICAL) { - OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276); - EvenPtr32 = - (int *)((Frame + ((EvenLine) * 1716)) + 276); - for (i = 0; i < u_boot_logo.width / 2; i++) { - /* enlarge one pixel to m x n */ - for (n = 0; n < HORIZONTAL; n++) { - *OddPtr32++ = *data; - *EvenPtr32++ = *data; - } - data++; - } - } - } -} - -void video_putc(const char c) -{ -} - -void video_puts(const char *s) -{ -} - -static int video_init(void) -{ - char *NTSCFrame; - NTSCFrame = (char *)NTSC_FRAME_ADDR; - NTSC_framebuffer_init(NTSCFrame); - fill_frame(NTSCFrame, BLUE); - - *pPPI_CONTROL = 0x0082; - *pPPI_FRAME = 0x020D; - - *pDMA0_START_ADDR = NTSCFrame; - *pDMA0_X_COUNT = 0x035A; - *pDMA0_X_MODIFY = 0x0002; - *pDMA0_Y_COUNT = 0x020D; - *pDMA0_Y_MODIFY = 0x0002; - *pDMA0_CONFIG = 0x1015; - *pPPI_CONTROL = 0x0083; - return 0; -} - -int drv_video_init(void) -{ - int error, devices = 1; - - device_t videodev; - - video_init(); /* Video initialization */ - - memset(&videodev, 0, sizeof(videodev)); - - strcpy(videodev.name, "video"); - videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ - videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */ - videodev.putc = video_putc; /* 'putc' function */ - videodev.puts = video_puts; /* 'puts' function */ - - error = device_register(&videodev); - - return (error == 0) ? devices : error; -} -#endif diff --git a/cpu/bf561/video.h b/cpu/bf561/video.h deleted file mode 100644 index d237f6a3c7..0000000000 --- a/cpu/bf561/video.h +++ /dev/null @@ -1,25 +0,0 @@ -#include <video_logo.h> -#define write_dest_byte(val) {*dest++=val;} -#define BLACK (0x01800180) /* black pixel pattern */ -#define BLUE (0x296E29F0) /* blue pixel pattern */ -#define RED (0x51F0515A) /* red pixel pattern */ -#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */ -#define GREEN (0x91229136) /* green pixel pattern */ -#define CYAN (0xAA10AAA6) /* cyan pixel pattern */ -#define YELLOW (0xD292D210) /* yellow pixel pattern */ -#define WHITE (0xFE80FE80) /* white pixel pattern */ - -#define true 1 -#define false 0 - -typedef struct { - unsigned int SAV; - unsigned int EAV; -} SystemCodeType; - -const SystemCodeType SystemCodeMap[4] = { - {0xFF000080, 0xFF00009D}, - {0xFF0000AB, 0xFF0000B6}, - {0xFF0000C7, 0xFF0000DA}, - {0xFF0000EC, 0xFF0000F1} -}; diff --git a/cpu/blackfin/.gitignore b/cpu/blackfin/.gitignore new file mode 100644 index 0000000000..0ec9d5672e --- /dev/null +++ b/cpu/blackfin/.gitignore @@ -0,0 +1 @@ +bootrom-asm-offsets.[chs] diff --git a/cpu/blackfin/Makefile b/cpu/blackfin/Makefile new file mode 100644 index 0000000000..f194a38350 --- /dev/null +++ b/cpu/blackfin/Makefile @@ -0,0 +1,65 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Licensed under the GPL-2 or later. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +EXTRA := +CEXTRA := initcode.o +SEXTRA := start.o +SOBJS := interrupt.o cache.o flush.o +COBJS := cpu.o traps.o interrupts.o reset.o serial.o i2c.o watchdog.o + +ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) +COBJS += initcode.o +endif + +SRCS := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +EXTRA := $(addprefix $(obj),$(EXTRA)) +CEXTRA := $(addprefix $(obj),$(CEXTRA)) +SEXTRA := $(addprefix $(obj),$(SEXTRA)) + +all: $(obj).depend $(LIB) $(obj).depend $(EXTRA) $(CEXTRA) $(SEXTRA) check_initcode + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +$(OBJS): $(obj)bootrom-asm-offsets.h +$(obj)bootrom-asm-offsets.c: bootrom-asm-offsets.c.in bootrom-asm-offsets.awk + echo '#include <asm/mach-common/bits/bootrom.h>' | $(CPP) $(CPPFLAGS) - | gawk -f ./bootrom-asm-offsets.awk > $@.tmp + mv $@.tmp $@ +$(obj)bootrom-asm-offsets.s: $(obj)bootrom-asm-offsets.c + $(CC) $(CFLAGS) -S $^ -o $@.tmp + mv $@.tmp $@ +$(obj)bootrom-asm-offsets.h: $(obj)bootrom-asm-offsets.s + sed -ne "/^->/{s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; s:->::; p;}" $^ > $@ + +# make sure our initcode (which goes into LDR) does not +# have relocs or external references +READINIT = env LC_ALL=C $(CROSS_COMPILE)readelf -s $< +check_initcode: $(obj)initcode.o +ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) + @if $(READINIT) | grep '\<GLOBAL\>.*\<UND\>' ; then \ + echo "$< contains external references!" 1>&2 ; \ + exit 1 ; \ + fi +endif + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/blackfin/bootrom-asm-offsets.awk b/cpu/blackfin/bootrom-asm-offsets.awk new file mode 100755 index 0000000000..1d61824254 --- /dev/null +++ b/cpu/blackfin/bootrom-asm-offsets.awk @@ -0,0 +1,41 @@ +#!/usr/bin/gawk -f +BEGIN { + print "/* DO NOT EDIT: AUTOMATICALLY GENERATED" + print " * Input files: bootrom-asm-offsets.awk bootrom-asm-offsets.c.in" + print " * DO NOT EDIT: AUTOMATICALLY GENERATED" + print " */" + print "" + system("cat bootrom-asm-offsets.c.in") + print "{" +} + +{ + /* find a structure definition */ + if ($0 ~ /typedef struct .* {/) { + delete members; + i = 0; + + /* extract each member of the structure */ + while (1) { + getline + if ($1 == "}") + break; + gsub(/[*;]/, ""); + members[i++] = $NF; + } + + /* grab the structure's name */ + struct = $NF; + sub(/;$/, "", struct); + + /* output the DEFINE() macros */ + while (i-- > 0) + print "\tDEFINE(" struct ", " members[i] ");" + print "" + } +} + +END { + print "\treturn 0;" + print "}" +} diff --git a/cpu/blackfin/bootrom-asm-offsets.c.in b/cpu/blackfin/bootrom-asm-offsets.c.in new file mode 100644 index 0000000000..3146e46674 --- /dev/null +++ b/cpu/blackfin/bootrom-asm-offsets.c.in @@ -0,0 +1,12 @@ +/* A little trick taken from the kernel asm-offsets.h where we convert + * the C structures automatically into a bunch of defines for use in + * the assembly files. + */ + +#include <linux/stddef.h> +#include <asm/mach-common/bits/bootrom.h> + +#define _DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val)) +#define DEFINE(s, m) _DEFINE(offset_##s##_##m, offsetof(s, m)) + +int main(int argc, char *argv[]) diff --git a/cpu/blackfin/cache.S b/cpu/blackfin/cache.S new file mode 100644 index 0000000000..51bdb30e32 --- /dev/null +++ b/cpu/blackfin/cache.S @@ -0,0 +1,61 @@ +/* cache.S - low level cache handling routines + * Copyright (C) 2003-2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#include <asm/linkage.h> +#include <config.h> +#include <asm/blackfin.h> + +.text +.align 2 +ENTRY(_blackfin_icache_flush_range) + R2 = -32; + R2 = R0 & R2; + P0 = R2; + P1 = R1; + CSYNC; +1: + IFLUSH[P0++]; + CC = P0 < P1(iu); + IF CC JUMP 1b(bp); + IFLUSH[P0]; + SSYNC; + RTS; +ENDPROC(_blackfin_icache_flush_range) + +ENTRY(_blackfin_dcache_flush_range) + R2 = -32; + R2 = R0 & R2; + P0 = R2; + P1 = R1; + CSYNC; +1: + FLUSH[P0++]; + CC = P0 < P1(iu); + IF CC JUMP 1b(bp); + FLUSH[P0]; + SSYNC; + RTS; +ENDPROC(_blackfin_dcache_flush_range) + +ENTRY(_blackfin_dcache_invalidate_range) + R2 = -32; + R2 = R0 & R2; + P0 = R2; + P1 = R1; + CSYNC; +1: + FLUSHINV[P0++]; + CC = P0 < P1(iu); + IF CC JUMP 1b(bp); + + /* + * If the data crosses a cache line, then we'll be pointing to + * the last cache line, but won't have flushed/invalidated it yet, so do + * one more. + */ + FLUSHINV[P0]; + SSYNC; + RTS; +ENDPROC(_blackfin_dcache_invalidate_range) diff --git a/cpu/blackfin/cpu.c b/cpu/blackfin/cpu.c new file mode 100644 index 0000000000..53de5aba67 --- /dev/null +++ b/cpu/blackfin/cpu.c @@ -0,0 +1,141 @@ +/* + * U-boot - cpu.c CPU specific functions + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> +#include <asm/blackfin.h> +#include <asm/cplb.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/mpu.h> +#include <asm/mach-common/bits/trace.h> + +#include "cpu.h" +#include "serial.h" + +void icache_enable(void) +{ + bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() | (IMC | ENICPLB)); + SSYNC(); +} + +void icache_disable(void) +{ + bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() & ~(IMC | ENICPLB)); + SSYNC(); +} + +int icache_status(void) +{ + return bfin_read_IMEM_CONTROL() & ENICPLB; +} + +void dcache_enable(void) +{ + bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() | (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)); + SSYNC(); +} + +void dcache_disable(void) +{ + bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0)); + SSYNC(); +} + +int dcache_status(void) +{ + return bfin_read_DMEM_CONTROL() & ENDCPLB; +} + +__attribute__ ((__noreturn__)) +void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) +{ + /* Build a NOP slide over the LDR jump block. Whee! */ + serial_early_puts("NOP Slide\n"); + char nops[0xC]; + memset(nops, 0x00, sizeof(nops)); + extern char _stext_l1; + memcpy(&_stext_l1 - sizeof(nops), nops, sizeof(nops)); + + if (!loaded_from_ldr) { + /* Relocate sections into L1 if the LDR didn't do it -- don't + * check length because the linker script does the size + * checking at build time. + */ + serial_early_puts("L1 Relocate\n"); + extern char _stext_l1, _etext_l1, _stext_l1_lma; + memcpy(&_stext_l1, &_stext_l1_lma, (&_etext_l1 - &_stext_l1)); + extern char _sdata_l1, _edata_l1, _sdata_l1_lma; + memcpy(&_sdata_l1, &_sdata_l1_lma, (&_edata_l1 - &_sdata_l1)); + } +#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) + /* The BF537 bootrom will reset the EBIU_AMGCTL register on us + * after it has finished loading the LDR. So configure it again. + */ + else + bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); +#endif + +#ifdef CONFIG_DEBUG_DUMP + /* Turn on hardware trace buffer */ + bfin_write_TBUFCTL(TBUFPWR | TBUFEN); +#endif + +#ifndef CONFIG_PANIC_HANG + /* Reset upon a double exception rather than just hanging. + * Do not do bfin_read on SWRST as that will reset status bits. + */ + bfin_write_SWRST(DOUBLE_FAULT); +#endif + + serial_early_puts("Board init flash\n"); + board_init_f(bootflag); +} + +int exception_init(void) +{ + bfin_write_EVT3(trap); + return 0; +} + +int irq_init(void) +{ +#ifdef SIC_IMASK0 + bfin_write_SIC_IMASK0(0); + bfin_write_SIC_IMASK1(0); +# ifdef SIC_IMASK2 + bfin_write_SIC_IMASK2(0); +# endif +#elif defined(SICA_IMASK0) + bfin_write_SICA_IMASK0(0); + bfin_write_SICA_IMASK1(0); +#else + bfin_write_SIC_IMASK(0); +#endif + bfin_write_EVT2(evt_default); /* NMI */ + bfin_write_EVT5(evt_default); /* hardware error */ + bfin_write_EVT6(evt_default); /* core timer */ + bfin_write_EVT7(evt_default); + bfin_write_EVT8(evt_default); + bfin_write_EVT9(evt_default); + bfin_write_EVT10(evt_default); + bfin_write_EVT11(evt_default); + bfin_write_EVT12(evt_default); + bfin_write_EVT13(evt_default); + bfin_write_EVT14(evt_default); + bfin_write_EVT15(evt_default); + bfin_write_ILAT(0); + CSYNC(); + /* enable all interrupts except for core timer */ + irq_flags = 0xffffffbf; + local_irq_enable(); + CSYNC(); + return 0; +} diff --git a/cpu/bf561/start1.S b/cpu/blackfin/cpu.h index 6d4731b696..0a13c285e0 100644 --- a/cpu/bf561/start1.S +++ b/cpu/blackfin/cpu.h @@ -1,7 +1,7 @@ /* - * U-boot - start1.S Code running out of RAM after relocation + * U-boot - cpu.h * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -22,17 +22,17 @@ * MA 02110-1301 USA */ -#define ASSEMBLY -#include <linux/config.h> -#include <config.h> -#include <asm/blackfin.h> +#ifndef _CPU_H_ +#define _CPU_H_ -.global start1; -.global _start1; +#include <command.h> -.text -_start1: -start1: - sp += -12; - call _board_init_f; - sp += 12; +void board_reset(void) __attribute__((__weak__)); +void bfin_reset_or_hang(void) __attribute__((__noreturn__)); +void bfin_panic(struct pt_regs *reg); +void dump(struct pt_regs *regs); + +asmlinkage void trap(void); +asmlinkage void evt_default(void); + +#endif diff --git a/cpu/blackfin/flush.S b/cpu/blackfin/flush.S new file mode 100644 index 0000000000..8072b8643f --- /dev/null +++ b/cpu/blackfin/flush.S @@ -0,0 +1,230 @@ +/* flush.S - low level cache flushing routines + * Copyright (C) 2003-2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#include <config.h> +#include <asm/blackfin.h> +#include <asm/cplb.h> +#include <asm/mach-common/bits/mpu.h> + +.text + +/* This is an external function being called by the user + * application through __flush_cache_all. Currently this function + * serves the purpose of flushing all the pending writes in + * in the data cache. + */ + +ENTRY(_flush_data_cache) + [--SP] = ( R7:6, P5:4 ); + LINK 12; + SP += -12; + P5.H = HI(DCPLB_ADDR0); + P5.L = LO(DCPLB_ADDR0); + P4.H = HI(DCPLB_DATA0); + P4.L = LO(DCPLB_DATA0); + R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z); + R6 = 16; +.Lnext: R0 = [P5++]; + R1 = [P4++]; + CC = BITTST(R1, 14); /* Is it write-through?*/ + IF CC JUMP .Lskip; /* If so, ignore it.*/ + R2 = R1 & R7; /* Is it a dirty, cached page?*/ + CC = R2; + IF !CC JUMP .Lskip; /* If not, ignore it.*/ + [--SP] = RETS; + CALL _dcplb_flush; /* R0 = page, R1 = data*/ + RETS = [SP++]; +.Lskip: R6 += -1; + CC = R6; + IF CC JUMP .Lnext; + SSYNC; + SP += 12; + UNLINK; + ( R7:6, P5:4 ) = [SP++]; + RTS; +ENDPROC(_flush_data_cache) + +/* This is an internal function to flush all pending + * writes in the cache associated with a particular DCPLB. + * + * R0 - page's start address + * R1 - CPLB's data field. + */ + +.align 2 +ENTRY(_dcplb_flush) + [--SP] = ( R7:0, P5:0 ); + [--SP] = LC0; + [--SP] = LT0; + [--SP] = LB0; + [--SP] = LC1; + [--SP] = LT1; + [--SP] = LB1; + + /* If it's a 1K or 4K page, then it's quickest to + * just systematically flush all the addresses in + * the page, regardless of whether they're in the + * cache, or dirty. If it's a 1M or 4M page, there + * are too many addresses, and we have to search the + * cache for lines corresponding to the page. + */ + + CC = BITTST(R1, 17); /* 1MB or 4MB */ + IF !CC JUMP .Ldflush_whole_page; + + /* We're only interested in the page's size, so extract + * this from the CPLB (bits 17:16), and scale to give an + * offset into the page_size and page_prefix tables. + */ + + R1 <<= 14; + R1 >>= 30; + R1 <<= 2; + + /* The page could be mapped into Bank A or Bank B, depending + * on (a) whether both banks are configured as cache, and + * (b) on whether address bit A[x] is set. x is determined + * by DCBS in DMEM_CONTROL + */ + + R2 = 0; /* Default to Bank A (Bank B would be 1)*/ + + P0.L = LO(DMEM_CONTROL); + P0.H = HI(DMEM_CONTROL); + + R3 = [P0]; /* If Bank B is not enabled as cache*/ + CC = BITTST(R3, 2); /* then Bank A is our only option.*/ + IF CC JUMP .Lbank_chosen; + + R4 = 1<<14; /* If DCBS==0, use A[14].*/ + R5 = R4 << 7; /* If DCBS==1, use A[23];*/ + CC = BITTST(R3, 4); + IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/ + R5 = R0 & R4; /* Use it to test the Page address*/ + CC = R5; /* and if that bit is set, we use Bank B,*/ + R2 = CC; /* else we use Bank A.*/ + R2 <<= 23; /* The Bank selection's at posn 23.*/ + +.Lbank_chosen: + + /* We can also determine the sub-bank used, because this is + * taken from bits 13:12 of the address. + */ + + R3 = ((12<<8)|2); /* Extraction pattern */ + nop; /*Anamoly 05000209*/ + R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/ + /* Save in extraction pattern for later deposit.*/ + R3.H = R4.L << 0; + + /* So: + * R0 = Page start + * R1 = Page length (actually, offset into size/prefix tables) + * R2 = Bank select mask + * R3 = sub-bank deposit values + * + * The cache has 2 Ways, and 64 sets, so we iterate through + * the sets, accessing the tag for each Way, for our Bank and + * sub-bank, looking for dirty, valid tags that match our + * address prefix. + */ + + P5.L = LO(DTEST_COMMAND); + P5.H = HI(DTEST_COMMAND); + P4.L = LO(DTEST_DATA0); + P4.H = HI(DTEST_DATA0); + + P0.L = page_prefix_table; + P0.H = page_prefix_table; + P1 = R1; + R5 = 0; /* Set counter*/ + P0 = P1 + P0; + R4 = [P0]; /* This is the address prefix*/ + + + /* We're reading (bit 1==0) the tag (bit 2==0), and we + * don't care about which double-word, since we're only + * fetching tags, so we only have to set Set, Bank, + * Sub-bank and Way. + */ + + P2 = 2; + LSETUP (.Lfs1, .Lfe1) LC1 = P2; +.Lfs1: P0 = 64; /* iterate over all sets*/ + LSETUP (.Lfs0, .Lfe0) LC0 = P0; +.Lfs0: R6 = R5 << 5; /* Combine set*/ + R6.H = R3.H << 0 ; /* and sub-bank*/ + R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/ + BITSET(R6,14); + [P5] = R6; /* Issue Command*/ + SSYNC; + R7 = [P4]; /* and read Tag.*/ + CC = BITTST(R7, 0); /* Check if valid*/ + IF !CC JUMP .Lfskip; /* and skip if not.*/ + CC = BITTST(R7, 1); /* Check if dirty*/ + IF !CC JUMP .Lfskip; /* and skip if not.*/ + + /* Compare against the page address. First, plant bits 13:12 + * into the tag, since those aren't part of the returned data. + */ + + R7 = DEPOSIT(R7, R3); /* set 13:12*/ + R1 = R7 & R4; /* Mask off lower bits*/ + CC = R1 == R0; /* Compare against page start.*/ + IF !CC JUMP .Lfskip; /* Skip it if it doesn't match.*/ + + /* Tag address matches against page, so this is an entry + * we must flush. + */ + + R7 >>= 10; /* Mask off the non-address bits*/ + R7 <<= 10; + P3 = R7; + SSYNC; + FLUSHINV [P3]; /* And flush the entry*/ +.Lfskip: +.Lfe0: R5 += 1; /* Advance to next Set*/ +.Lfe1: BITSET(R2, 26); /* Go to next Way.*/ + +.Ldfinished: + SSYNC; /* Ensure the data gets out to mem.*/ + + /*Finished. Restore context.*/ + LB1 = [SP++]; + LT1 = [SP++]; + LC1 = [SP++]; + LB0 = [SP++]; + LT0 = [SP++]; + LC0 = [SP++]; + ( R7:0, P5:0 ) = [SP++]; + RTS; + +.Ldflush_whole_page: + + /* It's a 1K or 4K page, so quicker to just flush the + * entire page. + */ + + P1 = 32; /* For 1K pages*/ + P2 = P1 << 2; /* For 4K pages*/ + P0 = R0; /* Start of page*/ + CC = BITTST(R1, 16); /* Whether 1K or 4K*/ + IF CC P1 = P2; + P1 += -1; /* Unroll one iteration*/ + SSYNC; + FLUSHINV [P0++]; /* because CSYNC can't end loops.*/ + LSETUP (.Leall, .Leall) LC0 = P1; +.Leall: FLUSHINV [P0++]; + SSYNC; + JUMP .Ldfinished; +ENDPROC(_dcplb_flush) + +.align 4; +page_prefix_table: +.byte4 0xFFFFFC00; /* 1K */ +.byte4 0xFFFFF000; /* 4K */ +.byte4 0xFFF00000; /* 1M */ +.byte4 0xFFC00000; /* 4M */ +.page_prefix_table.end: diff --git a/cpu/bf537/i2c.c b/cpu/blackfin/i2c.c index ab7dd388c9..47be2587d5 100644 --- a/cpu/bf537/i2c.c +++ b/cpu/blackfin/i2c.c @@ -1,18 +1,10 @@ -/**************************************************************** - * $ID: i2c.c 24 Oct 2006 12:00:00 +0800 $ * - * * - * Description: * - * * - * Maintainer: sonicz <sonic.zhang@analog.com> * - * * - * CopyRight (c) 2006 Analog Device * - * All rights reserved. * - * * - * This file is free software; * - * you are free to modify and/or redistribute it * - * under the terms of the GNU General Public Licence (GPL).* - * * - ****************************************************************/ +/* + * i2c.c - driver for Blackfin on-chip TWI/I2C + * + * Copyright (c) 2006-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ #include <common.h> @@ -23,10 +15,45 @@ #include <asm/io.h> #include <asm/mach-common/bits/twi.h> -DECLARE_GLOBAL_DATA_PTR; +/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ +#ifdef TWI0_CLKDIV +#define bfin_read_TWI_CLKDIV() bfin_read_TWI0_CLKDIV() +#define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val) +#define bfin_read_TWI_CONTROL() bfin_read_TWI0_CONTROL() +#define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val) +#define bfin_read_TWI_SLAVE_CTL() bfin_read_TWI0_SLAVE_CTL() +#define bfin_write_TWI_SLAVE_CTL(val) bfin_write_TWI0_SLAVE_CTL(val) +#define bfin_read_TWI_SLAVE_STAT() bfin_read_TWI0_SLAVE_STAT() +#define bfin_write_TWI_SLAVE_STAT(val) bfin_write_TWI0_SLAVE_STAT(val) +#define bfin_read_TWI_SLAVE_ADDR() bfin_read_TWI0_SLAVE_ADDR() +#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write_TWI0_SLAVE_ADDR(val) +#define bfin_read_TWI_MASTER_CTL() bfin_read_TWI0_MASTER_CTL() +#define bfin_write_TWI_MASTER_CTL(val) bfin_write_TWI0_MASTER_CTL(val) +#define bfin_read_TWI_MASTER_STAT() bfin_read_TWI0_MASTER_STAT() +#define bfin_write_TWI_MASTER_STAT(val) bfin_write_TWI0_MASTER_STAT(val) +#define bfin_read_TWI_MASTER_ADDR() bfin_read_TWI0_MASTER_ADDR() +#define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val) +#define bfin_read_TWI_INT_STAT() bfin_read_TWI0_INT_STAT() +#define bfin_write_TWI_INT_STAT(val) bfin_write_TWI0_INT_STAT(val) +#define bfin_read_TWI_INT_MASK() bfin_read_TWI0_INT_MASK() +#define bfin_write_TWI_INT_MASK(val) bfin_write_TWI0_INT_MASK(val) +#define bfin_read_TWI_FIFO_CTL() bfin_read_TWI0_FIFO_CTL() +#define bfin_write_TWI_FIFO_CTL(val) bfin_write_TWI0_FIFO_CTL(val) +#define bfin_read_TWI_FIFO_STAT() bfin_read_TWI0_FIFO_STAT() +#define bfin_write_TWI_FIFO_STAT(val) bfin_write_TWI0_FIFO_STAT(val) +#define bfin_read_TWI_XMT_DATA8() bfin_read_TWI0_XMT_DATA8() +#define bfin_write_TWI_XMT_DATA8(val) bfin_write_TWI0_XMT_DATA8(val) +#define bfin_read_TWI_XMT_DATA_16() bfin_read_TWI0_XMT_DATA16() +#define bfin_write_TWI_XMT_DATA16(val) bfin_write_TWI0_XMT_DATA16(val) +#define bfin_read_TWI_RCV_DATA8() bfin_read_TWI0_RCV_DATA8() +#define bfin_write_TWI_RCV_DATA8(val) bfin_write_TWI0_RCV_DATA8(val) +#define bfin_read_TWI_RCV_DATA16() bfin_read_TWI0_RCV_DATA16() +#define bfin_write_TWI_RCV_DATA16(val) bfin_write_TWI0_RCV_DATA16(val) +#endif #ifdef DEBUG_I2C #define PRINTD(fmt,args...) do { \ + DECLARE_GLOBAL_DATA_PTR; \ if (gd->have_console) \ printf(fmt ,##args); \ } while (0) @@ -50,14 +77,12 @@ struct i2c_msg { /** * i2c_reset: - reset the host controller - * */ - static void i2c_reset(void) { /* Disable TWI */ bfin_write_TWI_CONTROL(0); - sync(); + SSYNC(); /* Set TWI internal clock as 10MHz */ bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F); @@ -74,7 +99,7 @@ static void i2c_reset(void) /* Enable TWI */ bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA); - sync(); + SSYNC(); } int wait_for_completion(struct i2c_msg *msg, int timeout_count) @@ -95,10 +120,10 @@ int wait_for_completion(struct i2c_msg *msg, int timeout_count) } else if (msg->flags & I2C_M_STOP) bfin_write_TWI_MASTER_CTL (bfin_read_TWI_MASTER_CTL() | STOP); - sync(); + SSYNC(); /* Clear status */ bfin_write_TWI_INT_STAT(XMTSERV); - sync(); + SSYNC(); i = 0; } if (RCVSERV & twi_int_stat) { @@ -109,11 +134,11 @@ int wait_for_completion(struct i2c_msg *msg, int timeout_count) } else if (msg->flags & I2C_M_STOP) { bfin_write_TWI_MASTER_CTL (bfin_read_TWI_MASTER_CTL() | STOP); - sync(); + SSYNC(); } /* Clear interrupt source */ bfin_write_TWI_INT_STAT(RCVSERV); - sync(); + SSYNC(); i = 0; } if (MERR & twi_int_stat) { @@ -121,7 +146,7 @@ int wait_for_completion(struct i2c_msg *msg, int timeout_count) bfin_write_TWI_INT_MASK(0); bfin_write_TWI_MASTER_STAT(0x3e); bfin_write_TWI_MASTER_CTL(0); - sync(); + SSYNC(); /* * if both err and complete int stats are set, * return proper results. @@ -130,7 +155,7 @@ int wait_for_completion(struct i2c_msg *msg, int timeout_count) bfin_write_TWI_INT_STAT(MCOMP); bfin_write_TWI_INT_MASK(0); bfin_write_TWI_MASTER_CTL(0); - sync(); + SSYNC(); /* * If it is a quick transfer, * only address bug no data, not an err. @@ -150,10 +175,10 @@ int wait_for_completion(struct i2c_msg *msg, int timeout_count) } if (MCOMP & twi_int_stat) { bfin_write_TWI_INT_STAT(MCOMP); - sync(); + SSYNC(); bfin_write_TWI_INT_MASK(0); bfin_write_TWI_MASTER_CTL(0); - sync(); + SSYNC(); return 0; } } @@ -187,7 +212,8 @@ int i2c_transfer(struct i2c_msg *msg) goto transfer_error; } - while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) ; + while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) + continue; /* Set Transmit device address */ bfin_write_TWI_MASTER_ADDR(msg->addr); @@ -197,9 +223,9 @@ int i2c_transfer(struct i2c_msg *msg) * Data in FIFO should be discarded before start a new operation. */ bfin_write_TWI_FIFO_CTL(0x3); - sync(); + SSYNC(); bfin_write_TWI_FIFO_CTL(0); - sync(); + SSYNC(); if (!(msg->flags & I2C_M_RD)) { /* Transmit first data */ @@ -208,7 +234,7 @@ int i2c_transfer(struct i2c_msg *msg) len); bfin_write_TWI_XMT_DATA8(*(msg->buf++)); msg->len--; - sync(); + SSYNC(); } } @@ -218,7 +244,7 @@ int i2c_transfer(struct i2c_msg *msg) /* Interrupt mask . Enable XMT, RCV interrupt */ bfin_write_TWI_INT_MASK(MCOMP | MERR | ((msg->flags & I2C_M_RD) ? RCVSERV : XMTSERV)); - sync(); + SSYNC(); if (len > 0 && len <= 255) bfin_write_TWI_MASTER_CTL((len << 6)); @@ -233,12 +259,12 @@ int i2c_transfer(struct i2c_msg *msg) ((msg->flags & I2C_M_RD) ? MDIR : 0) | ((CONFIG_TWICLK_KHZ > 100) ? FAST : 0)); - sync(); + SSYNC(); ret = wait_for_completion(msg, timeout_count); PRINTD("3 in i2c_transfer: ret=%d\n", ret); -transfer_error: + transfer_error: switch (ret) { case 1: PRINTD(("i2c_transfer: error: transfer fail\n")); @@ -415,4 +441,4 @@ void i2c_reg_write(uchar chip, uchar reg, uchar val) i2c_write(chip, reg, 0, &val, 1); } -#endif /* CONFIG_HARD_I2C */ +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c new file mode 100644 index 0000000000..ffc8420f1a --- /dev/null +++ b/cpu/blackfin/initcode.c @@ -0,0 +1,353 @@ +/* + * initcode.c - Initialize the processor. This is usually entails things + * like external memory, voltage regulators, etc... Note that this file + * cannot make any function calls as it may be executed all by itself by + * the Blackfin's bootrom in LDR format. + * + * Copyright (c) 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <config.h> +#include <asm/blackfin.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> + +#define BFIN_IN_INITCODE +#include "serial.h" + +__attribute__((always_inline)) +static inline uint32_t serial_init(void) +{ +#ifdef __ADSPBF54x__ +# ifdef BFIN_BOOT_UART_USE_RTS +# define BFIN_UART_USE_RTS 1 +# else +# define BFIN_UART_USE_RTS 0 +# endif + if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { + size_t i; + + /* force RTS rather than relying on auto RTS */ + bfin_write_UART1_MCR(bfin_read_UART1_MCR() | FCPOL); + + /* Wait for the line to clear up. We cannot rely on UART + * registers as none of them reflect the status of the RSR. + * Instead, we'll sleep for ~10 bit times at 9600 baud. + * We can precalc things here by assuming boot values for + * PLL rather than loading registers and calculating. + * baud = SCLK / (16 ^ (1 - EDBO) * Divisor) + * EDB0 = 0 + * Divisor = (SCLK / baud) / 16 + * SCLK = baud * 16 * Divisor + * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5 + * CCLK = (16 * Divisor * 5) * (9600 / 10) + * In reality, this will probably be just about 1 second delay, + * so assuming 9600 baud is OK (both as a very low and too high + * speed as this will buffer things enough). + */ +#define _NUMBITS (10) /* how many bits to delay */ +#define _LOWBAUD (9600) /* low baud rate */ +#define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */ +#define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */ +#define _NUMINS (3) /* how many instructions in loop */ +#define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS) + i = _CCLK; + while (i--) + asm volatile("" : : : "memory"); + } +#endif + + uint32_t old_baud = serial_early_get_baud(); + + if (BFIN_DEBUG_EARLY_SERIAL) { + serial_early_init(); + + /* If the UART is off, that means we need to program + * the baud rate ourselves initially. + */ + if (!old_baud) { + old_baud = CONFIG_BAUDRATE; + serial_early_set_baud(CONFIG_BAUDRATE); + } + } + + return old_baud; +} + +__attribute__((always_inline)) +static inline void serial_deinit(void) +{ +#ifdef __ADSPBF54x__ + if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { + /* clear forced RTS rather than relying on auto RTS */ + bfin_write_UART1_MCR(bfin_read_UART1_MCR() & ~FCPOL); + } +#endif +} + +/* We need to reset the baud rate when we have early debug turned on + * or when we are booting over the UART. + * XXX: we should fix this to calc the old baud and restore it rather + * than hardcoding it via CONFIG_LDR_LOAD_BAUD ... but we have + * to figure out how to avoid the division in the baud calc ... + */ +__attribute__((always_inline)) +static inline void serial_reset_baud(uint32_t baud) +{ + if (!BFIN_DEBUG_EARLY_SERIAL && CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) + return; + +#ifndef CONFIG_LDR_LOAD_BAUD +# define CONFIG_LDR_LOAD_BAUD 115200 +#endif + + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) + serial_early_set_baud(baud); + else if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) + serial_early_set_baud(CONFIG_LDR_LOAD_BAUD); + else + serial_early_set_baud(CONFIG_BAUDRATE); +} + +__attribute__((always_inline)) +static inline void serial_putc(char c) +{ + if (!BFIN_DEBUG_EARLY_SERIAL) + return; + + if (c == '\n') + *pUART_THR = '\r'; + + *pUART_THR = c; + + while (!(*pUART_LSR & TEMT)) + continue; +} + + +/* Max SCLK can be 133MHz ... dividing that by 4 gives + * us a freq of 33MHz for SPI which should generally be + * slow enough for the slow reads the bootrom uses. + */ +#ifndef CONFIG_SPI_BAUD_INITBLOCK +# define CONFIG_SPI_BAUD_INITBLOCK 4 +#endif + +/* PLL_DIV defines */ +#ifndef CONFIG_PLL_DIV_VAL +# if (CONFIG_CCLK_DIV == 1) +# define CONFIG_CCLK_ACT_DIV CCLK_DIV1 +# elif (CONFIG_CCLK_DIV == 2) +# define CONFIG_CCLK_ACT_DIV CCLK_DIV2 +# elif (CONFIG_CCLK_DIV == 4) +# define CONFIG_CCLK_ACT_DIV CCLK_DIV4 +# elif (CONFIG_CCLK_DIV == 8) +# define CONFIG_CCLK_ACT_DIV CCLK_DIV8 +# else +# define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly +# endif +# define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV) +#endif + +#ifndef CONFIG_PLL_LOCKCNT_VAL +# define CONFIG_PLL_LOCKCNT_VAL 0x0300 +#endif + +#ifndef CONFIG_PLL_CTL_VAL +# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9)) +#endif + +#ifndef CONFIG_EBIU_RSTCTL_VAL +# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */ +#endif + +#ifndef CONFIG_EBIU_MBSCTL_VAL +# define CONFIG_EBIU_MBSCTL_VAL 0 +#endif + +/* Make sure our voltage value is sane so we don't blow up! */ +#ifndef CONFIG_VR_CTL_VAL +# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV) +# if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) +# define CCLK_VLEV_120 400000000 +# define CCLK_VLEV_125 533000000 +# elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) +# define CCLK_VLEV_120 401000000 +# define CCLK_VLEV_125 401000000 +# elif defined(__ADSPBF561__) +# define CCLK_VLEV_120 300000000 +# define CCLK_VLEV_125 501000000 +# endif +# if BFIN_CCLK < CCLK_VLEV_120 +# define CONFIG_VR_CTL_VLEV VLEV_120 +# elif BFIN_CCLK < CCLK_VLEV_125 +# define CONFIG_VR_CTL_VLEV VLEV_125 +# else +# define CONFIG_VR_CTL_VLEV VLEV_130 +# endif +# if defined(__ADSPBF52x__) /* TBD; use default */ +# undef CONFIG_VR_CTL_VLEV +# define CONFIG_VR_CTL_VLEV VLEV_110 +# elif defined(__ADSPBF54x__) /* TBD; use default */ +# undef CONFIG_VR_CTL_VLEV +# define CONFIG_VR_CTL_VLEV VLEV_120 +# endif + +# ifdef CONFIG_BFIN_MAC +# define CONFIG_VR_CTL_CLKBUF CLKBUFOE +# else +# define CONFIG_VR_CTL_CLKBUF 0 +# endif + +# if defined(__ADSPBF52x__) +# define CONFIG_VR_CTL_FREQ FREQ_1000 +# else +# define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000) +# endif + +# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ) +#endif + +__attribute__((saveall)) +void initcode(ADI_BOOT_DATA *bootstruct) +{ + uint32_t old_baud = serial_init(); + +#ifdef CONFIG_HW_WATCHDOG +# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE +# define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000 +# endif + /* Program the watchdog with an initial timeout of ~20 seconds. + * Hopefully that should be long enough to load the u-boot LDR + * (from wherever) and then the common u-boot code can take over. + * In bypass mode, the start.S would have already set a much lower + * timeout, so don't clobber that. + */ + if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) { + bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE)); + bfin_write_WDOG_CTL(0); + } +#endif + + serial_putc('S'); + + /* Blackfin bootroms use the SPI slow read opcode instead of the SPI + * fast read, so we need to slow down the SPI clock a lot more during + * boot. Once we switch over to u-boot's SPI flash driver, we'll + * increase the speed appropriately. + */ + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) +#ifdef SPI0_BAUD + bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK); +#else + bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK); +#endif + + serial_putc('B'); + + /* Disable all peripheral wakeups except for the PLL event. */ +#ifdef SIC_IWR0 + bfin_write_SIC_IWR0(1); + bfin_write_SIC_IWR1(0); +# ifdef SIC_IWR2 + bfin_write_SIC_IWR2(0); +# endif +#elif defined(SICA_IWR0) + bfin_write_SICA_IWR0(1); + bfin_write_SICA_IWR1(0); +#else + bfin_write_SIC_IWR(1); +#endif + + serial_putc('L'); + + bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL); + + serial_putc('A'); + + /* Only reprogram when needed to avoid triggering unnecessary + * PLL relock sequences. + */ + if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) { + serial_putc('!'); + bfin_write_VR_CTL(CONFIG_VR_CTL_VAL); + asm("idle;"); + } + + serial_putc('C'); + + bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL); + + serial_putc('K'); + + /* Only reprogram when needed to avoid triggering unnecessary + * PLL relock sequences. + */ + if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) { + serial_putc('!'); + bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL); + asm("idle;"); + } + + /* Since we've changed the SCLK above, we may need to update + * the UART divisors (UART baud rates are based on SCLK). + */ + serial_reset_baud(old_baud); + + serial_putc('F'); + + /* Program the async banks controller. */ + bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); + bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL); + bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); + +#ifdef EBIU_MODE + /* Not all parts have these additional MMRs. */ + bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL); + bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL); + bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL); +#endif + + serial_putc('I'); + + /* Program the external memory controller. */ +#ifdef EBIU_RSTCTL + bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL); + bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL); + bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL); + bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL); +# ifdef CONFIG_EBIU_DDRCTL3_VAL + /* default is disable, so don't need to force this */ + bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL); +# endif +#else + bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL); + bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL); + bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL); +#endif + + serial_putc('N'); + + /* Restore all peripheral wakeups. */ +#ifdef SIC_IWR0 + bfin_write_SIC_IWR0(-1); + bfin_write_SIC_IWR1(-1); +# ifdef SIC_IWR2 + bfin_write_SIC_IWR2(-1); +# endif +#elif defined(SICA_IWR0) + bfin_write_SICA_IWR0(-1); + bfin_write_SICA_IWR1(-1); +#else + bfin_write_SIC_IWR(-1); +#endif + + serial_putc('>'); + serial_putc('\n'); + + serial_deinit(); +} diff --git a/cpu/blackfin/interrupt.S b/cpu/blackfin/interrupt.S new file mode 100644 index 0000000000..dd2cc5320c --- /dev/null +++ b/cpu/blackfin/interrupt.S @@ -0,0 +1,33 @@ +/* + * interrupt.S - trampoline default exceptions/interrupts to C handlers + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#include <asm/blackfin.h> +#include <asm/entry.h> + +.text + +/* default entry point for exceptions */ +ENTRY(_trap) + SAVE_ALL_SYS + r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ + sp += -12; + call _trap_c; + sp += 12; + RESTORE_ALL_SYS + rtx; +ENDPROC(_trap) + +/* default entry point for interrupts */ +ENTRY(_evt_default) + SAVE_ALL_SYS + r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */ + sp += -12; + call _bfin_panic; + sp += 12; + RESTORE_ALL_SYS + rti; +ENDPROC(_evt_default) diff --git a/cpu/bf561/interrupts.c b/cpu/blackfin/interrupts.c index 78800611a3..80c5505454 100644 --- a/cpu/bf561/interrupts.c +++ b/cpu/blackfin/interrupts.c @@ -1,7 +1,7 @@ /* * U-boot - interrupts.c Interrupt related routines * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005-2008 Analog Devices Inc. * * This file is based on interrupts.c * Copyright 1996 Roman Zippel @@ -14,24 +14,8 @@ * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #include <common.h> @@ -49,7 +33,7 @@ int irq_flags; /* needed by asm-blackfin/system.h */ /* * This function is derived from PowerPC code (read timebase as long long). - * On BF561 it just returns the timer value. + * On Blackfin it just returns the timer value. */ unsigned long long get_ticks(void) { @@ -58,7 +42,7 @@ unsigned long long get_ticks(void) /* * This function is derived from PowerPC code (timebase clock frequency). - * On BF561 it returns the number of timer ticks per second. + * On Blackfin it returns the number of timer ticks per second. */ ulong get_tbclk(void) { @@ -70,18 +54,15 @@ ulong get_tbclk(void) void enable_interrupts(void) { + local_irq_restore(int_flag); } int disable_interrupts(void) { + local_irq_save(int_flag); return 1; } -int interrupt_init(void) -{ - return (0); -} - void udelay(unsigned long usec) { unsigned long delay, start, stop; @@ -101,16 +82,17 @@ void udelay(unsigned long usec) usec -= 1000; } - asm volatile (" %0 = CYCLES;":"=r" (start)); + asm volatile (" %0 = CYCLES;" : "=r" (start)); do { - asm volatile (" %0 = CYCLES; ":"=r" (stop)); + asm volatile (" %0 = CYCLES; " : "=r" (stop)); } while (stop - start < delay); } return; } -void timer_init(void) +#define MAX_TIM_LOAD 0xFFFFFFFF +int timer_init(void) { *pTCNTL = 0x1; *pTSCALE = 0x0; @@ -121,6 +103,8 @@ void timer_init(void) timestamp = 0; last_time = 0; + + return 0; } /* @@ -157,11 +141,15 @@ ulong get_timer(ulong base) milisec = clocks / (CONFIG_CCLK_HZ / 1000); /* - * Find the number of millisonds - * that got elapsed before this TCOUNT - * cycle + * Find the number of millisonds that + * got elapsed before this TCOUNT cycle */ milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000)); return (milisec - base); } + +void reset_timer(void) +{ + timestamp = 0; +} diff --git a/cpu/blackfin/reset.c b/cpu/blackfin/reset.c new file mode 100644 index 0000000000..d1e34b3f94 --- /dev/null +++ b/cpu/blackfin/reset.c @@ -0,0 +1,96 @@ +/* + * reset.c - logic for resetting the cpu + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> +#include <asm/blackfin.h> +#include "cpu.h" + +/* A system soft reset makes external memory unusable so force + * this function into L1. We use the compiler ssync here rather + * than SSYNC() because it's safe (no interrupts and such) and + * we save some L1. We do not need to force sanity in the SYSCR + * register as the BMODE selection bit is cleared by the soft + * reset while the Core B bit (on dual core parts) is cleared by + * the core reset. + */ +__attribute__ ((__l1_text__, __noreturn__)) +void bfin_reset(void) +{ + /* Wait for completion of "system" events such as cache line + * line fills so that we avoid infinite stalls later on as + * much as possible. This code is in L1, so it won't trigger + * any such event after this point in time. + */ + __builtin_bfin_ssync(); + + while (1) { + /* Initiate System software reset. */ + bfin_write_SWRST(0x7); + + /* Due to the way reset is handled in the hardware, we need + * to delay for 7 SCLKS. The only reliable way to do this is + * to calculate the CCLK/SCLK ratio and multiply 7. For now, + * we'll assume worse case which is a 1:15 ratio. + */ + asm( + "LSETUP (1f, 1f) LC0 = %0\n" + "1: nop;" + : + : "a" (15 * 7) + : "LC0", "LB0", "LT0" + ); + + /* Clear System software reset */ + bfin_write_SWRST(0); + + /* Wait for the SWRST write to complete. Cannot rely on SSYNC + * though as the System state is all reset now. + */ + asm( + "LSETUP (1f, 1f) LC1 = %0\n" + "1: nop;" + : + : "a" (15 * 1) + : "LC1", "LB1", "LT1" + ); + + /* Issue core reset */ + asm("raise 1"); + } +} + +/* We need to trampoline ourselves up into L1 since our linker + * does not have relaxtion support and will only generate a + * PC relative call with a 25 bit immediate. This is not enough + * to get us from the top of SDRAM into L1. + */ +__attribute__ ((__noreturn__)) +static inline void bfin_reset_trampoline(void) +{ + if (board_reset) + board_reset(); + while (1) + asm("jump (%0);" : : "a" (bfin_reset)); +} + +__attribute__ ((__noreturn__)) +void bfin_reset_or_hang(void) +{ +#ifdef CONFIG_PANIC_HANG + hang(); +#else + bfin_reset_trampoline(); +#endif +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + bfin_reset_trampoline(); + return 0; +} diff --git a/cpu/blackfin/serial.c b/cpu/blackfin/serial.c new file mode 100644 index 0000000000..0dfee51423 --- /dev/null +++ b/cpu/blackfin/serial.c @@ -0,0 +1,124 @@ +/* + * U-boot - serial.c Blackfin Serial Driver + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>, + * BuyWays B.V. (www.buyways.nl) + * + * Based heavily on: + * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs. + * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com> + * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com> + * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com> + * + * Based on code from 68328 version serial driver imlpementation which was: + * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu> + * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com> + * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org> + * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/blackfin.h> +#include <asm/mach-common/bits/uart.h> + +#if defined(UART_LSR) && (CONFIG_UART_CONSOLE != 0) +# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART +#endif + +#include "serial.h" + +/* Symbol for our assembly to call. */ +void serial_set_baud(uint32_t baud) +{ + serial_early_set_baud(baud); +} + +/* Symbol for common u-boot code to call. + * Setup the baudrate (brg: baudrate generator). + */ +void serial_setbrg(void) +{ + DECLARE_GLOBAL_DATA_PTR; + serial_set_baud(gd->baudrate); +} + +/* Symbol for our assembly to call. */ +void serial_initialize(void) +{ + serial_early_init(); +} + +/* Symbol for common u-boot code to call. */ +int serial_init(void) +{ + serial_initialize(); + serial_setbrg(); + return 0; +} + +void serial_putc(const char c) +{ + /* send a \r for compatibility */ + if (c == '\n') + serial_putc('\r'); + + WATCHDOG_RESET(); + + /* wait for the hardware fifo to clear up */ + while (!(*pUART_LSR & THRE)) + continue; + + /* queue the character for transmission */ + *pUART_THR = c; + SSYNC(); + + WATCHDOG_RESET(); + + /* wait for the byte to be shifted over the line */ + while (!(*pUART_LSR & TEMT)) + continue; +} + +int serial_tstc(void) +{ + WATCHDOG_RESET(); + return (*pUART_LSR & DR) ? 1 : 0; +} + +int serial_getc(void) +{ + uint16_t uart_lsr_val, uart_rbr_val; + + /* wait for data ! */ + while (!serial_tstc()) + continue; + + /* clear the status and grab the new byte */ + uart_lsr_val = *pUART_LSR; + uart_rbr_val = *pUART_RBR; + + if (uart_lsr_val & (OE|PE|FE|BI)) { + /* Some parts are read-to-clear while others are + * write-to-clear. Just do the write for everyone + * since it cant hurt (other than code size). + */ + *pUART_LSR = (OE|PE|FE|BI); + return -1; + } + + return uart_rbr_val & 0xFF; +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h new file mode 100644 index 0000000000..1f0f4b46c7 --- /dev/null +++ b/cpu/blackfin/serial.h @@ -0,0 +1,275 @@ +/* + * serial.h - common serial defines for early debug and serial driver. + * any functions defined here must be always_inline since + * initcode cannot have function calls. + * + * Copyright (c) 2004-2007 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_CPU_SERIAL_H__ +#define __BFIN_CPU_SERIAL_H__ + +#include <asm/blackfin.h> +#include <asm/mach-common/bits/uart.h> + +#ifdef CONFIG_DEBUG_EARLY_SERIAL +# define BFIN_DEBUG_EARLY_SERIAL 1 +#else +# define BFIN_DEBUG_EARLY_SERIAL 0 +#endif + +#define LOB(x) ((x) & 0xFF) +#define HIB(x) (((x) >> 8) & 0xFF) + +#ifndef UART_LSR +# if (CONFIG_UART_CONSOLE == 3) +# define pUART_DLH pUART3_DLH +# define pUART_DLL pUART3_DLL +# define pUART_GCTL pUART3_GCTL +# define pUART_IER pUART3_IER +# define pUART_IERC pUART3_IER_CLEAR +# define pUART_LCR pUART3_LCR +# define pUART_LSR pUART3_LSR +# define pUART_RBR pUART3_RBR +# define pUART_THR pUART3_THR +# define UART_THR UART3_THR +# define UART_LSR UART3_LSR +# elif (CONFIG_UART_CONSOLE == 2) +# define pUART_DLH pUART2_DLH +# define pUART_DLL pUART2_DLL +# define pUART_GCTL pUART2_GCTL +# define pUART_IER pUART2_IER +# define pUART_IERC pUART2_IER_CLEAR +# define pUART_LCR pUART2_LCR +# define pUART_LSR pUART2_LSR +# define pUART_RBR pUART2_RBR +# define pUART_THR pUART2_THR +# define UART_THR UART2_THR +# define UART_LSR UART2_LSR +# elif (CONFIG_UART_CONSOLE == 1) +# define pUART_DLH pUART1_DLH +# define pUART_DLL pUART1_DLL +# define pUART_GCTL pUART1_GCTL +# define pUART_IER pUART1_IER +# define pUART_IERC pUART1_IER_CLEAR +# define pUART_LCR pUART1_LCR +# define pUART_LSR pUART1_LSR +# define pUART_RBR pUART1_RBR +# define pUART_THR pUART1_THR +# define UART_THR UART1_THR +# define UART_LSR UART1_LSR +# elif (CONFIG_UART_CONSOLE == 0) +# define pUART_DLH pUART0_DLH +# define pUART_DLL pUART0_DLL +# define pUART_GCTL pUART0_GCTL +# define pUART_IER pUART0_IER +# define pUART_IERC pUART0_IER_CLEAR +# define pUART_LCR pUART0_LCR +# define pUART_LSR pUART0_LSR +# define pUART_RBR pUART0_RBR +# define pUART_THR pUART0_THR +# define UART_THR UART0_THR +# define UART_LSR UART0_LSR +# endif +#endif + +#ifndef __ASSEMBLY__ + +/* We cannot use get_sclk() in initcode as it is defined elsewhere. */ +#ifdef BFIN_IN_INITCODE +# define get_sclk() (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV) +#endif + +#ifdef __ADSPBF54x__ +# define ACCESS_LATCH() +# define ACCESS_PORT_IER() +# define CLEAR_IER() (*pUART_IERC = 0) +#else +# define ACCESS_LATCH() (*pUART_LCR |= DLAB) +# define ACCESS_PORT_IER() (*pUART_LCR &= ~DLAB) +# define CLEAR_IER() (*pUART_IER = 0) +#endif + +__attribute__((always_inline)) +static inline void serial_do_portmux(void) +{ +#ifdef __ADSPBF52x__ +# define DO_MUX(port, mux, tx, rx) \ + bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \ + bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); + switch (CONFIG_UART_CONSOLE) { + case 0: DO_MUX(G, 2, 7, 8); break; /* Port G; mux 2; PG2 and PG8 */ + case 1: DO_MUX(F, 5, 14, 15); break; /* Port F; mux 5; PF14 and PF15 */ + } + SSYNC(); +#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) +# define DO_MUX(func, tx, rx) \ + bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~(func)); \ + bfin_write_PORTF_FER(bfin_read_PORTF_FER() | PF##tx | PF##rx); + switch (CONFIG_UART_CONSOLE) { + case 0: DO_MUX(PFDE, 0, 1); break; + case 1: DO_MUX(PFTE, 2, 3); break; + } + SSYNC(); +#elif defined(__ADSPBF54x__) +# define DO_MUX(port, tx, rx) \ + bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_1 | PORT_x_MUX_##rx##_FUNC_1); \ + bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); + switch (CONFIG_UART_CONSOLE) { + case 0: DO_MUX(E, 7, 8); break; /* Port E; PE7 and PE8 */ + case 1: DO_MUX(H, 0, 1); break; /* Port H; PH0 and PH1 */ + case 2: DO_MUX(B, 4, 5); break; /* Port B; PB4 and PB5 */ + case 3: DO_MUX(B, 6, 7); break; /* Port B; PB6 and PB7 */ + } + SSYNC(); +#endif +} + +__attribute__((always_inline)) +static inline void serial_early_init(void) +{ + /* handle portmux crap on different Blackfins */ + serial_do_portmux(); + + /* Enable UART */ + *pUART_GCTL = UCEN; + + /* Set LCR to Word Lengh 8-bit word select */ + *pUART_LCR = WLS_8; + + SSYNC(); +} + +__attribute__((always_inline)) +static inline uint32_t serial_early_get_baud(void) +{ + /* If the UART isnt enabled, then we are booting an LDR + * from a non-UART source (so like flash) which means + * the baud rate here is meaningless. + */ + if ((*pUART_GCTL & UCEN) != UCEN) + return 0; + +#if (0) /* See comment for serial_reset_baud() in initcode.c */ + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH(); + SSYNC(); + + uint8_t dll = *pUART_DLL; + uint8_t dlh = *pUART_DLH; + uint16_t divisor = (dlh << 8) | dll; + uint32_t baud = get_sclk() / (divisor * 16); + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER(); + SSYNC(); + + return baud; +#else + return CONFIG_BAUDRATE; +#endif +} + +__attribute__((always_inline)) +static inline void serial_early_set_baud(uint32_t baud) +{ + /* Translate from baud into divisor in terms of SCLK. + * The +1 is to make sure we over sample just a little + * rather than under sample the incoming signals. + */ + uint16_t divisor = (get_sclk() / (baud * 16)) + 1; + + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH(); + SSYNC(); + + /* Program the divisor to get the baud rate we want */ + *pUART_DLL = LOB(divisor); + *pUART_DLH = HIB(divisor); + SSYNC(); + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER(); + SSYNC(); +} + +#ifndef BFIN_IN_INITCODE +__attribute__((always_inline)) +static inline void serial_early_puts(const char *s) +{ + if (BFIN_DEBUG_EARLY_SERIAL) { + serial_puts("Early: "); + serial_puts(s); + } +} +#endif + +#else + +.macro serial_early_init +#ifdef CONFIG_DEBUG_EARLY_SERIAL + call _serial_initialize; +#endif +.endm + +.macro serial_early_set_baud +#ifdef CONFIG_DEBUG_EARLY_SERIAL + R0.L = LO(CONFIG_BAUDRATE); + R0.H = HI(CONFIG_BAUDRATE); + call _serial_set_baud; +#endif +.endm + +/* Recursively expand calls to _serial_putc for every byte + * passed to us. Append a newline when we're all done. + */ +.macro _serial_early_putc byte:req morebytes:vararg +#ifdef CONFIG_DEBUG_EARLY_SERIAL + R0 = \byte; + call _serial_putc; +.ifnb \morebytes + _serial_early_putc \morebytes +.else +.if (\byte != '\n') + _serial_early_putc '\n' +.endif +.endif +#endif +.endm + +/* Wrapper around recurisve _serial_early_putc macro which + * simply prepends the string "Early: " + */ +.macro serial_early_putc byte:req morebytes:vararg +#ifdef CONFIG_DEBUG_EARLY_SERIAL + _serial_early_putc 'E', 'a', 'r', 'l', 'y', ':', ' ', \byte, \morebytes +#endif +.endm + +/* Since we embed the string right into our .text section, we need + * to find its address. We do this by getting our PC and adding 2 + * bytes (which is the length of the jump instruction). Then we + * pass this address to serial_puts(). + */ +#ifdef CONFIG_DEBUG_EARLY_SERIAL +# define serial_early_puts(str) \ + call _get_pc; \ + jump 1f; \ + .ascii "Early:"; \ + .ascii __FILE__; \ + .ascii ": "; \ + .ascii str; \ + .asciz "\n"; \ + .align 4; \ +1: \ + R0 += 2; \ + call _serial_puts; +#else +# define serial_early_puts(str) +#endif + +#endif + +#endif diff --git a/cpu/blackfin/start.S b/cpu/blackfin/start.S new file mode 100644 index 0000000000..30212e9281 --- /dev/null +++ b/cpu/blackfin/start.S @@ -0,0 +1,219 @@ +/* + * U-boot - start.S Startup file for Blackfin u-boot + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * This file is based on head.S + * Copyright (c) 2003 Metrowerks/Motorola + * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, + * Kenneth Albanowski <kjahds@kjahds.com>, + * The Silver Hammer Group, Ltd. + * (c) 1995, Dionne & Associates + * (c) 1995, DKG Display Tech. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <config.h> +#include <asm/blackfin.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/dma.h> +#include <asm/mach-common/bits/pll.h> + +#include "serial.h" + +/* It may seem odd that we make calls to functions even though we haven't + * relocated ourselves yet out of {flash,ram,wherever}. This is OK because + * the "call" instruction in the Blackfin architecture is actually PC + * relative. So we can call functions all we want and not worry about them + * not being relocated yet. + */ + +.text +ENTRY(_start) + + /* Set our initial stack to L1 scratch space */ + sp.l = LO(L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE); + sp.h = HI(L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE); + +#ifdef CONFIG_HW_WATCHDOG +# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START +# define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000 +# endif + /* Program the watchdog with an initial timeout of ~5 seconds. + * That should be long enough to bootstrap ourselves up and + * then the common u-boot code can take over. + */ + P0.L = LO(WDOG_CNT); + P0.H = HI(WDOG_CNT); + R0.L = 0; + R0.H = HI(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_START)); + [P0] = R0; + /* fire up the watchdog - R0.L above needs to be 0x0000 */ + W[P0 + (WDOG_CTL - WDOG_CNT)] = R0; +#endif + + /* Turn on the serial for debugging the init process */ + serial_early_init + serial_early_set_baud + + serial_early_puts("Init Registers"); + + /* Disable nested interrupts and enable CYCLES for udelay() */ + R0 = CCEN | 0x30; + SYSCFG = R0; + + /* Zero out registers required by Blackfin ABI. + * http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface + */ + r1 = 0 (x); + /* Disable circular buffers */ + l0 = r1; + l1 = r1; + l2 = r1; + l3 = r1; + /* Disable hardware loops in case we were started by 'go' */ + lc0 = r1; + lc1 = r1; + + /* Save RETX so we can pass it while booting Linux */ + r7 = RETX; + +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) + /* In bypass mode, we don't have an LDR with an init block + * so we need to explicitly call it ourselves. This will + * reprogram our clocks and setup our async banks. + */ + /* XXX: we should DMA this into L1, put external memory into + * self refresh, and then jump there ... + */ + call _get_pc; + r3 = 0x0; + r3.h = 0x2000; + cc = r0 < r3 (iu); + if cc jump .Lproc_initialized; + + serial_early_puts("Program Clocks"); + + call _initcode; + + /* Since we reprogrammed SCLK, we need to update the serial divisor */ + serial_early_set_baud + +.Lproc_initialized: +#endif + + /* Inform upper layers if we had to do the relocation ourselves. + * This allows us to detect whether we were loaded by 'go 0x1000' + * or by the bootrom from an LDR. "r6" is "loaded_from_ldr". + */ + r6 = 1 (x); + + /* Relocate from wherever are (FLASH/RAM/etc...) to the + * hardcoded monitor location in the end of RAM. + */ + serial_early_puts("Relocate"); + call _get_pc; +.Loffset: + r2.l = .Loffset; + r2.h = .Loffset; + r3.l = _start; + r3.h = _start; + r1 = r2 - r3; + + r0 = r0 - r1; + + cc = r0 == r3; + if cc jump .Lnorelocate; + + r6 = 0 (x); + p1 = r0; + + p2.l = LO(CFG_MONITOR_BASE); + p2.h = HI(CFG_MONITOR_BASE); + + p3 = 0x04; + p4.l = LO(CFG_MONITOR_BASE + CFG_MONITOR_LEN); + p4.h = HI(CFG_MONITOR_BASE + CFG_MONITOR_LEN); +.Lloop1: + r1 = [p1 ++ p3]; + [p2 ++ p3] = r1; + cc=p2==p4; + if !cc jump .Lloop1; + + /* Initialize BSS section ... we know that memset() does not + * use the BSS, so it is safe to call here. The bootrom LDR + * takes care of clearing things for us. + */ + serial_early_puts("Zero BSS"); + r0.l = __bss_start; + r0.h = __bss_start; + r1 = 0 (x); + r2.l = __bss_end; + r2.h = __bss_end; + r2 = r2 - r0; + call _memset; + +.Lnorelocate: + + /* Setup the actual stack in external memory */ + r0.h = HI(CONFIG_STACKBASE); + r0.l = LO(CONFIG_STACKBASE); + sp = r0; + fp = sp; + + /* Now lower ourselves from the highest interrupt level to + * the lowest. We do this by masking all interrupts but 15, + * setting the 15 handler to "board_init_f", raising the 15 + * interrupt, and then returning from the highest interrupt + * level to the dummy "jump" until the interrupt controller + * services the pending 15 interrupt. + */ + serial_early_puts("Lower to 15"); + r0 = r7; + r1 = r6; + p0.l = LO(EVT15); + p0.h = HI(EVT15); + p1.l = _cpu_init_f; + p1.h = _cpu_init_f; + [p0] = p1; + p2.l = LO(IMASK); + p2.h = HI(IMASK); + p3.l = LO(EVT_IVG15); + p3.h = HI(EVT_IVG15); + [p2] = p3; + raise 15; + p4.l = .LWAIT_HERE; + p4.h = .LWAIT_HERE; + reti = p4; + rti; + +.LWAIT_HERE: + jump .LWAIT_HERE; +ENDPROC(_start) + +LENTRY(_get_pc) + r0 = rets; +#if ANOMALY_05000371 + NOP; + NOP; + NOP; +#endif + rts; +ENDPROC(_get_pc) diff --git a/cpu/blackfin/system_map.S b/cpu/blackfin/system_map.S new file mode 100644 index 0000000000..286d7f34a0 --- /dev/null +++ b/cpu/blackfin/system_map.S @@ -0,0 +1,18 @@ +/* + * system_map.S - optional symbol lookup for debugging + * + * Copyright (c) 2007 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#include <config.h> + +#ifdef CONFIG_DEBUG_DUMP_SYMS +.data +.global _system_map +.type _system_map,@object +_system_map: +#include SYM_FILE +.asciz "" +.size _system_map,.-_system_map +#endif diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c new file mode 100644 index 0000000000..4474fe51d5 --- /dev/null +++ b/cpu/blackfin/traps.c @@ -0,0 +1,353 @@ +/* + * U-boot - traps.c Routines related to interrupts and exceptions + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * This file is based on + * No original Copyright holder listed, + * Probabily original (C) Roman Zippel (assigned DJD, 1999) + * + * Copyright 2003 Metrowerks - for Blackfin + * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca> + * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org> + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <linux/types.h> +#include <asm/traps.h> +#include <asm/cplb.h> +#include <asm/io.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/mpu.h> +#include <asm/mach-common/bits/trace.h> +#include "cpu.h" + +#define trace_buffer_save(x) \ + do { \ + (x) = bfin_read_TBUFCTL(); \ + bfin_write_TBUFCTL((x) & ~TBUFEN); \ + } while (0) + +#define trace_buffer_restore(x) \ + bfin_write_TBUFCTL((x)) + +/* The purpose of this map is to provide a mapping of address<->cplb settings + * rather than an exact map of what is actually addressable on the part. This + * map covers all current Blackfin parts. If you try to access an address that + * is in this map but not actually on the part, you won't get an exception and + * reboot, you'll get an external hardware addressing error and reboot. Since + * only the ends matter (you did something wrong and the board reset), the means + * are largely irrelevant. + */ +struct memory_map { + uint32_t start, end; + uint32_t data_flags, inst_flags; +}; +const struct memory_map const bfin_memory_map[] = { + { /* external memory */ + .start = 0x00000000, + .end = 0x20000000, + .data_flags = SDRAM_DGENERIC, + .inst_flags = SDRAM_IGENERIC, + }, + { /* async banks */ + .start = 0x20000000, + .end = 0x30000000, + .data_flags = SDRAM_EBIU, + .inst_flags = SDRAM_INON_CHBL, + }, + { /* everything on chip */ + .start = 0xE0000000, + .end = 0xFFFFFFFF, + .data_flags = L1_DMEMORY, + .inst_flags = L1_IMEMORY, + } +}; + +void trap_c(struct pt_regs *regs) +{ + uint32_t trapnr = (regs->seqstat & EXCAUSE); + bool data = false; + + switch (trapnr) { + /* 0x26 - Data CPLB Miss */ + case VEC_CPLB_M: + + if (ANOMALY_05000261) { + static uint32_t last_cplb_fault_retx; + /* + * Work around an anomaly: if we see a new DCPLB fault, + * return without doing anything. Then, + * if we get the same fault again, handle it. + */ + if (last_cplb_fault_retx != regs->retx) { + last_cplb_fault_retx = regs->retx; + return; + } + } + + data = true; + /* fall through */ + + /* 0x27 - Instruction CPLB Miss */ + case VEC_CPLB_I_M: { + volatile uint32_t *CPLB_ADDR_BASE, *CPLB_DATA_BASE, *CPLB_ADDR, *CPLB_DATA; + uint32_t new_cplb_addr = 0, new_cplb_data = 0; + static size_t last_evicted; + size_t i; + + new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1); + + for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) { + /* if the exception is inside this range, lets use it */ + if (new_cplb_addr >= bfin_memory_map[i].start && + new_cplb_addr < bfin_memory_map[i].end) + break; + } + if (i == ARRAY_SIZE(bfin_memory_map)) { + printf("%cCPLB exception outside of memory map at 0x%p\n", + (data ? 'D' : 'I'), new_cplb_addr); + bfin_panic(regs); + } else + debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end); + new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags); + + /* Turn the cache off */ + SSYNC(); + if (data) { + asm(" .align 8; "); + *pDMEM_CONTROL &= ~ENDCPLB; + } else { + asm(" .align 8; "); + *pIMEM_CONTROL &= ~ENICPLB; + } + SSYNC(); + + if (data) { + CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0; + CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0; + } else { + CPLB_ADDR_BASE = (uint32_t *)ICPLB_ADDR0; + CPLB_DATA_BASE = (uint32_t *)ICPLB_DATA0; + } + + /* find the next unlocked entry and evict it */ + i = last_evicted & 0xF; + debug("last evicted = %i\n", i); + CPLB_DATA = CPLB_DATA_BASE + i; + while (*CPLB_DATA & CPLB_LOCK) { + debug("skipping %i %p - %08X\n", i, CPLB_DATA, *CPLB_DATA); + i = (i + 1) & 0xF; /* wrap around */ + CPLB_DATA = CPLB_DATA_BASE + i; + } + CPLB_ADDR = CPLB_ADDR_BASE + i; + + debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA); + last_evicted = i + 1; + *CPLB_ADDR = new_cplb_addr; + *CPLB_DATA = new_cplb_data; + + /* dump current table for debugging purposes */ + CPLB_ADDR = CPLB_ADDR_BASE; + CPLB_DATA = CPLB_DATA_BASE; + for (i = 0; i < 16; ++i) + debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++); + + /* Turn the cache back on */ + SSYNC(); + if (data) { + asm(" .align 8; "); + *pDMEM_CONTROL |= ENDCPLB; + } else { + asm(" .align 8; "); + *pIMEM_CONTROL |= ENICPLB; + } + SSYNC(); + + break; + } + + default: + /* All traps come here */ + bfin_panic(regs); + } +} + +#ifdef CONFIG_DEBUG_DUMP +# define ENABLE_DUMP 1 +#else +# define ENABLE_DUMP 0 +#endif + +#ifdef CONFIG_DEBUG_DUMP_SYMS +# define ENABLE_DUMP_SYMS 1 +#else +# define ENABLE_DUMP_SYMS 0 +#endif + +static const char *symbol_lookup(unsigned long addr, unsigned long *caddr) +{ + if (!ENABLE_DUMP_SYMS) + return NULL; + + extern const char system_map[] __attribute__((__weak__)); + const char *sym, *csym; + char *esym; + unsigned long sym_addr; + + sym = system_map; + csym = NULL; + *caddr = 0; + + while (*sym) { + sym_addr = simple_strtoul(sym, &esym, 16); + sym = esym + 1; + if (sym_addr > addr) + break; + *caddr = sym_addr; + csym = sym; + sym += strlen(sym) + 1; + } + + return csym; +} + +static void decode_address(char *buf, unsigned long address) +{ + unsigned long sym_addr; + const char *sym = symbol_lookup(address, &sym_addr); + + if (sym) { + sprintf(buf, "<0x%p> { %s + 0x%x }", address, sym, address - sym_addr); + return; + } + + if (!address) + sprintf(buf, "<0x%p> /* Maybe null pointer? */", address); + else if (address >= CFG_MONITOR_BASE && + address < CFG_MONITOR_BASE + CFG_MONITOR_LEN) + sprintf(buf, "<0x%p> /* somewhere in u-boot */", address); + else + sprintf(buf, "<0x%p> /* unknown address */", address); +} + +void dump(struct pt_regs *fp) +{ + char buf[150]; + size_t i; + + if (!ENABLE_DUMP) + return; + + printf("SEQUENCER STATUS:\n"); + printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", + fp->seqstat, fp->ipend, fp->syscfg); + printf(" HWERRCAUSE: 0x%lx\n", (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P); + printf(" EXCAUSE : 0x%lx\n", (fp->seqstat & EXCAUSE) >> EXCAUSE_P); + for (i = 6; i <= 15; ++i) { + if (fp->ipend & (1 << i)) { + decode_address(buf, bfin_read32(EVT0 + 4*i)); + printf(" physical IVG%i asserted : %s\n", i, buf); + } + } + decode_address(buf, fp->rete); + printf(" RETE: %s\n", buf); + decode_address(buf, fp->retn); + printf(" RETN: %s\n", buf); + decode_address(buf, fp->retx); + printf(" RETX: %s\n", buf); + decode_address(buf, fp->rets); + printf(" RETS: %s\n", buf); + decode_address(buf, fp->pc); + printf(" PC : %s\n", buf); + + if (fp->seqstat & EXCAUSE) { + decode_address(buf, bfin_read_DCPLB_FAULT_ADDR()); + printf("DCPLB_FAULT_ADDR: %s\n", buf); + decode_address(buf, bfin_read_ICPLB_FAULT_ADDR()); + printf("ICPLB_FAULT_ADDR: %s\n", buf); + } + + printf("\nPROCESSOR STATE:\n"); + printf(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", + fp->r0, fp->r1, fp->r2, fp->r3); + printf(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n", + fp->r4, fp->r5, fp->r6, fp->r7); + printf(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n", + fp->p0, fp->p1, fp->p2, fp->p3); + printf(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n", + fp->p4, fp->p5, fp->fp, fp); + printf(" LB0: %08lx LT0: %08lx LC0: %08lx\n", + fp->lb0, fp->lt0, fp->lc0); + printf(" LB1: %08lx LT1: %08lx LC1: %08lx\n", + fp->lb1, fp->lt1, fp->lc1); + printf(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n", + fp->b0, fp->l0, fp->m0, fp->i0); + printf(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n", + fp->b1, fp->l1, fp->m1, fp->i1); + printf(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n", + fp->b2, fp->l2, fp->m2, fp->i2); + printf(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n", + fp->b3, fp->l3, fp->m3, fp->i3); + printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", + fp->a0w, fp->a0x, fp->a1w, fp->a1x); + + printf("USP : %08lx ASTAT: %08lx\n", + fp->usp, fp->astat); + + printf("\n"); +} + +void dump_bfin_trace_buffer(void) +{ + char buf[150]; + unsigned long tflags; + size_t i = 0; + + if (!ENABLE_DUMP) + return; + + trace_buffer_save(tflags); + + printf("Hardware Trace:\n"); + + if (bfin_read_TBUFSTAT() & TBUFCNT) { + for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) { + decode_address(buf, bfin_read_TBUF()); + printf("%4i Target : %s\n", i, buf); + decode_address(buf, bfin_read_TBUF()); + printf(" Source : %s\n", buf); + } + } + + trace_buffer_restore(tflags); +} + +void bfin_panic(struct pt_regs *regs) +{ + if (ENABLE_DUMP) { + unsigned long tflags; + trace_buffer_save(tflags); + } + + puts( + "\n" + "\n" + "\n" + "Ack! Something bad happened to the Blackfin!\n" + "\n" + ); + dump(regs); + dump_bfin_trace_buffer(); + printf( + "\n" + "Please reset the board\n" + "\n" + ); + bfin_reset_or_hang(); +} diff --git a/cpu/blackfin/watchdog.c b/cpu/blackfin/watchdog.c new file mode 100644 index 0000000000..b47c6b688d --- /dev/null +++ b/cpu/blackfin/watchdog.c @@ -0,0 +1,25 @@ +/* + * watchdog.c - driver for Blackfin on-chip watchdog + * + * Copyright (c) 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/blackfin.h> + +#ifdef CONFIG_HW_WATCHDOG +void hw_watchdog_reset(void) +{ + bfin_write_WDOG_STAT(0); +} + +void hw_watchdog_init(void) +{ + bfin_write_WDOG_CNT(5 * get_sclk()); /* 5 second timeout */ + hw_watchdog_reset(); + bfin_write_WDOG_CTL(0x0); +} +#endif diff --git a/cpu/bf537/Makefile b/cpu/leon2/Makefile index 06d1aae4e2..7cc4420179 100644 --- a/cpu/bf537/Makefile +++ b/cpu/leon2/Makefile @@ -1,8 +1,5 @@ -# U-boot - Makefile # -# Copyright (c) 2005-2007 Analog Devices Inc. -# -# (C) Copyright 2000-2004 +# (C) Copyright 2003-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -20,24 +17,23 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -# MA 02110-1301 USA +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA # include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o -COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o i2c.o - -EXTRA = init_sdram_bootrom_initblock.o +START = start.o +SOBJS = +COBJS = cpu_init.o serial.o cpu.o interrupts.o prom.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) START := $(addprefix $(obj),$(START)) -all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA) +all: $(obj).depend $(START) $(LIB) $(LIB): $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) @@ -47,6 +43,12 @@ $(LIB): $(OBJS) # defines $(obj).depend target include $(SRCTREE)/rules.mk +$(START): $(START:.o=.S) + $(CC) -D__ASSEMBLY__ $(DBGFLAGS) $(OPTFLAGS) -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \ + -I$(TOPDIR)/include -fno-builtin -ffreestanding -nostdinc -isystem $(gccincdir) -pipe \ + $(PLATFORM_CPPFLAGS) -Wall -Wstrict-prototypes \ + -I$(TOPDIR)/board -c -o $(START) $(START:.o=.S) + sinclude $(obj).depend ######################################################################### diff --git a/cpu/bf533/config.mk b/cpu/leon2/config.mk index 2caa3cc7d3..30b224a068 100644 --- a/cpu/bf533/config.mk +++ b/cpu/leon2/config.mk @@ -1,8 +1,5 @@ -# U-boot - config.mk # -# Copyright (c) 2005-2007 Analog Devices Inc. -# -# (C) Copyright 2000-2004 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -20,8 +17,10 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -# MA 02110-1301 USA +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA # -PLATFORM_RELFLAGS += -mcpu=bf533 +PLATFORM_RELFLAGS += -fPIC + +PLATFORM_CPPFLAGS += -DCONFIG_LEON diff --git a/cpu/leon2/cpu.c b/cpu/leon2/cpu.c new file mode 100644 index 0000000000..1c1e24b16c --- /dev/null +++ b/cpu/leon2/cpu.c @@ -0,0 +1,58 @@ +/* CPU specific code for the LEON2 CPU + * + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void _reset_reloc(void); + +int checkcpu(void) +{ + /* check LEON version here */ + printf("CPU: LEON2\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +void cpu_reset(void) +{ + /* Interrupts off */ + disable_interrupts(); + + /* jump to restart in flash */ + _reset_reloc(); +} + +int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + cpu_reset(); + + return 1; +} + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/leon2/cpu_init.c b/cpu/leon2/cpu_init.c new file mode 100644 index 0000000000..a24f778c6d --- /dev/null +++ b/cpu/leon2/cpu_init.c @@ -0,0 +1,142 @@ +/* Initializes CPU and basic hardware such as memory + * controllers, IRQ controller and system timer 0. + * + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/asi.h> +#include <asm/leon.h> + +#include <config.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* reset CPU (jump to 0, without reset) */ +void start(void); + +struct { + gd_t gd_area; + bd_t bd; +} global_data; + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers. + * + * Run from FLASH/PROM: + * - until memory controller is set up, only registers avaiable + * - no global variables available for writing + * - constants avaiable + */ + +void cpu_init_f(void) +{ + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + + /* initialize the IRQMP */ + leon2->Interrupt_Force = 0; + leon2->Interrupt_Pending = 0; + leon2->Interrupt_Clear = 0xfffe; /* clear all old pending interrupts */ + leon2->Interrupt_Mask = 0xfffe0000; /* mask all IRQs */ + + /* cache */ + + /* I/O port setup */ +#ifdef LEON2_IO_PORT_DIR + leon2->PIO_Direction = LEON2_IO_PORT_DIR; +#endif +#ifdef LEON2_IO_PORT_DATA + leon2->PIO_Data = LEON2_IO_PORT_DATA; +#endif +#ifdef LEON2_IO_PORT_INT + leon2->PIO_Interrupt = LEON2_IO_PORT_INT; +#else + leon2->PIO_Interrupt = 0; +#endif +} + +void cpu_init_f2(void) +{ + +} + +/* + * initialize higher level parts of CPU like time base and timers + */ +int cpu_init_r(void) +{ + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + + /* initialize prescaler common to all timers to 1MHz */ + leon2->Scaler_Counter = leon2->Scaler_Reload = + (((CONFIG_SYS_CLK_FREQ / 1000) + 500) / 1000) - 1; + + return (0); +} + +/* Uses Timer 0 to get accurate + * pauses. Max 2 raised to 32 ticks + * + */ +void cpu_wait_ticks(unsigned long ticks) +{ + unsigned long start = get_timer(0); + while (get_timer(start) < ticks) ; +} + +/* initiate and setup timer0 interrupt to 1MHz + * Return irq number for timer int or a negative number for + * dealing with self + */ +int timer_interrupt_init_cpu(void) +{ + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + + /* 1ms ticks */ + leon2->Timer_Counter_1 = 0; + leon2->Timer_Reload_1 = 999; /* (((1000000 / 100) - 1)) */ + leon2->Timer_Control_1 = + (LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS | LEON2_TIMER_CTRL_LD); + + return LEON2_TIMER1_IRQNO; +} + +/* + * This function is intended for SHORT delays only. + */ +unsigned long cpu_usec2ticks(unsigned long usec) +{ + /* timer set to 1kHz ==> 1 clk tick = 1 msec */ + if (usec < 1000) + return 1; + return (usec / 1000); +} + +unsigned long cpu_ticks2usec(unsigned long ticks) +{ + /* 1tick = 1usec */ + return ticks * 1000; +} diff --git a/cpu/leon2/interrupts.c b/cpu/leon2/interrupts.c new file mode 100644 index 0000000000..35b375c782 --- /dev/null +++ b/cpu/leon2/interrupts.c @@ -0,0 +1,217 @@ +/* + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * + * (C) Copyright 2006 + * Detlev Zundel, DENX Software Engineering, dzu@denx.de + * + * (C) Copyright -2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 + * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/stack.h> +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <command.h> +#include <asm/irq.h> + +#include <asm/leon.h> + +/* 15 normal irqs and a non maskable interrupt */ +#define NR_IRQS 15 + +struct irq_action { + interrupt_handler_t *handler; + void *arg; + unsigned int count; +}; + +static struct irq_action irq_handlers[NR_IRQS] = { {0}, }; +static int spurious_irq_cnt = 0; +static int spurious_irq = 0; + +static inline unsigned int leon2_get_irqmask(unsigned int irq) +{ + if ((irq < 0) || (irq >= NR_IRQS)) { + return 0; + } else { + return (1 << irq); + } +} + +static void leon2_ic_disable(unsigned int irq) +{ + unsigned int mask, pil; + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + + pil = intLock(); + + /* get mask of interrupt */ + mask = leon2_get_irqmask(irq); + + /* set int level */ + leon2->Interrupt_Mask = + SPARC_NOCACHE_READ(&leon2->Interrupt_Mask) & (~mask); + + intUnlock(pil); +} + +static void leon2_ic_enable(unsigned int irq) +{ + unsigned int mask, pil; + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + + pil = intLock(); + + /* get mask of interrupt */ + mask = leon2_get_irqmask(irq); + + /* set int level */ + leon2->Interrupt_Mask = + SPARC_NOCACHE_READ(&leon2->Interrupt_Mask) | mask; + + intUnlock(pil); +} + +void handler_irq(int irq, struct pt_regs *regs) +{ + if (irq_handlers[irq].handler) { + if (((unsigned int)irq_handlers[irq].handler > CFG_RAM_END) || + ((unsigned int)irq_handlers[irq].handler < CFG_RAM_BASE) + ) { + printf("handler_irq: bad handler: %x, irq number %d\n", + (unsigned int)irq_handlers[irq].handler, irq); + return; + } + irq_handlers[irq].handler(irq_handlers[irq].arg); + irq_handlers[irq].count++; + } else { + spurious_irq_cnt++; + spurious_irq = irq; + } +} + +void leon2_force_int(int irq) +{ + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + + if ((irq >= NR_IRQS) || (irq < 0)) + return; + printf("Forcing interrupt %d\n", irq); + + leon2->Interrupt_Force = + SPARC_NOCACHE_READ(&leon2->Interrupt_Force) | (1 << irq); +} + +/****************************************************************************/ + +int interrupt_init_cpu(void) +{ + return (0); +} + +/****************************************************************************/ + +/* Handle Timer 0 IRQ */ +void timer_interrupt_cpu(void *arg) +{ + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + + leon2->Timer_Control_1 = + (LEON2_TIMER_CTRL_EN | LEON2_TIMER_CTRL_RS | LEON2_TIMER_CTRL_LD); + + /* nothing to do here */ + return; +} + +/****************************************************************************/ + +/* + * Install and free a interrupt handler. + */ + +void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg) +{ + if (irq < 0 || irq >= NR_IRQS) { + printf("irq_install_handler: bad irq number %d\n", irq); + return; + } + + if (irq_handlers[irq].handler != NULL) + printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n", + (ulong) handler, (ulong) irq_handlers[irq].handler); + + if (((unsigned int)handler > CFG_RAM_END) || + ((unsigned int)handler < CFG_RAM_BASE) + ) { + printf("irq_install_handler: bad handler: %x, irq number %d\n", + (unsigned int)handler, irq); + return; + } + irq_handlers[irq].handler = handler; + irq_handlers[irq].arg = arg; + + /* enable irq on LEON2 hardware */ + leon2_ic_enable(irq); + +} + +void irq_free_handler(int irq) +{ + if (irq < 0 || irq >= NR_IRQS) { + printf("irq_free_handler: bad irq number %d\n", irq); + return; + } + + /* disable irq on LEON2 hardware */ + leon2_ic_disable(irq); + + irq_handlers[irq].handler = NULL; + irq_handlers[irq].arg = NULL; +} + +/****************************************************************************/ + +#if defined(CONFIG_CMD_IRQ) +void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + int irq; + unsigned int pil = get_pil(); + printf("PIL level: %u\n\r", pil); + printf("Spurious IRQ: %u, last unknown IRQ: %d\n", + spurious_irq_cnt, spurious_irq); + + puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n"); + + for (irq = 0; irq < NR_IRQS; irq++) { + if (irq_handlers[irq].handler != NULL) { + printf("%02d %08lx %08lx %ld\n", irq, + (unsigned int)irq_handlers[irq].handler, + (unsigned int)irq_handlers[irq].arg, + irq_handlers[irq].count); + } + } +} +#endif diff --git a/cpu/leon2/prom.c b/cpu/leon2/prom.c new file mode 100644 index 0000000000..b03199577f --- /dev/null +++ b/cpu/leon2/prom.c @@ -0,0 +1,1047 @@ +/* prom.c - emulates a sparc v0 PROM for the linux kernel. + * + * Copyright (C) 2003 Konrad Eisele <eiselekd@web.de> + * Copyright (C) 2004 Stefan Holst <mail@s-holst.de> + * Copyright (C) 2007 Daniel Hellstrom <daniel@gaisler.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/prom.h> +#include <asm/machines.h> +#include <asm/srmmu.h> +#include <asm/processor.h> +#include <asm/irq.h> +#include <asm/leon.h> + +#include <config.h> +/* +#define PRINT_ROM_VEC +*/ +extern struct linux_romvec *kernel_arg_promvec; + +#define PROM_PGT __attribute__ ((__section__ (".prom.pgt"))) +#define PROM_TEXT __attribute__ ((__section__ (".prom.text"))) +#define PROM_DATA __attribute__ ((__section__ (".prom.data"))) + +/* for __va */ +extern int __prom_start; +#define PAGE_OFFSET 0xf0000000 +#define phys_base CFG_SDRAM_BASE +#define PROM_OFFS 8192 +#define PROM_SIZE_MASK (PROM_OFFS-1) +#define __va(x) ( \ + (void *)( ((unsigned long)(x))-PROM_OFFS+ \ + (CFG_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \ + ) +#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CFG_PROM_OFFSET-TEXT_BASE)) + +struct property { + char *name; + char *value; + int length; +}; + +struct node { + int level; + struct property *properties; +}; + +static void leon_reboot(char *bcommand); +static void leon_halt(void); +static int leon_nbputchar(int c); +static int leon_nbgetchar(void); + +static int no_nextnode(int node); +static int no_child(int node); +static int no_proplen(int node, char *name); +static int no_getprop(int node, char *name, char *value); +static int no_setprop(int node, char *name, char *value, int len); +static char *no_nextprop(int node, char *name); + +static struct property PROM_TEXT *find_property(int node, char *name); +static int PROM_TEXT leon_strcmp(const char *s1, const char *s2); +static void *PROM_TEXT leon_memcpy(void *dest, const void *src, size_t n); +static void PROM_TEXT leon_reboot_physical(char *bcommand); + +void __inline__ leon_flush_cache_all(void) +{ + __asm__ __volatile__(" flush "); + __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory"); +} + +void __inline__ leon_flush_tlb_all(void) +{ + leon_flush_cache_all(); + __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400), + "i"(ASI_MMUFLUSH):"memory"); +} + +typedef struct { + unsigned int ctx_table[256]; + unsigned int pgd_table[256]; +} sparc_srmmu_setup; + +sparc_srmmu_setup srmmu_tables PROM_PGT = { + {0}, + {0x1e, + 0x10001e, + 0x20001e, + 0x30001e, + 0x40001e, + 0x50001e, + 0x60001e, + 0x70001e, + 0x80001e, + 0x90001e, + 0xa0001e, + 0xb0001e, + 0xc0001e, + 0xd0001e, + 0xe0001e, + 0xf0001e, + 0x100001e, + 0x110001e, + 0x120001e, + 0x130001e, + 0x140001e, + 0x150001e, + 0x160001e, + 0x170001e, + 0x180001e, + 0x190001e, + 0x1a0001e, + 0x1b0001e, + 0x1c0001e, + 0x1d0001e, + 0x1e0001e, + 0x1f0001e, + 0x200001e, + 0x210001e, + 0x220001e, + 0x230001e, + 0x240001e, + 0x250001e, + 0x260001e, + 0x270001e, + 0x280001e, + 0x290001e, + 0x2a0001e, + 0x2b0001e, + 0x2c0001e, + 0x2d0001e, + 0x2e0001e, + 0x2f0001e, + 0x300001e, + 0x310001e, + 0x320001e, + 0x330001e, + 0x340001e, + 0x350001e, + 0x360001e, + 0x370001e, + 0x380001e, + 0x390001e, + 0x3a0001e, + 0x3b0001e, + 0x3c0001e, + 0x3d0001e, + 0x3e0001e, + 0x3f0001e, + 0x400001e, + 0x410001e, + 0x420001e, + 0x430001e, + 0x440001e, + 0x450001e, + 0x460001e, + 0x470001e, + 0x480001e, + 0x490001e, + 0x4a0001e, + 0x4b0001e, + 0x4c0001e, + 0x4d0001e, + 0x4e0001e, + 0x4f0001e, + 0x500001e, + 0x510001e, + 0x520001e, + 0x530001e, + 0x540001e, + 0x550001e, + 0x560001e, + 0x570001e, + 0x580001e, + 0x590001e, + 0x5a0001e, + 0x5b0001e, + 0x5c0001e, + 0x5d0001e, + 0x5e0001e, + 0x5f0001e, + 0x600001e, + 0x610001e, + 0x620001e, + 0x630001e, + 0x640001e, + 0x650001e, + 0x660001e, + 0x670001e, + 0x680001e, + 0x690001e, + 0x6a0001e, + 0x6b0001e, + 0x6c0001e, + 0x6d0001e, + 0x6e0001e, + 0x6f0001e, + 0x700001e, + 0x710001e, + 0x720001e, + 0x730001e, + 0x740001e, + 0x750001e, + 0x760001e, + 0x770001e, + 0x780001e, + 0x790001e, + 0x7a0001e, + 0x7b0001e, + 0x7c0001e, + 0x7d0001e, + 0x7e0001e, + 0x7f0001e, + 0x800001e, + 0x810001e, + 0x820001e, + 0x830001e, + 0x840001e, + 0x850001e, + 0x860001e, + 0x870001e, + 0x880001e, + 0x890001e, + 0x8a0001e, + 0x8b0001e, + 0x8c0001e, + 0x8d0001e, + 0x8e0001e, + 0x8f0001e, + 0x900001e, + 0x910001e, + 0x920001e, + 0x930001e, + 0x940001e, + 0x950001e, + 0x960001e, + 0x970001e, + 0x980001e, + 0x990001e, + 0x9a0001e, + 0x9b0001e, + 0x9c0001e, + 0x9d0001e, + 0x9e0001e, + 0x9f0001e, + 0xa00001e, + 0xa10001e, + 0xa20001e, + 0xa30001e, + 0xa40001e, + 0xa50001e, + 0xa60001e, + 0xa70001e, + 0xa80001e, + 0xa90001e, + 0xaa0001e, + 0xab0001e, + 0xac0001e, + 0xad0001e, + 0xae0001e, + 0xaf0001e, + 0xb00001e, + 0xb10001e, + 0xb20001e, + 0xb30001e, + 0xb40001e, + 0xb50001e, + 0xb60001e, + 0xb70001e, + 0xb80001e, + 0xb90001e, + 0xba0001e, + 0xbb0001e, + 0xbc0001e, + 0xbd0001e, + 0xbe0001e, + 0xbf0001e, + 0xc00001e, + 0xc10001e, + 0xc20001e, + 0xc30001e, + 0xc40001e, + 0xc50001e, + 0xc60001e, + 0xc70001e, + 0xc80001e, + 0xc90001e, + 0xca0001e, + 0xcb0001e, + 0xcc0001e, + 0xcd0001e, + 0xce0001e, + 0xcf0001e, + 0xd00001e, + 0xd10001e, + 0xd20001e, + 0xd30001e, + 0xd40001e, + 0xd50001e, + 0xd60001e, + 0xd70001e, + 0xd80001e, + 0xd90001e, + 0xda0001e, + 0xdb0001e, + 0xdc0001e, + 0xdd0001e, + 0xde0001e, + 0xdf0001e, + 0xe00001e, + 0xe10001e, + 0xe20001e, + 0xe30001e, + 0xe40001e, + 0xe50001e, + 0xe60001e, + 0xe70001e, + 0xe80001e, + 0xe90001e, + 0xea0001e, + 0xeb0001e, + 0xec0001e, + 0xed0001e, + 0xee0001e, + 0xef0001e, + 0x400001e /* default */ + } +}; + +/* a self contained prom info structure */ +struct leon_reloc_func { + struct property *(*find_property) (int node, char *name); + int (*strcmp) (char *s1, char *s2); + void *(*memcpy) (void *dest, const void *src, size_t n); + void (*reboot_physical) (char *cmd); +}; + +struct leon_prom_info { + int freq_khz; + int leon_nctx; + int mids[32]; + int baudrates[2]; + struct leon_reloc_func reloc_funcs; + struct property root_properties[4]; + struct property cpu_properties[7]; +#undef CPUENTRY +#define CPUENTRY(idx) struct property cpu_properties##idx[4] + CPUENTRY(1); + CPUENTRY(2); + CPUENTRY(3); + CPUENTRY(4); + CPUENTRY(5); + CPUENTRY(6); + CPUENTRY(7); + CPUENTRY(8); + CPUENTRY(9); + CPUENTRY(10); + CPUENTRY(11); + CPUENTRY(12); + CPUENTRY(13); + CPUENTRY(14); + CPUENTRY(15); + CPUENTRY(16); + CPUENTRY(17); + CPUENTRY(18); + CPUENTRY(19); + CPUENTRY(20); + CPUENTRY(21); + CPUENTRY(22); + CPUENTRY(23); + CPUENTRY(24); + CPUENTRY(25); + CPUENTRY(26); + CPUENTRY(27); + CPUENTRY(28); + CPUENTRY(29); + CPUENTRY(30); + CPUENTRY(31); + struct idprom idprom; + struct linux_nodeops nodeops; + struct linux_mlist_v0 *totphys_p; + struct linux_mlist_v0 totphys; + struct linux_mlist_v0 *avail_p; + struct linux_mlist_v0 avail; + struct linux_mlist_v0 *prommap_p; + void (*synchook) (void); + struct linux_arguments_v0 *bootargs_p; + struct linux_arguments_v0 bootargs; + struct linux_romvec romvec; + struct node nodes[35]; + char s_device_type[12]; + char s_cpu[4]; + char s_mid[4]; + char s_idprom[7]; + char s_compatability[14]; + char s_leon2[6]; + char s_mmu_nctx[9]; + char s_frequency[16]; + char s_uart1_baud[11]; + char s_uart2_baud[11]; + char arg[256]; +}; + +/* static prom info */ +static struct leon_prom_info PROM_DATA spi = { + CONFIG_SYS_CLK_FREQ / 1000, + 256, + { +#undef CPUENTRY +#define CPUENTRY(idx) idx + CPUENTRY(0), + CPUENTRY(1), + CPUENTRY(2), + CPUENTRY(3), + CPUENTRY(4), + CPUENTRY(5), + CPUENTRY(6), + CPUENTRY(7), + CPUENTRY(8), + CPUENTRY(9), + CPUENTRY(10), + CPUENTRY(11), + CPUENTRY(12), + CPUENTRY(13), + CPUENTRY(14), + CPUENTRY(15), + CPUENTRY(16), + CPUENTRY(17), + CPUENTRY(18), + CPUENTRY(19), + CPUENTRY(20), + CPUENTRY(21), + CPUENTRY(22), + CPUENTRY(23), + CPUENTRY(24), + CPUENTRY(25), + CPUENTRY(26), + CPUENTRY(27), + CPUENTRY(28), + CPUENTRY(29), + CPUENTRY(30), + 31}, + {38400, 38400}, + { + __va(find_property), + __va(leon_strcmp), + __va(leon_memcpy), + __phy(leon_reboot_physical), + }, + { + {__va(spi.s_device_type), __va(spi.s_idprom), 4}, + {__va(spi.s_idprom), (char *)__va(&spi.idprom), sizeof(struct idprom)}, + {__va(spi.s_compatability), __va(spi.s_leon2), 5}, + {NULL, NULL, -1} + }, + { + {__va(spi.s_device_type), __va(spi.s_cpu), 4}, + {__va(spi.s_mid), __va(&spi.mids[0]), 4}, + {__va(spi.s_mmu_nctx), (char *)__va(&spi.leon_nctx), 4}, + {__va(spi.s_frequency), (char *)__va(&spi.freq_khz), 4}, + {__va(spi.s_uart1_baud), (char *)__va(&spi.baudrates[0]), 4}, + {__va(spi.s_uart2_baud), (char *)__va(&spi.baudrates[1]), 4}, + {NULL, NULL, -1} + }, +#undef CPUENTRY +#define CPUENTRY(idx) \ + { /* cpu_properties */ \ + {__va(spi.s_device_type), __va(spi.s_cpu), 4}, \ + {__va(spi.s_mid), __va(&spi.mids[idx]), 4}, \ + {__va(spi.s_frequency), (char *)__va(&spi.freq_khz), 4}, \ + {NULL, NULL, -1} \ + } + CPUENTRY(1), + CPUENTRY(2), + CPUENTRY(3), + CPUENTRY(4), + CPUENTRY(5), + CPUENTRY(6), + CPUENTRY(7), + CPUENTRY(8), + CPUENTRY(9), + CPUENTRY(10), + CPUENTRY(11), + CPUENTRY(12), + CPUENTRY(13), + CPUENTRY(14), + CPUENTRY(15), + CPUENTRY(16), + CPUENTRY(17), + CPUENTRY(18), + CPUENTRY(19), + CPUENTRY(20), + CPUENTRY(21), + CPUENTRY(22), + CPUENTRY(23), + CPUENTRY(24), + CPUENTRY(25), + CPUENTRY(26), + CPUENTRY(27), + CPUENTRY(28), + CPUENTRY(29), + CPUENTRY(30), + CPUENTRY(31), + { + 0x01, /* format */ + M_LEON2 | M_LEON2_SOC, /* machine type */ + {0, 0, 0, 0, 0, 0}, /* eth */ + 0, /* date */ + 0, /* sernum */ + 0, /* checksum */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} /* reserved */ + }, + { + __va(no_nextnode), + __va(no_child), + __va(no_proplen), + __va(no_getprop), + __va(no_setprop), + __va(no_nextprop) + }, + __va(&spi.totphys), + { + NULL, + (char *)CFG_SDRAM_BASE, + 0, + }, + __va(&spi.avail), + { + NULL, + (char *)CFG_SDRAM_BASE, + 0, + }, + NULL, /* prommap_p */ + NULL, + __va(&spi.bootargs), + { + {NULL, __va(spi.arg), NULL /*... */ }, + /*... */ + }, + { + 0, + 0, /* sun4c v0 prom */ + 0, 0, + {__va(&spi.totphys_p), __va(&spi.prommap_p), __va(&spi.avail_p)}, + __va(&spi.nodeops), + NULL, {NULL /* ... */ }, + NULL, NULL, + NULL, NULL, /* pv_getchar, pv_putchar */ + __va(leon_nbgetchar), __va(leon_nbputchar), + NULL, + __va(leon_reboot), + NULL, + NULL, + NULL, + __va(leon_halt), + __va(&spi.synchook), + {NULL}, + __va(&spi.bootargs_p) + /*... */ + }, + { + {0, __va(spi.root_properties + 3) /* NULL, NULL, -1 */ }, + {0, __va(spi.root_properties)}, + /* cpu 0, must be spi.nodes[2] see leon_prom_init() */ + {1, __va(spi.cpu_properties)}, + +#undef CPUENTRY +#define CPUENTRY(idx) \ + {1, __va(spi.cpu_properties##idx) } /* cpu <idx> */ + CPUENTRY(1), + CPUENTRY(2), + CPUENTRY(3), + CPUENTRY(4), + CPUENTRY(5), + CPUENTRY(6), + CPUENTRY(7), + CPUENTRY(8), + CPUENTRY(9), + CPUENTRY(10), + CPUENTRY(11), + CPUENTRY(12), + CPUENTRY(13), + CPUENTRY(14), + CPUENTRY(15), + CPUENTRY(16), + CPUENTRY(17), + CPUENTRY(18), + CPUENTRY(19), + CPUENTRY(20), + CPUENTRY(21), + CPUENTRY(22), + CPUENTRY(23), + CPUENTRY(24), + CPUENTRY(25), + CPUENTRY(26), + CPUENTRY(27), + CPUENTRY(28), + CPUENTRY(29), + CPUENTRY(30), + CPUENTRY(31), + {-1, __va(spi.root_properties + 3) /* NULL, NULL, -1 */ } + }, + "device_type", + "cpu", + "mid", + "idprom", + "compatability", + "leon2", + "mmu-nctx", + "clock-frequency", + "uart1_baud", + "uart2_baud", + CONFIG_DEFAULT_KERNEL_COMMAND_LINE +}; + +/* from arch/sparc/kernel/setup.c */ +#define RAMDISK_LOAD_FLAG 0x4000 +extern unsigned short root_flags; +extern unsigned short root_dev; +extern unsigned short ram_flags; +extern unsigned int sparc_ramdisk_image; +extern unsigned int sparc_ramdisk_size; +extern int root_mountflags; + +extern char initrd_end, initrd_start; + +/* Reboot the CPU = jump to beginning of flash again. + * + * Make sure that all function are inlined here. + */ +static void PROM_TEXT leon_reboot(char *bcommand) +{ + register char *arg = bcommand; + void __attribute__ ((noreturn)) (*reboot_physical) (char *cmd); + + /* get physical address */ + struct leon_prom_info *pspi = + (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + unsigned int *srmmu_ctx_table; + + /* Turn of Interrupts */ + set_pil(0xf); + + /* Set kernel's context, context zero */ + srmmu_set_context(0); + + /* Get physical address of the MMU shutdown routine */ + reboot_physical = (void *) + SPARC_BYPASS_READ(&pspi->reloc_funcs.reboot_physical); + + /* Now that we know the physical address of the function + * we can make the MMU allow jumping to it. + */ + srmmu_ctx_table = (unsigned int *)srmmu_get_ctable_ptr(); + + srmmu_ctx_table = (unsigned int *)SPARC_BYPASS_READ(srmmu_ctx_table); + + /* get physical address of kernel's context table (assume ptd) */ + srmmu_ctx_table = (unsigned int *) + (((unsigned int)srmmu_ctx_table & 0xfffffffc) << 4); + + /* enable access to physical address of MMU shutdown function */ + SPARC_BYPASS_WRITE(&srmmu_ctx_table + [((unsigned int)reboot_physical) >> 24], + (((unsigned int)reboot_physical & 0xff000000) >> 4) | + 0x1e); + + /* flush TLB cache */ + leon_flush_tlb_all(); + + /* flash instruction & data cache */ + sparc_icache_flush_all(); + sparc_dcache_flush_all(); + + /* jump to physical address function + * so that when the MMU is disabled + * we can continue to execute + */ + reboot_physical(arg); +} + +static void PROM_TEXT leon_reboot_physical(char *bcommand) +{ + void __attribute__ ((noreturn)) (*reset) (void); + + /* Turn off MMU */ + srmmu_set_mmureg(0); + + /* Hardcoded start address */ + reset = CFG_MONITOR_BASE; + + /* flush data cache */ + sparc_dcache_flush_all(); + + /* flush instruction cache */ + sparc_icache_flush_all(); + + /* Jump to start in Flash */ + reset(); +} + +static void PROM_TEXT leon_halt(void) +{ + while (1) ; +} + +/* get single char, don't care for blocking*/ +static int PROM_TEXT leon_nbgetchar(void) +{ + return -1; +} + +/* put single char, don't care for blocking*/ +static int PROM_TEXT leon_nbputchar(int c) +{ + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + + /***** put char in buffer... *********** + * Make sure all functions are inline! * + ***************************************/ + + /* Wait for last character to go. */ + while (!(SPARC_BYPASS_READ(&leon2->UART_Status_1) + & LEON2_UART_STAT_THE)) ; + + /* Send data */ + SPARC_BYPASS_WRITE(&leon2->UART_Channel_1, c); + + /* Wait for data to be sent */ + while (!(SPARC_BYPASS_READ(&leon2->UART_Status_1) + & LEON2_UART_STAT_TSE)) ; + + return 0; +} + +/* node ops */ + +/*#define nodes ((struct node *)__va(&pspi->nodes))*/ +#define nodes ((struct node *)(pspi->nodes)) + +static int PROM_TEXT no_nextnode(int node) +{ + /* get physical address */ + struct leon_prom_info *pspi = + (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + /* convert into virtual address */ + pspi = (struct leon_prom_info *) + (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET); + + if (nodes[node].level == nodes[node + 1].level) + return node + 1; + return -1; +} + +static int PROM_TEXT no_child(int node) +{ + /* get physical address */ + struct leon_prom_info *pspi = (struct leon_prom_info *) + (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + /* convert into virtual address */ + pspi = (struct leon_prom_info *) + (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET); + + if (nodes[node].level == nodes[node + 1].level - 1) + return node + 1; + return -1; +} + +static struct property PROM_TEXT *find_property(int node, char *name) +{ + /* get physical address */ + struct leon_prom_info *pspi = (struct leon_prom_info *) + (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + /* convert into virtual address */ + pspi = (struct leon_prom_info *) + (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET); + + struct property *prop = &nodes[node].properties[0]; + while (prop && prop->name) { + if (pspi->reloc_funcs.strcmp(prop->name, name) == 0) + return prop; + prop++; + } + return NULL; +} + +static int PROM_TEXT no_proplen(int node, char *name) +{ + /* get physical address */ + struct leon_prom_info *pspi = (struct leon_prom_info *) + (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + /* convert into virtual address */ + pspi = (struct leon_prom_info *) + (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET); + + struct property *prop = pspi->reloc_funcs.find_property(node, name); + if (prop) + return prop->length; + return -1; +} + +static int PROM_TEXT no_getprop(int node, char *name, char *value) +{ + /* get physical address */ + struct leon_prom_info *pspi = (struct leon_prom_info *) + (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + /* convert into virtual address */ + pspi = (struct leon_prom_info *) + (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET); + + struct property *prop = pspi->reloc_funcs.find_property(node, name); + if (prop) { + pspi->reloc_funcs.memcpy(value, prop->value, prop->length); + return 1; + } + return -1; +} + +static int PROM_TEXT no_setprop(int node, char *name, char *value, int len) +{ + return -1; +} + +static char PROM_TEXT *no_nextprop(int node, char *name) +{ + /* get physical address */ + struct leon_prom_info *pspi = (struct leon_prom_info *) + (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + struct property *prop; + + /* convert into virtual address */ + pspi = (struct leon_prom_info *) + (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET); + + if (!name || !name[0]) + return nodes[node].properties[0].name; + + prop = pspi->reloc_funcs.find_property(node, name); + if (prop) + return prop[1].name; + return NULL; +} + +static int PROM_TEXT leon_strcmp(const char *s1, const char *s2) +{ + register char result; + + while (1) { + result = *s1 - *s2; + if (result || !*s1) + break; + s2++; + s1++; + } + + return result; +} + +static void *PROM_TEXT leon_memcpy(void *dest, const void *src, size_t n) +{ + char *dst = (char *)dest, *source = (char *)src; + + while (n--) { + *dst = *source; + dst++; + source++; + } + return dest; +} + +#define GETREGSP(sp) __asm__ __volatile__("mov %%sp, %0" : "=r" (sp)) + +void leon_prom_init(struct leon_prom_info *pspi) +{ + unsigned long i; + unsigned char cksum, *ptr; + char *addr_str, *end; + unsigned long sp; + GETREGSP(sp); + + pspi->freq_khz = CONFIG_SYS_CLK_FREQ / 1000; + + /* Set Available main memory size */ + pspi->totphys.num_bytes = CFG_PROM_OFFSET - CFG_SDRAM_BASE; + pspi->avail.num_bytes = pspi->totphys.num_bytes; + +#undef nodes + pspi->nodes[3].level = -1; + pspi->nodes[3].properties = __va(spi.root_properties + 3); + + /* Set Ethernet MAC address from environment */ + if ((addr_str = getenv("ethaddr")) != NULL) { + for (i = 0; i < 6; i++) { + pspi->idprom.id_ethaddr[i] = addr_str ? + simple_strtoul(addr_str, &end, 16) : 0; + if (addr_str) { + addr_str = (*end) ? end + 1 : end; + } + } + } else { + /* HW Address not found in environment, + * Set default HW address + */ + pspi->idprom.id_ethaddr[0] = 0; + pspi->idprom.id_ethaddr[1] = 0; + pspi->idprom.id_ethaddr[2] = 0; + pspi->idprom.id_ethaddr[3] = 0; + pspi->idprom.id_ethaddr[4] = 0; + pspi->idprom.id_ethaddr[5] = 0; + } + + ptr = (unsigned char *)&pspi->idprom; + for (i = cksum = 0; i <= 0x0E; i++) + cksum ^= *ptr++; + pspi->idprom.id_cksum = cksum; +} + +static inline void set_cache(unsigned long regval) +{ + asm volatile ("sta %0, [%%g0] %1\n\t":: "r" (regval), "i"(2):"memory"); +} + +extern unsigned short bss_start, bss_end; + +/* mark as section .img.main.text, to be referenced in linker script */ +int prom_init(void) +{ + struct leon_prom_info *pspi = (void *) + ((((unsigned int)&spi) & PROM_SIZE_MASK) + CFG_PROM_OFFSET); + + /* disable mmu */ + srmmu_set_mmureg(0x00000000); + __asm__ __volatile__("flush\n\t"); + + /* init prom info struct */ + leon_prom_init(pspi); + + kernel_arg_promvec = &pspi->romvec; +#ifdef PRINT_ROM_VEC + printf("Kernel rom vec: 0x%lx\n", (unsigned int)(&pspi->romvec)); +#endif + return 0; +} + +/* Copy current kernel boot argument to ROMvec */ +void prepare_bootargs(char *bootargs) +{ + struct leon_prom_info *pspi; + char *src, *dst; + int left; + + /* if no bootargs set, skip copying ==> default bootline */ + if (bootargs && (*bootargs != '\0')) { + pspi = (void *)((((unsigned int)&spi) & PROM_SIZE_MASK) + + CFG_PROM_OFFSET); + src = bootargs; + dst = &pspi->arg[0]; + left = 255; /* max len */ + while (*src && left > 0) { + *dst++ = *src++; + left--; + } + /* terminate kernel command line string */ + *dst = 0; + } +} + +void srmmu_init_cpu(unsigned int entry) +{ + sparc_srmmu_setup *psrmmu_tables = (void *) + ((((unsigned int)&srmmu_tables) & PROM_SIZE_MASK) + + CFG_PROM_OFFSET); + + /* Make context 0 (kernel's context) point + * to our prepared memory mapping + */ +#define PTD 1 + psrmmu_tables->ctx_table[0] = + ((unsigned int)&psrmmu_tables->pgd_table[0x00]) >> 4 | PTD; + + /* Set virtual kernel address 0xf0000000 + * to SRAM/SDRAM address. + * Make it READ/WRITE/EXEC to SuperUser + */ +#define PTE 2 +#define ACC_SU_ALL 0x1c + psrmmu_tables->pgd_table[0xf0] = + (CFG_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf1] = + ((CFG_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf2] = + ((CFG_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf3] = + ((CFG_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf4] = + ((CFG_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf5] = + ((CFG_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf6] = + ((CFG_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf7] = + ((CFG_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE; + + /* convert rom vec pointer to virtual address */ + kernel_arg_promvec = (struct linux_romvec *) + (((unsigned int)kernel_arg_promvec & 0x0fffffff) | 0xf0000000); + + /* Set Context pointer to point to context table + * 256 contexts supported. + */ + srmmu_set_ctable_ptr((unsigned int)&psrmmu_tables->ctx_table[0]); + + /* Set kernel's context, context zero */ + srmmu_set_context(0); + + /* Invalidate all Cache */ + __asm__ __volatile__("flush\n\t"); + + srmmu_set_mmureg(0x00000001); + leon_flush_tlb_all(); + leon_flush_cache_all(); +} diff --git a/cpu/leon2/serial.c b/cpu/leon2/serial.c new file mode 100644 index 0000000000..ce9457f5a9 --- /dev/null +++ b/cpu/leon2/serial.c @@ -0,0 +1,165 @@ +/* GRLIB APBUART Serial controller driver + * + * (C) Copyright 2008 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/leon.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Force cache miss each time a serial controller reg is read */ +#define CACHE_BYPASS 1 + +#ifdef CACHE_BYPASS +#define READ_BYTE(var) SPARC_NOCACHE_READ_BYTE((unsigned int)&(var)) +#define READ_HWORD(var) SPARC_NOCACHE_READ_HWORD((unsigned int)&(var)) +#define READ_WORD(var) SPARC_NOCACHE_READ((unsigned int)&(var)) +#define READ_DWORD(var) SPARC_NOCACHE_READ_DWORD((unsigned int)&(var)) +#endif + +int serial_init(void) +{ + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + LEON2_Uart_regs *regs; + unsigned int tmp; + + /* Init LEON2 UART + * + * Set scaler / baud rate + * + * Receiver & transmitter enable + */ +#if LEON2_CONSOLE_SELECT == LEON_CONSOLE_UART1 + regs = (LEON2_Uart_regs *) & leon2->UART_Channel_1; +#else + regs = (LEON2_Uart_regs *) & leon2->UART_Channel_2; +#endif + + regs->UART_Scaler = CFG_LEON2_UART1_SCALER; + + /* Let bit 11 be unchanged (debug bit for GRMON) */ + tmp = READ_WORD(regs->UART_Control); + + regs->UART_Control = ((tmp & LEON2_UART_CTRL_DBG) | + (LEON2_UART1_LOOPBACK_ENABLE << 7) | + (LEON2_UART1_FLOWCTRL_ENABLE << 6) | + (LEON2_UART1_PARITY_ENABLE << 5) | + (LEON2_UART1_ODDPAR_ENABLE << 4) | + LEON2_UART_CTRL_RE | LEON2_UART_CTRL_TE); + + return 0; +} + +void serial_putc(const char c) +{ + if (c == '\n') + serial_putc_raw('\r'); + + serial_putc_raw(c); +} + +void serial_putc_raw(const char c) +{ + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + LEON2_Uart_regs *regs; + +#if LEON2_CONSOLE_SELECT == LEON_CONSOLE_UART1 + regs = (LEON2_Uart_regs *) & leon2->UART_Channel_1; +#else + regs = (LEON2_Uart_regs *) & leon2->UART_Channel_2; +#endif + + /* Wait for last character to go. */ + while (!(READ_WORD(regs->UART_Status) & LEON2_UART_STAT_THE)) ; + + /* Send data */ + regs->UART_Channel = c; + +#ifdef LEON_DEBUG + /* Wait for data to be sent */ + while (!(READ_WORD(regs->UART_Status) & LEON2_UART_STAT_TSE)) ; +#endif +} + +void serial_puts(const char *s) +{ + while (*s) { + serial_putc(*s++); + } +} + +int serial_getc(void) +{ + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + LEON2_Uart_regs *regs; + +#if LEON2_CONSOLE_SELECT == LEON_CONSOLE_UART1 + regs = (LEON2_Uart_regs *) & leon2->UART_Channel_1; +#else + regs = (LEON2_Uart_regs *) & leon2->UART_Channel_2; +#endif + + /* Wait for a character to arrive. */ + while (!(READ_WORD(regs->UART_Status) & LEON2_UART_STAT_DR)) ; + + /* read data */ + return READ_WORD(regs->UART_Channel); +} + +int serial_tstc(void) +{ + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + LEON2_Uart_regs *regs; + +#if LEON2_CONSOLE_SELECT == LEON_CONSOLE_UART1 + regs = (LEON2_Uart_regs *) & leon2->UART_Channel_1; +#else + regs = (LEON2_Uart_regs *) & leon2->UART_Channel_2; +#endif + + return (READ_WORD(regs->UART_Status) & LEON2_UART_STAT_DR); +} + +/* set baud rate for uart */ +void serial_setbrg(void) +{ + /* update baud rate settings, read it from gd->baudrate */ + unsigned int scaler; + LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; + LEON2_Uart_regs *regs; + +#if LEON2_CONSOLE_SELECT == LEON_CONSOLE_UART1 + regs = (LEON2_Uart_regs *) & leon2->UART_Channel_1; +#else + regs = (LEON2_Uart_regs *) & leon2->UART_Channel_2; +#endif + + if (gd->baudrate > 0) { + scaler = + (((CONFIG_SYS_CLK_FREQ * 10) / (gd->baudrate * 8)) - + 5) / 10; + regs->UART_Scaler = scaler; + } +} diff --git a/cpu/leon2/start.S b/cpu/leon2/start.S new file mode 100644 index 0000000000..60d3fadef4 --- /dev/null +++ b/cpu/leon2/start.S @@ -0,0 +1,661 @@ +/* This is where the SPARC/LEON3 starts + * Copyright (C) 2007, + * Daniel Hellstrom, daniel@gaisler.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/asmmacro.h> +#include <asm/winmacro.h> +#include <asm/psr.h> +#include <asm/stack.h> +#include <asm/leon.h> +#include <version.h> + +/* Entry for traps which jump to a programmer-specified trap handler. */ +#define TRAPR(H) \ + wr %g0, 0xfe0, %psr; \ + mov %g0, %tbr; \ + ba (H); \ + mov %g0, %wim; + +#define TRAP(H) \ + mov %psr, %l0; \ + ba (H); \ + nop; nop; + +#define TRAPI(ilevel) \ + mov ilevel, %l7; \ + mov %psr, %l0; \ + b _irq_entry; \ + mov %wim, %l3 + +/* Unexcpected trap will halt the processor by forcing it to error state */ +#undef BAD_TRAP +#define BAD_TRAP ta 0; nop; nop; nop; + +/* Software trap. Treat as BAD_TRAP for the time being... */ +#define SOFT_TRAP TRAP(_hwerr) + +#define PSR_INIT 0x1FC0 /* Disable traps, set s and ps */ +#define WIM_INIT 2 + +/* All traps low-level code here must end with this macro. */ +#define RESTORE_ALL b ret_trap_entry; clr %l6; + +#define WRITE_PAUSE nop;nop;nop + +WINDOWSIZE = (16 * 4) +ARGPUSHSIZE = (6 * 4) +ARGPUSH = (WINDOWSIZE + 4) +MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4) + +/* Number of register windows */ +#ifndef CFG_SPARC_NWINDOWS +#error Must define number of SPARC register windows, default is 8 +#endif + +#define STACK_ALIGN 8 +#define SA(X) (((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1)) + + .section ".start", "ax" + .globl _start, start, _trap_table + .globl _irq_entry, nmi_trap + .globl _reset_reloc + +/* at address 0 + * Hardware traps + */ +start: +_start: +_trap_table: + TRAPR(_hardreset); ! 00 reset trap + BAD_TRAP; ! 01 instruction_access_exception + BAD_TRAP; ! 02 illegal_instruction + BAD_TRAP; ! 03 priveleged_instruction + BAD_TRAP; ! 04 fp_disabled + TRAP(_window_overflow); ! 05 window_overflow + TRAP(_window_underflow); ! 06 window_underflow + BAD_TRAP; ! 07 Memory Address Not Aligned + BAD_TRAP; ! 08 Floating Point Exception + BAD_TRAP; ! 09 Data Miss Exception + BAD_TRAP; ! 0a Tagged Instruction Ovrflw + BAD_TRAP; ! 0b Watchpoint Detected + BAD_TRAP; ! 0c + BAD_TRAP; ! 0d + BAD_TRAP; ! 0e + BAD_TRAP; ! 0f + BAD_TRAP; ! 10 + TRAPI(1); ! 11 IRQ level 1 + TRAPI(2); ! 12 IRQ level 2 + TRAPI(3); ! 13 IRQ level 3 + TRAPI(4); ! 14 IRQ level 4 + TRAPI(5); ! 15 IRQ level 5 + TRAPI(6); ! 16 IRQ level 6 + TRAPI(7); ! 17 IRQ level 7 + TRAPI(8); ! 18 IRQ level 8 + TRAPI(9); ! 19 IRQ level 9 + TRAPI(10); ! 1a IRQ level 10 + TRAPI(11); ! 1b IRQ level 11 + TRAPI(12); ! 1c IRQ level 12 + TRAPI(13); ! 1d IRQ level 13 + TRAPI(14); ! 1e IRQ level 14 + TRAP(_nmi_trap); ! 1f IRQ level 15 / + ! NMI (non maskable interrupt) + BAD_TRAP; ! 20 r_register_access_error + BAD_TRAP; ! 21 instruction access error + BAD_TRAP; ! 22 + BAD_TRAP; ! 23 + BAD_TRAP; ! 24 co-processor disabled + BAD_TRAP; ! 25 uniplemented FLUSH + BAD_TRAP; ! 26 + BAD_TRAP; ! 27 + BAD_TRAP; ! 28 co-processor exception + BAD_TRAP; ! 29 data access error + BAD_TRAP; ! 2a division by zero + BAD_TRAP; ! 2b data store error + BAD_TRAP; ! 2c data access MMU miss + BAD_TRAP; ! 2d + BAD_TRAP; ! 2e + BAD_TRAP; ! 2f + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30-33 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34-37 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38-3b + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3c-3f + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40-43 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44-47 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48-4b + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4c-4f + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50-53 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54-57 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58-5b + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5c-5f + + /* implementaion dependent */ + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60-63 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64-67 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68-6b + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6c-6f + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70-73 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74-77 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78-7b + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 7c-7f + + /* Software traps, not handled */ + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 80-83 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84-87 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88-8b + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8c-8f + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90-93 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94-97 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98-9b + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9c-9f + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! a0-a3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! a4-a7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! a8-ab + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! ac-af + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! b0-b3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! b4-b7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! b8-bb + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! bc-bf + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! c0-c3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! c4-c7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! c8-cb + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! cc-cf + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! d0-d3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! d4-d7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! d8-db + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! dc-df + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! e0-e3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! e4-e7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! e8-eb + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! ec-ef + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f0-f3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f4-f7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f8-fb + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! fc-ff +/* + * Version string + */ + + .data + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + .section ".text" + .align 4 + +_hardreset: +1000: + flush + nop + nop + nop + + /* Init Cache */ + set (LEON2_PREGS+LEON_REG_CACHECTRL_OFFSET), %g1 + set 0x0081000f, %g2 + st %g2, [%g1] + + mov %g0, %y + clr %g1 + clr %g2 + clr %g3 + clr %g4 + clr %g5 + clr %g6 + clr %g7 + + mov %asr17, %g3 + and %g3, 0x1f, %g3 +clear_window: + mov %g0, %l0 + mov %g0, %l1 + mov %g0, %l2 + mov %g0, %l3 + mov %g0, %l4 + mov %g0, %l5 + mov %g0, %l6 + mov %g0, %l7 + mov %g0, %o0 + mov %g0, %o1 + mov %g0, %o2 + mov %g0, %o3 + mov %g0, %o4 + mov %g0, %o5 + mov %g0, %o6 + mov %g0, %o7 + subcc %g3, 1, %g3 + bge clear_window + save + +leon2_init: + /* LEON2 Register Base in g1 */ + set LEON2_PREGS, %g1 + +leon2_init_cache: + /* Set Cache control register */ + set 0x1000f, %g2 + st %g2, [%g1 + 0x14] + +leon2_init_clear: + + /* Clear LEON2 registers */ + st %g0, [%g1 + LEON2_ECTRL] + st %g0, [%g1 + LEON2_IMASK] + st %g0, [%g1 + LEON2_IPEND] + st %g0, [%g1 + LEON2_IFORCE] + st %g0, [%g1 + LEON2_ICLEAR] + st %g0, [%g1 + LEON2_IOREG] + st %g0, [%g1 + LEON2_IODIR] + st %g0, [%g1 + LEON2_IOICONF] + st %g0, [%g1 + LEON2_UCTRL0] + st %g0, [%g1 + LEON2_UCTRL1] + +leon2_init_ioport: + /* I/O port initialization */ + set 0xaa00, %g2 + st %g2, [%g1 + LEON2_IOREG] + +leon2_init_mctrl: + + /* memory config register 1 */ + set CFG_GRLIB_MEMCFG1, %g2 + ld [%g1], %g3 ! + and %g3, 0x300, %g3 + or %g2, %g3, %g2 + st %g2, [%g1 + LEON2_MCFG1] + set CFG_GRLIB_MEMCFG2, %g2 ! Load memory config register 2 +#if !( defined(TSIM) || !defined(BZIMAGE)) + st %g2, [%g1 + LEON2_MCFG2] ! only for prom version, else done by "dumon -i" +#endif + set CFG_GRLIB_MEMCFG3, %g2 ! Init FT register + st %g2, [%g1 + LEON2_ECTRL] + ld [%g1 + LEON2_ECTRL], %g2 + srl %g2, 30, %g2 + andcc %g2, 3, %g6 + bne,a leon2_init_wim + mov %g0, %asr16 ! clear err_reg + +leon2_init_wim: + set WIM_INIT, %g3 + mov %g3, %wim + +leon2_init_psr: + set 0x1000, %g3 + mov %psr, %g2 + wr %g2, %g3, %psr + nop + nop + nop + +leon2_init_stackp: + set CFG_INIT_SP_OFFSET, %fp + andn %fp, 0x0f, %fp + sub %fp, 64, %sp + +cpu_init_unreloc: + call cpu_init_f + nop + +/* un relocated start address of monitor */ +#define TEXT_START _text + +/* un relocated end address of monitor */ +#define DATA_END __init_end + +reloc: + set TEXT_START,%g2 + set DATA_END,%g3 + set CFG_RELOC_MONITOR_BASE,%g4 +reloc_loop: + ldd [%g2],%l0 + ldd [%g2+8],%l2 + std %l0,[%g4] + std %l2,[%g4+8] + inc 16,%g2 + subcc %g3,%g2,%g0 + bne reloc_loop + inc 16,%g4 + + clr %l0 + clr %l1 + clr %l2 + clr %l3 + clr %g2 + +/* register g4 contain address to start + * This means that BSS must be directly after data and code segments + * + * g3 is length of bss = (__bss_end-__bss_start) + * + */ + +clr_bss: +/* clear bss area (the relocated) */ + set __bss_start,%g2 + set __bss_end,%g3 + sub %g3,%g2,%g3 + add %g3,%g4,%g3 + clr %g1 /* std %g0 uses g0 and g1 */ +/* clearing 16byte a time ==> linker script need to align to 16 byte offset */ +clr_bss_16: + std %g0,[%g4] + std %g0,[%g4+8] + inc 16,%g4 + cmp %g3,%g4 + bne clr_bss_16 + nop + +/* add offsets to GOT table */ +fixup_got: + set __got_start,%g4 + set __got_end,%g3 +/* + * new got offset = (old GOT-PTR (read with ld) - + * CFG_RELOC_MONITOR_BASE(from define) ) + + * Destination Address (from define) + */ + set CFG_RELOC_MONITOR_BASE,%g2 + set TEXT_START, %g1 + add %g4,%g2,%g4 + sub %g4,%g1,%g4 + add %g3,%g2,%g3 + sub %g3,%g1,%g3 + sub %g2,%g1,%g2 ! prepare register with (new base address) - + ! (old base address) +got_loop: + ld [%g4],%l0 ! load old GOT-PTR + add %l0,%g2,%l0 ! increase with (new base address) - + ! (old base) + st %l0,[%g4] + inc 4,%g4 + cmp %g3,%g4 + bne got_loop + nop + +prom_relocate: + set __prom_start, %g2 + set __prom_end, %g3 + set CFG_PROM_OFFSET, %g4 + +prom_relocate_loop: + ldd [%g2],%l0 + ldd [%g2+8],%l2 + std %l0,[%g4] + std %l2,[%g4+8] + inc 16,%g2 + subcc %g3,%g2,%g0 + bne prom_relocate_loop + inc 16,%g4 + +/* Trap table has been moved, lets tell CPU about + * the new trap table address + */ + + set CFG_RELOC_MONITOR_BASE, %g2 + wr %g0, %g2, %tbr + +/* call relocate*/ + nop +/* Call relocated init functions */ +jump: + set cpu_init_f2,%o1 + set CFG_RELOC_MONITOR_BASE,%o2 + add %o1,%o2,%o1 + sub %o1,%g1,%o1 + call %o1 + clr %o0 + + set board_init_f,%o1 + set CFG_RELOC_MONITOR_BASE,%o2 + add %o1,%o2,%o1 + sub %o1,%g1,%o1 + call %o1 + clr %o0 + +dead: ta 0 ! if call returns... + nop + +/* Interrupt handler caller, + * reg L7: interrupt number + * reg L0: psr after interrupt + * reg L1: PC + * reg L2: next PC + * reg L3: wim + */ +_irq_entry: + SAVE_ALL + + or %l0, PSR_PIL, %g2 + wr %g2, 0x0, %psr + WRITE_PAUSE + wr %g2, PSR_ET, %psr + WRITE_PAUSE + mov %l7, %o0 ! irq level + set handler_irq, %o1 + set (CFG_RELOC_MONITOR_BASE-TEXT_BASE), %o2 + add %o1, %o2, %o1 + call %o1 + add %sp, SF_REGS_SZ, %o1 ! pt_regs ptr + or %l0, PSR_PIL, %g2 ! restore PIL after handler_irq + wr %g2, PSR_ET, %psr ! keep ET up + WRITE_PAUSE + + RESTORE_ALL + +!Window overflow trap handler. + .global _window_overflow + +_window_overflow: + + mov %wim, %l3 ! Calculate next WIM + mov %g1, %l7 + srl %l3, 1, %g1 + sll %l3, (CFG_SPARC_NWINDOWS-1) , %l4 + or %l4, %g1, %g1 + + save ! Get into window to be saved. + mov %g1, %wim + nop; + nop; + nop + st %l0, [%sp + 0]; + st %l1, [%sp + 4]; + st %l2, [%sp + 8]; + st %l3, [%sp + 12]; + st %l4, [%sp + 16]; + st %l5, [%sp + 20]; + st %l6, [%sp + 24]; + st %l7, [%sp + 28]; + st %i0, [%sp + 32]; + st %i1, [%sp + 36]; + st %i2, [%sp + 40]; + st %i3, [%sp + 44]; + st %i4, [%sp + 48]; + st %i5, [%sp + 52]; + st %i6, [%sp + 56]; + st %i7, [%sp + 60]; + restore ! Go back to trap window. + mov %l7, %g1 + jmp %l1 ! Re-execute save. + rett %l2 + +/* Window underflow trap handler. */ + + .global _window_underflow + +_window_underflow: + + mov %wim, %l3 ! Calculate next WIM + sll %l3, 1, %l4 + srl %l3, (CFG_SPARC_NWINDOWS-1), %l5 + or %l5, %l4, %l5 + mov %l5, %wim + nop; nop; nop + restore ! Two restores to get into the + restore ! window to restore + ld [%sp + 0], %l0; ! Restore window from the stack + ld [%sp + 4], %l1; + ld [%sp + 8], %l2; + ld [%sp + 12], %l3; + ld [%sp + 16], %l4; + ld [%sp + 20], %l5; + ld [%sp + 24], %l6; + ld [%sp + 28], %l7; + ld [%sp + 32], %i0; + ld [%sp + 36], %i1; + ld [%sp + 40], %i2; + ld [%sp + 44], %i3; + ld [%sp + 48], %i4; + ld [%sp + 52], %i5; + ld [%sp + 56], %i6; + ld [%sp + 60], %i7; + save ! Get back to the trap window. + save + jmp %l1 ! Re-execute restore. + rett %l2 + + retl + +_nmi_trap: + nop + jmp %l1 + rett %l2 + +_hwerr: + ta 0 + nop + nop + b _hwerr ! loop infinite + nop + +/* Registers to not touch at all. */ +#define t_psr l0 /* Set by caller */ +#define t_pc l1 /* Set by caller */ +#define t_npc l2 /* Set by caller */ +#define t_wim l3 /* Set by caller */ +#define t_twinmask l4 /* Set at beginning of this entry routine. */ +#define t_kstack l5 /* Set right before pt_regs frame is built */ +#define t_retpc l6 /* If you change this, change winmacro.h header file */ +#define t_systable l7 /* Never touch this, could be the syscall table ptr. */ +#define curptr g6 /* Set after pt_regs frame is built */ + +trap_setup: +/* build a pt_regs trap frame. */ + sub %fp, (SF_REGS_SZ + PT_REGS_SZ), %t_kstack + PT_STORE_ALL(t_kstack, t_psr, t_pc, t_npc, g2) + + /* See if we are in the trap window. */ + mov 1, %t_twinmask + sll %t_twinmask, %t_psr, %t_twinmask ! t_twinmask = (1 << psr) + andcc %t_twinmask, %t_wim, %g0 + beq 1f ! in trap window, clean up + nop + + /*------------------------------------------------- + * Spill , adjust %wim and go. + */ + srl %t_wim, 0x1, %g2 ! begin computation of new %wim + + set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1 + + sll %t_wim, %g3, %t_wim ! NWINDOWS-1 + or %t_wim, %g2, %g2 + and %g2, 0xff, %g2 + + save %g0, %g0, %g0 ! get in window to be saved + + /* Set new %wim value */ + wr %g2, 0x0, %wim + + /* Save the kernel window onto the corresponding stack. */ + RW_STORE(sp) + + restore %g0, %g0, %g0 + /*-------------------------------------------------*/ + +1: + /* Trap from kernel with a window available. + * Just do it... + */ + jmpl %t_retpc + 0x8, %g0 ! return to caller + mov %t_kstack, %sp ! jump onto new stack + +#define twin_tmp1 l4 +#define glob_tmp g4 +#define curptr g6 +ret_trap_entry: + wr %t_psr, 0x0, %psr ! enable nesting again, clear ET + + /* Will the rett land us in the invalid window? */ + mov 2, %g1 + sll %g1, %t_psr, %g1 + + set CFG_SPARC_NWINDOWS, %g2 !NWINDOWS + + srl %g1, %g2, %g2 + or %g1, %g2, %g1 + rd %wim, %g2 + andcc %g2, %g1, %g0 + be 1f ! Nope, just return from the trap + sll %g2, 0x1, %g1 + + /* We have to grab a window before returning. */ + set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1 + + srl %g2, %g3, %g2 + or %g1, %g2, %g1 + and %g1, 0xff, %g1 + + wr %g1, 0x0, %wim + + /* Grrr, make sure we load from the right %sp... */ + PT_LOAD_ALL(sp, t_psr, t_pc, t_npc, g1) + + restore %g0, %g0, %g0 + RW_LOAD(sp) + b 2f + save %g0, %g0, %g0 + + /* Reload the entire frame in case this is from a + * kernel system call or whatever... + */ +1: + PT_LOAD_ALL(sp, t_psr, t_pc, t_npc, g1) +2: + wr %t_psr, 0x0, %psr + nop; + nop; + nop + + jmp %t_pc + rett %t_npc + +/* This is called from relocated C-code. + * It resets the system by jumping to _start + */ +_reset_reloc: + set start, %l0 + call %l0 + nop diff --git a/cpu/leon3/Makefile b/cpu/leon3/Makefile new file mode 100644 index 0000000000..182543dd10 --- /dev/null +++ b/cpu/leon3/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +SOBJS = +COBJS = cpu_init.o serial.o cpu.o ambapp.o interrupts.o prom.o usb_uhci.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +$(START): $(START:.o=.S) + $(CC) -D__ASSEMBLY__ $(DBGFLAGS) $(OPTFLAGS) -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \ + -I$(TOPDIR)/include -fno-builtin -ffreestanding -nostdinc -isystem $(gccincdir) -pipe \ + $(PLATFORM_CPPFLAGS) -Wall -Wstrict-prototypes \ + -I$(TOPDIR)/board -c -o $(START) $(START:.o=.S) + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/leon3/ambapp.c b/cpu/leon3/ambapp.c new file mode 100644 index 0000000000..efd41ae0a8 --- /dev/null +++ b/cpu/leon3/ambapp.c @@ -0,0 +1,359 @@ +/* Gaisler AMBA Plug&Play bus scanning. Functions + * ending on _nomem is inteded to be used only during + * initialization, only registers are used (no ram). + * + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <ambapp.h> + +#if defined(CONFIG_CMD_AMBAPP) +extern void ambapp_print_apb(apbctrl_pp_dev * apb, + ambapp_ahbdev * apbmst, int index); +extern void ambapp_print_ahb(ahbctrl_pp_dev * ahb, int index); +extern int ambapp_apb_print; +extern int ambapp_ahb_print; +#endif + +static int ambapp_apb_scan(unsigned int vendor, /* Plug&Play Vendor ID */ + unsigned int driver, /* Plug&Play Device ID */ + ambapp_apbdev * dev, /* Result(s) is placed here */ + int index, /* Index of device to start copying Plug&Play + * info into dev + */ + int max_cnt /* Maximal count that dev can hold, if dev + * is NULL function will stop scanning after + * max_cnt devices are found. + */ + ) +{ + int i, cnt = 0; + unsigned int apbmst_base; + ambapp_ahbdev apbmst; + apbctrl_pp_dev *apb; + + if (max_cnt == 0) + return 0; + + /* Get AMBA APB Master */ + if (ambapp_ahbslv_first(VENDOR_GAISLER, GAISLER_APBMST, &apbmst) != 1) { + return 0; + } + + /* Get APB CTRL Plug&Play info area */ + apbmst_base = apbmst.address[0] & LEON3_IO_AREA; + apb = (apbctrl_pp_dev *) (apbmst_base | LEON3_CONF_AREA); + + for (i = 0; i < LEON3_APB_SLAVES; i++) { +#if defined(CONFIG_CMD_AMBAPP) + if (ambapp_apb_print && amba_vendor(apb->conf) + && amba_device(apb->conf)) { + ambapp_print_apb(apb, &apbmst, i); + } +#endif + if ((amba_vendor(apb->conf) == vendor) && + (amba_device(apb->conf) == driver) && ((index < 0) + || (index-- == 0))) { + /* Convert Plug&Play info into a more readable format */ + cnt++; + if (dev) { + dev->irq = amba_irq(apb->conf); + dev->ver = amba_ver(apb->conf); + dev->address = + (apbmst_base | + (((apb-> + bar & 0xfff00000) >> 12))) & (((apb-> + bar & + 0x0000fff0) + << 4) | + 0xfff00000); + dev++; + } + /* found max devices? */ + if (cnt >= max_cnt) + return cnt; + } + /* Get next Plug&Play entry */ + apb++; + } + return cnt; +} + +unsigned int ambapp_apb_next_nomem(register unsigned int vendor, /* Plug&Play Vendor ID */ + register unsigned int driver, /* Plug&Play Device ID */ + register int index) +{ + register int i; + register ahbctrl_pp_dev *apbmst; + register apbctrl_pp_dev *apb; + register unsigned int apbmst_base; + + /* APBMST is a AHB Slave */ + apbmst = ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_APBMST, 1, 0); + if (!apbmst) + return 0; + + apbmst_base = amba_membar_start(apbmst->bars[0]); + if (amba_membar_type(apbmst->bars[0]) == AMBA_TYPE_AHBIO) + apbmst_base = AMBA_TYPE_AHBIO_ADDR(apbmst_base); + apbmst_base &= LEON3_IO_AREA; + + /* Find the vendor/driver device on the first APB bus */ + apb = (apbctrl_pp_dev *) (apbmst_base | LEON3_CONF_AREA); + + for (i = 0; i < LEON3_APB_SLAVES; i++) { + if ((amba_vendor(apb->conf) == vendor) && + (amba_device(apb->conf) == driver) && ((index < 0) + || (index-- == 0))) { + /* Convert Plug&Play info info a more readable format */ + return (apbmst_base | (((apb->bar & 0xfff00000) >> 12))) + & (((apb->bar & 0x0000fff0) << 4) | 0xfff00000); + } + /* Get next Plug&Play entry */ + apb++; + } + return 0; +} + +/****************************** APB SLAVES ******************************/ + +int ambapp_apb_count(unsigned int vendor, unsigned int driver) +{ + return ambapp_apb_scan(vendor, driver, NULL, 0, LEON3_APB_SLAVES); +} + +int ambapp_apb_first(unsigned int vendor, + unsigned int driver, ambapp_apbdev * dev) +{ + return ambapp_apb_scan(vendor, driver, dev, 0, 1); +} + +int ambapp_apb_next(unsigned int vendor, + unsigned int driver, ambapp_apbdev * dev, int index) +{ + return ambapp_apb_scan(vendor, driver, dev, index, 1); +} + +int ambapp_apbs_first(unsigned int vendor, + unsigned int driver, ambapp_apbdev * dev, int max_cnt) +{ + return ambapp_apb_scan(vendor, driver, dev, 0, max_cnt); +} + +enum { + AHB_SCAN_MASTER = 0, + AHB_SCAN_SLAVE = 1 +}; + +/* Scan AMBA Plug&Play bus for AMBA AHB Masters or AHB Slaves + * for a certain matching Vendor and Device ID. + * + * Return number of devices found. + * + * Compact edition... + */ +static int ambapp_ahb_scan(unsigned int vendor, /* Plug&Play Vendor ID */ + unsigned int driver, /* Plug&Play Device ID */ + ambapp_ahbdev * dev, /* Result(s) is placed here */ + int index, /* Index of device to start copying Plug&Play + * info into dev + */ + int max_cnt, /* Maximal count that dev can hold, if dev + * is NULL function will stop scanning after + * max_cnt devices are found. + */ + int type /* Selectes what type of devices to scan. + * 0=AHB Masters + * 1=AHB Slaves + */ + ) +{ + int i, j, cnt = 0, max_pp_devs; + unsigned int addr; + ahbctrl_info *info = (ahbctrl_info *) (LEON3_IO_AREA | LEON3_CONF_AREA); + ahbctrl_pp_dev *ahb; + + if (max_cnt == 0) + return 0; + + if (type == 0) { + max_pp_devs = LEON3_AHB_MASTERS; + ahb = info->masters; + } else { + max_pp_devs = LEON3_AHB_SLAVES; + ahb = info->slaves; + } + + for (i = 0; i < max_pp_devs; i++) { +#if defined(CONFIG_CMD_AMBAPP) + if (ambapp_ahb_print && amba_vendor(ahb->conf) && + amba_device(ahb->conf)) { + ambapp_print_ahb(ahb, i); + } +#endif + if ((amba_vendor(ahb->conf) == vendor) && + (amba_device(ahb->conf) == driver) && + ((index < 0) || (index-- == 0))) { + /* Convert Plug&Play info info a more readable format */ + cnt++; + if (dev) { + dev->irq = amba_irq(ahb->conf); + dev->ver = amba_ver(ahb->conf); + dev->userdef[0] = ahb->userdef[0]; + dev->userdef[1] = ahb->userdef[1]; + dev->userdef[2] = ahb->userdef[2]; + for (j = 0; j < 4; j++) { + addr = amba_membar_start(ahb->bars[j]); + if (amba_membar_type(ahb->bars[j]) == + AMBA_TYPE_AHBIO) + addr = + AMBA_TYPE_AHBIO_ADDR(addr); + dev->address[j] = addr; + } + dev++; + } + /* found max devices? */ + if (cnt >= max_cnt) + return cnt; + } + /* Get next Plug&Play entry */ + ahb++; + } + return cnt; +} + +unsigned int ambapp_ahb_get_info(ahbctrl_pp_dev * ahb, int info) +{ + register unsigned int ret; + + if (!ahb) + return 0; + + switch (info) { + default: + info = 0; + case 0: + case 1: + case 2: + case 3: + /* Get Address from PnP Info */ + ret = amba_membar_start(ahb->bars[info]); + if (amba_membar_type(ahb->bars[info]) == AMBA_TYPE_AHBIO) + ret = AMBA_TYPE_AHBIO_ADDR(ret); + return ret; + } + return 0; + +} + +ahbctrl_pp_dev *ambapp_ahb_next_nomem(register unsigned int vendor, /* Plug&Play Vendor ID */ + register unsigned int driver, /* Plug&Play Device ID */ + register unsigned int opts, /* 1=slave, 0=master */ + register int index) +{ + register ahbctrl_pp_dev *ahb; + register ahbctrl_info *info = + (ahbctrl_info *) (LEON3_IO_AREA | LEON3_CONF_AREA); + register int i; + register int max_pp_devs; + + if (opts == 0) { + max_pp_devs = LEON3_AHB_MASTERS; + ahb = info->masters; + } else { + max_pp_devs = LEON3_AHB_SLAVES; + ahb = info->slaves; + } + + for (i = 0; i < max_pp_devs; i++) { + if ((amba_vendor(ahb->conf) == vendor) && + (amba_device(ahb->conf) == driver) && + ((index < 0) || (index-- == 0))) { + /* Convert Plug&Play info info a more readable format */ + return ahb; + } + /* Get next Plug&Play entry */ + ahb++; + } + return 0; +} + +/****************************** AHB MASTERS ******************************/ +int ambapp_ahbmst_count(unsigned int vendor, unsigned int driver) +{ + /* Get number of devices of this vendor&device ID */ + return ambapp_ahb_scan(vendor, driver, NULL, 0, LEON3_AHB_MASTERS, + AHB_SCAN_MASTER); +} + +int ambapp_ahbmst_first(unsigned int vendor, unsigned int driver, + ambapp_ahbdev * dev) +{ + /* find first device of this */ + return ambapp_ahb_scan(vendor, driver, dev, 0, 1, AHB_SCAN_MASTER); +} + +int ambapp_ahbmst_next(unsigned int vendor, + unsigned int driver, ambapp_ahbdev * dev, int index) +{ + /* find first device of this */ + return ambapp_ahb_scan(vendor, driver, dev, index, 1, AHB_SCAN_MASTER); +} + +int ambapp_ahbmsts_first(unsigned int vendor, + unsigned int driver, ambapp_ahbdev * dev, int max_cnt) +{ + /* find first device of this */ + return ambapp_ahb_scan(vendor, driver, dev, 0, max_cnt, + AHB_SCAN_MASTER); +} + +/****************************** AHB SLAVES ******************************/ +int ambapp_ahbslv_count(unsigned int vendor, unsigned int driver) +{ + /* Get number of devices of this vendor&device ID */ + return ambapp_ahb_scan(vendor, driver, NULL, 0, LEON3_AHB_SLAVES, + AHB_SCAN_SLAVE); +} + +int ambapp_ahbslv_first(unsigned int vendor, unsigned int driver, + ambapp_ahbdev * dev) +{ + /* find first device of this */ + return ambapp_ahb_scan(vendor, driver, dev, 0, 1, AHB_SCAN_SLAVE); +} + +int ambapp_ahbslv_next(unsigned int vendor, + unsigned int driver, ambapp_ahbdev * dev, int index) +{ + /* find first device of this */ + return ambapp_ahb_scan(vendor, driver, dev, index, 1, AHB_SCAN_SLAVE); +} + +int ambapp_ahbslvs_first(unsigned int vendor, + unsigned int driver, ambapp_ahbdev * dev, int max_cnt) +{ + /* find first device of this */ + return ambapp_ahb_scan(vendor, driver, dev, 0, max_cnt, AHB_SCAN_SLAVE); +} diff --git a/cpu/bf537/config.mk b/cpu/leon3/config.mk index fbbe75dede..30b224a068 100644 --- a/cpu/bf537/config.mk +++ b/cpu/leon3/config.mk @@ -1,8 +1,5 @@ -# U-boot - config.mk # -# Copyright (c) 2005-2007 Analog Devices Inc. -# -# (C) Copyright 2000-2004 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -20,8 +17,10 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -# MA 02110-1301 USA +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA # -PLATFORM_RELFLAGS += -mcpu=bf537 +PLATFORM_RELFLAGS += -fPIC + +PLATFORM_CPPFLAGS += -DCONFIG_LEON diff --git a/cpu/leon3/cpu.c b/cpu/leon3/cpu.c new file mode 100644 index 0000000000..306a210048 --- /dev/null +++ b/cpu/leon3/cpu.c @@ -0,0 +1,67 @@ +/* CPU specific code for the LEON3 CPU + * + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> + +#include <asm/io.h> +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void _reset_reloc(void); + +int checkcpu(void) +{ + /* check LEON version here */ + printf("CPU: LEON3\n"); + return 0; +} + +/* ------------------------------------------------------------------------- */ + +void cpu_reset(void) +{ + /* Interrupts off */ + disable_interrupts(); + + /* jump to restart in flash */ + _reset_reloc(); +} + +int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + cpu_reset(); + + return 1; + +} + +u64 flash_read64(void *addr) +{ + return __raw_readq(addr); +} + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/leon3/cpu_init.c b/cpu/leon3/cpu_init.c new file mode 100644 index 0000000000..4fe7d4b8d1 --- /dev/null +++ b/cpu/leon3/cpu_init.c @@ -0,0 +1,254 @@ +/* Initializes CPU and basic hardware such as memory + * controllers, IRQ controller and system timer 0. + * + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/asi.h> +#include <asm/leon.h> +#include <ambapp.h> + +#include <config.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* reset CPU (jump to 0, without reset) */ +void start(void); + +/* find & initialize the memory controller */ +int init_memory_ctrl(void); + +ambapp_dev_irqmp *irqmp = NULL; +ambapp_dev_mctrl memctrl; +ambapp_dev_gptimer *gptimer = NULL; +unsigned int gptimer_irq = 0; +int leon3_snooping_avail = 0; + +struct { + gd_t gd_area; + bd_t bd; +} global_data; + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers. + * + * Run from FLASH/PROM: + * - until memory controller is set up, only registers avaiable + * - no global variables available for writing + * - constants avaiable + */ + +void cpu_init_f(void) +{ + /* these varaiable must not be initialized */ + ambapp_dev_irqmp *irqmp; + ambapp_apbdev apbdev; + register unsigned int apbmst; + + /* find AMBA APB Master */ + apbmst = (unsigned int) + ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_APBMST, 1, 0); + if (!apbmst) { + /* + * no AHB/APB bridge, something is wrong + * ==> jump to start (or hang) + */ + while (1) ; + } + /* Init memory controller */ + if (init_memory_ctrl()) { + while (1) ; + } + + /**************************************************** + * From here we can use the main memory and the stack. + */ + + /* Find AMBA APB IRQMP Controller */ + if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_IRQMP, &apbdev) != 1) { + /* no IRQ controller, something is wrong + * ==> jump to start (or hang) + */ + while (1) ; + } + irqmp = (ambapp_dev_irqmp *) apbdev.address; + + /* initialize the IRQMP */ + irqmp->ilevel = 0xf; /* all IRQ off */ + irqmp->iforce = 0; + irqmp->ipend = 0; + irqmp->iclear = 0xfffe; /* clear all old pending interrupts */ + irqmp->cpu_mask[0] = 0; /* mask all IRQs on CPU 0 */ + irqmp->cpu_force[0] = 0; /* no force IRQ on CPU 0 */ + + /* cache */ +} + +void cpu_init_f2(void) +{ + +} + +/* + * initialize higher level parts of CPU like time base and timers + */ +int cpu_init_r(void) +{ + ambapp_apbdev apbdev; + + /* + * Find AMBA APB IRQMP Controller, + * When we come so far we know there is a IRQMP available + */ + ambapp_apb_first(VENDOR_GAISLER, GAISLER_IRQMP, &apbdev); + irqmp = (ambapp_dev_irqmp *) apbdev.address; + + /* timer */ + if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_GPTIMER, &apbdev) != 1) { + printf("cpu_init_r: gptimer not found!\n"); + return 1; + } + gptimer = (ambapp_dev_gptimer *) apbdev.address; + gptimer_irq = apbdev.irq; + + /* initialize prescaler common to all timers to 1MHz */ + gptimer->scalar = gptimer->scalar_reload = + (((CONFIG_SYS_CLK_FREQ / 1000) + 500) / 1000) - 1; + + return (0); +} + +/* find & setup memory controller */ +int init_memory_ctrl() +{ + register ambapp_dev_mctrl *mctrl; + register ambapp_dev_sdctrl *sdctrl; + register ambapp_dev_ddrspa *ddrspa; + register ambapp_dev_ddr2spa *ddr2spa; + register ahbctrl_pp_dev *ahb; + register unsigned int base; + register int not_found_mctrl = -1; + + /* find ESA Memory controller */ + base = ambapp_apb_next_nomem(VENDOR_ESA, ESA_MCTRL, 0); + if (base) { + mctrl = (ambapp_dev_mctrl *) base; + + /* config MCTRL memory controller */ + mctrl->mcfg1 = CFG_GRLIB_MEMCFG1 | (mctrl->mcfg1 & 0x300); + mctrl->mcfg2 = CFG_GRLIB_MEMCFG2; + mctrl->mcfg3 = CFG_GRLIB_MEMCFG3; + not_found_mctrl = 0; + } + + /* find Gaisler Fault Tolerant Memory controller */ + base = ambapp_apb_next_nomem(VENDOR_GAISLER, GAISLER_FTMCTRL, 0); + if (base) { + mctrl = (ambapp_dev_mctrl *) base; + + /* config MCTRL memory controller */ + mctrl->mcfg1 = CFG_GRLIB_FT_MEMCFG1 | (mctrl->mcfg1 & 0x300); + mctrl->mcfg2 = CFG_GRLIB_FT_MEMCFG2; + mctrl->mcfg3 = CFG_GRLIB_FT_MEMCFG3; + not_found_mctrl = 0; + } + + /* find SDRAM controller */ + base = ambapp_apb_next_nomem(VENDOR_GAISLER, GAISLER_SDCTRL, 0); + if (base) { + sdctrl = (ambapp_dev_sdctrl *) base; + + /* config memory controller */ + sdctrl->sdcfg = CFG_GRLIB_SDRAM; + not_found_mctrl = 0; + } + + ahb = ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_DDR2SPA, 1, 0); + if (ahb) { + ddr2spa = (ambapp_dev_ddr2spa *) ambapp_ahb_get_info(ahb, 1); + + /* Config DDR2 memory controller */ + ddr2spa->cfg1 = CFG_GRLIB_DDR2_CFG1; + ddr2spa->cfg3 = CFG_GRLIB_DDR2_CFG3; + not_found_mctrl = 0; + } + + ahb = ambapp_ahb_next_nomem(VENDOR_GAISLER, GAISLER_DDRSPA, 1, 0); + if (ahb) { + ddrspa = (ambapp_dev_ddrspa *) ambapp_ahb_get_info(ahb, 1); + + /* Config DDR memory controller */ + ddrspa->ctrl = CFG_GRLIB_DDR_CFG; + not_found_mctrl = 0; + } + + /* failed to find any memory controller */ + return not_found_mctrl; +} + +/* Uses Timer 0 to get accurate + * pauses. Max 2 raised to 32 ticks + * + */ +void cpu_wait_ticks(unsigned long ticks) +{ + unsigned long start = get_timer(0); + while (get_timer(start) < ticks) ; +} + +/* initiate and setup timer0 interrupt to 1MHz + * Return irq number for timer int or a negative number for + * dealing with self + */ +int timer_interrupt_init_cpu(void) +{ + /* 1ms ticks */ + gptimer->e[0].val = 0; + gptimer->e[0].rld = 999; /* (((1000000 / 100) - 1)) */ + gptimer->e[0].ctrl = + (LEON3_GPTIMER_EN | + LEON3_GPTIMER_RL | LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN); + + return gptimer_irq; +} + +/* + * This function is intended for SHORT delays only. + */ +unsigned long cpu_usec2ticks(unsigned long usec) +{ + /* timer set to 1kHz ==> 1 clk tick = 1 msec */ + if (usec < 1000) + return 1; + return (usec / 1000); +} + +unsigned long cpu_ticks2usec(unsigned long ticks) +{ + /* 1tick = 1usec */ + return ticks * 1000; +} diff --git a/cpu/leon3/interrupts.c b/cpu/leon3/interrupts.c new file mode 100644 index 0000000000..26926321a5 --- /dev/null +++ b/cpu/leon3/interrupts.c @@ -0,0 +1,219 @@ +/* + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com + * + * (C) Copyright 2006 + * Detlev Zundel, DENX Software Engineering, dzu@denx.de + * + * (C) Copyright -2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001 + * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/stack.h> +#include <common.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <command.h> +#include <asm/irq.h> + +#include <asm/leon.h> +#include <ambapp.h> + +/* 15 normal irqs and a non maskable interrupt */ +#define NR_IRQS 15 + +struct irq_action { + interrupt_handler_t *handler; + void *arg; + unsigned int count; +}; + +extern ambapp_dev_irqmp *irqmp; +extern ambapp_dev_gptimer *gptimer; + +static struct irq_action irq_handlers[NR_IRQS] = { {0}, }; +static int spurious_irq_cnt = 0; +static int spurious_irq = 0; + +static inline unsigned int irqmp_get_irqmask(unsigned int irq) +{ + if ((irq < 0) || (irq >= NR_IRQS)) { + return 0; + } else { + return (1 << irq); + } + +} + +static void leon3_ic_disable(unsigned int irq) +{ + unsigned int mask, pil; + if (!irqmp) + return; + + pil = intLock(); + + /* get mask of interrupt */ + mask = irqmp_get_irqmask(irq); + + /* set int level */ + irqmp->cpu_mask[0] = SPARC_NOCACHE_READ(&irqmp->cpu_mask[0]) & (~mask); + + intUnlock(pil); +} + +static void leon3_ic_enable(unsigned int irq) +{ + unsigned int mask, pil; + if (!irqmp) + return; + + pil = intLock(); + + /* get mask of interrupt */ + mask = irqmp_get_irqmask(irq); + + /* set int level */ + irqmp->cpu_mask[0] = SPARC_NOCACHE_READ(&irqmp->cpu_mask[0]) | mask; + + intUnlock(pil); + +} + +void handler_irq(int irq, struct pt_regs *regs) +{ + if (irq_handlers[irq].handler) { + if (((unsigned int)irq_handlers[irq].handler > CFG_RAM_END) || + ((unsigned int)irq_handlers[irq].handler < CFG_RAM_BASE) + ) { + printf("handler_irq: bad handler: %x, irq number %d\n", + (unsigned int)irq_handlers[irq].handler, irq); + return; + } + irq_handlers[irq].handler(irq_handlers[irq].arg); + irq_handlers[irq].count++; + } else { + spurious_irq_cnt++; + spurious_irq = irq; + } +} + +void leon3_force_int(int irq) +{ + if (!irqmp || (irq >= NR_IRQS) || (irq < 0)) + return; + printf("Forcing interrupt %d\n", irq); + + irqmp->iforce = SPARC_NOCACHE_READ(&irqmp->iforce) | (1 << irq); +} + +/****************************************************************************/ + +int interrupt_init_cpu(void) +{ + + return (0); +} + +/****************************************************************************/ + +/* Handle Timer 0 IRQ */ +void timer_interrupt_cpu(void *arg) +{ + gptimer->e[0].ctrl = (LEON3_GPTIMER_EN | + LEON3_GPTIMER_RL | + LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN); + /* nothing to do here */ + return; +} + +/****************************************************************************/ + +/* + * Install and free a interrupt handler. + */ + +void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg) +{ + if (irq < 0 || irq >= NR_IRQS) { + printf("irq_install_handler: bad irq number %d\n", irq); + return; + } + + if (irq_handlers[irq].handler != NULL) + printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n", + (ulong) handler, (ulong) irq_handlers[irq].handler); + + if (((unsigned int)handler > CFG_RAM_END) || + ((unsigned int)handler < CFG_RAM_BASE) + ) { + printf("irq_install_handler: bad handler: %x, irq number %d\n", + (unsigned int)handler, irq); + return; + } + irq_handlers[irq].handler = handler; + irq_handlers[irq].arg = arg; + + /* enable irq on IRQMP hardware */ + leon3_ic_enable(irq); + +} + +void irq_free_handler(int irq) +{ + if (irq < 0 || irq >= NR_IRQS) { + printf("irq_free_handler: bad irq number %d\n", irq); + return; + } + + /* disable irq on IRQMP hardware */ + leon3_ic_disable(irq); + + irq_handlers[irq].handler = NULL; + irq_handlers[irq].arg = NULL; +} + +/****************************************************************************/ + +#if defined(CONFIG_CMD_IRQ) +void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + int irq; + unsigned int pil = get_pil(); + printf("PIL level: %u\n\r", pil); + printf("Spurious IRQ: %u, last unknown IRQ: %d\n", + spurious_irq_cnt, spurious_irq); + + puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n"); + + for (irq = 0; irq < NR_IRQS; irq++) { + if (irq_handlers[irq].handler != NULL) { + printf("%02d %08lx %08lx %ld\n", irq, + (unsigned int)irq_handlers[irq].handler, + (unsigned int)irq_handlers[irq].arg, + irq_handlers[irq].count); + } + } +} +#endif diff --git a/cpu/leon3/prom.c b/cpu/leon3/prom.c new file mode 100644 index 0000000000..9fa2d040e8 --- /dev/null +++ b/cpu/leon3/prom.c @@ -0,0 +1,1078 @@ +/* prom.c - emulates a sparc v0 PROM for the linux kernel. + * + * Copyright (C) 2003 Konrad Eisele <eiselekd@web.de> + * Copyright (C) 2004 Stefan Holst <mail@s-holst.de> + * Copyright (C) 2007 Daniel Hellstrom <daniel@gaisler.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/prom.h> +#include <asm/machines.h> +#include <asm/srmmu.h> +#include <asm/processor.h> +#include <asm/irq.h> +#include <asm/leon.h> +#include <ambapp.h> + +#include <config.h> +/* +#define PRINT_ROM_VEC +*/ +extern struct linux_romvec *kernel_arg_promvec; +extern ambapp_dev_apbuart *leon3_apbuart; + +#define PROM_PGT __attribute__ ((__section__ (".prom.pgt"))) +#define PROM_TEXT __attribute__ ((__section__ (".prom.text"))) +#define PROM_DATA __attribute__ ((__section__ (".prom.data"))) + +ambapp_dev_gptimer *gptimer; + +/* for __va */ +extern int __prom_start; +#define PAGE_OFFSET 0xf0000000 +#define phys_base CFG_SDRAM_BASE +#define PROM_OFFS 8192 +#define PROM_SIZE_MASK (PROM_OFFS-1) +#define __va(x) ( \ + (void *)( ((unsigned long)(x))-PROM_OFFS+ \ + (CFG_PROM_OFFSET-phys_base)+PAGE_OFFSET-TEXT_BASE ) \ + ) +#define __phy(x) ((void *)(((unsigned long)(x))-PROM_OFFS+CFG_PROM_OFFSET-TEXT_BASE)) + +struct property { + char *name; + char *value; + int length; +}; + +struct node { + int level; + struct property *properties; +}; + +static void leon_reboot(char *bcommand); +static void leon_halt(void); +static int leon_nbputchar(int c); +static int leon_nbgetchar(void); + +static int no_nextnode(int node); +static int no_child(int node); +static int no_proplen(int node, char *name); +static int no_getprop(int node, char *name, char *value); +static int no_setprop(int node, char *name, char *value, int len); +static char *no_nextprop(int node, char *name); + +static struct property PROM_TEXT *find_property(int node, char *name); +static int PROM_TEXT leon_strcmp(const char *s1, const char *s2); +static void *PROM_TEXT leon_memcpy(void *dest, const void *src, size_t n); +static void PROM_TEXT leon_reboot_physical(char *bcommand); + +void __inline__ leon_flush_cache_all(void) +{ + __asm__ __volatile__(" flush "); + __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory"); +} + +void __inline__ leon_flush_tlb_all(void) +{ + leon_flush_cache_all(); + __asm__ __volatile__("sta %%g0, [%0] %1\n\t"::"r"(0x400), + "i"(ASI_MMUFLUSH):"memory"); +} + +typedef struct { + unsigned int ctx_table[256]; + unsigned int pgd_table[256]; +} sparc_srmmu_setup; + +sparc_srmmu_setup srmmu_tables PROM_PGT = { + {0}, + {0x1e, + 0x10001e, + 0x20001e, + 0x30001e, + 0x40001e, + 0x50001e, + 0x60001e, + 0x70001e, + 0x80001e, + 0x90001e, + 0xa0001e, + 0xb0001e, + 0xc0001e, + 0xd0001e, + 0xe0001e, + 0xf0001e, + 0x100001e, + 0x110001e, + 0x120001e, + 0x130001e, + 0x140001e, + 0x150001e, + 0x160001e, + 0x170001e, + 0x180001e, + 0x190001e, + 0x1a0001e, + 0x1b0001e, + 0x1c0001e, + 0x1d0001e, + 0x1e0001e, + 0x1f0001e, + 0x200001e, + 0x210001e, + 0x220001e, + 0x230001e, + 0x240001e, + 0x250001e, + 0x260001e, + 0x270001e, + 0x280001e, + 0x290001e, + 0x2a0001e, + 0x2b0001e, + 0x2c0001e, + 0x2d0001e, + 0x2e0001e, + 0x2f0001e, + 0x300001e, + 0x310001e, + 0x320001e, + 0x330001e, + 0x340001e, + 0x350001e, + 0x360001e, + 0x370001e, + 0x380001e, + 0x390001e, + 0x3a0001e, + 0x3b0001e, + 0x3c0001e, + 0x3d0001e, + 0x3e0001e, + 0x3f0001e, + 0x400001e, + 0x410001e, + 0x420001e, + 0x430001e, + 0x440001e, + 0x450001e, + 0x460001e, + 0x470001e, + 0x480001e, + 0x490001e, + 0x4a0001e, + 0x4b0001e, + 0x4c0001e, + 0x4d0001e, + 0x4e0001e, + 0x4f0001e, + 0x500001e, + 0x510001e, + 0x520001e, + 0x530001e, + 0x540001e, + 0x550001e, + 0x560001e, + 0x570001e, + 0x580001e, + 0x590001e, + 0x5a0001e, + 0x5b0001e, + 0x5c0001e, + 0x5d0001e, + 0x5e0001e, + 0x5f0001e, + 0x600001e, + 0x610001e, + 0x620001e, + 0x630001e, + 0x640001e, + 0x650001e, + 0x660001e, + 0x670001e, + 0x680001e, + 0x690001e, + 0x6a0001e, + 0x6b0001e, + 0x6c0001e, + 0x6d0001e, + 0x6e0001e, + 0x6f0001e, + 0x700001e, + 0x710001e, + 0x720001e, + 0x730001e, + 0x740001e, + 0x750001e, + 0x760001e, + 0x770001e, + 0x780001e, + 0x790001e, + 0x7a0001e, + 0x7b0001e, + 0x7c0001e, + 0x7d0001e, + 0x7e0001e, + 0x7f0001e, + 0x800001e, + 0x810001e, + 0x820001e, + 0x830001e, + 0x840001e, + 0x850001e, + 0x860001e, + 0x870001e, + 0x880001e, + 0x890001e, + 0x8a0001e, + 0x8b0001e, + 0x8c0001e, + 0x8d0001e, + 0x8e0001e, + 0x8f0001e, + 0x900001e, + 0x910001e, + 0x920001e, + 0x930001e, + 0x940001e, + 0x950001e, + 0x960001e, + 0x970001e, + 0x980001e, + 0x990001e, + 0x9a0001e, + 0x9b0001e, + 0x9c0001e, + 0x9d0001e, + 0x9e0001e, + 0x9f0001e, + 0xa00001e, + 0xa10001e, + 0xa20001e, + 0xa30001e, + 0xa40001e, + 0xa50001e, + 0xa60001e, + 0xa70001e, + 0xa80001e, + 0xa90001e, + 0xaa0001e, + 0xab0001e, + 0xac0001e, + 0xad0001e, + 0xae0001e, + 0xaf0001e, + 0xb00001e, + 0xb10001e, + 0xb20001e, + 0xb30001e, + 0xb40001e, + 0xb50001e, + 0xb60001e, + 0xb70001e, + 0xb80001e, + 0xb90001e, + 0xba0001e, + 0xbb0001e, + 0xbc0001e, + 0xbd0001e, + 0xbe0001e, + 0xbf0001e, + 0xc00001e, + 0xc10001e, + 0xc20001e, + 0xc30001e, + 0xc40001e, + 0xc50001e, + 0xc60001e, + 0xc70001e, + 0xc80001e, + 0xc90001e, + 0xca0001e, + 0xcb0001e, + 0xcc0001e, + 0xcd0001e, + 0xce0001e, + 0xcf0001e, + 0xd00001e, + 0xd10001e, + 0xd20001e, + 0xd30001e, + 0xd40001e, + 0xd50001e, + 0xd60001e, + 0xd70001e, + 0xd80001e, + 0xd90001e, + 0xda0001e, + 0xdb0001e, + 0xdc0001e, + 0xdd0001e, + 0xde0001e, + 0xdf0001e, + 0xe00001e, + 0xe10001e, + 0xe20001e, + 0xe30001e, + 0xe40001e, + 0xe50001e, + 0xe60001e, + 0xe70001e, + 0xe80001e, + 0xe90001e, + 0xea0001e, + 0xeb0001e, + 0xec0001e, + 0xed0001e, + 0xee0001e, + 0xef0001e, + 0x400001e /* default */ + } +}; + +/* a self contained prom info structure */ +struct leon_reloc_func { + struct property *(*find_property) (int node, char *name); + int (*strcmp) (char *s1, char *s2); + void *(*memcpy) (void *dest, const void *src, size_t n); + void (*reboot_physical) (char *cmd); + ambapp_dev_apbuart *leon3_apbuart; +}; + +struct leon_prom_info { + int freq_khz; + int leon_nctx; + int mids[32]; + int baudrates[2]; + struct leon_reloc_func reloc_funcs; + struct property root_properties[4]; + struct property cpu_properties[7]; +#undef CPUENTRY +#define CPUENTRY(idx) struct property cpu_properties##idx[4] + CPUENTRY(1); + CPUENTRY(2); + CPUENTRY(3); + CPUENTRY(4); + CPUENTRY(5); + CPUENTRY(6); + CPUENTRY(7); + CPUENTRY(8); + CPUENTRY(9); + CPUENTRY(10); + CPUENTRY(11); + CPUENTRY(12); + CPUENTRY(13); + CPUENTRY(14); + CPUENTRY(15); + CPUENTRY(16); + CPUENTRY(17); + CPUENTRY(18); + CPUENTRY(19); + CPUENTRY(20); + CPUENTRY(21); + CPUENTRY(22); + CPUENTRY(23); + CPUENTRY(24); + CPUENTRY(25); + CPUENTRY(26); + CPUENTRY(27); + CPUENTRY(28); + CPUENTRY(29); + CPUENTRY(30); + CPUENTRY(31); + struct idprom idprom; + struct linux_nodeops nodeops; + struct linux_mlist_v0 *totphys_p; + struct linux_mlist_v0 totphys; + struct linux_mlist_v0 *avail_p; + struct linux_mlist_v0 avail; + struct linux_mlist_v0 *prommap_p; + void (*synchook) (void); + struct linux_arguments_v0 *bootargs_p; + struct linux_arguments_v0 bootargs; + struct linux_romvec romvec; + struct node nodes[35]; + char s_device_type[12]; + char s_cpu[4]; + char s_mid[4]; + char s_idprom[7]; + char s_compatability[14]; + char s_leon2[6]; + char s_mmu_nctx[9]; + char s_frequency[16]; + char s_uart1_baud[11]; + char s_uart2_baud[11]; + char arg[256]; +}; + +/* static prom info */ +static struct leon_prom_info PROM_DATA spi = { + CONFIG_SYS_CLK_FREQ / 1000, + 256, + { +#undef CPUENTRY +#define CPUENTRY(idx) idx + CPUENTRY(0), + CPUENTRY(1), + CPUENTRY(2), + CPUENTRY(3), + CPUENTRY(4), + CPUENTRY(5), + CPUENTRY(6), + CPUENTRY(7), + CPUENTRY(8), + CPUENTRY(9), + CPUENTRY(10), + CPUENTRY(11), + CPUENTRY(12), + CPUENTRY(13), + CPUENTRY(14), + CPUENTRY(15), + CPUENTRY(16), + CPUENTRY(17), + CPUENTRY(18), + CPUENTRY(19), + CPUENTRY(20), + CPUENTRY(21), + CPUENTRY(22), + CPUENTRY(23), + CPUENTRY(24), + CPUENTRY(25), + CPUENTRY(26), + CPUENTRY(27), + CPUENTRY(28), + CPUENTRY(29), + CPUENTRY(30), + 31}, + {38400, 38400}, + { + __va(find_property), + __va(leon_strcmp), + __va(leon_memcpy), + __phy(leon_reboot_physical), + }, + { + {__va(spi.s_device_type), __va(spi.s_idprom), 4}, + {__va(spi.s_idprom), (char *)__va(&spi.idprom), sizeof(struct idprom)}, + {__va(spi.s_compatability), __va(spi.s_leon2), 5}, + {NULL, NULL, -1} + }, + { + {__va(spi.s_device_type), __va(spi.s_cpu), 4}, + {__va(spi.s_mid), __va(&spi.mids[0]), 4}, + {__va(spi.s_mmu_nctx), (char *)__va(&spi.leon_nctx), 4}, + {__va(spi.s_frequency), (char *)__va(&spi.freq_khz), 4}, + {__va(spi.s_uart1_baud), (char *)__va(&spi.baudrates[0]), 4}, + {__va(spi.s_uart2_baud), (char *)__va(&spi.baudrates[1]), 4}, + {NULL, NULL, -1} + }, +#undef CPUENTRY +#define CPUENTRY(idx) \ + { /* cpu_properties */ \ + {__va(spi.s_device_type), __va(spi.s_cpu), 4}, \ + {__va(spi.s_mid), __va(&spi.mids[idx]), 4}, \ + {__va(spi.s_frequency), (char *)__va(&spi.freq_khz), 4}, \ + {NULL, NULL, -1} \ + } + CPUENTRY(1), + CPUENTRY(2), + CPUENTRY(3), + CPUENTRY(4), + CPUENTRY(5), + CPUENTRY(6), + CPUENTRY(7), + CPUENTRY(8), + CPUENTRY(9), + CPUENTRY(10), + CPUENTRY(11), + CPUENTRY(12), + CPUENTRY(13), + CPUENTRY(14), + CPUENTRY(15), + CPUENTRY(16), + CPUENTRY(17), + CPUENTRY(18), + CPUENTRY(19), + CPUENTRY(20), + CPUENTRY(21), + CPUENTRY(22), + CPUENTRY(23), + CPUENTRY(24), + CPUENTRY(25), + CPUENTRY(26), + CPUENTRY(27), + CPUENTRY(28), + CPUENTRY(29), + CPUENTRY(30), + CPUENTRY(31), + { + 0x01, /* format */ + M_LEON2 | M_LEON2_SOC, /* machine type */ + {0, 0, 0, 0, 0, 0}, /* eth */ + 0, /* date */ + 0, /* sernum */ + 0, /* checksum */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} /* reserved */ + }, + { + __va(no_nextnode), + __va(no_child), + __va(no_proplen), + __va(no_getprop), + __va(no_setprop), + __va(no_nextprop) + }, + __va(&spi.totphys), + { + NULL, + (char *)CFG_SDRAM_BASE, + 0, + }, + __va(&spi.avail), + { + NULL, + (char *)CFG_SDRAM_BASE, + 0, + }, + NULL, /* prommap_p */ + NULL, + __va(&spi.bootargs), + { + {NULL, __va(spi.arg), NULL /*... */ }, + /*... */ + }, + { + 0, + 0, /* sun4c v0 prom */ + 0, 0, + {__va(&spi.totphys_p), __va(&spi.prommap_p), __va(&spi.avail_p)}, + __va(&spi.nodeops), + NULL, {NULL /* ... */ }, + NULL, NULL, + NULL, NULL, /* pv_getchar, pv_putchar */ + __va(leon_nbgetchar), __va(leon_nbputchar), + NULL, + __va(leon_reboot), + NULL, + NULL, + NULL, + __va(leon_halt), + __va(&spi.synchook), + {NULL}, + __va(&spi.bootargs_p) + /*... */ + }, + { + {0, __va(spi.root_properties + 3) /* NULL, NULL, -1 */ }, + {0, __va(spi.root_properties)}, + /* cpu 0, must be spi.nodes[2] see leon_prom_init() */ + {1, __va(spi.cpu_properties)}, + +#undef CPUENTRY +#define CPUENTRY(idx) \ + {1, __va(spi.cpu_properties##idx) } /* cpu <idx> */ + CPUENTRY(1), + CPUENTRY(2), + CPUENTRY(3), + CPUENTRY(4), + CPUENTRY(5), + CPUENTRY(6), + CPUENTRY(7), + CPUENTRY(8), + CPUENTRY(9), + CPUENTRY(10), + CPUENTRY(11), + CPUENTRY(12), + CPUENTRY(13), + CPUENTRY(14), + CPUENTRY(15), + CPUENTRY(16), + CPUENTRY(17), + CPUENTRY(18), + CPUENTRY(19), + CPUENTRY(20), + CPUENTRY(21), + CPUENTRY(22), + CPUENTRY(23), + CPUENTRY(24), + CPUENTRY(25), + CPUENTRY(26), + CPUENTRY(27), + CPUENTRY(28), + CPUENTRY(29), + CPUENTRY(30), + CPUENTRY(31), + {-1, __va(spi.root_properties + 3) /* NULL, NULL, -1 */ } + }, + "device_type", + "cpu", + "mid", + "idprom", + "compatability", + "leon2", + "mmu-nctx", + "clock-frequency", + "uart1_baud", + "uart2_baud", + CONFIG_DEFAULT_KERNEL_COMMAND_LINE +}; + +/* from arch/sparc/kernel/setup.c */ +#define RAMDISK_LOAD_FLAG 0x4000 +extern unsigned short root_flags; +extern unsigned short root_dev; +extern unsigned short ram_flags; +extern unsigned int sparc_ramdisk_image; +extern unsigned int sparc_ramdisk_size; +extern int root_mountflags; + +extern char initrd_end, initrd_start; + +/* Reboot the CPU = jump to beginning of flash again. + * + * Make sure that all function are inlined here. + */ +static void PROM_TEXT leon_reboot(char *bcommand) +{ + register char *arg = bcommand; + void __attribute__ ((noreturn)) (*reboot_physical) (char *cmd); + + /* get physical address */ + struct leon_prom_info *pspi = + (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + unsigned int *srmmu_ctx_table; + + /* Turn of Interrupts */ + set_pil(0xf); + + /* Set kernel's context, context zero */ + srmmu_set_context(0); + + /* Get physical address of the MMU shutdown routine */ + reboot_physical = (void *) + SPARC_BYPASS_READ(&pspi->reloc_funcs.reboot_physical); + + /* Now that we know the physical address of the function + * we can make the MMU allow jumping to it. + */ + srmmu_ctx_table = (unsigned int *)srmmu_get_ctable_ptr(); + + srmmu_ctx_table = (unsigned int *)SPARC_BYPASS_READ(srmmu_ctx_table); + + /* get physical address of kernel's context table (assume ptd) */ + srmmu_ctx_table = (unsigned int *) + (((unsigned int)srmmu_ctx_table & 0xfffffffc) << 4); + + /* enable access to physical address of MMU shutdown function */ + SPARC_BYPASS_WRITE(&srmmu_ctx_table + [((unsigned int)reboot_physical) >> 24], + (((unsigned int)reboot_physical & 0xff000000) >> 4) | + 0x1e); + + /* flush TLB cache */ + leon_flush_tlb_all(); + + /* flash instruction & data cache */ + sparc_icache_flush_all(); + sparc_dcache_flush_all(); + + /* jump to physical address function + * so that when the MMU is disabled + * we can continue to execute + */ + reboot_physical(arg); +} + +static void PROM_TEXT leon_reboot_physical(char *bcommand) +{ + void __attribute__ ((noreturn)) (*reset) (void); + + /* Turn off MMU */ + srmmu_set_mmureg(0); + + /* Hardcoded start address */ + reset = CFG_MONITOR_BASE; + + /* flush data cache */ + sparc_dcache_flush_all(); + + /* flush instruction cache */ + sparc_icache_flush_all(); + + /* Jump to start in Flash */ + reset(); +} + +static void PROM_TEXT leon_halt(void) +{ + while (1) ; +} + +/* get single char, don't care for blocking*/ +static int PROM_TEXT leon_nbgetchar(void) +{ + return -1; +} + +/* put single char, don't care for blocking*/ +static int PROM_TEXT leon_nbputchar(int c) +{ + ambapp_dev_apbuart *uart; + + /* get physical address */ + struct leon_prom_info *pspi = + (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + uart = (ambapp_dev_apbuart *) + SPARC_BYPASS_READ(&pspi->reloc_funcs.leon3_apbuart); + + /* no UART? */ + if (!uart) + return 0; + + /***** put char in buffer... *********** + * Make sure all functions are inline! * + ***************************************/ + + /* Wait for last character to go. */ + while (!(SPARC_BYPASS_READ(&uart->status) + & LEON_REG_UART_STATUS_THE)) ; + + /* Send data */ + SPARC_BYPASS_WRITE(&uart->data, c); + + /* Wait for data to be sent */ + while (!(SPARC_BYPASS_READ(&uart->status) + & LEON_REG_UART_STATUS_TSE)) ; + + return 0; +} + +/* node ops */ + +/*#define nodes ((struct node *)__va(&pspi->nodes))*/ +#define nodes ((struct node *)(pspi->nodes)) + +static int PROM_TEXT no_nextnode(int node) +{ + /* get physical address */ + struct leon_prom_info *pspi = + (void *)(CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + /* convert into virtual address */ + pspi = (struct leon_prom_info *) + (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET); + + if (nodes[node].level == nodes[node + 1].level) + return node + 1; + return -1; +} + +static int PROM_TEXT no_child(int node) +{ + /* get physical address */ + struct leon_prom_info *pspi = (struct leon_prom_info *) + (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + /* convert into virtual address */ + pspi = (struct leon_prom_info *) + (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET); + + if (nodes[node].level == nodes[node + 1].level - 1) + return node + 1; + return -1; +} + +static struct property PROM_TEXT *find_property(int node, char *name) +{ + /* get physical address */ + struct leon_prom_info *pspi = (struct leon_prom_info *) + (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + /* convert into virtual address */ + pspi = (struct leon_prom_info *) + (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET); + + struct property *prop = &nodes[node].properties[0]; + while (prop && prop->name) { + if (pspi->reloc_funcs.strcmp(prop->name, name) == 0) + return prop; + prop++; + } + return NULL; +} + +static int PROM_TEXT no_proplen(int node, char *name) +{ + /* get physical address */ + struct leon_prom_info *pspi = (struct leon_prom_info *) + (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + /* convert into virtual address */ + pspi = (struct leon_prom_info *) + (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET); + + struct property *prop = pspi->reloc_funcs.find_property(node, name); + if (prop) + return prop->length; + return -1; +} + +static int PROM_TEXT no_getprop(int node, char *name, char *value) +{ + /* get physical address */ + struct leon_prom_info *pspi = (struct leon_prom_info *) + (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + + /* convert into virtual address */ + pspi = (struct leon_prom_info *) + (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET); + + struct property *prop = pspi->reloc_funcs.find_property(node, name); + if (prop) { + pspi->reloc_funcs.memcpy(value, prop->value, prop->length); + return 1; + } + return -1; +} + +static int PROM_TEXT no_setprop(int node, char *name, char *value, int len) +{ + return -1; +} + +static char PROM_TEXT *no_nextprop(int node, char *name) +{ + /* get physical address */ + struct leon_prom_info *pspi = (struct leon_prom_info *) + (CFG_PROM_OFFSET + sizeof(srmmu_tables)); + struct property *prop; + + /* convert into virtual address */ + pspi = (struct leon_prom_info *) + (((unsigned int)pspi & 0x0fffffff) | PAGE_OFFSET); + + if (!name || !name[0]) + return nodes[node].properties[0].name; + + prop = pspi->reloc_funcs.find_property(node, name); + if (prop) + return prop[1].name; + return NULL; +} + +static int PROM_TEXT leon_strcmp(const char *s1, const char *s2) +{ + register char result; + + while (1) { + result = *s1 - *s2; + if (result || !*s1) + break; + s2++; + s1++; + } + + return result; +} + +static void *PROM_TEXT leon_memcpy(void *dest, const void *src, size_t n) +{ + char *dst = (char *)dest, *source = (char *)src; + + while (n--) { + *dst = *source; + dst++; + source++; + } + return dest; +} + +#define GETREGSP(sp) __asm__ __volatile__("mov %%sp, %0" : "=r" (sp)) + +void leon_prom_init(struct leon_prom_info *pspi) +{ + unsigned long i; + unsigned char cksum, *ptr; + char *addr_str, *end; + unsigned long sp; + GETREGSP(sp); + + pspi->freq_khz = CONFIG_SYS_CLK_FREQ / 1000; + + /* Set Available main memory size */ + pspi->totphys.num_bytes = CFG_PROM_OFFSET - CFG_SDRAM_BASE; + pspi->avail.num_bytes = pspi->totphys.num_bytes; + + /* Set the pointer to the Console UART in romvec */ + pspi->reloc_funcs.leon3_apbuart = leon3_apbuart; + + { + int j = 1; +#ifdef CONFIG_SMP + ambapp_dev_irqmp *b; + b = (ambapp_dev_irqmp *) leon3_getapbbase(VENDOR_GAISLER, + GAISLER_IRQMP); + if (b) { + j = 1 + ((LEON3_BYPASS_LOAD_PA(&(b->mpstatus)) + >> LEON3_IRQMPSTATUS_CPUNR) & 0xf); + } +#endif +#undef nodes + pspi->nodes[2 + j].level = -1; + pspi->nodes[2 + j].properties = __va(spi.root_properties + 3); + } + + /* Set Ethernet MAC address from environment */ + if ((addr_str = getenv("ethaddr")) != NULL) { + for (i = 0; i < 6; i++) { + pspi->idprom.id_ethaddr[i] = addr_str ? + simple_strtoul(addr_str, &end, 16) : 0; + if (addr_str) { + addr_str = (*end) ? end + 1 : end; + } + } + } else { + /* HW Address not found in environment, + * Set default HW address + */ + pspi->idprom.id_ethaddr[0] = 0; + pspi->idprom.id_ethaddr[1] = 0; + pspi->idprom.id_ethaddr[2] = 0; + pspi->idprom.id_ethaddr[3] = 0; + pspi->idprom.id_ethaddr[4] = 0; + pspi->idprom.id_ethaddr[5] = 0; + } + + ptr = (unsigned char *)&pspi->idprom; + for (i = cksum = 0; i <= 0x0E; i++) + cksum ^= *ptr++; + pspi->idprom.id_cksum = cksum; +} + +static inline void set_cache(unsigned long regval) +{ + asm volatile ("sta %0, [%%g0] %1\n\t":: "r" (regval), "i"(2):"memory"); +} + +extern unsigned short bss_start, bss_end; + +/* mark as section .img.main.text, to be referenced in linker script */ +int prom_init(void) +{ + struct leon_prom_info *pspi = (void *) + ((((unsigned int)&spi) & PROM_SIZE_MASK) + CFG_PROM_OFFSET); + + /* disable mmu */ + srmmu_set_mmureg(0x00000000); + __asm__ __volatile__("flush\n\t"); + + /* init prom info struct */ + leon_prom_init(pspi); + + kernel_arg_promvec = &pspi->romvec; +#ifdef PRINT_ROM_VEC + printf("Kernel rom vec: 0x%lx\n", (unsigned int)(&pspi->romvec)); +#endif + return 0; +} + +/* Copy current kernel boot argument to ROMvec */ +void prepare_bootargs(char *bootargs) +{ + struct leon_prom_info *pspi; + char *src, *dst; + int left; + + /* if no bootargs set, skip copying ==> default bootline */ + if (bootargs && (*bootargs != '\0')) { + pspi = (void *)((((unsigned int)&spi) & PROM_SIZE_MASK) + + CFG_PROM_OFFSET); + src = bootargs; + dst = &pspi->arg[0]; + left = 255; /* max len */ + while (*src && left > 0) { + *dst++ = *src++; + left--; + } + /* terminate kernel command line string */ + *dst = 0; + } +} + +void srmmu_init_cpu(unsigned int entry) +{ + sparc_srmmu_setup *psrmmu_tables = (void *) + ((((unsigned int)&srmmu_tables) & PROM_SIZE_MASK) + + CFG_PROM_OFFSET); + + /* Make context 0 (kernel's context) point + * to our prepared memory mapping + */ +#define PTD 1 + psrmmu_tables->ctx_table[0] = + ((unsigned int)&psrmmu_tables->pgd_table[0x00]) >> 4 | PTD; + + /* Set virtual kernel address 0xf0000000 + * to SRAM/SDRAM address. + * Make it READ/WRITE/EXEC to SuperUser + */ +#define PTE 2 +#define ACC_SU_ALL 0x1c + psrmmu_tables->pgd_table[0xf0] = + (CFG_SDRAM_BASE >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf1] = + ((CFG_SDRAM_BASE + 0x1000000) >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf2] = + ((CFG_SDRAM_BASE + 0x2000000) >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf3] = + ((CFG_SDRAM_BASE + 0x3000000) >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf4] = + ((CFG_SDRAM_BASE + 0x4000000) >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf5] = + ((CFG_SDRAM_BASE + 0x5000000) >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf6] = + ((CFG_SDRAM_BASE + 0x6000000) >> 4) | ACC_SU_ALL | PTE; + psrmmu_tables->pgd_table[0xf7] = + ((CFG_SDRAM_BASE + 0x7000000) >> 4) | ACC_SU_ALL | PTE; + + /* convert rom vec pointer to virtual address */ + kernel_arg_promvec = (struct linux_romvec *) + (((unsigned int)kernel_arg_promvec & 0x0fffffff) | 0xf0000000); + + /* Set Context pointer to point to context table + * 256 contexts supported. + */ + srmmu_set_ctable_ptr((unsigned int)&psrmmu_tables->ctx_table[0]); + + /* Set kernel's context, context zero */ + srmmu_set_context(0); + + /* Invalidate all Cache */ + __asm__ __volatile__("flush\n\t"); + + srmmu_set_mmureg(0x00000001); + leon_flush_tlb_all(); + leon_flush_cache_all(); +} diff --git a/cpu/leon3/serial.c b/cpu/leon3/serial.c new file mode 100644 index 0000000000..27d5cd3803 --- /dev/null +++ b/cpu/leon3/serial.c @@ -0,0 +1,139 @@ +/* GRLIB APBUART Serial controller driver + * + * (C) Copyright 2007 + * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/leon.h> +#include <ambapp.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Force cache miss each time a serial controller reg is read */ +#define CACHE_BYPASS 1 + +#ifdef CACHE_BYPASS +#define READ_BYTE(var) SPARC_NOCACHE_READ_BYTE((unsigned int)&(var)) +#define READ_HWORD(var) SPARC_NOCACHE_READ_HWORD((unsigned int)&(var)) +#define READ_WORD(var) SPARC_NOCACHE_READ((unsigned int)&(var)) +#define READ_DWORD(var) SPARC_NOCACHE_READ_DWORD((unsigned int)&(var)) +#endif + +ambapp_dev_apbuart *leon3_apbuart = NULL; + +int serial_init(void) +{ + ambapp_apbdev apbdev; + unsigned int tmp; + + /* find UART */ + if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_APBUART, &apbdev) == 1) { + + leon3_apbuart = (ambapp_dev_apbuart *) apbdev.address; + + /* found apbuart, let's init... + * + * Set scaler / baud rate + * + * Receiver & transmitter enable + */ + leon3_apbuart->scaler = CFG_GRLIB_APBUART_SCALER; + + /* Let bit 11 be unchanged (debug bit for GRMON) */ + tmp = READ_WORD(leon3_apbuart->ctrl); + + leon3_apbuart->ctrl = ((tmp & LEON_REG_UART_CTRL_DBG) | + LEON_REG_UART_CTRL_RE | + LEON_REG_UART_CTRL_TE); + + return 0; + } + return -1; /* didn't find hardware */ +} + +void serial_putc(const char c) +{ + if (c == '\n') + serial_putc_raw('\r'); + + serial_putc_raw(c); +} + +void serial_putc_raw(const char c) +{ + if (!leon3_apbuart) + return; + + /* Wait for last character to go. */ + while (!(READ_WORD(leon3_apbuart->status) & LEON_REG_UART_STATUS_THE)) ; + + /* Send data */ + leon3_apbuart->data = c; + +#ifdef LEON_DEBUG + /* Wait for data to be sent */ + while (!(READ_WORD(leon3_apbuart->status) & LEON_REG_UART_STATUS_TSE)) ; +#endif +} + +void serial_puts(const char *s) +{ + while (*s) { + serial_putc(*s++); + } +} + +int serial_getc(void) +{ + if (!leon3_apbuart) + return 0; + + /* Wait for a character to arrive. */ + while (!(READ_WORD(leon3_apbuart->status) & LEON_REG_UART_STATUS_DR)) ; + + /* read data */ + return READ_WORD(leon3_apbuart->data); +} + +int serial_tstc(void) +{ + if (leon3_apbuart) + return (READ_WORD(leon3_apbuart->status) & + LEON_REG_UART_STATUS_DR); + return 0; +} + +/* set baud rate for uart */ +void serial_setbrg(void) +{ + /* update baud rate settings, read it from gd->baudrate */ + unsigned int scaler; + if (leon3_apbuart && (gd->baudrate > 0)) { + scaler = + (((CONFIG_SYS_CLK_FREQ * 10) / (gd->baudrate * 8)) - + 5) / 10; + leon3_apbuart->scaler = scaler; + } + return; +} diff --git a/cpu/leon3/start.S b/cpu/leon3/start.S new file mode 100644 index 0000000000..2f1d099e37 --- /dev/null +++ b/cpu/leon3/start.S @@ -0,0 +1,616 @@ +/* This is where the SPARC/LEON3 starts + * Copyright (C) 2007, + * Daniel Hellstrom, daniel@gaisler.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/asmmacro.h> +#include <asm/winmacro.h> +#include <asm/psr.h> +#include <asm/stack.h> +#include <asm/leon.h> +#include <version.h> + +/* Entry for traps which jump to a programmer-specified trap handler. */ +#define TRAPR(H) \ + wr %g0, 0xfe0, %psr; \ + mov %g0, %tbr; \ + ba (H); \ + mov %g0, %wim; + +#define TRAP(H) \ + mov %psr, %l0; \ + ba (H); \ + nop; nop; + +#define TRAPI(ilevel) \ + mov ilevel, %l7; \ + mov %psr, %l0; \ + b _irq_entry; \ + mov %wim, %l3 + +/* Unexcpected trap will halt the processor by forcing it to error state */ +#undef BAD_TRAP +#define BAD_TRAP ta 0; nop; nop; nop; + +/* Software trap. Treat as BAD_TRAP for the time being... */ +#define SOFT_TRAP TRAP(_hwerr) + +#define PSR_INIT 0x1FC0 /* Disable traps, set s and ps */ +#define WIM_INIT 2 + +/* All traps low-level code here must end with this macro. */ +#define RESTORE_ALL b ret_trap_entry; clr %l6; + +#define WRITE_PAUSE nop;nop;nop + +WINDOWSIZE = (16 * 4) +ARGPUSHSIZE = (6 * 4) +ARGPUSH = (WINDOWSIZE + 4) +MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4) + +/* Number of register windows */ +#ifndef CFG_SPARC_NWINDOWS +#error Must define number of SPARC register windows, default is 8 +#endif + +#define STACK_ALIGN 8 +#define SA(X) (((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1)) + + .section ".start", "ax" + .globl _start, start, _trap_table + .globl _irq_entry, nmi_trap + .globl _reset_reloc + +/* at address 0 + * Hardware traps + */ +start: +_start: +_trap_table: + TRAPR(_hardreset); ! 00 reset trap + BAD_TRAP; ! 01 instruction_access_exception + BAD_TRAP; ! 02 illegal_instruction + BAD_TRAP; ! 03 priveleged_instruction + BAD_TRAP; ! 04 fp_disabled + TRAP(_window_overflow); ! 05 window_overflow + TRAP(_window_underflow); ! 06 window_underflow + BAD_TRAP; ! 07 Memory Address Not Aligned + BAD_TRAP; ! 08 Floating Point Exception + BAD_TRAP; ! 09 Data Miss Exception + BAD_TRAP; ! 0a Tagged Instruction Ovrflw + BAD_TRAP; ! 0b Watchpoint Detected + BAD_TRAP; ! 0c + BAD_TRAP; ! 0d + BAD_TRAP; ! 0e + BAD_TRAP; ! 0f + BAD_TRAP; ! 10 + TRAPI(1); ! 11 IRQ level 1 + TRAPI(2); ! 12 IRQ level 2 + TRAPI(3); ! 13 IRQ level 3 + TRAPI(4); ! 14 IRQ level 4 + TRAPI(5); ! 15 IRQ level 5 + TRAPI(6); ! 16 IRQ level 6 + TRAPI(7); ! 17 IRQ level 7 + TRAPI(8); ! 18 IRQ level 8 + TRAPI(9); ! 19 IRQ level 9 + TRAPI(10); ! 1a IRQ level 10 + TRAPI(11); ! 1b IRQ level 11 + TRAPI(12); ! 1c IRQ level 12 + TRAPI(13); ! 1d IRQ level 13 + TRAPI(14); ! 1e IRQ level 14 + TRAP(_nmi_trap); ! 1f IRQ level 15 / + ! NMI (non maskable interrupt) + BAD_TRAP; ! 20 r_register_access_error + BAD_TRAP; ! 21 instruction access error + BAD_TRAP; ! 22 + BAD_TRAP; ! 23 + BAD_TRAP; ! 24 co-processor disabled + BAD_TRAP; ! 25 uniplemented FLUSH + BAD_TRAP; ! 26 + BAD_TRAP; ! 27 + BAD_TRAP; ! 28 co-processor exception + BAD_TRAP; ! 29 data access error + BAD_TRAP; ! 2a division by zero + BAD_TRAP; ! 2b data store error + BAD_TRAP; ! 2c data access MMU miss + BAD_TRAP; ! 2d + BAD_TRAP; ! 2e + BAD_TRAP; ! 2f + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30-33 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34-37 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38-3b + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3c-3f + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40-43 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44-47 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48-4b + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4c-4f + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50-53 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54-57 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58-5b + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5c-5f + + /* implementaion dependent */ + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60-63 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64-67 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68-6b + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6c-6f + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70-73 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74-77 + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78-7b + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 7c-7f + + /* Software traps, not handled */ + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 80-83 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84-87 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88-8b + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8c-8f + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90-93 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94-97 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98-9b + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9c-9f + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! a0-a3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! a4-a7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! a8-ab + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! ac-af + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! b0-b3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! b4-b7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! b8-bb + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! bc-bf + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! c0-c3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! c4-c7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! c8-cb + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! cc-cf + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! d0-d3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! d4-d7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! d8-db + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! dc-df + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! e0-e3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! e4-e7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! e8-eb + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! ec-ef + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f0-f3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f4-f7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! f8-fb + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! fc-ff +/* + * Version string + */ + + .data + .extern leon3_snooping_avail + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + .section ".text" + .align 4 + +_hardreset: +1000: + flush + + /* Enable I/D-Cache and Snooping */ + set 0x0081000f, %g2 + sta %g2, [%g0] 2 + + mov %g0, %y + clr %g1 + clr %g2 + clr %g3 + clr %g4 + clr %g5 + clr %g6 + clr %g7 + + mov %asr17, %g3 + and %g3, 0x1f, %g3 +clear_window: + mov %g0, %l0 + mov %g0, %l1 + mov %g0, %l2 + mov %g0, %l3 + mov %g0, %l4 + mov %g0, %l5 + mov %g0, %l6 + mov %g0, %l7 + mov %g0, %o0 + mov %g0, %o1 + mov %g0, %o2 + mov %g0, %o3 + mov %g0, %o4 + mov %g0, %o5 + mov %g0, %o6 + mov %g0, %o7 + subcc %g3, 1, %g3 + bge clear_window + save + +wininit: + set WIM_INIT, %g3 + mov %g3, %wim + +stackp: + set CFG_INIT_SP_OFFSET, %fp + andn %fp, 0x0f, %fp + sub %fp, 64, %sp + +cpu_init_unreloc: + call cpu_init_f + nop + +/* un relocated start address of monitor */ +#define TEXT_START _text + +/* un relocated end address of monitor */ +#define DATA_END __init_end + +reloc: + set TEXT_START,%g2 + set DATA_END,%g3 + set CFG_RELOC_MONITOR_BASE,%g4 +reloc_loop: + ldd [%g2],%l0 + ldd [%g2+8],%l2 + std %l0,[%g4] + std %l2,[%g4+8] + inc 16,%g2 + subcc %g3,%g2,%g0 + bne reloc_loop + inc 16,%g4 + + clr %l0 + clr %l1 + clr %l2 + clr %l3 + clr %g2 + +/* register g4 contain address to start + * This means that BSS must be directly after data and code segments + * + * g3 is length of bss = (__bss_end-__bss_start) + * + */ + +clr_bss: +/* clear bss area (the relocated) */ + set __bss_start,%g2 + set __bss_end,%g3 + sub %g3,%g2,%g3 + add %g3,%g4,%g3 + clr %g1 /* std %g0 uses g0 and g1 */ +/* clearing 16byte a time ==> linker script need to align to 16 byte offset */ +clr_bss_16: + std %g0,[%g4] + std %g0,[%g4+8] + inc 16,%g4 + cmp %g3,%g4 + bne clr_bss_16 + nop + +/* add offsets to GOT table */ +fixup_got: + set __got_start,%g4 + set __got_end,%g3 +/* + * new got offset = (old GOT-PTR (read with ld) - + * CFG_RELOC_MONITOR_BASE(from define) ) + + * Destination Address (from define) + */ + set CFG_RELOC_MONITOR_BASE,%g2 + set TEXT_START, %g1 + add %g4,%g2,%g4 + sub %g4,%g1,%g4 + add %g3,%g2,%g3 + sub %g3,%g1,%g3 + sub %g2,%g1,%g2 ! prepare register with (new base address) - + ! (old base address) +got_loop: + ld [%g4],%l0 ! load old GOT-PTR + add %l0,%g2,%l0 ! increase with (new base address) - + ! (old base) + st %l0,[%g4] + inc 4,%g4 + cmp %g3,%g4 + bne got_loop + nop + +prom_relocate: + set __prom_start, %g2 + set __prom_end, %g3 + set CFG_PROM_OFFSET, %g4 + +prom_relocate_loop: + ldd [%g2],%l0 + ldd [%g2+8],%l2 + std %l0,[%g4] + std %l2,[%g4+8] + inc 16,%g2 + subcc %g3,%g2,%g0 + bne prom_relocate_loop + inc 16,%g4 + +/* Trap table has been moved, lets tell CPU about + * the new trap table address + */ + + set CFG_RELOC_MONITOR_BASE, %g2 + wr %g0, %g2, %tbr + nop + nop + nop + +/* If CACHE snooping is available in hardware the + * variable leon3_snooping_avail will be set to + * 0x800000 else 0. + */ +snoop_detect: + sethi %hi(0x00800000), %o0 + lda [%g0] 2, %o1 + and %o0, %o1, %o0 + sethi %hi(leon3_snooping_avail+CFG_RELOC_MONITOR_BASE-TEXT_BASE), %o1 + st %o0, [%lo(leon3_snooping_avail+CFG_RELOC_MONITOR_BASE-TEXT_BASE)+%o1] + +/* call relocate*/ + nop +/* Call relocated init functions */ +jump: + set cpu_init_f2,%o1 + set CFG_RELOC_MONITOR_BASE,%o2 + add %o1,%o2,%o1 + sub %o1,%g1,%o1 + call %o1 + clr %o0 + + set board_init_f,%o1 + set CFG_RELOC_MONITOR_BASE,%o2 + add %o1,%o2,%o1 + sub %o1,%g1,%o1 + call %o1 + clr %o0 + +dead: ta 0 ! if call returns... + nop + +/* Interrupt handler caller, + * reg L7: interrupt number + * reg L0: psr after interrupt + * reg L1: PC + * reg L2: next PC + * reg L3: wim + */ +_irq_entry: + SAVE_ALL + + or %l0, PSR_PIL, %g2 + wr %g2, 0x0, %psr + WRITE_PAUSE + wr %g2, PSR_ET, %psr + WRITE_PAUSE + mov %l7, %o0 ! irq level + set handler_irq, %o1 + set (CFG_RELOC_MONITOR_BASE-TEXT_BASE), %o2 + add %o1, %o2, %o1 + call %o1 + add %sp, SF_REGS_SZ, %o1 ! pt_regs ptr + or %l0, PSR_PIL, %g2 ! restore PIL after handler_irq + wr %g2, PSR_ET, %psr ! keep ET up + WRITE_PAUSE + + RESTORE_ALL + +!Window overflow trap handler. + .global _window_overflow + +_window_overflow: + + mov %wim, %l3 ! Calculate next WIM + mov %g1, %l7 + srl %l3, 1, %g1 + sll %l3, (CFG_SPARC_NWINDOWS-1) , %l4 + or %l4, %g1, %g1 + + save ! Get into window to be saved. + mov %g1, %wim + nop; + nop; + nop + st %l0, [%sp + 0]; + st %l1, [%sp + 4]; + st %l2, [%sp + 8]; + st %l3, [%sp + 12]; + st %l4, [%sp + 16]; + st %l5, [%sp + 20]; + st %l6, [%sp + 24]; + st %l7, [%sp + 28]; + st %i0, [%sp + 32]; + st %i1, [%sp + 36]; + st %i2, [%sp + 40]; + st %i3, [%sp + 44]; + st %i4, [%sp + 48]; + st %i5, [%sp + 52]; + st %i6, [%sp + 56]; + st %i7, [%sp + 60]; + restore ! Go back to trap window. + mov %l7, %g1 + jmp %l1 ! Re-execute save. + rett %l2 + +/* Window underflow trap handler. */ + + .global _window_underflow + +_window_underflow: + + mov %wim, %l3 ! Calculate next WIM + sll %l3, 1, %l4 + srl %l3, (CFG_SPARC_NWINDOWS-1), %l5 + or %l5, %l4, %l5 + mov %l5, %wim + nop; nop; nop + restore ! Two restores to get into the + restore ! window to restore + ld [%sp + 0], %l0; ! Restore window from the stack + ld [%sp + 4], %l1; + ld [%sp + 8], %l2; + ld [%sp + 12], %l3; + ld [%sp + 16], %l4; + ld [%sp + 20], %l5; + ld [%sp + 24], %l6; + ld [%sp + 28], %l7; + ld [%sp + 32], %i0; + ld [%sp + 36], %i1; + ld [%sp + 40], %i2; + ld [%sp + 44], %i3; + ld [%sp + 48], %i4; + ld [%sp + 52], %i5; + ld [%sp + 56], %i6; + ld [%sp + 60], %i7; + save ! Get back to the trap window. + save + jmp %l1 ! Re-execute restore. + rett %l2 + + retl + +_nmi_trap: + nop + jmp %l1 + rett %l2 + +_hwerr: + ta 0 + nop + nop + b _hwerr ! loop infinite + nop + +/* Registers to not touch at all. */ +#define t_psr l0 /* Set by caller */ +#define t_pc l1 /* Set by caller */ +#define t_npc l2 /* Set by caller */ +#define t_wim l3 /* Set by caller */ +#define t_twinmask l4 /* Set at beginning of this entry routine. */ +#define t_kstack l5 /* Set right before pt_regs frame is built */ +#define t_retpc l6 /* If you change this, change winmacro.h header file */ +#define t_systable l7 /* Never touch this, could be the syscall table ptr. */ +#define curptr g6 /* Set after pt_regs frame is built */ + +trap_setup: +/* build a pt_regs trap frame. */ + sub %fp, (SF_REGS_SZ + PT_REGS_SZ), %t_kstack + PT_STORE_ALL(t_kstack, t_psr, t_pc, t_npc, g2) + + /* See if we are in the trap window. */ + mov 1, %t_twinmask + sll %t_twinmask, %t_psr, %t_twinmask ! t_twinmask = (1 << psr) + andcc %t_twinmask, %t_wim, %g0 + beq 1f ! in trap window, clean up + nop + + /*------------------------------------------------- + * Spill , adjust %wim and go. + */ + srl %t_wim, 0x1, %g2 ! begin computation of new %wim + + set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1 + + sll %t_wim, %g3, %t_wim ! NWINDOWS-1 + or %t_wim, %g2, %g2 + and %g2, 0xff, %g2 + + save %g0, %g0, %g0 ! get in window to be saved + + /* Set new %wim value */ + wr %g2, 0x0, %wim + + /* Save the kernel window onto the corresponding stack. */ + RW_STORE(sp) + + restore %g0, %g0, %g0 + /*-------------------------------------------------*/ + +1: + /* Trap from kernel with a window available. + * Just do it... + */ + jmpl %t_retpc + 0x8, %g0 ! return to caller + mov %t_kstack, %sp ! jump onto new stack + +#define twin_tmp1 l4 +#define glob_tmp g4 +#define curptr g6 +ret_trap_entry: + wr %t_psr, 0x0, %psr ! enable nesting again, clear ET + + /* Will the rett land us in the invalid window? */ + mov 2, %g1 + sll %g1, %t_psr, %g1 + + set CFG_SPARC_NWINDOWS, %g2 !NWINDOWS + + srl %g1, %g2, %g2 + or %g1, %g2, %g1 + rd %wim, %g2 + andcc %g2, %g1, %g0 + be 1f ! Nope, just return from the trap + sll %g2, 0x1, %g1 + + /* We have to grab a window before returning. */ + set (CFG_SPARC_NWINDOWS-1), %g3 !NWINDOWS-1 + + srl %g2, %g3, %g2 + or %g1, %g2, %g1 + and %g1, 0xff, %g1 + + wr %g1, 0x0, %wim + + /* Grrr, make sure we load from the right %sp... */ + PT_LOAD_ALL(sp, t_psr, t_pc, t_npc, g1) + + restore %g0, %g0, %g0 + RW_LOAD(sp) + b 2f + save %g0, %g0, %g0 + + /* Reload the entire frame in case this is from a + * kernel system call or whatever... + */ +1: + PT_LOAD_ALL(sp, t_psr, t_pc, t_npc, g1) +2: + wr %t_psr, 0x0, %psr + nop; + nop; + nop + + jmp %t_pc + rett %t_npc + +/* This is called from relocated C-code. + * It resets the system by jumping to _start + */ +_reset_reloc: + set start, %l0 + call %l0 + nop diff --git a/cpu/leon3/usb_uhci.c b/cpu/leon3/usb_uhci.c new file mode 100644 index 0000000000..7910bebe14 --- /dev/null +++ b/cpu/leon3/usb_uhci.c @@ -0,0 +1,1313 @@ +/* + * Part of this code has been derived from linux: + * Universal Host Controller Interface driver for USB (take II). + * + * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar) + * Deti Fliegl, deti@fliegl.de (executive slave) (lead voice) + * Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader) + * Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter) + * (c) 2000 Yggdrasil Computing, Inc. (port of new PCI interface support + * from usb-ohci.c by Adam Richter, adam@yggdrasil.com). + * (C) 2000 David Brownell, david-b@pacbell.net (usb-ohci.c) + * + * HW-initalization based on material of + * + * (C) Copyright 1999 Linus Torvalds + * (C) Copyright 1999 Johannes Erdfelt + * (C) Copyright 1999 Randy Dunlap + * (C) Copyright 1999 Gregory P. Smith + * + * + * Adapted for U-Boot: + * (C) Copyright 2001 Denis Peter, MPL AG Switzerland + * (C) Copyright 2008, Daniel Hellström, daniel@gaisler.com + * Added AMBA Plug&Play detection of GRUSB, modified interrupt handler. + * Added cache flushes where needed. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * + */ + +/********************************************************************** + * How it works: + * ------------- + * The framelist / Transfer descriptor / Queue Heads are similar like + * in the linux usb_uhci.c. + * + * During initialization, the following skeleton is allocated in init_skel: + * + * framespecific | common chain + * + * framelist[] + * [ 0 ]-----> TD ---------\ + * [ 1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL + * ... TD ---------/ + * [1023]-----> TD --------/ + * + * ^^ ^^ ^^ ^^ ^^ + * 7 TDs for 1 TD for Start of Start of End Chain + * INT (2-128ms) 1ms-INT CTRL Chain BULK Chain + * + * + * Since this is a bootloader, the isochronous transfer descriptor have been removed. + * + * Interrupt Transfers. + * -------------------- + * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They + * will be inserted after the appropriate (depending the interval setting) skeleton TD. + * If an interrupt has been detected the dev->irqhandler is called. The status and number + * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the + * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned, + * the interrupt TD will be reactivated. + * + * Control Transfers + * ----------------- + * Control Transfers are issued by filling the tmp_td with the appropriate data and connect + * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued, + * the programm has to wait for completion. This does not allows asynchronous data transfer. + * + * Bulk Transfers + * -------------- + * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect + * them to the qh_bulk queue header. Before other control/bulk transfers can be issued, + * the programm has to wait for completion. This does not allows asynchronous data transfer. + * + * + */ + +#include <common.h> +#include <ambapp.h> +#include <asm/leon.h> +#include <asm/leon3.h> +#include <asm/processor.h> + +#ifdef CONFIG_USB_UHCI + +#include <usb.h> +#include "usb_uhci.h" + +#define USB_MAX_TEMP_TD 128 /* number of temporary TDs for bulk and control transfers */ +#define USB_MAX_TEMP_INT_TD 32 /* number of temporary TDs for Interrupt transfers */ + +extern int leon3_snooping_avail; +/* +#define out16r(address,data) (*(unsigned short *)(address) = \ + (unsigned short)( \ + (((unsigned short)(data)&0xff)<<8) | \ + (((unsigned short)(data)&0xff00)>>8) \ + )) + */ +#define out16r(address,data) _out16r((unsigned int)(address), (unsigned short)(data)) +void _out16r(unsigned int address, unsigned short data) +{ + unsigned short val = (unsigned short)((((unsigned short)(data) & 0xff) + << 8) | (((unsigned short)(data) + & 0xff00) >> 8)); +#ifdef UHCI_DEBUG_REGS + printf("out16r(0x%lx,0x%04x = 0x%04x)\n", address, val, data); +#endif + *(unsigned short *)(address) = val; +} + +#define out32r(address,data) _out32r((unsigned int)(address), (unsigned int)(data)) +void _out32r(unsigned int address, unsigned int data) +{ + unsigned int val = (unsigned int)((((unsigned int)(data) & 0x000000ff) + << 24) | (((unsigned int)(data) & + 0x0000ff00) << 8) | + (((unsigned int)(data) & 0x00ff0000) + >> 8) | (((unsigned int)(data) & + 0xff000000) >> 24)); +#ifdef UHCI_DEBUG_REGS + printf("out32r(0x%lx,0x%lx = 0x%lx)\n", address, val, data); +#endif + *(unsigned int *)address = val; +} + +#define in16r(address) _in16r((unsigned int)(address)) +unsigned short _in16r(unsigned int address) +{ + unsigned short val = sparc_load_reg_cachemiss_word(address); + val = ((val << 8) & 0xff00) | ((val >> 8) & 0xff); +#ifdef UHCI_DEBUG_REGS + printf("in16r(0x%lx): 0x%04x\n", address, val); +#endif + return val; +} + +#define in32r(address) _in32r((unsigned int)(address)) +unsigned int _in32r(unsigned int address) +{ + unsigned int val = sparc_load_reg_cachemiss(address); + val = + ((val << 24) & 0xff000000) | ((val << 8) & 0xff0000) | ((val >> 8) & + 0xff00) | + ((val >> 24) & 0xff); +#ifdef UHCI_DEBUG_REGS + printf("in32r(0x%lx): 0x%08x\n", address, val); +#endif + return val; +} + +#define READ32(address) sparc_load_reg_cachemiss((unsigned int)(address)) + +/*#define USB_UHCI_DEBUG*/ +#undef USB_UHCI_DEBUG + +void usb_show_td(int max); +#ifdef USB_UHCI_DEBUG +void grusb_show_regs(void); +#define USB_UHCI_PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define USB_UHCI_PRINTF(fmt,args...) +#endif + +static int grusb_irq = -1; /* irq vector, if -1 uhci is stopped / reseted */ +unsigned int usb_base_addr; /* base address */ + +static uhci_td_t td_int[8] __attribute__ ((aligned(16))); /* Interrupt Transfer descriptors */ +static uhci_qh_t qh_cntrl __attribute__ ((aligned(16))); /* control Queue Head */ +static uhci_qh_t qh_bulk __attribute__ ((aligned(16))); /* bulk Queue Head */ +static uhci_qh_t qh_end __attribute__ ((aligned(16))); /* end Queue Head */ +static uhci_td_t td_last __attribute__ ((aligned(16))); /* last TD (linked with end chain) */ + +/* temporary tds */ +static uhci_td_t tmp_td[USB_MAX_TEMP_TD] __attribute__ ((aligned(16))); /* temporary bulk/control td's */ +static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD] __attribute__ ((aligned(16))); /* temporary interrupt td's */ + +static unsigned long framelist[1024] __attribute__ ((aligned(0x1000))); /* frame list */ + +static struct virt_root_hub rh; /* struct for root hub */ + +/********************************************************************** + * some forward decleration + */ +int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, + struct devrequest *setup); + +/* fill a td with the approproiate data. Link, status, info and buffer + * are used by the USB controller itselfes, dev is used to identify the + * "connected" device + */ +void usb_fill_td(uhci_td_t * td, unsigned long link, unsigned long status, + unsigned long info, unsigned long buffer, unsigned long dev) +{ + td->link = swap_32(link); + td->status = swap_32(status); + if ((info & UHCI_PID) == 0) + info |= USB_PID_OUT; + td->info = swap_32(info); + td->buffer = swap_32(buffer); + td->dev_ptr = dev; +} + +/* fill a qh with the approproiate data. Head and element are used by the USB controller + * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh. + * Please note, that after completion of the td chain, the entry element is removed / + * marked invalid by the USB controller. + */ +void usb_fill_qh(uhci_qh_t * qh, unsigned long head, unsigned long element) +{ + qh->head = swap_32(head); + qh->element = swap_32(element); + qh->dev_ptr = 0L; +} + +/* get the status of a td->status + */ +unsigned long usb_uhci_td_stat(unsigned long status) +{ + unsigned long result = 0; + result |= (status & TD_CTRL_NAK) ? USB_ST_NAK_REC : 0; + result |= (status & TD_CTRL_STALLED) ? USB_ST_STALLED : 0; + result |= (status & TD_CTRL_DBUFERR) ? USB_ST_BUF_ERR : 0; + result |= (status & TD_CTRL_BABBLE) ? USB_ST_BABBLE_DET : 0; + result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0; + result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0; + result |= (status & TD_CTRL_ACTIVE) ? USB_ST_NOT_PROC : 0; + return result; +} + +/* get the status and the transfered len of a td chain. + * called from the completion handler + */ +int usb_get_td_status(uhci_td_t * td, struct usb_device *dev) +{ + unsigned long temp, info; + unsigned long stat; + uhci_td_t *mytd = td; + + if (dev->devnum == rh.devnum) + return 0; + dev->act_len = 0; + stat = 0; + do { + temp = swap_32((unsigned long)READ32(&mytd->status)); + stat = usb_uhci_td_stat(temp); + info = swap_32((unsigned long)READ32(&mytd->info)); + if (((info & 0xff) != USB_PID_SETUP) && (((info >> 21) & 0x7ff) != 0x7ff) && (temp & 0x7FF) != 0x7ff) { /* if not setup and not null data pack */ + dev->act_len += (temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */ + } + if (stat) { /* status no ok */ + dev->status = stat; + return -1; + } + temp = swap_32((unsigned long)READ32(&mytd->link)); + mytd = (uhci_td_t *) (temp & 0xfffffff0); + } while ((temp & 0x1) == 0); /* process all TDs */ + dev->status = stat; + return 0; /* Ok */ +} + +/*------------------------------------------------------------------- + * LOW LEVEL STUFF + * assembles QHs und TDs for control, bulk and iso + *-------------------------------------------------------------------*/ +int dummy(void) +{ + USB_UHCI_PRINTF("DUMMY\n"); + return 0; +} + +/* Submits a control message. That is a Setup, Data and Status transfer. + * Routine does not wait for completion. + */ +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup) +{ + unsigned long destination, status; + int maxsze = usb_maxpacket(dev, pipe); + unsigned long dataptr; + int len; + int pktsze; + int i = 0; + + if (!maxsze) { + USB_UHCI_PRINTF + ("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", + pipe); + return -1; + } + if (((pipe >> 8) & 0x7f) == rh.devnum) { + /* this is the root hub -> redirect it */ + return uhci_submit_rh_msg(dev, pipe, buffer, transfer_len, + setup); + } + USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n", + transfer_len, maxsze); + /* The "pipe" thing contains the destination in bits 8--18 */ + destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */ + /* 3 errors */ + status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27); + /* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */ + /* Build the TD for the control request, try forever, 8 bytes of data */ + usb_fill_td(&tmp_td[i], UHCI_PTR_TERM, status, destination | (7 << 21), + (unsigned long)setup, (unsigned long)dev); +#ifdef DEBUG_EXTRA + { + char *sp = (char *)setup; + printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe, + sp[0], sp[1], sp[2], sp[3], sp[4], sp[5], sp[6], sp[7]); + } +#endif + dataptr = (unsigned long)buffer; + len = transfer_len; + + /* If direction is "send", change the frame from SETUP (0x2D) + to OUT (0xE1). Else change it from SETUP to IN (0x69). */ + destination = + (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN) == + 0 ? USB_PID_OUT : USB_PID_IN); + while (len > 0) { + /* data stage */ + pktsze = len; + i++; + if (pktsze > maxsze) + pktsze = maxsze; + destination ^= 1 << TD_TOKEN_TOGGLE; /* toggle DATA0/1 */ + usb_fill_td(&tmp_td[i], UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21), dataptr, (unsigned long)dev); /* Status, pktsze bytes of data */ + tmp_td[i - 1].link = swap_32((unsigned long)&tmp_td[i]); + + dataptr += pktsze; + len -= pktsze; + } + + /* Build the final TD for control status */ + /* It's only IN if the pipe is out AND we aren't expecting data */ + + destination &= ~UHCI_PID; + if (((pipe & USB_DIR_IN) == 0) || (transfer_len == 0)) + destination |= USB_PID_IN; + else + destination |= USB_PID_OUT; + destination |= 1 << TD_TOKEN_TOGGLE; /* End in Data1 */ + i++; + status &= ~TD_CTRL_SPD; + /* no limit on errors on final packet , 0 bytes of data */ + usb_fill_td(&tmp_td[i], UHCI_PTR_TERM, status | TD_CTRL_IOC, + destination | (UHCI_NULL_DATA_SIZE << 21), 0, + (unsigned long)dev); + tmp_td[i - 1].link = swap_32((unsigned long)&tmp_td[i]); /* queue status td */ + /* usb_show_td(i+1); */ + USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n", i); + /* first mark the control QH element terminated */ + qh_cntrl.element = 0xffffffffL; + /* set qh active */ + qh_cntrl.dev_ptr = (unsigned long)dev; + /* fill in tmp_td_chain */ + dummy(); + qh_cntrl.element = swap_32((unsigned long)&tmp_td[0]); + return 0; +} + +/*------------------------------------------------------------------- + * Prepare TDs for bulk transfers. + */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len) +{ + unsigned long destination, status, info; + unsigned long dataptr; + int maxsze = usb_maxpacket(dev, pipe); + int len; + int i = 0; + + if (transfer_len < 0) { + printf("Negative transfer length in submit_bulk\n"); + return -1; + } + if (!maxsze) + return -1; + /* The "pipe" thing contains the destination in bits 8--18. */ + destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid(pipe); + /* 3 errors */ + status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27); + /* ((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */ + /* Build the TDs for the bulk request */ + len = transfer_len; + dataptr = (unsigned long)buffer; + do { + int pktsze = len; + if (pktsze > maxsze) + pktsze = maxsze; + /* pktsze bytes of data */ + info = + destination | (((pktsze - 1) & UHCI_NULL_DATA_SIZE) << 21) | + (usb_gettoggle + (dev, usb_pipeendpoint(pipe), + usb_pipeout(pipe)) << TD_TOKEN_TOGGLE); + + if ((len - pktsze) == 0) + status |= TD_CTRL_IOC; /* last one generates INT */ + + usb_fill_td(&tmp_td[i], UHCI_PTR_TERM, status, info, dataptr, (unsigned long)dev); /* Status, pktsze bytes of data */ + if (i > 0) + tmp_td[i - 1].link = swap_32((unsigned long)&tmp_td[i]); + i++; + dataptr += pktsze; + len -= pktsze; + usb_dotoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); + } while (len > 0); + /* first mark the bulk QH element terminated */ + qh_bulk.element = 0xffffffffL; + /* set qh active */ + qh_bulk.dev_ptr = (unsigned long)dev; + /* fill in tmp_td_chain */ + qh_bulk.element = swap_32((unsigned long)&tmp_td[0]); + return 0; +} + +/* search a free interrupt td + */ +uhci_td_t *uhci_alloc_int_td(void) +{ + int i; + for (i = 0; i < USB_MAX_TEMP_INT_TD; i++) { + if (tmp_int_td[i].dev_ptr == 0) /* no device assigned -> free TD */ + return &tmp_int_td[i]; + } + return NULL; +} + +/*------------------------------------------------------------------- + * submits USB interrupt (ie. polling ;-) + */ +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + int nint, n; + unsigned long status, destination; + unsigned long info, tmp; + uhci_td_t *mytd; + if (interval < 0 || interval >= 256) + return -1; + + if (interval == 0) + nint = 0; + else { + for (nint = 0, n = 1; nint <= 8; nint++, n += n) { /* round interval down to 2^n */ + if (interval < n) { + interval = n / 2; + break; + } + } + nint--; + } + + USB_UHCI_PRINTF("Rounded interval to %i, chain %i\n", interval, nint); + mytd = uhci_alloc_int_td(); + if (mytd == NULL) { + printf("No free INT TDs found\n"); + return -1; + } + status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27); +/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27); +*/ + + destination = + (pipe & PIPE_DEVEP_MASK) | usb_packetid(pipe) | + (((transfer_len - 1) & 0x7ff) << 21); + + info = + destination | + (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << + TD_TOKEN_TOGGLE); + tmp = swap_32(td_int[nint].link); + usb_fill_td(mytd, tmp, status, info, (unsigned long)buffer, + (unsigned long)dev); + /* Link it */ + tmp = swap_32((unsigned long)mytd); + td_int[nint].link = tmp; + + usb_dotoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); + + return 0; +} + +/********************************************************************** + * Low Level functions + */ + +void reset_hc(void) +{ + + /* Global reset for 100ms */ + out16r(usb_base_addr + USBPORTSC1, 0x0204); + out16r(usb_base_addr + USBPORTSC2, 0x0204); + out16r(usb_base_addr + USBCMD, USBCMD_GRESET | USBCMD_RS); + /* Turn off all interrupts */ + out16r(usb_base_addr + USBINTR, 0); + wait_ms(50); + out16r(usb_base_addr + USBCMD, 0); + wait_ms(10); +} + +void start_hc(void) +{ + int timeout = 1000; + + while (in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) { + if (!--timeout) { + printf("USBCMD_HCRESET timed out!\n"); + break; + } + } + /* Turn on all interrupts */ + out16r(usb_base_addr + USBINTR, + USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP); + /* Start at frame 0 */ + out16r(usb_base_addr + USBFRNUM, 0); + /* set Framebuffer base address */ + out32r(usb_base_addr + USBFLBASEADD, (unsigned long)&framelist); + /* Run and mark it configured with a 64-byte max packet */ + out16r(usb_base_addr + USBCMD, USBCMD_RS | USBCMD_CF | USBCMD_MAXP); +} + +/* Initialize the skeleton + */ +void usb_init_skel(void) +{ + unsigned long temp; + int n; + + for (n = 0; n < USB_MAX_TEMP_INT_TD; n++) + tmp_int_td[n].dev_ptr = 0L; /* no devices connected */ + /* last td */ + usb_fill_td(&td_last, UHCI_PTR_TERM, TD_CTRL_IOC, USB_PID_OUT, 0, 0L); + /* usb_fill_td(&td_last,UHCI_PTR_TERM,0,0,0); */ + /* End Queue Header */ + usb_fill_qh(&qh_end, UHCI_PTR_TERM, (unsigned long)&td_last); + /* Bulk Queue Header */ + temp = (unsigned long)&qh_end; + usb_fill_qh(&qh_bulk, temp | UHCI_PTR_QH, UHCI_PTR_TERM); + /* Control Queue Header */ + temp = (unsigned long)&qh_bulk; + usb_fill_qh(&qh_cntrl, temp | UHCI_PTR_QH, UHCI_PTR_TERM); + /* 1ms Interrupt td */ + temp = (unsigned long)&qh_cntrl; + usb_fill_td(&td_int[0], temp | UHCI_PTR_QH, 0, USB_PID_OUT, 0, 0L); + temp = (unsigned long)&td_int[0]; + for (n = 1; n < 8; n++) + usb_fill_td(&td_int[n], temp, 0, USB_PID_OUT, 0, 0L); + for (n = 0; n < 1024; n++) { + /* link all framelist pointers to one of the interrupts */ + int m, o; + if ((n & 127) == 127) + framelist[n] = swap_32((unsigned long)&td_int[0]); + else + for (o = 1, m = 2; m <= 128; o++, m += m) + if ((n & (m - 1)) == ((m - 1) / 2)) + framelist[n] = + swap_32((unsigned long)&td_int[o]); + + } +} + +/* check the common skeleton for completed transfers, and update the status + * of the "connected" device. Called from the IRQ routine. + */ +void usb_check_skel(void) +{ + struct usb_device *dev; + /* start with the control qh */ + if (qh_cntrl.dev_ptr != 0) { /* it's a device assigned check if this caused IRQ */ + dev = (struct usb_device *)qh_cntrl.dev_ptr; + /* Flush cache now that hardware updated DATA and TDs/QHs */ + if (!leon3_snooping_avail) + sparc_dcache_flush_all(); + usb_get_td_status(&tmp_td[0], dev); /* update status */ + if (!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ + qh_cntrl.dev_ptr = 0; + } + } + /* now process the bulk */ + if (qh_bulk.dev_ptr != 0) { /* it's a device assigned check if this caused IRQ */ + dev = (struct usb_device *)qh_bulk.dev_ptr; + /* Flush cache now that hardware updated DATA and TDs/QHs */ + if (!leon3_snooping_avail) + sparc_dcache_flush_all(); + usb_get_td_status(&tmp_td[0], dev); /* update status */ + if (!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ + qh_bulk.dev_ptr = 0; + } + } +} + +/* check the interrupt chain, ubdate the status of the appropriate device, + * call the appropriate irqhandler and reactivate the TD if the irqhandler + * returns with 1 + */ +void usb_check_int_chain(void) +{ + int i, res; + unsigned long link, status; + struct usb_device *dev; + uhci_td_t *td, *prevtd; + + for (i = 0; i < 8; i++) { + prevtd = &td_int[i]; /* the first previous td is the skeleton td */ + link = swap_32(READ32(&td_int[i].link)) & 0xfffffff0; /* next in chain */ + td = (uhci_td_t *) link; /* assign it */ + /* all interrupt TDs are finally linked to the td_int[0]. + * so we process all until we find the td_int[0]. + * if int0 chain points to a QH, we're also done + */ + while (((i > 0) && (link != (unsigned long)&td_int[0])) || + ((i == 0) + && !(swap_32(READ32(&td->link)) & UHCI_PTR_QH))) { + /* check if a device is assigned with this td */ + status = swap_32(READ32(&td->status)); + if ((td->dev_ptr != 0L) && !(status & TD_CTRL_ACTIVE)) { + /* td is not active and a device is assigned -> call irqhandler */ + dev = (struct usb_device *)td->dev_ptr; + dev->irq_act_len = ((status & 0x7FF) == 0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */ + dev->irq_status = usb_uhci_td_stat(status); /* get status */ + res = dev->irq_handle(dev); /* call irqhandler */ + if (res == 1) { + /* reactivate */ + status |= TD_CTRL_ACTIVE; + td->status = swap_32(status); + prevtd = td; /* previous td = this td */ + } else { + prevtd->link = READ32(&td->link); /* link previous td directly to the nex td -> unlinked */ + /* remove device pointer */ + td->dev_ptr = 0L; + } + } /* if we call the irq handler */ + link = swap_32(READ32(&td->link)) & 0xfffffff0; /* next in chain */ + td = (uhci_td_t *) link; /* assign it */ + } /* process all td in this int chain */ + } /* next interrupt chain */ +} + +/* usb interrupt service routine. + */ +void handle_usb_interrupt(void) +{ + unsigned short status; + static int error = 0; + + /* + * Read the interrupt status, and write it back to clear the + * interrupt cause + */ + + status = in16r(usb_base_addr + USBSTS); + + if (!status) /* shared interrupt, not mine */ + return; + if (status != 1) { + /* remove host controller halted state */ + if ((status & (USBSTS_HCPE | USBSTS_HCH)) == + (USBSTS_HCPE | USBSTS_HCH)) { + /* Stop due to bug in driver, or hardware */ + out16r(usb_base_addr + USBSTS, status); + out16r(usb_base_addr + USBCMD, + USBCMD_HCRESET | USBCMD_GRESET); + printf + ("GRUSB: HW detected error(s) in USB Descriptors (STS: 0x%x)\n", + status); + usb_show_td(8); + return; + } else if ((status & 0x20) + && ((in16r(usb_base_addr + USBCMD) & USBCMD_RS) == + 0)) { + if (error < 10) { + out16r(usb_base_addr + USBCMD, + USBCMD_RS | in16r(usb_base_addr + + USBCMD)); + error++; + } + } else + error = 0; + } + usb_check_int_chain(); /* call interrupt handlers for int tds */ + usb_check_skel(); /* call completion handler for common transfer routines */ + out16r(usb_base_addr + USBSTS, status); +} + +/* init uhci + */ +int usb_lowlevel_init(void) +{ + unsigned char temp; + ambapp_ahbdev ahbdev; + + /* Find GRUSB core using AMBA Plug&Play information */ + if (ambapp_ahbslv_first(VENDOR_GAISLER, GAISLER_UHCI, &ahbdev) != 1) { + printf("USB UHCI: Failed to find GRUSB controller\n"); + return -1; + } + usb_base_addr = ahbdev.address[0]; + grusb_irq = ahbdev.irq; + /* + usb_base_addr = 0xfffa0000; + grusb_irq = 10; + */ +#ifdef USB_UHCI_DEBUG + grusb_show_regs(); +#endif + memset(td_int, 0, sizeof(td_int)); + memset(tmp_td, 0, sizeof(tmp_td)); + memset(tmp_int_td, 0, sizeof(tmp_int_td)); + memset(&qh_cntrl, 0, sizeof(qh_cntrl)); + memset(&qh_end, 0, sizeof(qh_end)); + memset(&td_last, 0, sizeof(td_last)); + + irq_free_handler(grusb_irq); + USB_UHCI_PRINTF("GRUSB: at 0x%lx irq %d\n", usb_base_addr, grusb_irq); + rh.devnum = 0; + usb_init_skel(); + reset_hc(); + start_hc(); + irq_install_handler(grusb_irq, + (interrupt_handler_t *) handle_usb_interrupt, NULL); + return 0; +} + +/* stop uhci + */ +int usb_lowlevel_stop(void) +{ + if (grusb_irq == -1) + return 1; + irq_free_handler(grusb_irq); + reset_hc(); + grusb_irq = -1; + return 0; +} + +/******************************************************************************************* + * Virtual Root Hub + * Since the uhci does not have a real HUB, we simulate one ;-) + */ +#undef USB_RH_DEBUG + +#ifdef USB_RH_DEBUG +#define USB_RH_PRINTF(fmt,args...) printf (fmt ,##args) +static void usb_display_wValue(unsigned short wValue, unsigned short wIndex); +static void usb_display_Req(unsigned short req); +#else +#define USB_RH_PRINTF(fmt,args...) +static void usb_display_wValue(unsigned short wValue, unsigned short wIndex) +{ +} +static void usb_display_Req(unsigned short req) +{ +} +#endif + +static unsigned char root_hub_dev_des[] = { + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x00, /* __u16 bcdUSB; v1.0 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x01, /* __u8 iManufacturer; */ + 0x00, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static unsigned char root_hub_config_des[] = { + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x08, /* __u16 ep_wMaxPacketSize; 8 Bytes */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_hub_des[] = { + 0x09, /* __u8 bLength; */ + 0x29, /* __u8 bDescriptorType; Hub-descriptor */ + 0x02, /* __u8 bNbrPorts; */ + 0x00, /* __u16 wHubCharacteristics; */ + 0x00, + 0x01, /* __u8 bPwrOn2pwrGood; 2ms */ + 0x00, /* __u8 bHubContrCurrent; 0 mA */ + 0x00, /* __u8 DeviceRemovable; *** 7 Ports max *** */ + 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ +}; + +static unsigned char root_hub_str_index0[] = { + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = { + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'U', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* + * Root Hub Control Pipe (interrupt Pipes are not supported) + */ + +int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *cmd) +{ + void *data = buffer; + int leni = transfer_len; + int len = 0; + int status = 0; + int stat = 0; + int i; + + unsigned short cstatus; + + unsigned short bmRType_bReq; + unsigned short wValue; + unsigned short wIndex; + unsigned short wLength; + + if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + printf("Root-Hub submit IRQ: NOT implemented\n"); + return 0; + } + bmRType_bReq = cmd->requesttype | cmd->request << 8; + wValue = swap_16(cmd->value); + wIndex = swap_16(cmd->index); + wLength = swap_16(cmd->length); + usb_display_Req(bmRType_bReq); + for (i = 0; i < 8; i++) + rh.c_p_r[i] = 0; + USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n", + dev->devnum, 8, cmd->requesttype, cmd->request, wValue, + wIndex, wLength); + + switch (bmRType_bReq) { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + + case RH_GET_STATUS: + *(unsigned short *)data = swap_16(1); + len = 2; + break; + case RH_GET_STATUS | RH_INTERFACE: + *(unsigned short *)data = swap_16(0); + len = 2; + break; + case RH_GET_STATUS | RH_ENDPOINT: + *(unsigned short *)data = swap_16(0); + len = 2; + break; + case RH_GET_STATUS | RH_CLASS: + *(unsigned long *)data = swap_32(0); + len = 4; + break; /* hub power ** */ + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + + status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1)); + cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) | + ((status & USBPORTSC_PEC) >> (3 - 1)) | + (rh.c_p_r[wIndex - 1] << (0 + 4)); + status = (status & USBPORTSC_CCS) | ((status & USBPORTSC_PE) >> (2 - 1)) | ((status & USBPORTSC_SUSP) >> (12 - 2)) | ((status & USBPORTSC_PR) >> (9 - 4)) | (1 << 8) | /* power on ** */ + ((status & USBPORTSC_LSDA) << (-8 + 9)); + + *(unsigned short *)data = swap_16(status); + *(unsigned short *)(data + 2) = swap_16(cstatus); + len = 4; + break; + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) { + case (RH_ENDPOINT_STALL): + len = 0; + break; + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) { + case (RH_C_HUB_OVER_CURRENT): + len = 0; /* hub power over current ** */ + break; + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + usb_display_wValue(wValue, wIndex); + switch (wValue) { + case (RH_PORT_ENABLE): + status = + in16r(usb_base_addr + USBPORTSC1 + + 2 * (wIndex - 1)); + status = (status & 0xfff5) & ~USBPORTSC_PE; + out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), + status); + len = 0; + break; + case (RH_PORT_SUSPEND): + status = + in16r(usb_base_addr + USBPORTSC1 + + 2 * (wIndex - 1)); + status = (status & 0xfff5) & ~USBPORTSC_SUSP; + out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), + status); + len = 0; + break; + case (RH_PORT_POWER): + len = 0; /* port power ** */ + break; + case (RH_C_PORT_CONNECTION): + status = + in16r(usb_base_addr + USBPORTSC1 + + 2 * (wIndex - 1)); + status = (status & 0xfff5) | USBPORTSC_CSC; + out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), + status); + len = 0; + break; + case (RH_C_PORT_ENABLE): + status = + in16r(usb_base_addr + USBPORTSC1 + + 2 * (wIndex - 1)); + status = (status & 0xfff5) | USBPORTSC_PEC; + out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), + status); + len = 0; + break; + case (RH_C_PORT_SUSPEND): +/*** WR_RH_PORTSTAT(RH_PS_PSSC); */ + len = 0; + break; + case (RH_C_PORT_OVER_CURRENT): + len = 0; + break; + case (RH_C_PORT_RESET): + rh.c_p_r[wIndex - 1] = 0; + len = 0; + break; + } + break; + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + usb_display_wValue(wValue, wIndex); + switch (wValue) { + case (RH_PORT_SUSPEND): + status = + in16r(usb_base_addr + USBPORTSC1 + + 2 * (wIndex - 1)); + status = (status & 0xfff5) | USBPORTSC_SUSP; + out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), + status); + len = 0; + break; + case (RH_PORT_RESET): + status = + in16r(usb_base_addr + USBPORTSC1 + + 2 * (wIndex - 1)); + status = (status & 0xfff5) | USBPORTSC_PR; + out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), + status); + wait_ms(10); + status = (status & 0xfff5) & ~USBPORTSC_PR; + out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), + status); + udelay(10); + status = (status & 0xfff5) | USBPORTSC_PE; + out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), + status); + wait_ms(10); + status = (status & 0xfff5) | 0xa; + out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), + status); + len = 0; + break; + case (RH_PORT_POWER): + len = 0; /* port power ** */ + break; + case (RH_PORT_ENABLE): + status = + in16r(usb_base_addr + USBPORTSC1 + + 2 * (wIndex - 1)); + status = (status & 0xfff5) | USBPORTSC_PE; + out16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1), + status); + len = 0; + break; + } + break; + + case RH_SET_ADDRESS: + rh.devnum = wValue; + len = 0; + break; + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + i = sizeof(root_hub_config_des); + status = i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy(data, root_hub_dev_des, len); + break; + case (0x02): /* configuration descriptor */ + i = sizeof(root_hub_config_des); + status = i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy(data, root_hub_config_des, len); + break; + case (0x03): /*string descriptors */ + if (wValue == 0x0300) { + i = sizeof(root_hub_str_index0); + status = i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy(data, root_hub_str_index0, len); + break; + } + if (wValue == 0x0301) { + i = sizeof(root_hub_str_index1); + status = i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy(data, root_hub_str_index1, len); + break; + } + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + root_hub_hub_des[2] = 2; + i = sizeof(root_hub_hub_des); + status = i > wLength ? wLength : i; + len = leni > status ? status : leni; + memcpy(data, root_hub_hub_des, len); + break; + case RH_GET_CONFIGURATION: + *(unsigned char *)data = 0x01; + len = 1; + break; + case RH_SET_CONFIGURATION: + len = 0; + break; + default: + stat = USB_ST_STALLED; + } + USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n", stat, + in16r(usb_base_addr + USBPORTSC1), + in16r(usb_base_addr + USBPORTSC2)); + dev->act_len = len; + dev->status = stat; + return stat; + +} + +/******************************************************************************** + * Some Debug Routines + */ + +#ifdef USB_RH_DEBUG + +static void usb_display_Req(unsigned short req) +{ + USB_RH_PRINTF("- Root-Hub Request: "); + switch (req) { + case RH_GET_STATUS: + USB_RH_PRINTF("Get Status "); + break; + case RH_GET_STATUS | RH_INTERFACE: + USB_RH_PRINTF("Get Status Interface "); + break; + case RH_GET_STATUS | RH_ENDPOINT: + USB_RH_PRINTF("Get Status Endpoint "); + break; + case RH_GET_STATUS | RH_CLASS: + USB_RH_PRINTF("Get Status Class"); + break; /* hub power ** */ + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + USB_RH_PRINTF("Get Status Class Others"); + break; + case RH_CLEAR_FEATURE | RH_ENDPOINT: + USB_RH_PRINTF("Clear Feature Endpoint "); + break; + case RH_CLEAR_FEATURE | RH_CLASS: + USB_RH_PRINTF("Clear Feature Class "); + break; + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + USB_RH_PRINTF("Clear Feature Other Class "); + break; + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + USB_RH_PRINTF("Set Feature Other Class "); + break; + case RH_SET_ADDRESS: + USB_RH_PRINTF("Set Address "); + break; + case RH_GET_DESCRIPTOR: + USB_RH_PRINTF("Get Descriptor "); + break; + case RH_GET_DESCRIPTOR | RH_CLASS: + USB_RH_PRINTF("Get Descriptor Class "); + break; + case RH_GET_CONFIGURATION: + USB_RH_PRINTF("Get Configuration "); + break; + case RH_SET_CONFIGURATION: + USB_RH_PRINTF("Get Configuration "); + break; + default: + USB_RH_PRINTF("****UNKNOWN**** 0x%04X ", req); + } + USB_RH_PRINTF("\n"); + +} + +static void usb_display_wValue(unsigned short wValue, unsigned short wIndex) +{ + switch (wValue) { + case (RH_PORT_ENABLE): + USB_RH_PRINTF("Root-Hub: Enable Port %d\n", wIndex); + break; + case (RH_PORT_SUSPEND): + USB_RH_PRINTF("Root-Hub: Suspend Port %d\n", wIndex); + break; + case (RH_PORT_POWER): + USB_RH_PRINTF("Root-Hub: Port Power %d\n", wIndex); + break; + case (RH_C_PORT_CONNECTION): + USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n", wIndex); + break; + case (RH_C_PORT_ENABLE): + USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n", wIndex); + break; + case (RH_C_PORT_SUSPEND): + USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n", wIndex); + break; + case (RH_C_PORT_OVER_CURRENT): + USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n", + wIndex); + break; + case (RH_C_PORT_RESET): + USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n", wIndex); + break; + default: + USB_RH_PRINTF("Root-Hub: unknown %x %x\n", wValue, wIndex); + break; + } +} + +#endif + +/*#ifdef USB_UHCI_DEBUG*/ + +static int usb_display_td(uhci_td_t * td) +{ + unsigned long tmp; + int valid; + + printf("TD at %p:\n", td); + + tmp = swap_32(READ32(&td->link)); + printf("Link points to 0x%08lX, %s first, %s, %s\n", tmp & 0xfffffff0, + ((tmp & 0x4) == 0x4) ? "Depth" : "Breath", + ((tmp & 0x2) == 0x2) ? "QH" : "TD", + ((tmp & 0x1) == 0x1) ? "invalid" : "valid"); + valid = ((tmp & 0x1) == 0x0); + tmp = swap_32(READ32(&td->status)); + printf + (" %s %ld Errors %s %s %s \n %s %s %s %s %s %s\n Len 0x%lX\n", + (((tmp >> 29) & 0x1) == 0x1) ? "SPD Enable" : "SPD Disable", + ((tmp >> 28) & 0x3), + (((tmp >> 26) & 0x1) == 0x1) ? "Low Speed" : "Full Speed", + (((tmp >> 25) & 0x1) == 0x1) ? "ISO " : "", + (((tmp >> 24) & 0x1) == 0x1) ? "IOC " : "", + (((tmp >> 23) & 0x1) == 0x1) ? "Active " : "Inactive ", + (((tmp >> 22) & 0x1) == 0x1) ? "Stalled" : "", + (((tmp >> 21) & 0x1) == 0x1) ? "Data Buffer Error" : "", + (((tmp >> 20) & 0x1) == 0x1) ? "Babble" : "", + (((tmp >> 19) & 0x1) == 0x1) ? "NAK" : "", + (((tmp >> 18) & 0x1) == 0x1) ? "Bitstuff Error" : "", + (tmp & 0x7ff)); + tmp = swap_32(READ32(&td->info)); + printf(" MaxLen 0x%lX\n", ((tmp >> 21) & 0x7FF)); + printf(" %sEndpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n", + ((tmp >> 19) & 0x1) == 0x1 ? "TOGGLE " : "", ((tmp >> 15) & 0xF), + ((tmp >> 8) & 0x7F), tmp & 0xFF); + tmp = swap_32(READ32(&td->buffer)); + printf(" Buffer 0x%08lX\n", tmp); + printf(" DEV %08lX\n", td->dev_ptr); + return valid; +} + +void usb_show_td(int max) +{ + int i; + if (max > 0) { + for (i = 0; i < max; i++) { + usb_display_td(&tmp_td[i]); + } + } else { + i = 0; + do { + printf("tmp_td[%d]\n", i); + } while (usb_display_td(&tmp_td[i++])); + } +} + +void grusb_show_regs(void) +{ + unsigned int tmp; + + tmp = in16r(usb_base_addr + USBCMD); + printf(" USBCMD: 0x%04x\n", tmp); + tmp = in16r(usb_base_addr + USBSTS); + printf(" USBSTS: 0x%04x\n", tmp); + tmp = in16r(usb_base_addr + USBINTR); + printf(" USBINTR: 0x%04x\n", tmp); + tmp = in16r(usb_base_addr + USBFRNUM); + printf(" FRNUM: 0x%04x\n", tmp); + tmp = in32r(usb_base_addr + USBFLBASEADD); + printf(" FLBASEADD: 0x%08x\n", tmp); + tmp = in16r(usb_base_addr + USBSOF); + printf(" SOFMOD: 0x%04x\n", tmp); + tmp = in16r(usb_base_addr + USBPORTSC1); + printf(" PORTSC1: 0x%04x\n", tmp); +} + +/*#endif*/ +#endif /* CONFIG_USB_UHCI */ + +/* EOF */ diff --git a/cpu/leon3/usb_uhci.h b/cpu/leon3/usb_uhci.h new file mode 100644 index 0000000000..bf572a661b --- /dev/null +++ b/cpu/leon3/usb_uhci.h @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: Part of this code has been derived from linux + * + */ +#ifndef _USB_UHCI_H_ +#define _USB_UHCI_H_ + +/* Command register */ +#define USBCMD 0 +#define USBCMD_RS 0x0001 /* Run/Stop */ +#define USBCMD_HCRESET 0x0002 /* Host reset */ +#define USBCMD_GRESET 0x0004 /* Global reset */ +#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ +#define USBCMD_FGR 0x0010 /* Force Global Resume */ +#define USBCMD_SWDBG 0x0020 /* SW Debug mode */ +#define USBCMD_CF 0x0040 /* Config Flag (sw only) */ +#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ + +/* Status register */ +#define USBSTS 2 +#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ +#define USBSTS_ERROR 0x0002 /* Interrupt due to error */ +#define USBSTS_RD 0x0004 /* Resume Detect */ +#define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */ +#define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */ +#define USBSTS_HCH 0x0020 /* HC Halted */ + +/* Interrupt enable register */ +#define USBINTR 4 +#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ +#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ +#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ +#define USBINTR_SP 0x0008 /* Short packet interrupt enable */ + +#define USBFRNUM 6 +#define USBFLBASEADD 8 +#define USBSOF 12 + +/* USB port status and control registers */ +#define USBPORTSC1 16 +#define USBPORTSC2 18 +#define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */ +#define USBPORTSC_CSC 0x0002 /* Connect Status Change */ +#define USBPORTSC_PE 0x0004 /* Port Enable */ +#define USBPORTSC_PEC 0x0008 /* Port Enable Change */ +#define USBPORTSC_LS 0x0030 /* Line Status */ +#define USBPORTSC_RD 0x0040 /* Resume Detect */ +#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ +#define USBPORTSC_PR 0x0200 /* Port Reset */ +#define USBPORTSC_SUSP 0x1000 /* Suspend */ + +/* Legacy support register */ +#define USBLEGSUP 0xc0 +#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ + +#define UHCI_NULL_DATA_SIZE 0x7ff /* for UHCI controller TD */ +#define UHCI_PID 0xff /* PID MASK */ + +#define UHCI_PTR_BITS 0x000F +#define UHCI_PTR_TERM 0x0001 +#define UHCI_PTR_QH 0x0002 +#define UHCI_PTR_DEPTH 0x0004 + +/* for TD <status>: */ +#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ +#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ +#define TD_CTRL_LS (1 << 26) /* Low Speed Device */ +#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ +#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ +#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ +#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ +#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ +#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ +#define TD_CTRL_NAK (1 << 19) /* NAK Received */ +#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ +#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ +#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */ + +#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ + TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF) + +#define TD_TOKEN_TOGGLE 19 + +/* ------------------------------------------------------------------------------------ + Virtual Root HUB + ------------------------------------------------------------------------------------ */ +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +/* Our Vendor Specific feature */ +#define RH_REMOVE_EP 0x00 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + +/* Transfer descriptor structure */ +typedef struct { + unsigned long link; /* next td/qh (LE) */ + unsigned long status; /* status of the td */ + unsigned long info; /* Max Lenght / Endpoint / device address and PID */ + unsigned long buffer; /* pointer to data buffer (LE) */ + unsigned long dev_ptr; /* pointer to the assigned device (BE) */ + unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */ +} uhci_td_t, *puhci_td_t; + +/* Queue Header structure */ +typedef struct { + unsigned long head; /* Next QH (LE) */ + unsigned long element; /* Queue element pointer (LE) */ + unsigned long res[5]; /* reserved */ + unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */ +} uhci_qh_t, *puhci_qh_t; + +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + int numports; /* number of ports */ + int c_p_r[8]; /* C_PORT_RESET */ +}; + +#endif /* _USB_UHCI_H_ */ diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S index 0e2db1261f..1b47c9775d 100644 --- a/cpu/mcf5227x/start.S +++ b/cpu/mcf5227x/start.S @@ -354,3 +354,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S index 2bd603db66..ad04c0984a 100644 --- a/cpu/mcf523x/start.S +++ b/cpu/mcf523x/start.S @@ -338,3 +338,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk index c3899c507e..650e340aee 100644 --- a/cpu/mcf52x2/config.mk +++ b/cpu/mcf52x2/config.mk @@ -30,6 +30,7 @@ is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg)) is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg)) is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg)) is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg)) +is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg)) is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg)) @@ -47,6 +48,9 @@ endif ifneq (,$(findstring CONFIG_M5272,$(is5272))) PLATFORM_CPPFLAGS += -mcpu=5272 endif +ifneq (,$(findstring CONFIG_M5275,$(is5275))) +PLATFORM_CPPFLAGS += -mcpu=5275 +endif ifneq (,$(findstring CONFIG_M5282,$(is5282))) PLATFORM_CPPFLAGS += -mcpu=5282 endif diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index 71ea408aa5..d5d3d339c5 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -6,6 +6,9 @@ * (C) Copyright 2005 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> * + * MCF5275 additions + * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -180,6 +183,69 @@ int watchdog_init(void) #endif /* #ifdef CONFIG_M5272 */ +#ifdef CONFIG_M5275 +int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +{ + volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM); + + udelay(1000); + + rcm->rcr = RCM_RCR_SOFTRST; + + /* we don't return! */ + return 0; +}; + +int checkcpu(void) +{ + char buf[32]; + + printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", + strmhz(buf, CFG_CLK)); + return 0; +}; + + +#if defined(CONFIG_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void watchdog_reset(void) +{ + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdt->wsr = 0x5555; + wdt->wsr = 0xAAAA; +} + +int watchdog_disable(void) +{ + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + + wdt->wsr = 0x5555; /* reset watchdog counter */ + wdt->wsr = 0xAAAA; + wdt->wcr = 0; /* disable watchdog timer */ + + puts("WATCHDOG:disabled\n"); + return (0); +} + +int watchdog_init(void) +{ + volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + + wdt->wcr = 0; /* disable watchdog */ + + /* set timeout and enable watchdog */ + wdt->wmr = + ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; + wdt->wsr = 0x5555; /* reset watchdog counter */ + wdt->wsr = 0xAAAA; + + puts("WATCHDOG:enabled\n"); + return (0); +} +#endif /* #ifdef CONFIG_WATCHDOG */ + +#endif /* #ifdef CONFIG_M5275 */ + #ifdef CONFIG_M5282 int checkcpu(void) { diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 458b85ef14..207a37e7d5 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -10,6 +10,9 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * Hayden Fraser (Hayden.Fraser@freescale.com) * + * MCF5275 additions + * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -245,6 +248,114 @@ void uart_port_conf(void) } #endif /* #if defined(CONFIG_M5272) */ +#if defined(CONFIG_M5275) + +/* + * Breathe some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + /* if we come from RAM we assume the CPU is + * already initialized. + */ + +#ifndef CONFIG_MONITOR_IS_IN_RAM + volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG); + volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); + volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS); + + /* Kill watchdog so we can initialize the PLL */ + wdog_reg->wcr = 0; + + /* Memory Controller: */ + /* Flash */ + csctrl_reg->ar0 = CFG_AR0_PRELIM; + csctrl_reg->cr0 = CFG_CR0_PRELIM; + csctrl_reg->mr0 = CFG_MR0_PRELIM; + +#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM)) + csctrl_reg->ar1 = CFG_AR1_PRELIM; + csctrl_reg->cr1 = CFG_CR1_PRELIM; + csctrl_reg->mr1 = CFG_MR1_PRELIM; +#endif + +#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM)) + csctrl_reg->ar2 = CFG_AR2_PRELIM; + csctrl_reg->cr2 = CFG_CR2_PRELIM; + csctrl_reg->mr2 = CFG_MR2_PRELIM; +#endif + +#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM)) + csctrl_reg->ar3 = CFG_AR3_PRELIM; + csctrl_reg->cr3 = CFG_CR3_PRELIM; + csctrl_reg->mr3 = CFG_MR3_PRELIM; +#endif + +#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM)) + csctrl_reg->ar4 = CFG_AR4_PRELIM; + csctrl_reg->cr4 = CFG_CR4_PRELIM; + csctrl_reg->mr4 = CFG_MR4_PRELIM; +#endif + +#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM)) + csctrl_reg->ar5 = CFG_AR5_PRELIM; + csctrl_reg->cr5 = CFG_CR5_PRELIM; + csctrl_reg->mr5 = CFG_MR5_PRELIM; +#endif + +#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM)) + csctrl_reg->ar6 = CFG_AR6_PRELIM; + csctrl_reg->cr6 = CFG_CR6_PRELIM; + csctrl_reg->mr6 = CFG_MR6_PRELIM; +#endif + +#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM)) + csctrl_reg->ar7 = CFG_AR7_PRELIM; + csctrl_reg->cr7 = CFG_CR7_PRELIM; + csctrl_reg->mr7 = CFG_MR7_PRELIM; +#endif + +#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ + +#ifdef CONFIG_FSL_I2C + gpio_reg->par_feci2c = 0x000F; +#endif + + /* enable instruction cache now */ + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart |= UART0_ENABLE_MASK; + break; + case 1: + gpio->par_uart |= UART1_ENABLE_MASK; + break; + case 2: + gpio->par_uart |= UART2_ENABLE_MASK; + break; + } +} +#endif /* #if defined(CONFIG_M5275) */ + #if defined(CONFIG_M5282) /* * Breath some life into the CPU... diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c index 9167cec698..b8fb7bb0ee 100644 --- a/cpu/mcf52x2/interrupts.c +++ b/cpu/mcf52x2/interrupts.c @@ -59,7 +59,7 @@ void dtimer_intr_setup(void) #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5272 */ -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275) int interrupt_init(void) { volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); @@ -81,7 +81,7 @@ void dtimer_intr_setup(void) intp->imrl0 &= ~CFG_TMRINTR_MASK; } #endif /* CONFIG_MCFTMR */ -#endif /* CONFIG_M5282 | CONFIG_M5271 */ +#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */ #if defined(CONFIG_M5249) || defined(CONFIG_M5253) int interrupt_init(void) diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c index bc1e20023b..5fafcd8c5f 100644 --- a/cpu/mcf52x2/speed.c +++ b/cpu/mcf52x2/speed.c @@ -64,8 +64,20 @@ int get_clocks (void) #endif /* CONFIG_M5249 || CONFIG_M5253 */ +#if defined(CONFIG_M5275) + volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + + /* Setup PLL */ + pll->syncr = 0x01080000; + while (!(pll->synsr & FMPLL_SYNSR_LOCK) + ; + pll->syncr = 0x01000000; + while (!(pll->synsr & FMPLL_SYNSR_LOCK)) + ; +#endif + gd->cpu_clk = CFG_CLK; -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275) gd->bus_clk = gd->cpu_clk / 2; #else gd->bus_clk = gd->cpu_clk; diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 260a09abf7..2bc0df39ca 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -56,9 +56,7 @@ _vectors: .long 0x00000000 /* Flash offset is 0 until we setup CS0 */ -#if defined(CONFIG_R5200) -.long 0x400 -#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) +#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) .long _start - TEXT_BASE #else .long _START @@ -160,7 +158,7 @@ _copy_flash: _flashbar_setup: /* Initialize FLASHBAR: locate internal Flash and validate it */ move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 - movec %d0, %RAMBAR0 + movec %d0, %FLASHBAR jmp _after_flashbar_copy.L /* Force jump to absolute address */ _flashbar_setup_end: nop @@ -168,7 +166,7 @@ _after_flashbar_copy: #else /* Setup code to initialize FLASHBAR, if start from external Memory */ move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 - movec %d0, %RAMBAR0 + movec %d0, %RAMBAR1 #endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ #endif @@ -185,16 +183,15 @@ _after_flashbar_copy: movec %d0, %VBR #endif -#ifdef CONFIG_R5200 - move.l #(_flash_setup-CFG_FLASH_BASE), %a0 - move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1 - move.l #(CFG_INIT_RAM_ADDR), %a2 -_copy_flash: - move.l (%a0)+, (%a2)+ - cmp.l %a0, %a1 - bgt.s _copy_flash - jmp CFG_INIT_RAM_ADDR -_after_flash_copy: +#ifdef CONFIG_M5275 + /* Initialize IPSBAR */ + move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ + move.l %d0, 0x40000000 +/* movec %d0, %MBAR */ + + /* Initialize RAMBAR: locate SRAM and validate it */ + move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 + movec %d0, %RAMBAR1 #endif #if 0 @@ -219,24 +216,6 @@ _after_flash_copy: /*------------------------------------------------------------------------------*/ -#ifdef CONFIG_R5200 -_flash_setup: - /* CSAR0 */ - move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0 - move.w %d0, 0x40000080 - - /* CSCR0 */ - move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */ - move.w %d0, 0x4000008A - - /* CSMR0 */ - move.l #0x001f0001, %d0 /* 2 MB, valid */ - move.l %d0, 0x40000084 - - jmp _after_flash_copy.L -_flash_setup_end: -#endif - /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -394,6 +373,25 @@ icache_enable: rts #endif +#if defined(CONFIG_M5275) +/* + * Instruction cache only + */ + .globl icache_enable +icache_enable: + move.l #0x01400000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0x0000c000, %d0 /* Setup SDRAM caching */ + movec %d0, %ACR0 /* Enable cache */ + move.l #0x00000000, %d0 /* No other caching */ + movec %d0, %ACR1 /* Enable cache */ + move.l #0x80400100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + moveq #1, %d0 + move.l %d0, icache_state + rts +#endif + #ifdef CONFIG_M5282 .globl icache_enable icache_enable: @@ -478,3 +476,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S index 61be2eac69..a524f70783 100644 --- a/cpu/mcf532x/start.S +++ b/cpu/mcf532x/start.S @@ -333,3 +333,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf5445x/Makefile b/cpu/mcf5445x/Makefile index 26ec29895e..a549fdd2a3 100644 --- a/cpu/mcf5445x/Makefile +++ b/cpu/mcf5445x/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = lib$(CPU).a START = start.o -COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c new file mode 100644 index 0000000000..44d8505bcd --- /dev/null +++ b/cpu/mcf5445x/dspi.c @@ -0,0 +1,73 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spi.h> + +#if defined(CONFIG_CF_DSPI) +#include <asm/immap.h> +void dspi_init(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + + gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 | + GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 | + GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK; + + dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 | + DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 | + DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 | + DSPI_DMCR_CRXF | DSPI_DMCR_CTXF; + + dspi->dctar0 = DSPI_DCTAR_TRSZ(7) | DSPI_DCTAR_CPOL | DSPI_DCTAR_CPHA | + DSPI_DCTAR_PCSSCK_1CLK | DSPI_DCTAR_PASC(0) | + DSPI_DCTAR_PDT(0) | DSPI_DCTAR_CSSCK(0) | + DSPI_DCTAR_ASC(0) | DSPI_DCTAR_PBR(0) | + DSPI_DCTAR_DT(1) | DSPI_DCTAR_BR(1); +} + +void dspi_tx(int chipsel, u8 attrib, u16 data) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + + while ((dspi->dsr & 0x0000F000) >= 4) ; + + dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data; +} + +u16 dspi_rx(void) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + + while ((dspi->dsr & 0x000000F0) == 0) ; + + return (dspi->drfr & 0xFFFF); +} + +#endif /* CONFIG_HARD_SPI */ diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index d64c5af0db..0c5194acdb 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -379,3 +379,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S index 442665f250..c12d7a0fcb 100644 --- a/cpu/mcf547x_8x/start.S +++ b/cpu/mcf547x_8x/start.S @@ -359,3 +359,4 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" + .align 4 diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 443240e540..f593968320 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -1,5 +1,5 @@ /* - * Cache-handling routined for MIPS 4K CPUs + * Cache-handling routined for MIPS CPUs * * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> * @@ -24,15 +24,32 @@ #include <config.h> #include <version.h> +#include <asm/asm.h> #include <asm/regdef.h> #include <asm/mipsregs.h> #include <asm/addrspace.h> #include <asm/cacheops.h> - /* 16KB is the maximum size of instruction and data caches on - * MIPS 4K. - */ -#define MIPS_MAX_CACHE_SIZE 0x4000 +#define RA t8 + +/* + * 16kB is the maximum size of instruction and data caches on MIPS 4K, + * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. + * + * Note that the above size is the maximum size of primary cache. U-Boot + * doesn't have L2 cache support for now. + */ +#define MIPS_MAX_CACHE_SIZE 0x10000 + +#define INDEX_BASE KSEG0 + + .macro cache_op op addr + .set push + .set noreorder + .set mips3 + cache \op, 0(\addr) + .set pop + .endm /* * cacheop macro to automate cache operations @@ -103,6 +120,77 @@ #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) + .macro f_fill64 dst, offset, val + LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) +#if LONGSIZE == 4 + LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) +#endif + .endm + +/* + * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) + */ +LEAF(mips_init_icache) + blez a1, 9f + mtc0 zero, CP0_TAGLO + /* clear tag to invalidate */ + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, a1 +1: cache_op Index_Store_Tag_I t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b + /* fill once, so data field parity is correct */ + PTR_LI t0, INDEX_BASE +2: cache_op Fill t0 + PTR_ADDU t0, a2 + bne t0, t1, 2b + /* invalidate again - prudent but not strictly neccessary */ + PTR_LI t0, INDEX_BASE +1: cache_op Index_Store_Tag_I t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b +9: jr ra + END(mips_init_icache) + +/* + * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) + */ +LEAF(mips_init_dcache) + blez a1, 9f + mtc0 zero, CP0_TAGLO + /* clear all tags */ + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, a1 +1: cache_op Index_Store_Tag_D t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b + /* load from each line (in cached space) */ + PTR_LI t0, INDEX_BASE +2: LONG_L zero, 0(t0) + PTR_ADDU t0, a2 + bne t0, t1, 2b + /* clear all tags */ + PTR_LI t0, INDEX_BASE +1: cache_op Index_Store_Tag_D t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b +9: jr ra + END(mips_init_dcache) + /******************************************************************************* * * mips_cache_reset - low level initialisation of the primary caches @@ -119,10 +207,8 @@ * RETURNS: N/A * */ - .globl mips_cache_reset - .ent mips_cache_reset -mips_cache_reset: - +NESTED(mips_cache_reset, 0, ra) + move RA, ra li t2, CFG_ICACHE_SIZE li t3, CFG_DCACHE_SIZE li t4, CFG_CACHELINE_SIZE @@ -130,27 +216,14 @@ mips_cache_reset: li v0, MIPS_MAX_CACHE_SIZE - /* Now clear that much memory starting from zero. - */ - - li a0, KSEG1 - addu a1, a0, v0 -2: - sw zero, 0(a0) - sw zero, 4(a0) - sw zero, 8(a0) - sw zero, 12(a0) - sw zero, 16(a0) - sw zero, 20(a0) - sw zero, 24(a0) - sw zero, 28(a0) - addu a0, 32 - bltu a0, a1, 2b - - /* Set invalid tag. + /* + * Now clear that much memory starting from zero. */ - - mtc0 zero, CP0_TAGLO + PTR_LI a0, KSEG1 + PTR_ADDU a1, a0, v0 +2: PTR_ADDIU a0, 64 + f_fill64 a0, -64, zero + bne a0, a1, 2b /* * The caches are probably in an indeterminate state, @@ -158,48 +231,26 @@ mips_cache_reset: * invalidate, load/fill, invalidate for each line. */ - /* Assume bottom of RAM will generate good parity for the cache. - */ - - li a0, K0BASE - move a2, t2 # icacheSize - move a3, t4 # icacheLineSize - move a1, a2 - icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill)) - - /* To support Orion/R4600, we initialise the data cache in 3 passes. - */ - - /* 1: initialise dcache tags. + /* + * Assume bottom of RAM will generate good parity for the cache. */ - li a0, K0BASE - move a2, t3 # dcacheSize - move a3, t5 # dcacheLineSize - move a1, a2 - icacheop(a0,a1,a2,a3,Index_Store_Tag_D) - - /* 2: fill dcache. + /* + * Initialize the I-cache first, */ + move a1, t2 + move a2, t4 + bal mips_init_icache - li a0, K0BASE - move a2, t3 # dcacheSize - move a3, t5 # dcacheLineSize - move a1, a2 - icacheopn(a0,a1,a2,a3,1lw,(dummy)) - - /* 3: clear dcache tags. + /* + * then initialize D-cache. */ + move a1, t3 + move a2, t5 + bal mips_init_dcache - li a0, K0BASE - move a2, t3 # dcacheSize - move a3, t5 # dcacheLineSize - move a1, a2 - icacheop(a0,a1,a2,a3,Index_Store_Tag_D) - - j ra - - .end mips_cache_reset + jr RA + END(mips_cache_reset) /******************************************************************************* * @@ -208,15 +259,15 @@ mips_cache_reset: * RETURNS: 0 - cache disabled; 1 - cache enabled * */ - .globl dcache_status - .ent dcache_status -dcache_status: - - mfc0 v0, CP0_CONFIG - andi v0, v0, 1 - j ra - - .end dcache_status +LEAF(dcache_status) + mfc0 t0, CP0_CONFIG + li t1, CONF_CM_UNCACHED + andi t0, t0, CONF_CM_CMASK + move v0, zero + beq t0, t1, 2f + li v0, 1 +2: jr ra + END(dcache_status) /******************************************************************************* * @@ -225,19 +276,16 @@ dcache_status: * RETURNS: N/A * */ - .globl dcache_disable - .ent dcache_disable -dcache_disable: - +LEAF(dcache_disable) mfc0 t0, CP0_CONFIG li t1, -8 and t0, t0, t1 ori t0, t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG - j ra - - .end dcache_disable + jr ra + END(dcache_disable) +#ifdef CFG_INIT_RAM_LOCK_MIPS /******************************************************************************* * * mips_cache_lock - lock RAM area pointed to by a0 in cache. @@ -260,6 +308,7 @@ mips_cache_lock: move a1, a2 icacheop(a0,a1,a2,a3,0x1d) - j ra + jr ra .end mips_cache_lock +#endif /* CFG_INIT_RAM_LOCK_MIPS */ diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index 7559ac657f..e267bba469 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -23,24 +23,45 @@ #include <common.h> #include <command.h> -#include <asm/inca-ip.h> #include <asm/mipsregs.h> +#include <asm/cacheops.h> +#include <asm/reboot.h> + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void __attribute__((weak)) _machine_restart(void) +{ +} int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#if defined(CONFIG_INCA_IP) - *INCA_IP_WDT_RST_REQ = 0x3f; -#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229) - void (*f)(void) = (void *) 0xbfc00000; + _machine_restart(); - f(); -#endif fprintf(stderr, "*** reset failed ***\n"); return 0; } void flush_cache(ulong start_addr, ulong size) { + unsigned long lsize = CFG_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } } void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S index 71adaa19de..2ebcc91139 100644 --- a/cpu/mips/incaip_wdt.S +++ b/cpu/mips/incaip_wdt.S @@ -68,5 +68,5 @@ disable_incaip_wdt: li t1, WD_WRITE_ENDINIT sw t1, WD_CON0(t0) /* end command */ - j ra + jr ra nop diff --git a/cpu/mips/start.S b/cpu/mips/start.S index c92b162782..6e1a78ceac 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -27,6 +27,30 @@ #include <asm/regdef.h> #include <asm/mipsregs.h> + /* + * For the moment disable interrupts, mark the kernel mode and + * set ST0_KX so that the CPU does not spit fire when using + * 64-bit addresses. + */ + .macro setup_c0_status set clr + .set push + mfc0 t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0 t0, CP0_STATUS + .set noreorder + sll zero, 3 # ehb + .set pop + .endm + + .macro setup_c0_status_reset +#ifdef CONFIG_64BIT + setup_c0_status ST0_KX 0 +#else + setup_c0_status 0 0 +#endif + .endm + #define RVECENT(f,n) \ b f; nop #define XVECENT(f,bev) \ @@ -211,19 +235,11 @@ reset: mtc0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHHI - /* STATUS register */ -#ifdef CONFIG_TB0229 - li k0, ST0_CU0 -#else - mfc0 k0, CP0_STATUS -#endif - li k1, ~ST0_IE - and k0, k1 - mtc0 k0, CP0_STATUS - - /* CAUSE register */ + /* WP(Watch Pending), SW0/1 should be cleared. */ mtc0 zero, CP0_CAUSE + setup_c0_status_reset + /* Init Timer */ mtc0 zero, CP0_COUNT mtc0 zero, CP0_COMPARE @@ -240,14 +256,6 @@ reset: 1: lw gp, 0(ra) -#ifdef CONFIG_INCA_IP - /* Disable INCA-IP Watchdog. - */ - la t9, disable_incaip_wdt - jalr t9 - nop -#endif - /* Initialize any external memory. */ la t9, lowlevel_init @@ -267,16 +275,18 @@ reset: /* Set up temporary stack. */ +#ifdef CFG_INIT_RAM_LOCK_MIPS li a0, CFG_INIT_SP_OFFSET la t9, mips_cache_lock jalr t9 nop +#endif li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET la sp, 0(t0) la t9, board_init_f - j t9 + jr t9 nop /* @@ -332,7 +342,7 @@ relocate_code: /* Jump to where we've relocated ourselves. */ addi t0, a2, in_ram - _start - j t0 + jr t0 nop .gpword _GLOBAL_OFFSET_TABLE_ /* _GLOBAL_OFFSET_TABLE_ - _gp */ @@ -377,7 +387,7 @@ in_ram: move a0, a1 la t9, board_init_r - j t9 + jr t9 move a1, a2 /* delay slot */ .end relocate_code diff --git a/cpu/mpc5xx/u-boot.lds b/cpu/mpc5xx/u-boot.lds index ca1de954cd..386a6e01f4 100644 --- a/cpu/mpc5xx/u-boot.lds +++ b/cpu/mpc5xx/u-boot.lds @@ -22,7 +22,6 @@ */ OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index e4d6168224..ace16535ff 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -114,12 +114,14 @@ unsigned long get_tbclk (void) /* ------------------------------------------------------------------------- */ -#ifdef CONFIG_OF_LIBFDT +#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) void ft_cpu_setup(void *blob, bd_t *bd) { int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4; char * cpu_path = "/cpus/" OF_CPU; +#ifdef CONFIG_MPC5xxx_FEC char * eth_path = "/" OF_SOC "/ethernet@3000"; +#endif do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); @@ -127,7 +129,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1); do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency", bd->bi_busfreq*div, 1); +#ifdef CONFIG_MPC5xxx_FEC do_fixup_by_path(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0); do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0); +#endif } #endif diff --git a/cpu/mpc5xxx/u-boot-customlayout.lds b/cpu/mpc5xxx/u-boot-customlayout.lds index 4e10ddbcc2..bbb6cf8e04 100644 --- a/cpu/mpc5xxx/u-boot-customlayout.lds +++ b/cpu/mpc5xxx/u-boot-customlayout.lds @@ -22,7 +22,6 @@ */ OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS diff --git a/cpu/mpc5xxx/u-boot.lds b/cpu/mpc5xxx/u-boot.lds index bb2747b6d7..db6c6f29a0 100644 --- a/cpu/mpc5xxx/u-boot.lds +++ b/cpu/mpc5xxx/u-boot.lds @@ -22,7 +22,6 @@ */ OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS diff --git a/cpu/mpc8220/u-boot.lds b/cpu/mpc8220/u-boot.lds index 98b0a79244..ff4f3dce20 100644 --- a/cpu/mpc8220/u-boot.lds +++ b/cpu/mpc8220/u-boot.lds @@ -22,7 +22,6 @@ */ OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS diff --git a/cpu/mpc824x/u-boot.lds b/cpu/mpc824x/u-boot.lds index 036e61b908..1f2e7d7276 100644 --- a/cpu/mpc824x/u-boot.lds +++ b/cpu/mpc824x/u-boot.lds @@ -22,7 +22,6 @@ */ OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index 55e61a1887..414759e74c 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -300,7 +300,7 @@ void watchdog_reset (void) #endif /* CONFIG_WATCHDOG */ /* ------------------------------------------------------------------------- */ -#if defined(CONFIG_OF_LIBFDT) +#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) void ft_cpu_setup (void *blob, bd_t *bd) { char * cpu_path = "/cpus/" OF_CPU; diff --git a/cpu/mpc8260/u-boot.lds b/cpu/mpc8260/u-boot.lds index 8384549283..6f500c42f2 100644 --- a/cpu/mpc8260/u-boot.lds +++ b/cpu/mpc8260/u-boot.lds @@ -22,7 +22,6 @@ */ OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index 94a3cb8334..fcb6a52465 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -28,9 +28,20 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - spd_sdram.o ecc.o qe_io.o pci.o fdt.o +COBJS-y += traps.o +COBJS-y += cpu.o +COBJS-y += cpu_init.o +COBJS-y += speed.o +COBJS-y += interrupts.o +COBJS-y += spd_sdram.o +COBJS-y += ecc.o +COBJS-$(CONFIG_QE) += qe_io.o +COBJS-$(CONFIG_FSL_SERDES) += serdes.o +COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o + +COBJS := $(COBJS-y) SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index bff3cefda9..36de78d270 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -42,6 +42,30 @@ int checkcpu(void) u32 pvr = get_pvr(); u32 spridr; char buf[32]; + int i; + +#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} + const struct cpu_type { + char name[15]; + u32 partid; + } cpu_type_list [] = { + CPU_TYPE_ENTRY(8311), + CPU_TYPE_ENTRY(8313), + CPU_TYPE_ENTRY(8314), + CPU_TYPE_ENTRY(8315), + CPU_TYPE_ENTRY(8321), + CPU_TYPE_ENTRY(8323), + CPU_TYPE_ENTRY(8343), + CPU_TYPE_ENTRY(8347_TBGA_), + CPU_TYPE_ENTRY(8347_PBGA_), + CPU_TYPE_ENTRY(8349), + CPU_TYPE_ENTRY(8358_TBGA_), + CPU_TYPE_ENTRY(8358_PBGA_), + CPU_TYPE_ENTRY(8360), + CPU_TYPE_ENTRY(8377), + CPU_TYPE_ENTRY(8378), + CPU_TYPE_ENTRY(8379), + }; immr = (immap_t *)CFG_IMMR; @@ -69,130 +93,26 @@ int checkcpu(void) } spridr = immr->sysconf.spridr; - switch(spridr) { - case SPR_8349E_REV10: - case SPR_8349E_REV11: - case SPR_8349E_REV31: - puts("MPC8349E, "); - break; - case SPR_8349_REV10: - case SPR_8349_REV11: - case SPR_8349_REV31: - puts("MPC8349, "); - break; - case SPR_8347E_REV10_TBGA: - case SPR_8347E_REV11_TBGA: - case SPR_8347E_REV31_TBGA: - case SPR_8347E_REV10_PBGA: - case SPR_8347E_REV11_PBGA: - case SPR_8347E_REV31_PBGA: - puts("MPC8347E, "); - break; - case SPR_8347_REV10_TBGA: - case SPR_8347_REV11_TBGA: - case SPR_8347_REV31_TBGA: - case SPR_8347_REV10_PBGA: - case SPR_8347_REV11_PBGA: - case SPR_8347_REV31_PBGA: - puts("MPC8347, "); - break; - case SPR_8343E_REV10: - case SPR_8343E_REV11: - case SPR_8343E_REV31: - puts("MPC8343E, "); - break; - case SPR_8343_REV10: - case SPR_8343_REV11: - case SPR_8343_REV31: - puts("MPC8343, "); - break; - case SPR_8360E_REV10: - case SPR_8360E_REV11: - case SPR_8360E_REV12: - case SPR_8360E_REV20: - case SPR_8360E_REV21: - puts("MPC8360E, "); - break; - case SPR_8360_REV10: - case SPR_8360_REV11: - case SPR_8360_REV12: - case SPR_8360_REV20: - case SPR_8360_REV21: - puts("MPC8360, "); - break; - case SPR_8323E_REV10: - case SPR_8323E_REV11: - puts("MPC8323E, "); - break; - case SPR_8323_REV10: - case SPR_8323_REV11: - puts("MPC8323, "); - break; - case SPR_8321E_REV10: - case SPR_8321E_REV11: - puts("MPC8321E, "); - break; - case SPR_8321_REV10: - case SPR_8321_REV11: - puts("MPC8321, "); - break; - case SPR_8311_REV10: - puts("MPC8311, "); - break; - case SPR_8311E_REV10: - puts("MPC8311E, "); - break; - case SPR_8313_REV10: - puts("MPC8313, "); - break; - case SPR_8313E_REV10: - puts("MPC8313E, "); - break; - case SPR_8315E_REV10: - puts("MPC8315E, "); - break; - case SPR_8315_REV10: - puts("MPC8315, "); - break; - case SPR_8314E_REV10: - puts("MPC8314E, "); - break; - case SPR_8314_REV10: - puts("MPC8314, "); - break; - case SPR_8379E_REV10: - puts("MPC8379E, "); - break; - case SPR_8379_REV10: - puts("MPC8379, "); - break; - case SPR_8378E_REV10: - puts("MPC8378E, "); - break; - case SPR_8378_REV10: - puts("MPC8378, "); - break; - case SPR_8377E_REV10: - puts("MPC8377E, "); - break; - case SPR_8377_REV10: - puts("MPC8377, "); - break; - default: - printf("Rev: Unknown revision number:%08x\n" - "Warning: Unsupported cpu revision!\n",spridr); - return 0; - } -#if defined(CONFIG_MPC834X) - /* Multiple revisons of 834x processors may have the same SPRIDR value. - * So use PVR to identify the revision number. - */ - printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock)); -#else - printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock)); -#endif - printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000); + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) + if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) { + puts("MPC"); + puts(cpu_type_list[i].name); + if (IS_E_PROCESSOR(spridr)) + puts("E"); + if (REVID_MAJOR(spridr) >= 2) + puts("A"); + printf(", Rev: %d.%d", REVID_MAJOR(spridr), + REVID_MINOR(spridr)); + break; + } + + if (i == ARRAY_SIZE(cpu_type_list)) + printf("(SPRIDR %08x unknown), ", spridr); + + printf(" at %s MHz, ", strmhz(buf, clock)); + + printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk)); return 0; } diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index e643037d27..fba5b02ece 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -79,6 +79,12 @@ void cpu_init_f (volatile immap_t * im) (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT); #endif +#ifdef CFG_SPCR_OPT + /* Optimize transactions between CSB and other devices */ + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | + (CFG_SPCR_OPT << SPCR_OPT_SHIFT); +#endif + #ifdef CFG_SPCR_TSECEP /* all eTSEC's Emergency priority */ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index 6f55932da2..b39f678f1a 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -24,9 +24,6 @@ */ #include <common.h> - -#if defined(CONFIG_OF_LIBFDT) - #include <libfdt.h> #include <fdt_support.h> @@ -49,6 +46,14 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", gd->core_clk, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,soc", + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,soc", + "clock-frequency", bd->bi_busfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,immr", + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,immr", + "clock-frequency", bd->bi_busfreq, 1); #ifdef CONFIG_QE ft_qe_setup(blob); #endif @@ -68,4 +73,3 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } -#endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index 18558db537..adabf7aac7 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -33,7 +33,6 @@ #include <asm/mpc8349_pci.h> -#ifdef CONFIG_83XX_GENERIC_PCI #define MAX_BUSES 2 DECLARE_GLOBAL_DATA_PTR; @@ -209,4 +208,3 @@ void ft_pci_setup(void *blob, bd_t *bd) } } #endif /* CONFIG_OF_LIBFDT */ -#endif /* CONFIG_83XX_GENERIC_PCI */ diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c index 8b3937aa9b..ce91a07d72 100644 --- a/cpu/mpc83xx/qe_io.c +++ b/cpu/mpc83xx/qe_io.c @@ -25,7 +25,6 @@ #include "asm/io.h" #include "asm/immap_83xx.h" -#if defined(CONFIG_QE) #define NUM_OF_PINS 32 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) { @@ -81,5 +80,3 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val); } } - -#endif /* CONFIG_QE */ diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c new file mode 100644 index 0000000000..020c4c8f91 --- /dev/null +++ b/cpu/mpc83xx/serdes.c @@ -0,0 +1,145 @@ +/* + * Freescale SerDes initialization routine + * + * Copyright (C) 2007 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2008 MontaVista Software, Inc. All rights reserved. + * + * Author: Li Yang <leoli@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> + +/* SerDes registers */ +#define FSL_SRDSCR0_OFFS 0x0 +#define FSL_SRDSCR0_DPP_1V2 0x00008800 +#define FSL_SRDSCR1_OFFS 0x4 +#define FSL_SRDSCR1_PLLBW 0x00000040 +#define FSL_SRDSCR2_OFFS 0x8 +#define FSL_SRDSCR2_VDD_1V2 0x00800000 +#define FSL_SRDSCR2_SEIC_MASK 0x00001c1c +#define FSL_SRDSCR2_SEIC_SATA 0x00001414 +#define FSL_SRDSCR2_SEIC_PEX 0x00001010 +#define FSL_SRDSCR2_SEIC_SGMII 0x00000101 +#define FSL_SRDSCR3_OFFS 0xc +#define FSL_SRDSCR3_KFR_SATA 0x10100000 +#define FSL_SRDSCR3_KPH_SATA 0x04040000 +#define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000 +#define FSL_SRDSCR3_SDTXL_SATA 0x00000505 +#define FSL_SRDSCR4_OFFS 0x10 +#define FSL_SRDSCR4_PROT_SATA 0x00000808 +#define FSL_SRDSCR4_PROT_PEX 0x00000101 +#define FSL_SRDSCR4_PROT_SGMII 0x00000505 +#define FSL_SRDSCR4_PLANE_X2 0x01000000 +#define FSL_SRDSRSTCTL_OFFS 0x20 +#define FSL_SRDSRSTCTL_RST 0x80000000 +#define FSL_SRDSRSTCTL_SATA_RESET 0xf + +void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd) +{ + void *regs = (void *)CFG_IMMR + offset; + u32 tmp; + + /* 1.0V corevdd */ + if (vdd) { + /* DPPE/DPPA = 0 */ + tmp = in_be32(regs + FSL_SRDSCR0_OFFS); + tmp &= ~FSL_SRDSCR0_DPP_1V2; + out_be32(regs + FSL_SRDSCR0_OFFS, tmp); + + /* VDD = 0 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_VDD_1V2; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + } + + /* protocol specific configuration */ + switch (proto) { + case FSL_SERDES_PROTO_SATA: + /* Set and clear reset bits */ + tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); + tmp |= FSL_SRDSRSTCTL_SATA_RESET; + out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); + udelay(1000); + tmp &= ~FSL_SRDSRSTCTL_SATA_RESET; + out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); + + /* Configure SRDSCR1 */ + tmp = in_be32(regs + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_PLLBW; + out_be32(regs + FSL_SRDSCR1_OFFS, tmp); + + /* Configure SRDSCR2 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_SEIC_MASK; + tmp |= FSL_SRDSCR2_SEIC_SATA; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + + /* Configure SRDSCR3 */ + tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA | + FSL_SRDSCR3_SDFM_SATA_PEX | + FSL_SRDSCR3_SDTXL_SATA; + out_be32(regs + FSL_SRDSCR3_OFFS, tmp); + + /* Configure SRDSCR4 */ + tmp = rfcks | FSL_SRDSCR4_PROT_SATA; + out_be32(regs + FSL_SRDSCR4_OFFS, tmp); + break; + case FSL_SERDES_PROTO_PEX: + case FSL_SERDES_PROTO_PEX_X2: + /* Configure SRDSCR1 */ + tmp = in_be32(regs + FSL_SRDSCR1_OFFS); + tmp |= FSL_SRDSCR1_PLLBW; + out_be32(regs + FSL_SRDSCR1_OFFS, tmp); + + /* Configure SRDSCR2 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_SEIC_MASK; + tmp |= FSL_SRDSCR2_SEIC_PEX; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + + /* Configure SRDSCR3 */ + tmp = FSL_SRDSCR3_SDFM_SATA_PEX; + out_be32(regs + FSL_SRDSCR3_OFFS, tmp); + + /* Configure SRDSCR4 */ + tmp = rfcks | FSL_SRDSCR4_PROT_PEX; + if (proto == FSL_SERDES_PROTO_PEX_X2) + tmp |= FSL_SRDSCR4_PLANE_X2; + out_be32(regs + FSL_SRDSCR4_OFFS, tmp); + break; + case FSL_SERDES_PROTO_SGMII: + /* Configure SRDSCR1 */ + tmp = in_be32(regs + FSL_SRDSCR1_OFFS); + tmp &= ~FSL_SRDSCR1_PLLBW; + out_be32(regs + FSL_SRDSCR1_OFFS, tmp); + + /* Configure SRDSCR2 */ + tmp = in_be32(regs + FSL_SRDSCR2_OFFS); + tmp &= ~FSL_SRDSCR2_SEIC_MASK; + tmp |= FSL_SRDSCR2_SEIC_SGMII; + out_be32(regs + FSL_SRDSCR2_OFFS, tmp); + + /* Configure SRDSCR3 */ + out_be32(regs + FSL_SRDSCR3_OFFS, 0); + + /* Configure SRDSCR4 */ + tmp = rfcks | FSL_SRDSCR4_PROT_SGMII; + out_be32(regs + FSL_SRDSCR4_OFFS, tmp); + break; + default: + return; + } + + /* Do a software reset */ + tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); + tmp |= FSL_SRDSRSTCTL_RST; + out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); +} diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 0acca47717..70cd410298 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -34,10 +34,13 @@ #include <asm/mmu.h> #include <spd_sdram.h> +DECLARE_GLOBAL_DATA_PTR; + void board_add_ram_info(int use_default) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ddr83xx_t *ddr = &immap->ddr; + char buf[32]; printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); @@ -48,9 +51,11 @@ void board_add_ram_info(int use_default) puts(", 64-bit"); if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) - puts(", ECC on)"); + puts(", ECC on"); else - puts(", ECC off)"); + puts(", ECC off"); + + printf(", %s MHz)", strmhz(buf, gd->mem_clk)); #if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE) puts("\nSDRAM: "); @@ -60,8 +65,6 @@ void board_add_ram_info(int use_default) #ifdef CONFIG_SPD_EEPROM -DECLARE_GLOBAL_DATA_PTR; - #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) extern void dma_init(void); extern uint dma_check(void); @@ -78,12 +81,12 @@ extern int dma_xfer(void *dest, uint count, void *src); int picos_to_clk(int picos) { - unsigned int ddr_bus_clk; + unsigned int mem_bus_clk; int clks; - ddr_bus_clk = gd->ddr_clk >> 1; - clks = picos / (1000000000 / (ddr_bus_clk / 1000)); - if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0) + mem_bus_clk = gd->mem_clk >> 1; + clks = picos / (1000000000 / (mem_bus_clk / 1000)); + if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0) clks++; return clks; @@ -313,7 +316,7 @@ long int spd_sdram() debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate); - ddrc_clk = gd->ddr_clk / 1000000; + ddrc_clk = gd->mem_clk / 1000000; effective_data_rate = 0; if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */ @@ -598,7 +601,7 @@ long int spd_sdram() debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); /* Check DIMM data bus width */ - if (spd.dataw_lsb == 0x20) { + if (spd.dataw_lsb < 64) { if (spd.mem_type == SPD_MEMTYPE_DDR) burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ else @@ -760,7 +763,7 @@ long int spd_sdram() sdram_cfg |= SDRAM_CFG_RD_EN; /* The DIMM is 32bit width */ - if (spd.dataw_lsb == 0x20) { + if (spd.dataw_lsb < 64) { if (spd.mem_type == SPD_MEMTYPE_DDR) sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE; if (spd.mem_type == SPD_MEMTYPE_DDR2) diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index f598699b2c..16145dd355 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -122,9 +122,9 @@ int get_clocks(void) u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; - u32 ddr_clk; + u32 mem_clk; #if defined(CONFIG_MPC8360) - u32 ddr_sec_clk; + u32 mem_sec_clk; #endif #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) u32 qepmf; @@ -400,11 +400,11 @@ int get_clocks(void) return -12; } - ddr_clk = csb_clk * + mem_clk = csb_clk * (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT)); corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT; #if defined(CONFIG_MPC8360) - ddr_sec_clk = csb_clk * (1 + + mem_sec_clk = csb_clk * (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); #endif @@ -466,9 +466,9 @@ int get_clocks(void) gd->enc_clk = enc_clk; gd->lbiu_clk = lbiu_clk; gd->lclk_clk = lclk_clk; - gd->ddr_clk = ddr_clk; + gd->mem_clk = mem_clk; #if defined(CONFIG_MPC8360) - gd->ddr_sec_clk = ddr_sec_clk; + gd->mem_sec_clk = mem_sec_clk; #endif #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) gd->qe_clk = qe_clk; @@ -508,9 +508,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) #endif printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000); printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000); - printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000); + printf(" DDR: %4d MHz\n", gd->mem_clk / 1000000); #if defined(CONFIG_MPC8360) - printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000); + printf(" DDR Secondary: %4d MHz\n", gd->mem_sec_clk / 1000000); #endif printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000); printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000); diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 2205dca024..adbc585827 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -29,6 +29,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o resetvec.o +SOBJS-$(CONFIG_MP) += release.o +SOBJS = $(SOBJS-y) +COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \ diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index ac8b018b0a..74b210cd10 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2007 Freescale Semiconductor, Inc. + * Copyright 2004,2007,2008 Freescale Semiconductor, Inc. * (C) Copyright 2002, 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -30,6 +30,41 @@ #include <command.h> #include <asm/cache.h> +DECLARE_GLOBAL_DATA_PTR; + +struct cpu_type { + char name[15]; + u32 soc_ver; +}; + +#define CPU_TYPE_ENTRY(x) {#x, SVR_##x} + +struct cpu_type cpu_type_list [] = { + CPU_TYPE_ENTRY(8533), + CPU_TYPE_ENTRY(8533_E), + CPU_TYPE_ENTRY(8540), + CPU_TYPE_ENTRY(8541), + CPU_TYPE_ENTRY(8541_E), + CPU_TYPE_ENTRY(8543), + CPU_TYPE_ENTRY(8543_E), + CPU_TYPE_ENTRY(8544), + CPU_TYPE_ENTRY(8544_E), + CPU_TYPE_ENTRY(8545), + CPU_TYPE_ENTRY(8545_E), + CPU_TYPE_ENTRY(8547_E), + CPU_TYPE_ENTRY(8548), + CPU_TYPE_ENTRY(8548_E), + CPU_TYPE_ENTRY(8555), + CPU_TYPE_ENTRY(8555_E), + CPU_TYPE_ENTRY(8560), + CPU_TYPE_ENTRY(8567), + CPU_TYPE_ENTRY(8567_E), + CPU_TYPE_ENTRY(8568), + CPU_TYPE_ENTRY(8568_E), + CPU_TYPE_ENTRY(8572), + CPU_TYPE_ENTRY(8572_E), +}; + int checkcpu (void) { sys_info_t sysinfo; @@ -39,47 +74,26 @@ int checkcpu (void) uint fam; uint ver; uint major, minor; + int i; u32 ddr_ratio; volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); svr = get_svr(); - ver = SVR_VER(svr); + ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); puts("CPU: "); - switch (ver) { - case SVR_8540: - puts("8540"); - break; - case SVR_8541: - puts("8541"); - break; - case SVR_8555: - puts("8555"); - break; - case SVR_8560: - puts("8560"); - break; - case SVR_8548: - puts("8548"); - break; - case SVR_8548_E: - puts("8548_E"); - break; - case SVR_8544: - puts("8544"); - break; - case SVR_8544_E: - puts("8544_E"); - break; - case SVR_8568_E: - puts("8568_E"); - break; - default: + + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) + if (cpu_type_list[i].soc_ver == ver) { + puts(cpu_type_list[i].name); + break; + } + + if (i == ARRAY_SIZE(cpu_type_list)) puts("Unknown"); - break; - } + printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); @@ -102,19 +116,21 @@ int checkcpu (void) get_sys_info(&sysinfo); puts("Clock Configuration:\n"); - printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); - printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000); - + printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); + printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; switch (ddr_ratio) { case 0x0: - printf(" DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000); + printf(" DDR:%4lu MHz (%lu MT/s data rate), ", + DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); break; case 0x7: - printf(" DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000); + printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ", + DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000)); break; default: - printf(" DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000); + printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ", + DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); break; } @@ -137,15 +153,14 @@ int checkcpu (void) clkdiv *= 2; #endif printf("LBC:%4lu MHz\n", - sysinfo.freqSystemBus / 1000000 / clkdiv); + DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv); } else { printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); } - if (ver == SVR_8560) { - printf("CPM: %lu Mhz\n", - sysinfo.freqSystemBus / 1000000); - } +#ifdef CONFIG_CPM2 + printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); +#endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); @@ -190,11 +205,7 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { - - sys_info_t sys_info; - - get_sys_info(&sys_info); - return ((sys_info.freqSystemBus + 7L) / 8L); + return (gd->bus_clk + 4UL)/8UL; } diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c0ff1d5120..e3240b519e 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -33,6 +33,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/fsl_law.h> +#include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -127,12 +128,12 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { - set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR, + set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 0, BOOKE_PAGESZ_4K, 0); /* set up CCSR if we want it moved */ -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS) { u32 temp; @@ -141,7 +142,7 @@ void cpu_init_early_f(void) 1, 1, BOOKE_PAGESZ_4K, 0); temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT); - out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR >> 12); + out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12); temp = in_be32((volatile u32 *)CFG_CCSRBAR); } @@ -271,7 +272,7 @@ int cpu_init_r(void) uint l2srbar; svr = get_svr(); - ver = SVR_VER(svr); + ver = SVR_SOC_VER(svr); asm("msync;isync"); cache_ctl = l2cache->l2ctl; @@ -328,5 +329,8 @@ int cpu_init_r(void) qe_reset(); #endif +#if defined(CONFIG_MP) + setup_mp(); +#endif return 0; } diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index a6b014cec0..bb87740baa 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -28,6 +28,54 @@ #include <fdt_support.h> extern void ft_qe_setup(void *blob); +#ifdef CONFIG_MP +#include "mp.h" +DECLARE_GLOBAL_DATA_PTR; + +void ft_fixup_cpu(void *blob, u64 memory_limit) +{ + int off; + ulong spin_tbl_addr = get_spin_addr(); + u32 bootpg, id = get_my_id(); + + /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ + if ((u64)gd->ram_size > 0xfffff000) + bootpg = 0xfffff000; + else + bootpg = gd->ram_size - 4096; + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + + if (reg) { + if (*reg == id) { + fdt_setprop_string(blob, off, "status", "okay"); + } else { + u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; + val = cpu_to_fdt32(val); + fdt_setprop_string(blob, off, "status", + "disabled"); + fdt_setprop_string(blob, off, "enable-method", + "spin-table"); + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); + } + } else { + printf ("cpu NULL\n"); + } + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + + /* Reserve the boot page so OSes dont use it */ + if ((u64)bootpg < memory_limit) { + off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); + if (off < 0) + printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); + } +} +#endif void ft_cpu_setup(void *blob, bd_t *bd) { @@ -62,4 +110,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + +#ifdef CONFIG_MP + ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); +#endif } diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c new file mode 100644 index 0000000000..e733f7b00a --- /dev/null +++ b/cpu/mpc85xx/mp.c @@ -0,0 +1,214 @@ +/* + * Copyright 2008 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <ioports.h> +#include <lmb.h> +#include <asm/io.h> +#include "mp.h" + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_my_id() +{ + return mfspr(SPRN_PIR); +} + +int cpu_reset(int nr) +{ + volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + out_be32(&pic->pir, 1 << nr); + (void)in_be32(&pic->pir); + out_be32(&pic->pir, 0x0); + + return 0; +} + +int cpu_status(int nr) +{ + u32 *table, id = get_my_id(); + + if (nr == id) { + table = (u32 *)get_spin_addr(); + printf("table base @ 0x%08x\n", table); + } else { + table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; + printf("Running on cpu %d\n", id); + printf("\n"); + printf("table @ 0x%08x:\n", table); + printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); + printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); + printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); + printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]); + } + + return 0; +} + +static u8 boot_entry_map[4] = { + 0, + BOOT_ENTRY_PIR, + BOOT_ENTRY_R3_LOWER, + BOOT_ENTRY_R6_LOWER, +}; + +int cpu_release(int nr, int argc, char *argv[]) +{ + u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; + u64 boot_addr; + + if (nr == get_my_id()) { + printf("Invalid to release the boot core.\n\n"); + return 1; + } + + if (argc != 4) { + printf("Invalid number of arguments to release.\n\n"); + return 1; + } + +#ifdef CFG_64BIT_STRTOUL + boot_addr = simple_strtoull(argv[0], NULL, 16); +#else + boot_addr = simple_strtoul(argv[0], NULL, 16); +#endif + + /* handle pir, r3, r6 */ + for (i = 1; i < 4; i++) { + if (argv[i][0] != '-') { + u8 entry = boot_entry_map[i]; + val = simple_strtoul(argv[i], NULL, 16); + table[entry] = val; + } + } + + table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32); + table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff); + + return 0; +} + +ulong get_spin_addr(void) +{ + extern ulong __secondary_start_page; + extern ulong __spin_table; + + ulong addr = + (ulong)&__spin_table - (ulong)&__secondary_start_page; + addr += 0xfffff000; + + return addr; +} + +static void pq3_mp_up(unsigned long bootpg) +{ + u32 up, cpu_up_mask, whoami; + u32 *table = (u32 *)get_spin_addr(); + volatile u32 bpcr; + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + u32 devdisr; + int timeout = 10; + + whoami = in_be32(&pic->whoami); + out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); + + /* disable time base at the platform */ + devdisr = in_be32(&gur->devdisr); + if (whoami) + devdisr |= MPC85xx_DEVDISR_TB0; + else + devdisr |= MPC85xx_DEVDISR_TB1; + out_be32(&gur->devdisr, devdisr); + + /* release the hounds */ + up = ((1 << CONFIG_NR_CPUS) - 1); + bpcr = in_be32(&ecm->eebpcr); + bpcr |= (up << 24); + out_be32(&ecm->eebpcr, bpcr); + asm("sync; isync; msync"); + + cpu_up_mask = 1 << whoami; + /* wait for everyone */ + while (timeout) { + int i; + for (i = 1; i < CONFIG_NR_CPUS; i++) { + if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) + cpu_up_mask |= (1 << i); + }; + + if ((cpu_up_mask & up) == up) + break; + + udelay(100); + timeout--; + } + + if (timeout == 0) + printf("CPU up timeout. CPU up mask is %x should be %x\n", + cpu_up_mask, up); + + /* enable time base at the platform */ + if (whoami) + devdisr |= MPC85xx_DEVDISR_TB1; + else + devdisr |= MPC85xx_DEVDISR_TB0; + out_be32(&gur->devdisr, devdisr); + mtspr(SPRN_TBWU, 0); + mtspr(SPRN_TBWL, 0); + + devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); + out_be32(&gur->devdisr, devdisr); +} + +void cpu_mp_lmb_reserve(struct lmb *lmb) +{ + u32 bootpg; + + /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ + if ((u64)gd->ram_size > 0xfffff000) + bootpg = 0xfffff000; + else + bootpg = gd->ram_size - 4096; + + lmb_reserve(lmb, bootpg, 4096); +} + +void setup_mp(void) +{ + extern ulong __secondary_start_page; + ulong fixup = (ulong)&__secondary_start_page; + u32 bootpg; + + /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ + if ((u64)gd->ram_size > 0xfffff000) + bootpg = 0xfffff000; + else + bootpg = gd->ram_size - 4096; + + memcpy((void *)bootpg, (void *)fixup, 4096); + flush_cache(bootpg, 4096); + + pq3_mp_up(bootpg); +} diff --git a/cpu/mpc85xx/mp.h b/cpu/mpc85xx/mp.h new file mode 100644 index 0000000000..4329286f1f --- /dev/null +++ b/cpu/mpc85xx/mp.h @@ -0,0 +1,20 @@ +#ifndef __MPC85XX_MP_H_ +#define __MPC85XX_MP_H_ + +ulong get_spin_addr(void); +void setup_mp(void); +u32 get_my_id(void); +void cpu_mp_lmb_reserve(struct lmb *lmb); + +#define BOOT_ENTRY_ADDR_UPPER 0 +#define BOOT_ENTRY_ADDR_LOWER 1 +#define BOOT_ENTRY_R3_UPPER 2 +#define BOOT_ENTRY_R3_LOWER 3 +#define BOOT_ENTRY_RESV 4 +#define BOOT_ENTRY_PIR 5 +#define BOOT_ENTRY_R6_UPPER 6 +#define BOOT_ENTRY_R6_LOWER 7 +#define NUM_BOOT_ENTRY 8 +#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32)) + +#endif diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S new file mode 100644 index 0000000000..3b7366ff69 --- /dev/null +++ b/cpu/mpc85xx/release.S @@ -0,0 +1,182 @@ +#include <config.h> +#include <mpc85xx.h> +#include <version.h> + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> + +/* To boot secondary cpus, we need a place for them to start up. + * Normally, they start at 0xfffffffc, but that's usually the + * firmware, and we don't want to have to run the firmware again. + * Instead, the primary cpu will set the BPTR to point here to + * this page. We then set up the core, and head to + * start_secondary. Note that this means that the code below + * must never exceed 1023 instructions (the branch at the end + * would then be the 1024th). + */ + .globl __secondary_start_page + .align 12 +__secondary_start_page: +/* First do some preliminary setup */ + lis r3, HID0_EMCP@h /* enable machine check */ + ori r3,r3,HID0_TBEN@l /* enable Timebase */ +#ifdef CONFIG_PHYS_64BIT + ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ +#endif + mtspr SPRN_HID0,r3 + + li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mtspr SPRN_HID1,r3 + + /* Enable branch prediction */ + li r3,0x201 + mtspr SPRN_BUCSR,r3 + + /* Enable/invalidate the I-Cache */ + mfspr r0,SPRN_L1CSR1 + ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE) + mtspr SPRN_L1CSR1,r0 + isync + + /* Enable/invalidate the D-Cache */ + mfspr r0,SPRN_L1CSR0 + ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE) + msync + isync + mtspr SPRN_L1CSR0,r0 + isync + +#define toreset(x) (x - __secondary_start_page + 0xfffff000) + + /* get our PIR to figure out our table entry */ + lis r3,toreset(__spin_table)@h + ori r3,r3,toreset(__spin_table)@l + + /* r10 has the base address for the entry */ + mfspr r0,SPRN_PIR + mr r4,r0 + slwi r8,r4,5 + add r10,r3,r8 + +#define EPAPR_MAGIC (0x45504150) +#define ENTRY_ADDR_UPPER 0 +#define ENTRY_ADDR_LOWER 4 +#define ENTRY_R3_UPPER 8 +#define ENTRY_R3_LOWER 12 +#define ENTRY_RESV 16 +#define ENTRY_PIR 20 +#define ENTRY_R6_UPPER 24 +#define ENTRY_R6_LOWER 28 +#define ENTRY_SIZE 32 + + /* setup the entry */ + li r3,0 + li r8,1 + stw r0,ENTRY_PIR(r10) + stw r3,ENTRY_ADDR_UPPER(r10) + stw r8,ENTRY_ADDR_LOWER(r10) + stw r3,ENTRY_R3_UPPER(r10) + stw r4,ENTRY_R3_LOWER(r10) + stw r3,ENTRY_R6_UPPER(r10) + stw r3,ENTRY_R6_LOWER(r10) + + /* setup mapping for AS = 1, and jump there */ + lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h + mtspr SPRN_MAS0,r11 + lis r11,(MAS1_VALID|MAS1_IPROT)@h + ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l + mtspr SPRN_MAS1,r11 + lis r11,(0xfffff000|MAS2_I)@h + ori r11,r11,(0xfffff000|MAS2_I)@l + mtspr SPRN_MAS2,r11 + lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h + ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l + mtspr SPRN_MAS3,r11 + tlbwe + + bl 1f +1: mflr r11 + addi r11,r11,28 + mfmsr r13 + ori r12,r13,MSR_IS|MSR_DS@l + + mtspr SPRN_SRR0,r11 + mtspr SPRN_SRR1,r12 + rfi + + /* spin waiting for addr */ +2: + lwz r4,ENTRY_ADDR_LOWER(r10) + andi. r11,r4,1 + bne 2b + + /* get the upper bits of the addr */ + lwz r11,ENTRY_ADDR_UPPER(r10) + + /* setup branch addr */ + mtspr SPRN_SRR0,r4 + + /* mark the entry as released */ + li r8,3 + stw r8,ENTRY_ADDR_LOWER(r10) + + /* mask by ~64M to setup our tlb we will jump to */ + rlwinm r12,r4,0,0,5 + + /* setup r3, r4, r5, r6, r7, r8, r9 */ + lwz r3,ENTRY_R3_LOWER(r10) + li r4,0 + li r5,0 + lwz r6,ENTRY_R6_LOWER(r10) + lis r7,(64*1024*1024)@h + li r8,0 + li r9,0 + + /* load up the pir */ + lwz r0,ENTRY_PIR(r10) + mtspr SPRN_PIR,r0 + mfspr r0,SPRN_PIR + stw r0,ENTRY_PIR(r10) + +/* + * Coming here, we know the cpu has one TLB mapping in TLB1[0] + * which maps 0xfffff000-0xffffffff one-to-one. We set up a + * second mapping that maps addr 1:1 for 64M, and then we jump to + * addr + */ + lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h + mtspr SPRN_MAS0,r10 + lis r10,(MAS1_VALID|MAS1_IPROT)@h + ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l + mtspr SPRN_MAS1,r10 + /* WIMGE = 0b00000 for now */ + mtspr SPRN_MAS2,r12 + ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR) + mtspr SPRN_MAS3,r12 +#ifdef CONFIG_ENABLE_36BIT_PHYS + mtspr SPRN_MAS7,r11 +#endif + tlbwe + +/* Now we have another mapping for this page, so we jump to that + * mapping + */ + mtspr SPRN_SRR1,r13 + rfi + + .align 3 + .globl __spin_table +__spin_table: + .space CONFIG_NR_CPUS*ENTRY_SIZE + + /* Fill in the empty space. The actual reset vector is + * the last word of the page */ +__secondary_start_code_end: + .space 4092 - (__secondary_start_code_end - __secondary_start_page) +__secondary_reset_vector: + b __secondary_start_page diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index abc63c414b..435458a189 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -306,7 +306,7 @@ spd_sdram(void) * Adjust DDR II IO voltage biasing. * Only 8548 rev 1 needs the fix */ - if ((SVR_VER(get_svr()) == SVR_8548_E) && + if ((SVR_SOC_VER(get_svr()) == SVR_8548_E) && (SVR_MJREV(get_svr()) == 1) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 952f30cf39..699441b46a 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -48,6 +48,8 @@ void get_sys_info (sys_info_t * sysInfo) * overflow for processor speeds above 2GHz */ half_freqSystemBus = sysInfo->freqSystemBus/2; sysInfo->freqProcessor = e500_ratio*half_freqSystemBus; + + /* Note: freqDDRBus is the MCLK frequency, not the data rate. */ sysInfo->freqDDRBus = sysInfo->freqSystemBus; #ifdef CONFIG_DDR_CLK_FREQ @@ -63,6 +65,9 @@ void get_sys_info (sys_info_t * sysInfo) int get_clocks (void) { sys_info_t sys_info; +#ifdef CONFIG_MPC8544 + volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR; +#endif #if defined(CONFIG_CPM2) volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; uint sccr, dfbrg; @@ -75,8 +80,35 @@ int get_clocks (void) get_sys_info (&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; + gd->mem_clk = sys_info.freqDDRBus; + + /* + * The base clock for I2C depends on the actual SOC. Unfortunately, + * there is no pattern that can be used to determine the frequency, so + * the only choice is to look up the actual SOC number and use the value + * for that SOC. This information is taken from application note + * AN2919. + */ +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) gd->i2c1_clk = sys_info.freqSystemBus; - gd->i2c2_clk = sys_info.freqSystemBus; +#elif defined(CONFIG_MPC8544) + /* + * On the 8544, the I2C clock is the same as the SEC clock. This can be + * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See + * 4.4.3.3 of the 8544 RM. Note that this might actually work for all + * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the + * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. + */ + if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) + gd->i2c1_clk = sys_info.freqSystemBus / 3; + else + gd->i2c1_clk = sys_info.freqSystemBus / 2; +#else + /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ + gd->i2c1_clk = sys_info.freqSystemBus / 2; +#endif + gd->i2c2_clk = gd->i2c1_clk; #if defined(CONFIG_CPM2) gd->vco_out = 2*sys_info.freqSystemBus; @@ -96,14 +128,7 @@ int get_clocks (void) *********************************************/ ulong get_bus_freq (ulong dummy) { - ulong val; - - sys_info_t sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqSystemBus; - - return val; + return gd->bus_clk; } /******************************************** @@ -112,12 +137,5 @@ ulong get_bus_freq (ulong dummy) *********************************************/ ulong get_ddr_freq (ulong dummy) { - ulong val; - - sys_info_t sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqDDRBus; - - return val; + return gd->mem_clk; } diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index bf4e651aaf..3c7476445d 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -69,7 +69,7 @@ checkcpu(void) printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); svr = get_svr(); - ver = SVR_VER(svr); + ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); diff --git a/cpu/mpc8xx/Makefile b/cpu/mpc8xx/Makefile index 223b30cbcc..5f70459690 100644 --- a/cpu/mpc8xx/Makefile +++ b/cpu/mpc8xx/Makefile @@ -27,16 +27,29 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o kgdb.o -COBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \ - fec.o i2c.o interrupts.o lcd.o scc.o \ - serial.o speed.o spi.o \ - traps.o upatch.o video.o -SOBJS = plprcr_write.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) +START-y += start.o +START-y += kgdb.o +COBJS-y += bedbug_860.o +COBJS-y += commproc.o +COBJS-y += cpu.o +COBJS-y += cpu_init.o +COBJS-y += fec.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-y += i2c.o +COBJS-y += interrupts.o +COBJS-y += lcd.o +COBJS-y += scc.o +COBJS-y += serial.o +COBJS-y += speed.o +COBJS-y += spi.o +COBJS-y += traps.o +COBJS-y += upatch.o +COBJS-y += video.o +SOBJS-y += plprcr_write.o + +SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START-y)) all: $(obj).depend $(START) $(LIB) diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c index c878352512..ec6a3fd5d6 100644 --- a/cpu/mpc8xx/cpu.c +++ b/cpu/mpc8xx/cpu.c @@ -634,17 +634,4 @@ void reset_8xx_watchdog (volatile immap_t * immr) immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ # endif /* CONFIG_LWMON */ } - #endif /* CONFIG_WATCHDOG */ - -/* ------------------------------------------------------------------------- */ -#if defined(CONFIG_OF_LIBFDT) -void ft_cpu_setup (void *blob, bd_t *bd) -{ - char * cpu_path = "/cpus/" OF_CPU; - - do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); - do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); -} -#endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/mpc8xx/fdt.c b/cpu/mpc8xx/fdt.c new file mode 100644 index 0000000000..567094a96b --- /dev/null +++ b/cpu/mpc8xx/fdt.c @@ -0,0 +1,46 @@ +/* + * Copyright 2008 (C) Bryan O'Donoghue + * + * Code copied & edited from Freescale mpc85xx stuff. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void ft_cpu_setup(void *blob, bd_t *bd) +{ + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", get_tbclk(), 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", + gd->brg_clk, 1); + + /* Fixup ethernet MAC addresses */ + fdt_fixup_ethernet(blob, bd); + + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 11b089330b..070babcc9a 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -174,6 +174,27 @@ unsigned long measure_gclk(void) #endif +void get_brgclk(uint sccr) +{ + uint divider = 0; + + switch((sccr&SCCR_DFBRG11)>>11){ + case 0: + divider = 1; + break; + case 1: + divider = 4; + break; + case 2: + divider = 16; + break; + case 3: + divider = 64; + break; + } + gd->brg_clk = gd->cpu_clk/divider; +} + #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) /* @@ -223,6 +244,8 @@ int get_clocks (void) gd->bus_clk = gd->cpu_clk / 2; } + get_brgclk(sccr); + return (0); } @@ -254,6 +277,8 @@ int get_clocks_866 (void) gd->cpu_clk = measure_gclk (); #endif + get_brgclk(immr->im_clkrst.car_sccr); + /* if cpu clock <= 66 MHz then set bus division factor to 1, * otherwise set it to 2 */ diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index d990250fcb..c40e0ca480 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -274,7 +274,7 @@ static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) static void ppc_4xx_eth_halt (struct eth_device *dev) { EMAC_4XX_HW_PST hw_p = dev->priv; - uint32_t failsafe = 10000; + u32 val = 10000; out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ @@ -290,8 +290,8 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) /* wait for reset */ while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { udelay (1000); /* Delay 1 MS so as not to hammer the register */ - failsafe--; - if (failsafe == 0) + val--; + if (val == 0) break; } @@ -308,6 +308,13 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) hw_p->print_speed = 1; /* print speed message again next time */ #endif +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + /* don't bypass the TAHOE0/TAHOE1 cores for Linux */ + mfsdr(SDR0_ETH_CFG, val); + val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); + mtsdr(SDR0_ETH_CFG, val); +#endif + return; } @@ -494,11 +501,18 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) u32 zmiifer; /* ZMII0_FER reg. */ u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */ u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */ + int mode; zmiifer = 0; rmiifer = 0; rmiifer1 = 0; +#if defined(CONFIG_460EX) + mode = 9; +#else + mode = 10; +#endif + /* TODO: * NOTE: 460GT has 2 RGMII bridge cores: * emac0 ------ RGMII0_BASE @@ -520,7 +534,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) * Right now only 2*RGMII is supported. Please extend when needed. * sr - 2008-02-19 */ - switch (9) { + switch (mode) { case 1: /* 1 MII - 460EX */ /* GMC0 EMAC4_0, ZMII Bridge */ @@ -703,6 +717,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #ifdef CONFIG_4xx_DCACHE static u32 last_used_ea = 0; #endif +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) + int rgmii_channel; +#endif EMAC_4XX_HW_PST hw_p = dev->priv; @@ -836,10 +855,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg = CONFIG_PHY1_ADDR; break; #endif -#if defined (CONFIG_440GX) +#if defined (CONFIG_PHY2_ADDR) case 2: reg = CONFIG_PHY2_ADDR; break; +#endif +#if defined (CONFIG_PHY3_ADDR) case 3: reg = CONFIG_PHY3_ADDR; break; @@ -1006,12 +1027,17 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) + if (devnum >= 2) + rgmii_channel = devnum - 2; + else + rgmii_channel = devnum; + if (speed == 1000) - reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); + reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel)); else if (speed == 100) - reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); + reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel)); else if (speed == 10) - reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); + reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel)); else { printf("Error in RGMII Speed\n"); return -1; @@ -1057,7 +1083,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #ifdef CONFIG_4xx_DCACHE flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); if (!last_used_ea) +#if defined(CFG_MEM_TOP_HIDE) + bd_uncached = bis->bi_memsize + CFG_MEM_TOP_HIDE; +#else bd_uncached = bis->bi_memsize; +#endif else bd_uncached = last_used_ea + MAL_ALLOC_SIZE; @@ -1131,7 +1161,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif #if defined(CONFIG_460EX) || defined(CONFIG_460GT) - mtdcr (malrxctp8r, hw_p->rx); + mtdcr (malrxctp8r, hw_p->rx_phys); /* set RX buffer size */ mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16); #else @@ -1160,6 +1190,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); break; #endif /* CONFIG_440GX */ +#if defined (CONFIG_460GT) + case 2: + /* setup MAL tx & rx channel pointers */ + mtdcr (maltxbattr, 0x0); + mtdcr (malrxbattr, 0x0); + mtdcr (maltxctp2r, hw_p->tx_phys); + mtdcr (malrxctp16r, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16); + break; + case 3: + /* setup MAL tx & rx channel pointers */ + mtdcr (maltxbattr, 0x0); + mtdcr (malrxbattr, 0x0); + mtdcr (maltxctp3r, hw_p->tx_phys); + mtdcr (malrxctp24r, hw_p->rx_phys); + /* set RX buffer size */ + mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16); + break; +#endif /* CONFIG_460GT */ case 0: default: /* setup MAL tx & rx channel pointers */ @@ -1866,14 +1916,22 @@ int ppc_4xx_eth_initialize (bd_t * bis) case 2: memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], bis->bi_enet2addr, 6); +#if defined(CONFIG_460GT) + hw_addr[eth_num] = 0x300; +#else hw_addr[eth_num] = 0x400; +#endif break; #endif #ifdef CONFIG_HAS_ETH3 case 3: memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], bis->bi_enet3addr, 6); +#if defined(CONFIG_460GT) + hw_addr[eth_num] = 0x400; +#else hw_addr[eth_num] = 0x600; +#endif break; #endif } diff --git a/cpu/ppc4xx/cache.S b/cpu/ppc4xx/cache.S index 5124dec77f..ceb3ec0d34 100644 --- a/cpu/ppc4xx/cache.S +++ b/cpu/ppc4xx/cache.S @@ -166,9 +166,11 @@ _GLOBAL(invalidate_dcache) #ifdef CONFIG_440 .globl dcache_disable + .globl dcache_enable .globl icache_disable .globl icache_enable dcache_disable: +dcache_enable: icache_disable: icache_enable: blr diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 5d15e2f2a0..42eabfe568 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -99,10 +99,107 @@ DECLARE_GLOBAL_DATA_PTR; # endif #endif /* CFG_INIT_DCACHE_CS */ +#ifndef CFG_PLL_RECONFIG +#define CFG_PLL_RECONFIG 0 +#endif + +void reconfigure_pll(u32 new_cpu_freq) +{ +#if defined(CONFIG_440EPX) + int reset_needed = 0; + u32 reg, temp; + u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */ + fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */ + fbdv, target_fbdv, lfbdv, target_lfbdv, + perdv0, target_perdv0, /* CLK_PERD */ + spcid0, target_spcid0; /* CLK_SPCID */ + + /* Reconfigure clocks if necessary. + * See PPC440EPx User's Manual, sections 8.2 and 14 */ + if (new_cpu_freq == 667) { + target_prbdv0 = 2; + target_fwdva = 2; + target_fwdvb = 4; + target_fbdv = 20; + target_lfbdv = 1; + target_perdv0 = 4; + target_spcid0 = 4; + + mfcpr(clk_primbd, reg); + temp = (reg & PRBDV_MASK) >> 24; + prbdv0 = temp ? temp : 8; + if (prbdv0 != target_prbdv0) { + reg &= ~PRBDV_MASK; + reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); + mtcpr(clk_primbd, reg); + reset_needed = 1; + } + + mfcpr(clk_plld, reg); + + temp = (reg & PLLD_FWDVA_MASK) >> 16; + fwdva = temp ? temp : 16; + + temp = (reg & PLLD_FWDVB_MASK) >> 8; + fwdvb = temp ? temp : 8; + + temp = (reg & PLLD_FBDV_MASK) >> 24; + fbdv = temp ? temp : 32; + + temp = (reg & PLLD_LFBDV_MASK); + lfbdv = temp ? temp : 64; + + if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) { + reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK | + PLLD_FBDV_MASK | PLLD_LFBDV_MASK); + reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) | + ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) | + ((target_fbdv == 32 ? 0 : target_fbdv) << 24) | + (target_lfbdv == 64 ? 0 : target_lfbdv); + mtcpr(clk_plld, reg); + reset_needed = 1; + } + + mfcpr(clk_perd, reg); + perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24; + if (perdv0 != target_perdv0) { + reg &= ~CPR0_PERD_PERDV0_MASK; + reg |= (target_perdv0 << 24); + mtcpr(clk_perd, reg); + reset_needed = 1; + } + + mfcpr(clk_spcid, reg); + temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24; + spcid0 = temp ? temp : 4; + if (spcid0 != target_spcid0) { + reg &= ~CPR0_SPCID_SPCIDV0_MASK; + reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24); + mtcpr(clk_spcid, reg); + reset_needed = 1; + } + + /* Set reload inhibit so configuration will persist across + * processor resets */ + mfcpr(clk_icfg, reg); + reg &= ~CPR0_ICFG_RLI_MASK; + reg |= 1 << 31; + mtcpr(clk_icfg, reg); + } + + /* Reset processor if configuration changed */ + if (reset_needed) { + __asm__ __volatile__ ("sync; isync"); + mtspr(dbcr0, 0x20000000); + } +#endif +} + /* * Breath some life into the CPU... * - * Set up the memory map, + * Reconfigure PLL if necessary, + * set up the memory map, * initialize a bunch of registers */ void @@ -111,6 +208,7 @@ cpu_init_f (void) #if defined(CONFIG_WATCHDOG) unsigned long val; #endif + reconfigure_pll(CFG_PLL_RECONFIG); #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE) /* @@ -135,6 +233,7 @@ cpu_init_f (void) #if defined (CFG_GPIO0_TCR) out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ #endif +#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */ #if defined (CONFIG_405EP) /* @@ -147,7 +246,6 @@ cpu_init_f (void) */ mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); #endif /* CONFIG_405EP */ -#endif /* CONFIG_405EP */ #if defined(CFG_4xx_GPIO_TABLE) gpio_set_chip_configuration(); diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 60f89c97fc..e20c9ebf87 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -1093,10 +1093,10 @@ long int initdram(int board_type) program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); - /*------------------------------------------------------------------ + /* * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia - * board SDRAM, but may be overly concervate. - *-----------------------------------------------------------------*/ + * board SDRAM, but may be overly conservative. + */ mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) | DDR0_07_TFAW_ENCODE(13) | DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) | @@ -1181,26 +1181,29 @@ long int initdram(int board_type) denali_wait_for_dlllock(); #if defined(CONFIG_DDR_DATA_EYE) - /* -----------------------------------------------------------+ - * Perform data eye search if requested. - * ----------------------------------------------------------*/ - program_tlb(0, CFG_SDRAM_BASE, dram_size, TLB_WORD2_I_ENABLE); + /* + * Map the first 1 MiB of memory in the TLB, and perform the data eye + * search. + */ + program_tlb(0, CFG_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE); denali_core_search_data_eye(); denali_sdram_register_dump(); - remove_tlb(CFG_SDRAM_BASE, dram_size); + remove_tlb(CFG_SDRAM_BASE, TLB_1MB_SIZE); #endif #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) program_tlb(0, CFG_SDRAM_BASE, dram_size, 0); sync(); - eieio(); /* Zero the memory */ debug("Zeroing SDRAM..."); - dcbz_area(CFG_SDRAM_BASE, dram_size); +#if defined(CFG_MEM_TOP_HIDE) + dcbz_area(CFG_SDRAM_BASE, dram_size - CFG_MEM_TOP_HIDE); +#else +#error Please define CFG_MEM_TOP_HIDE (see README) in your board config file +#endif dflush(); debug("Completed\n"); sync(); - eieio(); remove_tlb(CFG_SDRAM_BASE, dram_size); #if defined(CONFIG_DDR_ECC) @@ -1211,7 +1214,6 @@ long int initdram(int board_type) u32 val; sync(); - eieio(); /* Clear error status */ mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); @@ -1229,7 +1231,6 @@ long int initdram(int board_type) print_mcsr(); #endif sync(); - eieio(); } #endif /* defined(CONFIG_DDR_ECC) */ #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */ diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 698bcb57d7..8620e2b484 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -218,15 +218,16 @@ static void uic_interrupt(u32 uic_base, int vec_base) } else { set_dcr(uic_base + UIC_ER, get_dcr(uic_base + UIC_ER) & - ~(0x80000000 >> vec)); + ~(0x80000000 >> (vec & 0x1f))); printf("Masking bogus interrupt vector %d" " (UIC_BASE=0x%x)\n", vec, uic_base); } /* - * After servicing the interrupt, we have to remove the status indicator. + * After servicing the interrupt, we have to remove the + * status indicator */ - set_dcr(uic_base + UIC_SR, (0x80000000 >> vec)); + set_dcr(uic_base + UIC_SR, (0x80000000 >> (vec & 0x1f))); } /* diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index fa799529d3..05b42fec97 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -165,6 +165,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) } } + sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv; + sysInfo->freqUART = sysInfo->freqProcessor; } diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c index 2bfcba19bd..f44822dbab 100644 --- a/cpu/ppc4xx/tlb.c +++ b/cpu/ppc4xx/tlb.c @@ -149,7 +149,9 @@ void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value) /* * Now check the end-address if it's in the range */ - if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) { + if (((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) || + ((tlb_vaddr < (vaddr + size - 1)) && + ((tlb_vaddr + tlb_size - 1) > (vaddr + size - 1)))) { /* * Found a TLB in the range. * Change cache attribute in tlb2 word. diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c index 5d50b3cea0..eae6adbc0b 100644 --- a/cpu/s3c44b0/cpu.c +++ b/cpu/s3c44b0/cpu.c @@ -155,7 +155,7 @@ int dcache_status (void) #define HEX2BCD(x) ((((x) / 10) << 4) + (x) % 10) #endif -void rtc_get (struct rtc_time* tm) +int rtc_get (struct rtc_time* tm) { RTCCON |= 1; tm->tm_year = BCD2HEX(BCDYEAR); @@ -184,6 +184,8 @@ void rtc_get (struct rtc_time* tm) tm->tm_year += 1900; else tm->tm_year += 2000; + + return 0; } void rtc_set (struct rtc_time* tm) diff --git a/cpu/sh4/cpu.c b/cpu/sh4/cpu.c index 0ebf95180c..d94e139815 100644 --- a/cpu/sh4/cpu.c +++ b/cpu/sh4/cpu.c @@ -24,6 +24,7 @@ #include <common.h> #include <command.h> #include <asm/processor.h> +#include <asm/cache.h> int checkcpu(void) { @@ -51,7 +52,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) void flush_cache (unsigned long addr, unsigned long size) { - + dcache_invalid_range( addr , addr + size ); } void icache_enable (void) |