diff options
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.SPL | 1 | ||||
| -rw-r--r-- | doc/README.atmel_mci | 12 | ||||
| -rw-r--r-- | doc/README.davinci | 9 | ||||
| -rw-r--r-- | doc/README.mx6qsabrelite | 67 | ||||
| -rw-r--r-- | doc/README.sbc8548 | 79 | ||||
| -rw-r--r-- | doc/git-mailrc | 5 |
6 files changed, 156 insertions, 17 deletions
diff --git a/doc/README.SPL b/doc/README.SPL index 89d24a7205..f01a8bd911 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -65,3 +65,4 @@ CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o) CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o) CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o) CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o) +CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o) diff --git a/doc/README.atmel_mci b/doc/README.atmel_mci index dee0cf0a9b..0cbd909829 100644 --- a/doc/README.atmel_mci +++ b/doc/README.atmel_mci @@ -59,17 +59,9 @@ int board_mmc_init(bd_t *bd) } /* this is a weak define that we are overriding */ -int board_mmc_getcd(u8 *cd, struct mmc *mmc) +int board_mmc_getcd(struct mmc *mmc) { - /* - * the only currently existing use of this function - * (fsl_esdhc.c) suggests this function must return - * *cs = TRUE if a card is NOT detected -> in most - * cases the value of the pin when the detect switch - * closes to GND - */ - *cd = at91_get_gpio_value (CONFIG_SYS_MMC_CD_PIN) ? 1 : 0; - return 0; + return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN); } #endif diff --git a/doc/README.davinci b/doc/README.davinci index 5f1bdc836c..aa7c85011a 100644 --- a/doc/README.davinci +++ b/doc/README.davinci @@ -95,6 +95,15 @@ into the RAM. The programmers and UBL are always released as part of any standard TI software release associated with an SOC. +Alternative boot method (DA850 EVM only): +For the DA850 EVM an SPL (secondary program loader, see doc/README.SPL) +is provided to load U-Boot directly from SPI flash. In this case, the +SPL does the low level initialization that is otherwise done by the SPL. +To build U-Boot with this SPL, do +make da850evm_config +make u-boot.ais +and program the resulting u-boot.ais file to the SPI flash of the DA850 EVM. + Environment Variables ===================== diff --git a/doc/README.mx6qsabrelite b/doc/README.mx6qsabrelite new file mode 100644 index 0000000000..4add2bf352 --- /dev/null +++ b/doc/README.mx6qsabrelite @@ -0,0 +1,67 @@ +U-Boot for the Freescale i.MX6q SabreLite board + +This file contains information for the port of U-Boot to the Freescale +i.MX6q SabreLite board. + +1. Boot source, boot from SD card +--------------------------------- + +The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports +boot from SD card only. However, by default, the early version of SabreLite +boards boot from the SPI NOR flash. These boards need to be reflashed with +a small SD card loader to support boot from SD card. This small SD card loader +will be flashed into the SPI NOR. The board will still boot from SPI NOR, but +the loader will in turn request the BootROM to load the U-Boot from SD card. +At the moment of writing, please check with Freescale on the availablity of +this small SD loader binary. + +To update the SPI-NOR on the SabreLite board without the Freescale +manufacturing tool use the following procedure: + +1. Write this SD card loader onto a large SD card using: + + sudo dd if=MX6_SPI_to_SD_loader.bin of=/dev/sXx + +Note: Replace sXx with the device representing the SD card in your system. + +Note: This writes SD card loader at address 0 + +2. Put this SD card into the slot for the large SD card (SD3 on the bottom of +the board) + +3. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot +(the default one the board is shipped with, starting from the SPI NOR) and +enter the following commands: + + MX6Q SABRELITE U-Boot > mmc dev 0 + MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200 + MX6Q SABRELITE U-Boot > sf probe 1 + MX6Q SABRELITE U-Boot > sf erase 0 0x40000 + MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000 + +4. done. + +In case you somehow do not succeed with this procedure you will have to use +the Freescale manufacturing tool in order to reflash the SPI-NOR. + +Note: The board now boots from full size SD3 on the bottom of the board. NOT + the micro SD4/BOOT slot on the top of the board. I.e. you have to use + full size SD cards. + +This information is taken from + +https://wiki.linaro.org/Boards/MX6QSabreLite + +2. Build +-------- + +To build U-Boot for the SabreLite board: + + make mx6qsabrelite_config + make u-boot.imx + +To copy the resulting u-boot.imx to the SD card: + + sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2&&sudo sync + +Note: Replace sXx with the device representing the SD card in your system. diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index 6cbe12f1f5..0f3f5432f2 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -62,6 +62,43 @@ a 33MHz PCI configuration is currently untested.) 02.00.00 0x1148 0x9e00 Network controller 0x00 => +Memory Size and using SPD: +========================== + +The default configuration uses hard coded memory configuration settings +for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD +EEPROM data to read what memory is installed. + +There is a hardware errata, which causes the older local bus SDRAM +SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so +that the SPD data can not be read reliably. You can test if your +board has the errata fix by running "i2c probe". If you see 0x53 +as a valid device, it has been fixed. If you only see 0x50, 0x51 +then your board does not have the fix. + +You can also visually inspect the board to see if this hardware +fix has been applied: + + 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on + the back of the PCB behind the DDR SDRAM SODIMM connector. + 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad + to R313 pin 2. Pin 2 for each resistor is the end of the + resistor closest to the CPU. + +Boards without the mod will have R314 and R313 in parallel, like "||". +After the mod, they will be touching and form an "L" shape. + +If you want to upgrade to larger RAM size, you can simply enable + #define CONFIG_SPD_EEPROM + #define CONFIG_DDR_SPD +in include/configs/sbc8548.h file. (The lines are already there +but listed as #undef). + +If you did the i2c test, and your board does not have the errata +fix, then you will have to physically remove the LBC 128MB DIMM +from the board's socket to resolve the above i2c address overlap +issue and allow SPD autodetection of RAM to work. + Updating U-boot with U-boot: ============================ @@ -86,6 +123,33 @@ The "md" steps in the above are just a precautionary step that allow you to confirm the u-boot version that was downloaded, and then confirm that it was copied to flash. +The above assumes that you are using the default board settings which +have u-boot in the 8MB flash, tied to /CS0. + +If you are running the default 8MB /CS0 settings but want to store an +image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled, +(as a backup, etc) then the steps will become: + + tftp u-boot.bin + md 200000 10 + protect off all + era eff00000 efffffff + cp.b 200000 eff00000 100000 + md eff00000 10 + protect on all + +Finally, if you are running the alternate 64MB /CS0 settings and want +to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT +enabled) the steps will become: + + tftp u-boot.bin + md 200000 10 + protect off all + era fff00000 ffffffff + cp.b 200000 fff00000 100000 + md fff00000 10 + protect on all + Hardware Reference: =================== @@ -100,6 +164,9 @@ Boot flash: Sodimm flash: intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000 + Note that this address reflects the default setting for + the JTAG debugging tools, but since the alignment is + rather inconvenient, u-boot puts it at 0xec00_0000. Jumpers: @@ -124,10 +191,9 @@ JP19 PCI mode PCI PCI-X onto /CS0 and the SODIMM flash on /CS6 (default). When JP12 is jumpered parallel to the LBC-SDRAM, then /CS0 is for the SODIMM flash and /CS6 is for the boot flash. Note that in this -alternate setting, you also need to switch SW2.8 to ON. Currently -u-boot doesn't support booting off the SODIMM in this alternate -setting without manually altering BR0/OR0 and BR6/OR6 in the -board config file appropriately. +alternate setting, you also need to switch SW2.8 to ON. +See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting +and boot u-boot from the 64MB SODIMM Switches: @@ -187,9 +253,12 @@ start end CS<n> width Desc. 0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB) f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB) f800_0000 f8b0_1fff CS5 - EPLD -fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) +fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*] ff80_0000 ffff_ffff CS0 8 Boot flash (8MB) +[*] fb80 represents the default programmed by WR JTAG register files, + but u-boot places the flash at either ec00 or fc00 based on JP12. + The EPLD on CS5 demuxes the following devices at the following offsets: offset size width device diff --git a/doc/git-mailrc b/doc/git-mailrc index 4039e55f5c..96f1d86e2b 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -39,16 +39,17 @@ alias arches arch alias arm uboot, aaribaud alias at91 uboot, reinhardm -alias davinci omap +alias davinci ti alias imx uboot, sbabic alias kirkwood uboot, prafulla -alias omap uboot, Sandeep Paulraj <s-paulraj@ti.com> +alias omap ti alias pxa uboot, marex alias s3c samsung alias s5pc samsung alias samsung uboot, prom alias tegra uboot, Simon Glass <sjg@chromium.org>, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com> alias tegra2 tegra +alias ti uboot, Sandeep Paulraj <s-paulraj@ti.com>, Tom Rini <trini@ti.com> alias avr32 uboot, reinhardm |