diff options
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.avb2 | 1 | ||||
| -rw-r--r-- | doc/README.uniphier | 55 | ||||
| -rw-r--r-- | doc/device-tree-bindings/phy/no-op.txt | 16 | ||||
| -rw-r--r-- | doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt | 73 | ||||
| -rw-r--r-- | doc/device-tree-bindings/rtc/brcm,brcmstb-waketimer.txt | 22 |
5 files changed, 167 insertions, 0 deletions
diff --git a/doc/README.avb2 b/doc/README.avb2 index 67784b529e..120279fedb 100644 --- a/doc/README.avb2 +++ b/doc/README.avb2 @@ -58,6 +58,7 @@ Slot verification result: ERROR_IO ----------------------------------- The following options must be enabled: CONFIG_LIBAVB=y +CONFIG_AVB_VERIFY=y CONFIG_CMD_AVB=y diff --git a/doc/README.uniphier b/doc/README.uniphier index 990806ab79..badfacd66a 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -332,6 +332,61 @@ for kernel, DTB, and Init ramdisk. If they are not displayed, the Verified Boot is not working. +Deployment for Distro Boot +-------------------------- + +UniPhier SoC family boot the kernel in a generic manner as described in +doc/README.distro . + +To boot the kernel, you need to deploy necesssary components to a file +system on one of your block devices (eMMC, NAND, USB drive, etc.). + +The components depend on the kernel image format. + +[1] Bare images + + - kernel + - init ramdisk + - device tree blob + - boot configuration file (extlinux.conf) + +Here is an exmple of the configuration file. + +-------------------->8-------------------- +menu title UniPhier Boot Options. + +timeout 50 +default UniPhier + +label UniPhier + kernel ../Image + initrd ../rootfs.cpio.gz + fdtdir .. +-------------------->8-------------------- + +Then, write 'Image', 'rootfs.cpio.gz', 'uniphier-ld20-ref.dtb' (DTB depends on +your board), and 'extlinux/extlinux.conf' to the file system. + +[2] FIT + + - FIT blob + - boot configuration file (extlinux.conf) + +-------------------->8-------------------- +menu title UniPhier Boot Options. + +timeout 50 +default UniPhier + +label UniPhier + kernel ../fitImage +-------------------->8-------------------- + +Since the init ramdisk and DTB are contained in the FIT blob, +you do not need to describe them in the configuration file. +Write 'fitImage' and 'extlinux/extlinux.conf' to the file system. + + UniPhier specific commands -------------------------- diff --git a/doc/device-tree-bindings/phy/no-op.txt b/doc/device-tree-bindings/phy/no-op.txt new file mode 100644 index 0000000000..a3381122e6 --- /dev/null +++ b/doc/device-tree-bindings/phy/no-op.txt @@ -0,0 +1,16 @@ +NOP PHY driver + +This driver is used to stub PHY operations in a driver (USB, SATA). +This is useful when the 'client' driver (USB, SATA, ...) uses the PHY framework +and there is no actual PHY harwdare to drive. + +Required properties: +- compatible : must contain "nop-phy" +- #phy-cells : must contain <0> + +Example: + +nop_phy { + compatible = "nop-phy"; + #phy-cells = <0>; +}; diff --git a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt new file mode 100644 index 0000000000..725ae71ae6 --- /dev/null +++ b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt @@ -0,0 +1,73 @@ +STMicroelectronics STM32 USB HS PHY controller + +The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI +switch. It controls PHY configuration and status, and the UTMI+ switch that +selects either OTG or HOST controller for the second PHY port. It also sets +PLL configuration. + +USBPHYC + |_ PLL + | + |_ PHY port#1 _________________ HOST controller + | _ | + | / 1|________________| + |_ PHY port#2 ----| |________________ + | \_0| | + |_ UTMI switch_______| OTG controller + + +Phy provider node +================= + +Required properties: +- compatible: must be "st,stm32mp1-usbphyc" +- reg: address and length of the usb phy control register set +- clocks: phandle + clock specifier for the PLL phy clock +- #address-cells: number of address cells for phys sub-nodes, must be <1> +- #size-cells: number of size cells for phys sub-nodes, must be <0> + +Optional properties: +- assigned-clocks: phandle + clock specifier for the PLL phy clock +- assigned-clock-parents: the PLL phy clock parent +- resets: phandle + reset specifier + +Required nodes: one sub-node per port the controller provides. + +Phy sub-nodes +============== + +Required properties: +- reg: phy port index +- phy-supply: phandle to the regulator providing 3V3 power to the PHY, + see phy-bindings.txt in the same directory. +- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY +- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY +- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY + port#1 and must be <1> for PHY port#2, to select USB controller + + +Example: + usbphyc: usb-phy@5a006000 { + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc_clk USBPHY_K>; + resets = <&rcc_rst USBPHY_R>; + #address-cells = <1>; + #size-cells = <0>; + + usbphyc_port0: usb-phy@0 { + reg = <0>; + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18> + #phy-cells = <0>; + }; + + usbphyc_port1: usb-phy@1 { + reg = <1>; + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18> + #phy-cells = <1>; + }; + }; diff --git a/doc/device-tree-bindings/rtc/brcm,brcmstb-waketimer.txt b/doc/device-tree-bindings/rtc/brcm,brcmstb-waketimer.txt new file mode 100644 index 0000000000..1d990bcc0b --- /dev/null +++ b/doc/device-tree-bindings/rtc/brcm,brcmstb-waketimer.txt @@ -0,0 +1,22 @@ +Broadcom STB wake-up Timer + +The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the +ability to wake up the system from low-power suspend/standby modes. + +Required properties: +- compatible : should contain "brcm,brcmstb-waketimer" +- reg : the register start and length for the WKTMR block +- interrupts : The TIMER interrupt +- interrupt-parent: The phandle to the Always-On (AON) Power Management (PM) L2 + interrupt controller node +- clocks : The phandle to the UPG fixed clock (27Mhz domain) + +Example: + +waketimer@f0411580 { + compatible = "brcm,brcmstb-waketimer"; + reg = <0xf0411580 0x14>; + interrupts = <0x3>; + interrupt-parent = <&aon_pm_l2_intc>; + clocks = <&upg_fixed>; +}; |