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-rw-r--r--doc/README.PIP405385
-rw-r--r--doc/README.RPXlite887
-rw-r--r--doc/README.Sandpoint8240397
3 files changed, 1669 insertions, 0 deletions
diff --git a/doc/README.PIP405 b/doc/README.PIP405
new file mode 100644
index 0000000000..c5ccf1875e
--- /dev/null
+++ b/doc/README.PIP405
@@ -0,0 +1,385 @@
+U-Boot Changes due to PIP405 Port:
+===================================
+
+Changed files:
+==============
+- MAKEALL added PIP405
+- makefile added PIP405
+- common/Makefile added Floppy disk and SCSI support
+- common/board.c added PIP405, SCSI support, get_PCI_freq()
+- common/bootm.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
+- common/cmd_i2c.c added "defined(CONFIG_PIP405)"
+- common/cmd_ide.c changed div. functions to work with block device
+ description
+ added ATAPI support
+- common/command.c added SCSI and Floppy support
+- common/console.c replaced // with /* comments
+ added console settings from environment
+- common/devices.c added ISA keyboard init
+- common/main.c corrected the read of bootdelay
+- cpu/ppc4xx/405gp_pci.c excluded file from PIP405
+- cpu/ppc4xx/i2c.c added 16bit read write I2C support
+ added page write
+- cpu/ppc4xx/speed.c added get_PCI_freq
+- cpu/ppc4xx/start.S added CONFIG_IDENT_STRING
+- disk/Makefile added part_iso for CD support
+- disk/part.c changed to work with block device description
+ added ISO CD support
+ added dev_print (was ide_print in cmd_ide.c)
+- disk/part_dos.c changed to work with block device description
+- disk/part_mac.c changed to work with block device description
+- include/ata.h added ATAPI commands
+- include/cmd_bsp.h added PIP405 commands definitions
+- include/cmd_condefs.h added Floppy and SCSI support
+- include/cmd_disk.h changed to work with block device description
+- include/config_LANTEC.h excluded CFG_CMD_FDC and CFG_CMD_SCSI from
+ CONFIG_CMD_FULL
+- include/config_hymod.h excluded CFG_CMD_FDC and CFG_CMD_SCSI from
+ CONFIG_CMD_FULL
+- include/flash.h added INTEL_ID_28F320C3T 0x88C488C4
+- include/i2c.h added "defined(CONFIG_PIP405)"
+- include/image.h added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
+- include/u-boot.h moved partitions functions definitions to part.h
+ added "defined(CONFIG_PIP405)"
+ added get_PCI_freq() definition
+- rtc/Makefile added MC146818 RTC support
+- tools/mkimage.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
+
+Added files:
+============
+- board/pip405 directory for PIP405
+- board/pip405/cmd_pip405.c board specific commands
+- board/pip405/config.mk config make
+- board/pip405/flash.c flash support
+- board/pip405/init.s start-up
+- board/pip405/kbd.c keyboard support
+- board/pip405/kbd.h keyboard support
+- board/pip405/Makefile Makefile
+- board/pip405/pci_piix4.h southbridge definitions
+- board/pip405/pci_pip405.c PCI support for PIP405
+- board/pip405/pci_pip405.h PCI support for PIP405
+- board/pip405/pip405.c PIP405 board init
+- board/pip405/pip405.h PIP405 board init
+- board/pip405/pip405_isa.c ISA support
+- board/pip405/pip405_isa.h ISA support
+- board/pip405/u-boot.lds Linker description
+- board/pip405/u-boot.lds.debugLinker description debug
+- board/pip405/sym53c8xx.c SYM53C810A support
+- board/pip405/sym53c8xx_defs.h SYM53C810A definitions
+- board/pip405/vga_table.h definitions of tables for VGA
+- board/pip405/video.c CT69000 support
+- board/pip405/video.h CT69000 support
+- common/cmd_fdc.c Floppy disk support
+- common/cmd_scsi.c SCSI support
+- disk/part_iso.c ISO CD ROM support
+- disk/part_iso.h ISO CD ROM support
+- include/cmd_fdc.h command forFloppy disk support
+- include/cmd_scsi.h command for SCSI support
+- include/part.h partitions functions definitions
+ (was part of u-boot.h)
+- include/scsi.h SCSI support
+- rtc/mc146818.c MC146818 RTC support
+
+
+New Config Switches:
+====================
+For detailed description, refer to the corresponding paragraph in the
+section "Changes".
+
+New Commands:
+-------------
+CFG_CMD_SCSI SCSI Support
+CFG_CMF_FDC Floppy disk support
+
+IDE additions:
+--------------
+CONFIG_IDE_RESET_ROUTINE defines that instead of a reset Pin,
+ the routine ide_set_reset(int idereset) is used.
+ATAPI support (experimental)
+----------------------------
+CONFIG_ATAPI enables ATAPI Support
+
+SCSI support (experimental) only SYM53C8xx supported
+----------------------------------------------------
+CONFIG_SCSI_SYM53C8XX type of SCSI controller
+CFG_SCSI_MAX_LUN 8 number of supported LUNs
+CFG_SCSI_MAX_SCSI_ID 7 maximum SCSI ID (0..6)
+CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN
+ maximum of Target devices (multiple LUN support
+ for boot)
+
+ISO (CD-Boot) partition support (Experimental)
+----------------------------------------------
+CONFIG_ISO_PARTITION CD-boot support
+
+RTC
+----
+CONFIG_RTC_MC146818 MC146818 RTC support
+
+Keyboard:
+---------
+CONFIG_ISA_KEYBOARD Standard (PC-Style) Keyboard support
+
+Video:
+------
+CONFIG_VIDEO_CT69000 Enable Chips & Technologies 69000 Video chip
+ CONFIG_VIDEO must be defined also
+
+External peripheral base address:
+---------------------------------
+CFG_ISA_IO_BASE_ADDRESS address of all ISA-bus related parts
+ _must_ be defined for ISA-bus parts
+
+Identify:
+---------
+CONFIG_IDENT_STRING added to the U_BOOT_VERSION String
+
+
+I2C stuff:
+----------
+CFG_EEPROM_PAGE_WRITE_ENABLE enables page write of the I2C EEPROM
+ CFG_EEPROM_PAGE_WRITE_BITS _must_ be
+ defined.
+
+
+Environment / Console:
+----------------------
+
+CFG_CONSOLE_IS_IN_ENV if defined, stdin, stdout and stderr used from
+ the values stored in the evironment.
+
+CFG_CONSOLE_OVERWRITE_ROUTINE if defined, console_overwrite() decides if the
+ values stored in the environment or the standard
+ serial in/out put should be assigned to the console.
+
+CFG_CONSOLE_ENV_OVERWRITE if defined, the start-up console switching
+ are stored in the environment.
+
+PIP405 specific:
+----------------
+CONFIG_PORT_ADDR address used to read boot configuration
+MULTI_PURPOSE_SOCKET_ADDR address of the multi purpose socked
+SDRAM_EEPROM_WRITE_ADDRESS addresses of the serial presence detect
+SDRAM_EEPROM_READ_ADDRESS EEPROM on the SDRAM module.
+
+
+Changes:
+========
+
+Added Devices:
+==============
+
+Floppy support:
+---------------
+Support of a standard floppy disk controller at address CFG_ISA_IO_BASE_ADDRESS
++ 0x3F0. Enabled with define CFG_CMD_FDC. Reads a unformated floppy disk with a
+image header (see: mkimage). No interrupts and no DMA are used for this.
+Added files:
+- common/cmd_fdc.c
+- include/cmd_fdc.h
+
+SCSI support:
+-------------
+Support for Symbios SYM53C810A chip. Implemented as follows:
+- without disconnect
+- only asynchrounous
+- multiple LUN support (caution, needs a lot of RAM. define CFG_SCSI_MAX_LUN 1 to
+ save RAM)
+- multiple SCSI ID support
+- no write support
+- analyses the MAC, DOS and ISO pratition similar to the IDE support
+- allows booting from SCSI devices similar to the IDE support.
+The device numbers are not assigned like they are within the IDE support. The first
+device found will get the number 0, the next 1 etc. If all SCSI IDs (0..6) and all
+LUNs (8) are enabled, 56 boot devices are possible. This uses a lot of RAM since the
+device descriptors are not yet dynamically allocated. 56 boot devices are overkill
+anyway. Please refer to the section "Todo" chapter "block device support enhancement".
+The SYM53C810A uses 1 Interrupt and must be able of mastering the PCI bus.
+Added files:
+- common/cmd_scsi.c
+- common/board.c
+- include/cmd_scsi.h
+- include/scsi.h
+- board/pip405/sym53c8xx.c
+- board/pip405/sym53c8xx_defs.h
+
+ATAPI support (IDE changes):
+----------------------------
+Added ATAPI support (with CONFIG_ATAPI) in the file cmd_ide.c.
+To support a hardreset, when the IDE reset pin is not connected to the
+CFG_PC_IDE_RESET pin, the switch CONFIG_IDE_RESET_ROUTINE has been added. When
+this switch is enabled the routine void ide_set_reset(int idereset) must be
+within the board specific files.
+Only read from ATAPI devices are supported.
+Found out that the function trim_trail cuts off the last character if the whole
+string is filled. Added function cpy_ident instead, which trims also leading
+spaces and copies the string in the buffer.
+Changed files:
+- common/cmd_ide.c
+- include/ata.h
+
+ISO partition support:
+----------------------
+Added CD boot support for El-Torito bootable ISO CDs. The bootfile image must contain
+the U-Boot image header. Since CDs do not have "partitions", the boot partition is 0.
+The bootcatalog feature has not been tested so far. CD Boot is supported for ATAPI
+("diskboot") and SCSI ("scsiboot") devices.
+Added files:
+- disk/iso_part.c
+- disk/iso_part.h
+
+Block device changes:
+---------------------
+To allow the use of dos_part.c, mac_part.c and iso_part.c, the parameter
+block_dev_desc will be used when accessing the functions in these files. The block
+device descriptor (block_dev_desc) contains a pointer to the read routine of the
+device, which will be used to read blocks from the device.
+Renamed function ide_print to dev_print and moved it to the file disk/part.c to use
+it for IDE ATAPI and SCSI devices.
+Please refer to the section "Todo" chapter "block device support enhancement".
+Added files:
+- include/part.h
+changed files:
+- disk/dos_part.c
+- disk/dos_part.h
+- disk/mac_part.c
+- disk/mac_part.h
+- disk/part.c
+- common/cmd_ide.c
+- include/u-boot.h
+
+
+MC146818 RTC support:
+---------------------
+Added support for MC146818 RTC with defining CONFIG_RTC_MC146818. The ISA bus IO
+base address must be defined with CFG_ISA_IO_BASE_ADDRESS.
+Added files:
+- rtc/mc146818.c
+
+Standard ISA bus Keyboard support:
+----------------------------------
+Added support for the standard PC kyeboard controller. For the PIP405 the superIO
+controller must be set up previously. The keyboard uses the standard ISA IRQ, so
+the ISA PIC must also be set up.
+Added files:
+- board/pip405/kbd.c
+- board/pip405/kbd.h
+- board/pip405/pip405_isa.c
+- board/pip405/pip405_isa.h
+
+Chips and Technologie 69000 VGA controller support:
+---------------------------------------------------
+Added support for the CT69000 VGA controller.
+Added files:
+- board/pip405/video.c
+- board/pip405/video.h
+- board/pip405/vga_table.h
+
+
+Changed Items:
+==============
+
+Identify:
+---------
+Added the config variable CONFIG_IDENT_STRING which will be added to the
+"U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate
+and custom versions.
+Changed files:
+- cpu/ppc4xx/start.s
+
+Firmware Image:
+---------------
+Added IH_OS_U_BOOT and IH_TYPE_FIRMWARE to the image definitions to allows the
+U-Boot update with prior CRC check.
+Changed files:
+- include/image.h
+- tools/mkimage.c
+- common/cmd_bootm.c
+
+Correct PCI Frequency for PPC405:
+---------------------------------
+Added function (in cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU.
+The PCI Frequency will now be set correct in the board description in common/board.c.
+(was set to the busfreq before).
+Changed files:
+- cpu/ppc4xx/speed.c
+- common/board.c
+
+I2C Stuff:
+----------
+Added defined(CONFIG_PIP405) at several points in common/cmd_i2c.c.
+Added 16bit read/write support for I2C (PPC405), and page write to
+I2C EEPROM if defined CFG_EEPROM_PAGE_WRITE_ENABLE.
+Changed files:
+- cpu/ppc4xx/i2c.c
+- common/cmd_i2c.c
+
+Environment / Console:
+----------------------
+Although in README.console described, the U-Boot has not assinged the values
+found in the environment to the console. Corrected this behavior, but only if
+CFG_CONSOLE_IS_IN_ENV is defined.
+If CFG_CONSOLE_OVERWRITE_ROUTINE is defined, console_overwrite() decides if the
+values stored in the environment or the standard serial in/output should be
+assigned to the console. This is useful if the environment values are not correct.
+If CFG_CONSOLE_ENV_OVERWRITE is defined the devices assigned to the console at
+start-up time will be written to the environment. This means that if the
+environment values are overwritten by the overwrite_console() routine, they will be
+stored in the environment.
+Changed files:
+- common/console.c
+
+Correct bootdelay intepretation:
+--------------------------------
+Changed bootdelay read from the environment from simple_strtoul (unsigned) to
+simple_strtol (signed), to be able to get a bootdelay of -1.
+Changed files:
+- common/main.c
+
+Todo:
+=====
+
+Block device support enhancement:
+---------------------------------
+Consider to unify the block device handling. Instead of using diskboot for IDE,
+scsiboot for SCSI and fdcboot for floppy disks, it would make sense to use only
+one command ("devboot" ???) with a parameter of the desired device ("hda1", "sda1",
+"fd0" ???) to boot from. The other ide commands can be handled in the same way
+("dev hda read.." instead of "ide read.." or "dev sda read.." instead of
+"scsi read..."). Todo this, a common way of assign a block device to its name
+(first found ide device = hda, second found hdb etc., or hda is device 0 on bus 0,
+hdb is device 1 on bus 0 etc.) as well as the names (hdx for ide, sdx for scsi, fx for
+floppy ???) must be defined.
+Maybe there are better ideas to do this.
+
+Console assingment:
+-------------------
+Consider to initialize and assign the console stdin, stdout and stderr as soon as
+possible to see the boot messages also on an other console than serial.
+
+
+Todo for PIP405:
+================
+
+LCD support for VGA:
+--------------------
+Add LCD support for the CT69000
+
+Default environment:
+--------------------
+Consider to write a default environment to the OTP part of the EEPROM and use it
+if the normal environment is not valid. Useful for serial# and ethaddr values.
+
+Watchdog:
+---------
+Implement Watchdog.
+
+Files clean-up:
+---------------
+Following files needs to be cleaned up:
+- cmd_pip405.c
+- flash.c
+- pci_pip405.c
+- pip405.c
+- pip405_isa.c
+Consider to split up the files in their functions.
diff --git a/doc/README.RPXlite b/doc/README.RPXlite
new file mode 100644
index 0000000000..25bf80b2a8
--- /dev/null
+++ b/doc/README.RPXlite
@@ -0,0 +1,887 @@
+# Porting U-Boot onto RPXlite board
+# Written by Yoo. Jonghoon
+# E-Mail : yooth@ipone.co.kr
+# IP ONE Inc.
+
+# Since 2001. 1. 29
+
+# Shell : bash
+# Cross-compile tools : Montavista Hardhat
+# Debugging tools : Windriver VisionProbe (PowerPC BDM)
+# ppcboot ver. : ppcboot-0.8.1
+
+###############################################################
+# 1. Hardware setting
+###############################################################
+
+1.1. Board, BDM settings
+ Install board, BDM, connect each other
+
+1.2. Save Register value
+ Boot with board-on monitor program and save the
+ register values with BDM.
+
+1.3. Configure flash programmer
+ Check flash memory area in the memory map.
+ 0xFFC00000 - 0xFFFFFFFF
+
+ Boot monitor program is at
+ 0xFFF00000
+
+ You can program on-board flash memory with VisionClick
+ flash programmer. Set the target flash device as:
+
+ 29DL800B
+
+ (?) The flash memory device in the board *is* 29LV800B,
+ but I cannot program it with '29LV800B' option.
+ (in VisionClick flash programming tools)
+ I don't know why...
+
+1.4. Save boot monitor program *IMPORTANT*
+ Upload boot monitor program from board to file.
+ boot monitor program starts at 0xFFF00000
+
+1.5. Test flash memory programming
+ Try to erase boot program in the flash memory,
+ and re-write them.
+ *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE
+ BEFORE ERASING FLASH
+
+###############################################################
+# 2. U-Boot setting
+###############################################################
+
+2.1. Download U-Boot tarball at
+ ftp://ftp.denx.de
+ (The latest version is ppcboot-0.8.1.tar.bz2)
+
+ To extract the archive use the following syntax :
+ > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf -
+
+2.2. Add the following lines in '.profile'
+ export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin
+
+2.3. Make board specific config, for example:
+ > cd ppcboot-0.8.1
+ > make TQM860L_config
+
+ Now we can build ppcboot bin files.
+ After make all, you must see these files in your
+ ppcboot root directory.
+
+ ppcboot
+ ppcboot.bin
+ ppcboot.srec
+ ppcboot.map
+
+2.4. Make your own board directory into the
+ ppcboot-0.8.1/board
+ and make your board-specific files here.
+
+ For exmanple, tqm8xx files are composed of
+ .depend : Nothing
+ Makefile : To make config file
+ config.mk : Sets base address
+ flash.c : Flash memory control files
+ ppcboot.lds : linker(ld) script? (I don't know this yet)
+ tqm8xx.c : DRAM control and board check routines
+
+ And, add your board config lines in the
+ ppcboot-0.8.1/Makefile
+
+ Finally, add config_(your board).h file in the
+ ppcboot-0.8.1/include/
+
+ I've made board/rpxlite directory, and just copied
+ tqm8xx settings for now.
+
+ Rebuild ppcboot for rpxlite board:
+ > make rpxlite_config
+ > make
+
+###############################################################
+# 3. U-Boot porting
+###############################################################
+
+3.1. My RPXlite files are based on tqm8xx board files.
+ > cd board
+ > cp -r tqm8xx RPXLITE
+ > cd RPXLITE
+ > mv tqm8xx.c RPXLITE.c
+ > cd ../../include
+ > cp config_tqm8xx.h config_RPXLITE.h
+
+3.2. Modified files are:
+ board/RPXLITE/RPXLITE.c /* DRAM-related routines */
+ board/RPXLITE/flash.c /* flash-related routines */
+ board/RPXLITE/config.mk /* set text base address */
+ cpu/mpc8xx/serial.c /* board specific register setting */
+ include/config_RPXLITE.h /* board specific registers */
+
+ See 'reg_config.txt' for register values in detail.
+
+###############################################################
+# 4. Running Linux
+###############################################################
+
+
+
+
+
+
+
+
+
+###############################################################
+# Misc Information
+###############################################################
+
+mem_config.txt:
+===============
+
+Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device
+manufacturer id : 01 (AMD)
+device id : 5B (AM29LV800B)
+size : 4Mbyte
+sector # : 19
+
+Sector information :
+
+number start addr. size
+00 FFC0_0000 64
+01 FFC1_0000 32
+02 FFC1_8000 32
+03 FFC2_0000 128
+04 FFC4_0000 256
+05 FFC8_0000 256
+06 FFCC_0000 256
+07 FFD0_0000 256
+08 FFD4_0000 256
+09 FFD8_0000 256
+10 FFDC_0000 256
+11 FFE0_0000 256
+12 FFE4_0000 256
+13 FFE8_0000 256
+14 FFEC_0000 256
+15 FFF0_0000 256
+16 FFF4_0000 256
+17 FFF8_0000 256
+18 FFFC_0000 256
+
+
+reg_config.txt:
+===============
+
+
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+/* SIU (System Interface Unit) */
+/* */
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+
+
+/*### IMMR */
+/*### Internal Memory Map Register */
+/*### Chap. 11.4.1 */
+
+ ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */
+ PARTNUM = 0x21
+ MASKNUM = 0x00
+
+ => 0xFA20 2100
+
+---------------------------------------------------------------------
+
+/*### SIUMCR */
+/*### SIU Module Configuration Register */
+/*### Chap. 11.4.2 */
+/*### Offset : 0x0000 0000 */
+
+ EARB = 0
+ EARP = 0
+ DSHW = 0
+ DBGC = 0
+ DBPC = 0
+ FRC = 0
+ DLK = 0
+ OPAR = 0
+ PNCS = 0
+ DPC = 0
+ MPRE = 0
+ MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */
+ AEME = 0
+ SEME = 0
+ BSC = 0
+ GB5E = 0
+ B2DD = 0
+ B3DD = 0
+
+ => 0x0000 0800
+
+---------------------------------------------------------------------
+
+/*### SYPCR */
+/*### System Protection Control Register */
+/*### Chap. 11.4.3 */
+/*### Offset : 0x0000 0004 */
+
+ SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */
+ BMT = 0x06 /* BUS monitoring timing */
+ BME = 1 /* BUS monitor enable */
+ SWF = 1
+ SWE = 0 /* SW watchdog disable */
+ SWRI = 0
+ SWP = 1
+
+ => 0xFFFF 0689
+
+---------------------------------------------------------------------
+
+/*### TESR */
+/*### Transfer Error Status Register */
+/*### Chap. 11.4.4 */
+/*### Offset : 0x0000 0020 */
+
+ IEXT = 0
+ ITMT = 0
+ IPB = 0000
+ DEXT = 0
+ DTMT = 0
+ DPB = 0000
+
+ => 0x0000 0000
+
+---------------------------------------------------------------------
+
+/*### SIPEND */
+/*### SIU Interrupt Pending Register */
+/*### Chap. 11.5.4.1 */
+/*### Offset : 0x0000 0010 */
+
+ IRQ0~IRQ7 = 0
+ LVL0~LVL7 = 0
+
+ => 0x0000 0000
+
+---------------------------------------------------------------------
+
+/*### SIMASK */
+/*### SIU Interrupt Mask Register */
+/*### Chap. 11.5.4.2 */
+/*### Offset : 0x0000 0014 */
+
+ IRM0~IRM7 = 0 /* Mask all interrupts */
+ LVL0~LVL7 = 0
+
+ => 0x0000 0000
+
+---------------------------------------------------------------------
+
+/*### SIEL */
+/*### SIU Interrupt Edge/Level Register */
+/*### Chap. 11.5.4.3 */
+/*### Offset : 0x0000 0018 */
+
+ ED0~ED7 = 0 /* Low level triggered */
+ WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */
+
+ => 0x0000 0000
+
+---------------------------------------------------------------------
+
+/*### SIVEC */
+/*### SIU Interrupt Vector Register */
+/*### Chap. 11.5.4.4 */
+/*### Offset : 0x0000 001C */
+
+ INTC = 3C /* The lowest interrupt is pending..(?) */
+
+ => 0x3C00 0000
+
+---------------------------------------------------------------------
+
+/*### SWSR */
+/*### Software Service Register */
+/*### Chap. 11.7.1 */
+/*### Offset : 0x0000 001E */
+
+ SEQ = 0
+
+ => 0x0000
+
+---------------------------------------------------------------------
+
+/*### SDCR */
+/*### SDMA Configuration Register */
+/*### Chap. 20.2.1 */
+/*### Offset : 0x0000 0032 */
+
+ FRZ = 0
+ RAID = 01 /* Priority level 5 (BR5) (normal operation) */
+
+ => 0x0000 0001
+
+
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+/* UPMA (User Programmable Machine A) */
+/* */
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+
+/*### Chap. 16.6.4.1 */
+/*### Offset = 0x0000 017c */
+
+ T0 = CFFF CC24 /* Single Read */
+ T1 = 0FFF CC04
+ T2 = 0CAF CC04
+ T3 = 03AF CC08
+ T4 = 3FBF CC27 /* last */
+ T5 = FFFF CC25
+ T6 = FFFF CC25
+ T7 = FFFF CC25
+ T8 = CFFF CC24 /* Burst Read */
+ T9 = 0FFF CC04
+ T10 = 0CAF CC84
+ T11 = 03AF CC88
+ T12 = 3FBF CC27 /* last */
+ T13 = FFFF CC25
+ T14 = FFFF CC25
+ T15 = FFFF CC25
+ T16 = FFFF CC25
+ T17 = FFFF CC25
+ T18 = FFFF CC25
+ T19 = FFFF CC25
+ T20 = FFFF CC25
+ T21 = FFFF CC25
+ T22 = FFFF CC25
+ T23 = FFFF CC25
+ T24 = CFFF CC24 /* Single Write */
+ T25 = 0FFF CC04
+ T26 = 0CFF CC04
+ T27 = 03FF CC00
+ T28 = 3FFF CC27 /* last */
+ T29 = FFFF CC25
+ T30 = FFFF CC25
+ T31 = FFFF CC25
+ T32 = CFFF CC24 /* Burst Write */
+ T33 = 0FFF CC04
+ T34 = 0CFF CC80
+ T35 = 03FF CC8C
+ T36 = 0CFF CC00
+ T37 = 33FF CC27 /* last */
+ T38 = FFFF CC25
+ T39 = FFFF CC25
+ T40 = FFFF CC25
+ T41 = FFFF CC25
+ T42 = FFFF CC25
+ T43 = FFFF CC25
+ T44 = FFFF CC25
+ T45 = FFFF CC25
+ T46 = FFFF CC25
+ T47 = FFFF CC25
+ T48 = C0FF CC24 /* Refresh */
+ T49 = 03FF CC24
+ T50 = 0FFF CC24
+ T51 = 0FFF CC24
+ T52 = 3FFF CC27 /* last */
+ T53 = FFFF CC25
+ T54 = FFFF CC25
+ T55 = FFFF CC25
+ T56 = FFFF CC25
+ T57 = FFFF CC25
+ T58 = FFFF CC25
+ T59 = FFFF CC25
+ T60 = FFFF CC25 /* Exception */
+ T61 = FFFF CC25
+ T62 = FFFF CC25
+ T63 = FFFF CC25
+
+
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+/* UPMB */
+/* */
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+---------------------------------------------------------------------
+
+/*### Chap. 16.6.4.1 */
+
+
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+/* MEMC */
+/* */
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+---------------------------------------------------------------------
+
+/*### BR0 & OR0 */
+/*### Base Registers & Option Registers */
+/*### Chap. 16.4.1 & 16.4.2 */
+/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */
+/*### Flash memory */
+
+ BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */
+ AT = 000
+ PS = 00
+ PARE = 0
+ WP = 0
+ MS = 0 /* GPCM */
+ V = 1 /* Valid */
+
+ => 0xFE00 0001
+
+ AM = 1111 1110 0000 0000 0 /* 32MBytes */
+ ATM = 000
+ CSNT/SAM = 0
+ ACS/G5LA,G5LS = 00
+ BIH = 1 /* Burst inhibited */
+ SCY = 0100 /* cycle length = 4 */
+ SETA = 0
+ TRLX = 0
+ EHTR = 0
+
+ => 0xFE00 0140
+
+/*### BR1 & OR1 */
+/*### Base Registers & Option Registers */
+/*### Chap. 16.4.1 & 16.4.2 */
+/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */
+/*### SDRAM */
+
+ BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */
+ AT = 000
+ PS = 00
+ PARE = 0
+ WP = 0
+ MS = 1 /* UPMA */
+ V = 1 /* Valid */
+
+ => 0x0000 0081
+
+ AM = 1111 1110 0000 0000 /* 32MBytes */
+ ATM = 000
+ CSNT/SAM = 1
+ ACS/G5LA,G5LS = 11
+ BIH = 0
+ SCY = 0000 /* cycle length = 0 */
+ SETA = 0
+ TRLX = 0
+ EHTR = 0
+
+ => 0xFE00 0E00
+
+/*### BR2 & OR2 */
+/*### Base Registers & Option Registers */
+/*### Chap. 16.4.1 & 16.4.2 */
+/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */
+
+ BR2 & OR2 = 0x0000 0000 /* Not used */
+
+/*### BR3 & OR3 */
+/*### Base Registers & Option Registers */
+/*### Chap. 16.4.1 & 16.4.2 */
+/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */
+/*### BCSR */
+
+ BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */
+ AT = 000
+ PS = 00
+ PARE = 0
+ WP = 0
+ MS = 0 /* GPCM */
+ V = 1 /* Valid */
+
+ => 0xFA40 0001
+
+ AM = 1111 1111 0111 1111 1 /* (?) */
+ ATM = 000
+ CSNT/SAM = 1
+ ACS/G5LA,G5LS = 00
+ BIH = 1 /* Burst inhibited */
+ SCY = 0001 /* cycle length = 1 */
+ SETA = 0
+ TRLX = 0
+
+ => 0xFF7F 8910
+
+/*### BR4 & OR4 */
+/*### Base Registers & Option Registers */
+/*### Chap. 16.4.1 & 16.4.2 */
+/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */
+/*### NVRAM & SRAM */
+
+ BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */
+ AT = 000
+ PS = 01
+ PARE = 0
+ WP = 0
+ MS = 0 /* GPCM */
+ V = 1 /* Valid */
+
+ => 0xFA00 0401
+
+ AM = 1111 1111 1111 1000 0 /* 8MByte */
+ ATM = 000
+ CSNT/SAM = 1
+ ACS/G5LA,G5LS = 00
+ BIH = 1 /* Burst inhibited */
+ SCY = 0111 /* cycle length = 7 */
+ SETA = 0
+ TRLX = 0
+
+ => 0xFFF8 0970
+
+/*### BR5 & OR5 */
+/*### Base Registers & Option Registers */
+/*### Chap. 16.4.1 & 16.4.2 */
+/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */
+
+ BR5 & OR5 = 0x0000 0000 /* Not used */
+
+/*### BR6 & OR6 */
+/*### Base Registers & Option Registers */
+/*### Chap. 16.4.1 & 16.4.2 */
+/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */
+
+ BR6 & OR6 = 0x0000 0000 /* Not used */
+
+/*### BR7 & OR7 */
+/*### Base Registers & Option Registers */
+/*### Chap. 16.4.1 & 16.4.2 */
+/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */
+
+ BR7 & OR7 = 0x0000 0000 /* Not used */
+
+/*### MAR */
+/*### Memory Address Register */
+/*### Chap. 16.4.7 */
+/*### Offset : 0x0000 0164 */
+
+ MA = External memory address
+
+/*### MCR */
+/*### Memory Command Register */
+/*### Chap. 16.4.5 */
+/*### Offset : 0x0000 0168 */
+
+ OP = xx /* Command op code */
+ UM = 1 /* Select UPMA */
+ MB = 001 /* Select CS1 */
+ MCLF = xxxx /* Loop times */
+ MAD = xx xxxx /* Memory array index */
+
+/*### MAMR */
+/*### Machine A Mode Register */
+/*### Chap. 16.4.4 */
+/*### Offset : 0x0000 0170 */
+
+ PTA = 0101 1000
+ PTAE = 1 /* Periodic timer A enabled */
+ AMA = 010
+ DSA = 00
+ G0CLA = 000
+ GPLA4DIS = 1
+ RLFA = 0100
+ WLFA = 0011
+ TLFA = 0000
+
+ => 0x58A0 1430
+
+/*### MBMR */
+/*### Machine B Mode Register */
+/*### Chap. 16.4.4 */
+/*### Offset : 0x0000 0174 */
+
+ PTA = 0100 1110
+ PTAE = 0 /* Periodic timer B disabled */
+ AMA = 000
+ DSA = 00
+ G0CLA = 000
+ GPLA4DIS = 1
+ RLFA = 0000
+ WLFA = 0000
+ TLFA = 0000
+
+ => 0x4E00 1000
+
+/*### MSTAT */
+/*### Memory Status Register */
+/*### Chap. 16.4.3 */
+/*### Offset : 0x0000 0178 */
+
+ PER0~PER7 = Parity error
+ WPER = Write protection error
+
+ => 0x0000
+
+/*### MPTPR */
+/*### Memory Periodic Timer Prescaler Register */
+/*### Chap. 16.4.8 */
+/*### Offset : 0x0000 017A */
+
+ PTP = 0000 1000 /* Divide by 8 */
+
+ => 0x0800
+
+/*### MDR */
+/*### Memory Data Register */
+/*### Chap. 16.4.6 */
+/*### Offset : 0x0000 017C */
+
+ MD = Memory data contains the RAM array word
+
+
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+/* TIMERS */
+/* */
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+---------------------------------------------------------------------
+
+/*### TBREFx */
+/*### Timebase Reference Registers */
+/*### Chap. 11.9.2 */
+/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */
+/*### (Locked) */
+
+ TBREFF0 = 0xFFFF FFFF
+ TBREFF1 = 0xFFFF FFFF
+
+---------------------------------------------------------------------
+
+/*### TBSCR */
+/*### Timebase Status and Control Registers */
+/*### Chap. 11.9.3 */
+/*### Offset : 0x0000 0200 */
+/*### (Locked) */
+
+ TBIRQ = 00000000
+ REF0 = 0
+ REF1 = 0
+ REFE0 = 0 /* Reference interrupt disable */
+ REFE1 = 0
+ TBF = 1
+ TBE = 1 /* Timebase enable */
+
+ => 0x0003
+
+---------------------------------------------------------------------
+
+/*### RTCSC */
+/*### Real-Time Clock Status and Control Registers */
+/*### Chap. 11.10.1 */
+/*### Offset : 0x0000 0220 */
+/*### (Locked) */
+
+ RTCIRQ = 00000000
+ SEC = 1
+ ALR = 0
+ 38K = 0 /* PITRTCLK is driven by 32.768KHz */
+ SIE = 0
+ ALE = 0
+ RTF = 0
+ RTE = 1 /* Real-Time clock enabled */
+
+ => 0x0081
+
+---------------------------------------------------------------------
+
+/*### RTC */
+/*### Real-Time Clock Registers */
+/*### Chap. 11.10.2 */
+/*### Offset : 0x0000 0224 */
+/*### (Locked) */
+
+ RTC = Real time clock measured in second
+
+---------------------------------------------------------------------
+
+/*### RTCAL */
+/*### Real-Time Clock Alarm Registers */
+/*### Chap. 11.10.3 */
+/*### Offset : 0x0000 022C */
+/*### (Locked) */
+
+ ALARM = 0xFFFF FFFF
+
+---------------------------------------------------------------------
+
+/*### RTSEC */
+/*### Real-Time Clock Alarm Second Registers */
+/*### Chap. 11.10.4 */
+/*### Offset : 0x0000 0228 */
+/*### (Locked) */
+
+ COUNTER = Counter bits(fraction of a second)
+
+---------------------------------------------------------------------
+
+/*### PISCR */
+/*### Periodic Interrupt Status and Control Register */
+/*### Chap. 11.11.1 */
+/*### Offset : 0x0000 0240 */
+/*### (Locked) */
+
+ PIRQ = 0
+ PS = 0 /* Write 1 to clear */
+ PIE = 0
+ PITF = 1
+ PTE = 0 /* PIT disabled */
+
+---------------------------------------------------------------------
+
+/*### PITC */
+/*### PIT Count Register */
+/*### Chap. 11.11.2 */
+/*### Offset : 0x0000 0244 */
+/*### (Locked) */
+
+ PITC = PIT count
+
+---------------------------------------------------------------------
+
+/*### PITR */
+/*### PIT Register */
+/*### Chap. 11.11.3 */
+/*### Offset : 0x0000 0248 */
+/*### (Locked) */
+
+ PIT = PIT count /* Read only */
+
+
+
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+/* CLOCKS */
+/* */
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+---------------------------------------------------------------------
+
+
+---------------------------------------------------------------------
+
+/*### SCCR */
+/*### System Clock and Reset Control Register */
+/*### Chap. 15.6.1 */
+/*### Offset : 0x0000 0280 */
+/*### (Locked) */
+
+ COM = 11 /* Clock output disabled */
+ TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */
+ RTDIV = 0 /* The clock is divided by 4 */
+ RTSEL = 0 /* OSCM(Crystal oscillator) is selected */
+ CRQEN = 0
+ PRQEN = 0
+ EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */
+ DFSYNC = 00 /* Divided by 1 (normal operation) */
+ DFBRG = 00 /* Divided by 1 (normal operation) */
+ DFNL = 000
+ DFNH = 000
+
+ => 0x6200 0000
+
+---------------------------------------------------------------------
+
+/*### PLPRCR */
+/*### PLL, Low-Power, and Reset Control Register */
+/*### Chap. 15.6.2 */
+/*### Offset : 0x0000 0284 */
+/*### (Locked) */
+
+ MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */
+ SPLSS = 0
+ TEXPS = 0
+ TMIST = 0
+ CSRC = 0 /* The general system clock is generated by the DFNH field */
+ LPM = 00 /* Normal high/normal low mode */
+ CSR = 0
+ LOLRE = 0
+ FIOPD = 0
+
+ => 0x0050 0000
+
+---------------------------------------------------------------------
+
+/*### RSR */
+/*### Reset Status Register */
+/*### Chap. 12.2 */
+/*### Offset : 0x0000 0288 */
+/*### (Locked) */
+
+ EHRS = External hard reset
+ ESRS = External soft reset
+ LLRS = Loss-of-lock reset
+ SWRS = Software watchdog reset
+ CSRS = Check stop reset
+ DBHRS = Debug port hard reset
+ DBSRS = Debug port soft reset
+ JTRS = JTAG reset
+
+
+
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+/* DMA */
+/* */
+/*------------------------------------------------------------------- */
+/*------------------------------------------------------------------- */
+---------------------------------------------------------------------
+
+/*### SDSR */
+/*### SDMA Status Register */
+/*### Chap. 20.2.2 */
+/*### Offset : 0x0000 0908 */
+
+ SBER = 0 /* SDMA channel bus error */
+ DSP2 = 0 /* DSP chain2 (Tx) interrupt */
+ DSP1 = 0 /* DSP chain1 (Rx) interrupt */
+
+ => 0x00
+
+/*### SDMR */
+/*### SDMA Mask Register */
+/*### Chap. 20.2.3 */
+/*### Offset : 0x0000 090C */
+
+ SBER = 0
+ DSP2 = 0
+ DSP1 = 0 /* All interrupts are masked */
+
+ => 0x00
+
+/*### SDAR */
+/*### SDMA Address Register */
+/*### Chap. 20.2.4 */
+/*### Offset : 0x0000 0904 */
+
+ AR = 0xxxxx xxxx /* current system address */
+
+ => 0xFA20 23AC
+
+/*### IDSRx */
+/*### IDMA Status Register */
+/*### Chap. 20.3.3.2 */
+/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */
+
+ AD = 0
+ DONE = 0
+ OB = 0
+
+ => 0x00
+
+/*### IDMRx */
+/*### IDMA Mask Register */
+/*### Chap. 20.3.3.3 */
+/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */
+
+ AD = 0
+ DONE = 0
+ OB = 0
+
diff --git a/doc/README.Sandpoint8240 b/doc/README.Sandpoint8240
new file mode 100644
index 0000000000..5cb79b32d6
--- /dev/null
+++ b/doc/README.Sandpoint8240
@@ -0,0 +1,397 @@
+The port was tested on a Sandpoint 8240 X3 board, with U-Boot
+installed in the flash memory of the CPU card. Please use the
+following DIP switch settings:
+
+Motherboard:
+
+SW1.1: on SW1.2: on SW1.3: on SW1.4: on
+SW1.5: on SW1.6: on SW1.7: on SW1.8: on
+
+SW2.1: on SW2.2: on SW2.3: on SW2.4: on
+SW2.5: on SW2.6: on SW2.7: on SW2.8: on
+
+
+CPU Card:
+
+SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on
+SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF
+
+SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF
+SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on
+
+
+
+The followind detailed description of installation and initial steps
+with U-Boot and QNX was provided by Jim Sandoz <sandoz@lucent.com>:
+
+
+Directions for installing U-Boot on Sandpoint+Unity8240
+using the Abatron BDI2000 BDM/JTAG debugger ...
+
+Background and Reference info:
+http://u-boot.sourceforge.net/
+http://www.abatron.ch/
+http://www.abatron.ch/BDI/bdihw.html
+http://www.abatron.ch/DataSheets/BDI2000.pdf
+http://www.abatron.ch/Manuals/ManGdbCOP-2000C.pdf
+http://e-www.motorola.com/collateral/SPX3UM.pdf
+http://e-www.motorola.com/collateral/UNITYX4CONFIG.pdf
+
+
+
+Connection Diagram:
+ ===========
+ === ===== |----- |
+| | <---------------> | | | | |
+|PC | rs232 | BDI |=============[] | |
+| | |2000 | BDM probe | | |
+| | <---------------> | | |----- |
+ === ethernet ===== | |
+ | |
+ ===========
+ Sandpoint X3 with
+ Unity 8240 proc
+
+
+PART 1)
+ DIP Switch Settings:
+
+Sandpoint X3 8240 processor board DIP switch settings, with
+U-Boot to be installed in the flash memory of the CPU card:
+
+Motorola Sandpoint X3 Motherboard:
+SW1.1: on SW1.2: on SW1.3: on SW1.4: on
+SW1.5: on SW1.6: on SW1.7: on SW1.8: on
+SW2.1: on SW2.2: on SW2.3: on SW2.4: on
+SW2.5: on SW2.6: on SW2.7: on SW2.8: on
+
+Motorola Unity 8240 CPU Card:
+SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on
+SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF
+SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF
+SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on
+
+
+PART 2)
+ Connect the BDI2000 Cable to the Sandpoint/Unity 8240:
+
+BDM Pin 1 on the Unity 8240 processor board is towards the
+PCI PMC connectors, or away from the socketed SDRAM, i.e.:
+
+ ====================
+ | ---------------- |
+ | | SDRAM | |
+ | | | |
+ | ---------------- |
+ | |~| |
+ | |B| ++++++ |
+ | |D| + uP + |
+ | |M| +8240+ |
+ | ~ 1 ++++++ |
+ | |
+ | |
+ | |
+ | PMC conn ====== |
+ | ===== ====== |
+ | |
+ ====================
+
+
+PART 3)
+ Setting up the BDI2000, and preparing for TCP/IP network comms:
+
+Connect the BDI2000 to the PC using the supplied serial cable.
+Download the BDI2000 software and install it using setup.exe.
+
+[Note: of course you can also use the Linux command line tool
+"bdisetup" to configure your BDI2000 - the sources are included on
+the floppy disk that comes with your BDI2000. Just in case you don't
+have any Windows PC's - like me :-) -- wd ]
+
+Power up the BDI2000; then follow directions to assign the IP
+address and related network information. Note that U-Boot
+will be loaded to the Sandpoint via tftp. You need to either
+use the Abatron-provided tftp application or provide a tftp
+server (e.g. Linux/Solaris/*BSD) somewhere on your network.
+Once the IP address etc are assigned via the RS232 port,
+further communication with the BDI2000 will happen via the
+ethernet connection.
+
+PART 4)
+ Making a TCP/IP network connection to the Abatron BDI2000:
+
+Telnet to the Abatron BDI2000. Assuming that all of the
+networking info was loaded via RS232 correctly, you will see
+the following (scrolling):
+
+- TARGET: waiting for target Vcc
+- TARGET: waiting for target Vcc
+
+
+PART 5)
+ Power up the target Sandpoint:
+If the BDM connections are correct, the following will now appear:
+
+- TARGET: waiting for target Vcc
+- TARGET: waiting for target Vcc
+- TARGET: processing power-up delay
+- TARGET: processing user reset request
+- BDI asserts HRESET
+- Reset JTAG controller passed
+- Bypass check: 0x55 => 0xAA
+- Bypass check: 0x55 => 0xAA
+- JTAG exists check passed
+- Target PVR is 0x00810101
+- COP status is 0x01
+- Check running state passed
+- BDI scans COP freeze command
+- BDI removes HRESET
+- COP status is 0x05
+- Check stopped state passed
+- Check LSRL length passed
+- BDI sets breakpoint at 0xFFF00100
+- BDI resumes program execution
+- Waiting for target stop passed
+- TARGET: Target PVR is 0x00810101
+- TARGET: reseting target passed
+- TARGET: processing target startup ....
+- TARGET: processing target startup passed
+BDI>
+
+
+PART 6)
+ Erase the current contents of the flash memory:
+
+BDI>era 0xFFF00000
+ Erasing flash at 0xfff00000
+ Erasing flash passed
+BDI>era 0xFFF04000
+ Erasing flash at 0xfff04000
+ Erasing flash passed
+BDI>era 0xFFF06000
+ Erasing flash at 0xfff06000
+ Erasing flash passed
+BDI>era 0xFFF08000
+ Erasing flash at 0xfff08000
+ Erasing flash passed
+BDI>era 0xFFF10000
+ Erasing flash at 0xfff10000
+ Erasing flash passed
+BDI>era 0xFFF20000
+ Erasing flash at 0xfff20000
+ Erasing flash passed
+
+
+PART 7)
+ Program the flash memory with the U-Boot image:
+
+BDI>prog 0xFFF00000 u-boot.bin bin
+ Programming u-boot.bin , please wait ....
+ Programming flash passed
+
+
+PART 8)
+ Connect PC to Sandpoint:
+Using a crossover serial cable, attach the PC serial port to the
+Sandpoint's COM1. Set communications parameters to 8N1 / 9600 baud.
+
+
+PART 9)
+ Reset the Unity and begin U-Boot execution:
+
+BDI>reset
+- TARGET: processing user reset request
+- TARGET: Target PVR is 0x00810101
+- TARGET: reseting target passed
+- TARGET: processing target init list ....
+- TARGET: processing target init list passed
+
+BDI>go
+
+Now see output from U-Boot running, sent via serial port:
+
+U-Boot 1.1.4 (Jan 23 2002 - 18:29:19)
+
+CPU: MPC8240 Revision 1.1 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: Sandpoint 8240 Unity
+DRAM: 64 MB
+FLASH: 2 MB
+PCI: scanning bus0 ...
+ bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE
+ 00 00 00 1057 0003 060000 13 00000008 00000000 01 00
+ 00 0b 00 10ad 0565 060100 10 00000000 00000000 00 00
+ 00 0f 00 8086 1229 020000 08 80000000 80000001 01 00
+In: serial
+Out: serial
+Err: serial
+=>
+
+
+PART 10)
+ Set and save any required environmental variables, examples of some:
+
+=> setenv ethaddr 00:03:47:97:D0:79
+=> setenv bootfile your_qnx_image_here
+=> setenv hostname sandpointX
+=> setenv netmask 255.255.255.0
+=> setenv ipaddr 192.168.0.11
+=> setenv serverip 192.168.0.10
+=> setenv gatewayip=192.168.0.1
+=> saveenv
+Saving Enviroment to Flash...
+Un-Protected 1 sectors
+Erasing Flash...
+ done
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+=>
+
+**** Example environment: ****
+
+=> printenv
+baudrate=9600
+bootfile=telemetry
+hostname=sp1
+ethaddr=00:03:47:97:E4:6B
+load=tftp 100000 u-boot.bin
+update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 $(filesize);saveenv
+filesize=1f304
+gatewayip=145.17.228.1
+netmask=255.255.255.0
+ipaddr=145.17.228.42
+serverip=145.17.242.46
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 332/8188 bytes
+=>
+
+here's some text useful stuff for cut-n-paste:
+setenv hostname sandpoint1
+setenv netmask 255.255.255.0
+setenv ipaddr 145.17.228.81
+setenv serverip 145.17.242.46
+setenv gatewayip 145.17.228.1
+saveenv
+
+PART 11)
+ Test U-Boot by tftp'ing new U-Boot, overwriting current:
+
+=> protect off all
+Un-Protect Flash Bank # 1
+=> tftp 100000 u-boot.bin
+eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
+ARP broadcast 1
+TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
+ gateway 145.17.228.1
+Filename 'u-boot.bin'.
+Load address: 0x100000
+Loading: #########################
+done
+Bytes transferred = 127628 (1f28c hex)
+=> era all
+Erase Flash Bank # 1
+ done
+Erase Flash Bank # 2 - missing
+=> cp.b 0x100000 FFF00000 1f28c
+Copy to Flash... done
+=> saveenv
+Saving Enviroment to Flash...
+Un-Protected 1 sectors
+Erasing Flash...
+ done
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+=> reset
+
+You can put these commands into some environment variables;
+
+=> setenv load tftp 100000 u-boot.bin
+=> setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \$(filesize)\;saveenv
+=> saveenv
+
+Then you just have to type "run load" then "run update"
+
+=> run load
+eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
+ARP broadcast 1
+TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
+ gateway 145.17.228.1
+Filename 'u-boot.bin'.
+Load address: 0x100000
+Loading: #########################
+done
+Bytes transferred = 127748 (1f304 hex)
+=> run update
+Un-Protect Flash Bank # 1
+Un-Protect Flash Bank # 2
+Erase Flash from 0xfff00000 to 0xfff3ffff
+ done
+Erased 7 sectors
+Copy to Flash... done
+Saving Enviroment to Flash...
+Un-Protected 1 sectors
+Erasing Flash...
+ done
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+=>
+
+
+PART 12)
+ Load OS image (ELF format) via U-Boot using tftp
+
+
+=> tftp 800000 sandpoint-simple.elf
+eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
+ARP broadcast 1
+TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
+ gateway 145.17.228.1
+Filename 'sandpoint-simple.elf'.
+Load address: 0x800000
+Loading: #################################################################
+ #################################################################
+ #################################################################
+ ########################
+done
+Bytes transferred = 1120284 (11181c hex)
+==>
+
+PART 13)
+ Begin OS image execution: (note that unless you have the
+serial parameters of your OS image set to 9600 (i.e. same as
+the U-Boot binary) you will get garbage here until you change
+the serial communications speed.
+
+=> bootelf 800000
+Loading @ 0x001f0100 (1120028 bytes)
+## Starting application at 0x001f1d28 ...
+Replace init_hwinfo() with a board specific version
+
+Loading QNX6....
+
+Header size=0x0000009c, Total Size=0x000005c0, #Cpu=1, Type=1
+<...loader and kernel messages snipped...>
+
+Welcome to Neutrino on the Sandpoint
+#
+
+
+other information:
+
+CVS Retrieval Notes:
+
+U-Boot's SourceForge CVS repository can be checked out
+through anonymous (pserver) CVS with the following
+instruction set. The module you wish to check out must
+be specified as the modulename. When prompted for a
+password for anonymous, simply press the Enter key.
+
+cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
+
+cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot
+
generated by cgit (git 2.34.1) at 2024-12-23 17:16:07 +0000