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-rw-r--r--drivers/axi/Kconfig32
-rw-r--r--drivers/axi/Makefile12
-rw-r--r--drivers/axi/axi-emul-uclass.c85
-rw-r--r--drivers/axi/axi-uclass.c39
-rw-r--r--drivers/axi/axi_sandbox.c77
-rw-r--r--drivers/axi/ihs_axi.c293
-rw-r--r--drivers/axi/sandbox_store.c123
7 files changed, 661 insertions, 0 deletions
diff --git a/drivers/axi/Kconfig b/drivers/axi/Kconfig
new file mode 100644
index 0000000000..f81d843f89
--- /dev/null
+++ b/drivers/axi/Kconfig
@@ -0,0 +1,32 @@
+menuconfig AXI
+ bool "AXI bus drivers"
+ help
+ Support AXI (Advanced eXtensible Interface) busses, a on-chip
+ interconnect specification for managing functional blocks in SoC
+ designs, which is also often used in designs involving FPGAs (e.g.
+ communication with IP cores in Xilinx FPGAs).
+
+ These types of busses expose a virtual address space that can be
+ accessed using different address widths (8, 16, and 32 are supported
+ for now).
+
+ Other similar bus architectures may be compatible as well.
+
+if AXI
+
+config IHS_AXI
+ bool "Enable IHS AXI driver"
+ depends on DM
+ help
+ Support for gdsys Integrated Hardware Systems Advanced eXtensible
+ Interface (IHS AXI) bus on a gdsys IHS FPGA used to communicate with
+ IP cores in the FPGA (e.g. video transmitter cores).
+
+config AXI_SANDBOX
+ bool "Enable AXI sandbox driver"
+ depends on DM
+ help
+ Support AXI (Advanced eXtensible Interface) emulation for the sandbox
+ environment.
+
+endif
diff --git a/drivers/axi/Makefile b/drivers/axi/Makefile
new file mode 100644
index 0000000000..66b6c5a28f
--- /dev/null
+++ b/drivers/axi/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2017
+# Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_AXI) += axi-uclass.o
+obj-$(CONFIG_IHS_AXI) += ihs_axi.o
+obj-$(CONFIG_SANDBOX) += axi-emul-uclass.o
+obj-$(CONFIG_SANDBOX) += sandbox_store.o
+obj-$(CONFIG_AXI_SANDBOX) += axi_sandbox.o
diff --git a/drivers/axi/axi-emul-uclass.c b/drivers/axi/axi-emul-uclass.c
new file mode 100644
index 0000000000..06c42006ee
--- /dev/null
+++ b/drivers/axi/axi-emul-uclass.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <axi.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <asm/axi.h>
+
+int axi_sandbox_get_emul(struct udevice *bus, ulong address,
+ enum axi_size_t size, struct udevice **emulp)
+{
+ struct udevice *dev;
+ u32 reg[2];
+ uint offset;
+
+ switch (size) {
+ case AXI_SIZE_8:
+ offset = 1;
+ break;
+ case AXI_SIZE_16:
+ offset = 2;
+ break;
+ case AXI_SIZE_32:
+ offset = 4;
+ break;
+ default:
+ debug("%s: Unknown AXI transfer size '%d'", bus->name, size);
+ offset = 0;
+ }
+
+ /*
+ * Note: device_find_* don't activate the devices; they're activated
+ * as-needed below.
+ */
+ for (device_find_first_child(bus, &dev);
+ dev;
+ device_find_next_child(&dev)) {
+ int ret;
+
+ ret = dev_read_u32_array(dev, "reg", reg, ARRAY_SIZE(reg));
+ if (ret) {
+ debug("%s: Could not read 'reg' property of %s\n",
+ bus->name, dev->name);
+ continue;
+ }
+
+ /*
+ * Does the transfer's address fall into this device's address
+ * space?
+ */
+ if (address >= reg[0] && address <= reg[0] + reg[1] - offset) {
+ /* If yes, activate it... */
+ if (device_probe(dev)) {
+ debug("%s: Could not activate %s\n",
+ bus->name, dev->name);
+ return -ENODEV;
+ }
+
+ /* ...and return it */
+ *emulp = dev;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
+int axi_get_store(struct udevice *dev, u8 **storep)
+{
+ struct axi_emul_ops *ops = axi_emul_get_ops(dev);
+
+ if (!ops->get_store)
+ return -ENOSYS;
+
+ return ops->get_store(dev, storep);
+}
+
+UCLASS_DRIVER(axi_emul) = {
+ .id = UCLASS_AXI_EMUL,
+ .name = "axi_emul",
+};
diff --git a/drivers/axi/axi-uclass.c b/drivers/axi/axi-uclass.c
new file mode 100644
index 0000000000..af8acd9f88
--- /dev/null
+++ b/drivers/axi/axi-uclass.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2017
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <axi.h>
+
+int axi_read(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct axi_ops *ops = axi_get_ops(dev);
+
+ if (!ops->read)
+ return -ENOSYS;
+
+ return ops->read(dev, address, data, size);
+}
+
+int axi_write(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct axi_ops *ops = axi_get_ops(dev);
+
+ if (!ops->write)
+ return -ENOSYS;
+
+ return ops->write(dev, address, data, size);
+}
+
+UCLASS_DRIVER(axi) = {
+ .id = UCLASS_AXI,
+ .name = "axi",
+ .post_bind = dm_scan_fdt_dev,
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+};
+
diff --git a/drivers/axi/axi_sandbox.c b/drivers/axi/axi_sandbox.c
new file mode 100644
index 0000000000..b91c91f6b3
--- /dev/null
+++ b/drivers/axi/axi_sandbox.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <axi.h>
+#include <dm.h>
+#include <asm/axi.h>
+
+/*
+ * This driver implements a AXI bus for the sandbox architecture for testing
+ * purposes.
+ *
+ * The bus forwards every access to it to a special AXI emulation device (which
+ * it gets via the axi_emul_get_ops function) that implements a simple
+ * read/write storage.
+ *
+ * The emulator device must still be contained in the device tree in the usual
+ * way, since configuration data for the storage is read from the DT.
+ */
+
+static int axi_sandbox_read(struct udevice *bus, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct axi_emul_ops *ops;
+ struct udevice *emul;
+ int ret;
+
+ /* Get emulator device */
+ ret = axi_sandbox_get_emul(bus, address, size, &emul);
+ if (ret)
+ return ret == -ENODEV ? 0 : ret;
+ /* Forward all reads to the AXI emulator */
+ ops = axi_emul_get_ops(emul);
+ if (!ops || !ops->read)
+ return -ENOSYS;
+
+ return ops->read(emul, address, data, size);
+}
+
+static int axi_sandbox_write(struct udevice *bus, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct axi_emul_ops *ops;
+ struct udevice *emul;
+ int ret;
+
+ /* Get emulator device */
+ ret = axi_sandbox_get_emul(bus, address, size, &emul);
+ if (ret)
+ return ret == -ENODEV ? 0 : ret;
+ /* Forward all writes to the AXI emulator */
+ ops = axi_emul_get_ops(emul);
+ if (!ops || !ops->write)
+ return -ENOSYS;
+
+ return ops->write(emul, address, data, size);
+}
+
+static const struct udevice_id axi_sandbox_ids[] = {
+ { .compatible = "sandbox,axi" },
+ { /* sentinel */ }
+};
+
+static const struct axi_ops axi_sandbox_ops = {
+ .read = axi_sandbox_read,
+ .write = axi_sandbox_write,
+};
+
+U_BOOT_DRIVER(axi_sandbox_bus) = {
+ .name = "axi_sandbox_bus",
+ .id = UCLASS_AXI,
+ .of_match = axi_sandbox_ids,
+ .ops = &axi_sandbox_ops,
+};
diff --git a/drivers/axi/ihs_axi.c b/drivers/axi/ihs_axi.c
new file mode 100644
index 0000000000..690aa7796b
--- /dev/null
+++ b/drivers/axi/ihs_axi.c
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * (C) Copyright 2017, 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <axi.h>
+#include <dm.h>
+#include <regmap.h>
+
+/**
+ * struct ihs_axi_regs - Structure for the register map of a IHS AXI device
+ * @interrupt_status: Status register to indicate certain events (e.g.
+ * error during transfer, transfer complete, etc.)
+ * @interrupt_enable_control: Register to both control which statuses will be
+ * indicated in the interrupt_status register, and
+ * to change bus settings
+ * @address_lsb: Least significant 16-bit word of the address of a
+ * device to transfer data from/to
+ * @address_msb: Most significant 16-bit word of the address of a
+ * device to transfer data from/to
+ * @write_data_lsb: Least significant 16-bit word of the data to be
+ * written to a device
+ * @write_data_msb: Most significant 16-bit word of the data to be
+ * written to a device
+ * @read_data_lsb: Least significant 16-bit word of the data read
+ * from a device
+ * @read_data_msb: Most significant 16-bit word of the data read
+ * from a device
+ */
+struct ihs_axi_regs {
+ u16 interrupt_status;
+ u16 interrupt_enable_control;
+ u16 address_lsb;
+ u16 address_msb;
+ u16 write_data_lsb;
+ u16 write_data_msb;
+ u16 read_data_lsb;
+ u16 read_data_msb;
+};
+
+/**
+ * ihs_axi_set() - Convenience macro to set values in register map
+ * @map: The register map to write to
+ * @member: The member of the ihs_axi_regs structure to write
+ * @val: The value to write to the register map
+ */
+#define ihs_axi_set(map, member, val) \
+ regmap_set(map, struct ihs_axi_regs, member, val)
+
+/**
+ * ihs_axi_get() - Convenience macro to read values from register map
+ * @map: The register map to read from
+ * @member: The member of the ihs_axi_regs structure to read
+ * @valp: Pointer to a buffer to receive the value read
+ */
+#define ihs_axi_get(map, member, valp) \
+ regmap_get(map, struct ihs_axi_regs, member, valp)
+
+/**
+ * struct ihs_axi_priv - Private data structure of IHS AXI devices
+ * @map: Register map for the IHS AXI device
+ */
+struct ihs_axi_priv {
+ struct regmap *map;
+};
+
+/**
+ * enum status_reg - Description of bits in the interrupt_status register
+ * @STATUS_READ_COMPLETE_EVENT: A read transfer was completed
+ * @STATUS_WRITE_COMPLETE_EVENT: A write transfer was completed
+ * @STATUS_TIMEOUT_EVENT: A timeout has occurred during the transfer
+ * @STATUS_ERROR_EVENT: A error has occurred during the transfer
+ * @STATUS_AXI_INT: A AXI interrupt has occurred
+ * @STATUS_READ_DATA_AVAILABLE: Data is available to be read
+ * @STATUS_BUSY: The bus is busy
+ * @STATUS_INIT_DONE: The bus has finished initializing
+ */
+enum status_reg {
+ STATUS_READ_COMPLETE_EVENT = BIT(15),
+ STATUS_WRITE_COMPLETE_EVENT = BIT(14),
+ STATUS_TIMEOUT_EVENT = BIT(13),
+ STATUS_ERROR_EVENT = BIT(12),
+ STATUS_AXI_INT = BIT(11),
+ STATUS_READ_DATA_AVAILABLE = BIT(7),
+ STATUS_BUSY = BIT(6),
+ STATUS_INIT_DONE = BIT(5),
+};
+
+/**
+ * enum control_reg - Description of bit fields in the interrupt_enable_control
+ * register
+ * @CONTROL_READ_COMPLETE_EVENT_ENABLE: STATUS_READ_COMPLETE_EVENT will be
+ * raised in the interrupt_status register
+ * @CONTROL_WRITE_COMPLETE_EVENT_ENABLE: STATUS_WRITE_COMPLETE_EVENT will be
+ * raised in the interrupt_status register
+ * @CONTROL_TIMEOUT_EVENT_ENABLE: STATUS_TIMEOUT_EVENT will be raised in
+ * the interrupt_status register
+ * @CONTROL_ERROR_EVENT_ENABLE: STATUS_ERROR_EVENT will be raised in
+ * the interrupt_status register
+ * @CONTROL_AXI_INT_ENABLE: STATUS_AXI_INT will be raised in the
+ * interrupt_status register
+ * @CONTROL_CMD_NOP: Configure bus to send a NOP command
+ * for the next transfer
+ * @CONTROL_CMD_WRITE: Configure bus to do a write transfer
+ * @CONTROL_CMD_WRITE_POST_INC: Auto-increment address after write
+ * transfer
+ * @CONTROL_CMD_READ: Configure bus to do a read transfer
+ * @CONTROL_CMD_READ_POST_INC: Auto-increment address after read
+ * transfer
+ */
+enum control_reg {
+ CONTROL_READ_COMPLETE_EVENT_ENABLE = BIT(15),
+ CONTROL_WRITE_COMPLETE_EVENT_ENABLE = BIT(14),
+ CONTROL_TIMEOUT_EVENT_ENABLE = BIT(13),
+ CONTROL_ERROR_EVENT_ENABLE = BIT(12),
+ CONTROL_AXI_INT_ENABLE = BIT(11),
+
+ CONTROL_CMD_NOP = 0x0,
+ CONTROL_CMD_WRITE = 0x8,
+ CONTROL_CMD_WRITE_POST_INC = 0x9,
+ CONTROL_CMD_READ = 0xa,
+ CONTROL_CMD_READ_POST_INC = 0xb,
+};
+
+/**
+ * enum axi_cmd - Determine if transfer is read or write transfer
+ * @AXI_CMD_READ: The transfer should be a read transfer
+ * @AXI_CMD_WRITE: The transfer should be a write transfer
+ */
+enum axi_cmd {
+ AXI_CMD_READ,
+ AXI_CMD_WRITE,
+};
+
+/**
+ * ihs_axi_transfer() - Run transfer on the AXI bus
+ * @bus: The AXI bus device on which to run the transfer on
+ * @address: The address to use in the transfer (i.e. which address to
+ * read/write from/to)
+ * @cmd: Should the transfer be a read or write transfer?
+ *
+ * Return: 0 if OK, -ve on error
+ */
+static int ihs_axi_transfer(struct udevice *bus, ulong address,
+ enum axi_cmd cmd)
+{
+ struct ihs_axi_priv *priv = dev_get_priv(bus);
+ /* Try waiting for events up to 10 times */
+ const uint WAIT_TRIES = 10;
+ u16 wait_mask = STATUS_TIMEOUT_EVENT |
+ STATUS_ERROR_EVENT;
+ u16 complete_flag;
+ u16 status;
+ uint k;
+
+ if (cmd == AXI_CMD_READ) {
+ complete_flag = STATUS_READ_COMPLETE_EVENT;
+ cmd = CONTROL_CMD_READ;
+ } else {
+ complete_flag = STATUS_WRITE_COMPLETE_EVENT;
+ cmd = CONTROL_CMD_WRITE;
+ }
+
+ wait_mask |= complete_flag;
+
+ /* Lower 16 bit */
+ ihs_axi_set(priv->map, address_lsb, address & 0xffff);
+ /* Upper 16 bit */
+ ihs_axi_set(priv->map, address_msb, (address >> 16) & 0xffff);
+
+ ihs_axi_set(priv->map, interrupt_status, wait_mask);
+ ihs_axi_set(priv->map, interrupt_enable_control, cmd);
+
+ for (k = WAIT_TRIES; k > 0; --k) {
+ ihs_axi_get(priv->map, interrupt_status, &status);
+ if (status & wait_mask)
+ break;
+ udelay(1);
+ }
+
+ /*
+ * k == 0 -> Tries ran out with no event we were waiting for actually
+ * occurring.
+ */
+ if (!k)
+ ihs_axi_get(priv->map, interrupt_status, &status);
+
+ if (status & complete_flag)
+ return 0;
+
+ if (status & STATUS_ERROR_EVENT) {
+ debug("%s: Error occurred during transfer\n", bus->name);
+ return -EIO;
+ }
+
+ debug("%s: Transfer timed out\n", bus->name);
+ return -ETIMEDOUT;
+}
+
+/*
+ * API
+ */
+
+static int ihs_axi_read(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct ihs_axi_priv *priv = dev_get_priv(dev);
+ int ret;
+ u16 data_lsb, data_msb;
+ u32 *p = data;
+
+ if (size != AXI_SIZE_32) {
+ debug("%s: transfer size '%d' not supported\n",
+ dev->name, size);
+ return -ENOSYS;
+ }
+
+ ret = ihs_axi_transfer(dev, address, AXI_CMD_READ);
+ if (ret < 0) {
+ debug("%s: Error during AXI transfer (err = %d)\n",
+ dev->name, ret);
+ return ret;
+ }
+
+ ihs_axi_get(priv->map, read_data_lsb, &data_lsb);
+ ihs_axi_get(priv->map, read_data_msb, &data_msb);
+
+ /* Assemble data from two 16-bit words */
+ *p = (data_msb << 16) | data_lsb;
+
+ return 0;
+}
+
+static int ihs_axi_write(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct ihs_axi_priv *priv = dev_get_priv(dev);
+ int ret;
+ u32 *p = data;
+
+ if (size != AXI_SIZE_32) {
+ debug("%s: transfer size '%d' not supported\n",
+ dev->name, size);
+ return -ENOSYS;
+ }
+
+ /* Lower 16 bit */
+ ihs_axi_set(priv->map, write_data_lsb, *p & 0xffff);
+ /* Upper 16 bit */
+ ihs_axi_set(priv->map, write_data_msb, (*p >> 16) & 0xffff);
+
+ ret = ihs_axi_transfer(dev, address, AXI_CMD_WRITE);
+ if (ret < 0) {
+ debug("%s: Error during AXI transfer (err = %d)\n",
+ dev->name, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id ihs_axi_ids[] = {
+ { .compatible = "gdsys,ihs_axi" },
+ { /* sentinel */ }
+};
+
+static const struct axi_ops ihs_axi_ops = {
+ .read = ihs_axi_read,
+ .write = ihs_axi_write,
+};
+
+static int ihs_axi_probe(struct udevice *dev)
+{
+ struct ihs_axi_priv *priv = dev_get_priv(dev);
+
+ regmap_init_mem(dev_ofnode(dev), &priv->map);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(ihs_axi_bus) = {
+ .name = "ihs_axi_bus",
+ .id = UCLASS_AXI,
+ .of_match = ihs_axi_ids,
+ .ops = &ihs_axi_ops,
+ .priv_auto_alloc_size = sizeof(struct ihs_axi_priv),
+ .probe = ihs_axi_probe,
+};
diff --git a/drivers/axi/sandbox_store.c b/drivers/axi/sandbox_store.c
new file mode 100644
index 0000000000..d724f19079
--- /dev/null
+++ b/drivers/axi/sandbox_store.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#include <common.h>
+#include <axi.h>
+#include <dm.h>
+
+/**
+ * struct sandbox_store_priv - Private data structure of a AXI store device
+ * @store: The buffer holding the device's internal memory, which is read from
+ * and written to using the driver's methods
+ */
+struct sandbox_store_priv {
+ u8 *store;
+};
+
+/**
+ * copy_axi_data() - Copy data from source to destination with a given AXI
+ * transfer width
+ * @src: Pointer to the data source from where data will be read
+ * @dst: Pointer to the data destination where data will be written to
+ * @size: Size of the data to be copied given by a axi_size_t enum value
+ *
+ * Return: 0 if OK, -ve on error
+ */
+static int copy_axi_data(void *src, void *dst, enum axi_size_t size)
+{
+ switch (size) {
+ case AXI_SIZE_8:
+ *((u8 *)dst) = *((u8 *)src);
+ return 0;
+ case AXI_SIZE_16:
+ *((u16 *)dst) = be16_to_cpu(*((u16 *)src));
+ return 0;
+ case AXI_SIZE_32:
+ *((u32 *)dst) = be32_to_cpu(*((u32 *)src));
+ return 0;
+ default:
+ debug("%s: Unknown AXI transfer size '%d'\n", __func__, size);
+ return -EINVAL;
+ }
+}
+
+static int sandbox_store_read(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct sandbox_store_priv *priv = dev_get_priv(dev);
+
+ return copy_axi_data(priv->store + address, data, size);
+}
+
+static int sandbox_store_write(struct udevice *dev, ulong address, void *data,
+ enum axi_size_t size)
+{
+ struct sandbox_store_priv *priv = dev_get_priv(dev);
+
+ return copy_axi_data(data, priv->store + address, size);
+}
+
+static int sandbox_store_get_store(struct udevice *dev, u8 **store)
+{
+ struct sandbox_store_priv *priv = dev_get_priv(dev);
+
+ *store = priv->store;
+
+ return 0;
+}
+
+static const struct udevice_id sandbox_store_ids[] = {
+ { .compatible = "sandbox,sandbox_store" },
+ { /* sentinel */ }
+};
+
+static const struct axi_emul_ops sandbox_store_ops = {
+ .read = sandbox_store_read,
+ .write = sandbox_store_write,
+ .get_store = sandbox_store_get_store,
+};
+
+static int sandbox_store_probe(struct udevice *dev)
+{
+ struct sandbox_store_priv *priv = dev_get_priv(dev);
+ u32 reg[2];
+ int ret;
+
+ ret = dev_read_u32_array(dev, "reg", reg, ARRAY_SIZE(reg));
+ if (ret) {
+ debug("%s: Could not read 'reg' property\n", dev->name);
+ return -EINVAL;
+ }
+
+ /*
+ * Allocate the device's internal storage that will be read
+ * from/written to
+ */
+ priv->store = calloc(reg[1], 1);
+ if (!priv->store)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int sandbox_store_remove(struct udevice *dev)
+{
+ struct sandbox_store_priv *priv = dev_get_priv(dev);
+
+ free(priv->store);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(sandbox_axi_store) = {
+ .name = "sandbox_axi_store",
+ .id = UCLASS_AXI_EMUL,
+ .of_match = sandbox_store_ids,
+ .ops = &sandbox_store_ops,
+ .priv_auto_alloc_size = sizeof(struct sandbox_store_priv),
+ .probe = sandbox_store_probe,
+ .remove = sandbox_store_remove,
+};
generated by cgit (git 2.34.1) at 2025-01-08 15:50:01 +0000