diff options
Diffstat (limited to 'drivers/clk/renesas/r8a77970-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a77970-cpg-mssr.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index 28d9459285..fe36b11f7e 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -19,6 +19,41 @@ #include "renesas-cpg-mssr.h" +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A77970_CLK_OSC, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL4, + CLK_PLL1_DIV2, + CLK_PLL1_DIV4, + CLK_PLL0D2, + CLK_PLL0D3, + CLK_PLL0D5, + CLK_PLL1D2, + CLK_PE, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + CLK_RPCSRC, + CLK_SSPSRC, + CLK_RINT, + + /* Module Clocks */ + MOD_CLK_BASE +}; + static const struct cpg_core_clk r8a77970_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -128,6 +163,9 @@ static const struct cpg_mssr_info r8a77970_cpg_mssr_info = { .mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table), .reset_node = "renesas,r8a77970-rst", .extalr_node = "extalr", + .mod_clk_base = MOD_CLK_BASE, + .clk_extal_id = CLK_EXTAL, + .clk_extalr_id = CLK_EXTALR, }; static const struct udevice_id r8a77970_clk_ids[] = { |