diff options
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk-uclass.c | 46 | ||||
| -rw-r--r-- | drivers/clk/clk_fixed_rate.c | 7 | ||||
| -rw-r--r-- | drivers/clk/mediatek/Makefile | 2 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7622.c | 678 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7629.c | 42 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8512.c | 873 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mtk.c | 74 | ||||
| -rw-r--r-- | drivers/clk/mediatek/clk-mtk.h | 26 |
8 files changed, 1717 insertions, 31 deletions
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 9aa8537004..93cb490eb5 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -344,6 +344,34 @@ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) return clk_get_by_index(dev, index, clk); } +int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) +{ + int index; + + debug("%s(node=%p, name=%s, clk=%p)\n", __func__, + ofnode_get_name(node), name, clk); + clk->dev = NULL; + + index = ofnode_stringlist_search(node, "clock-names", name); + if (index < 0) { + debug("fdt_stringlist_search() failed: %d\n", index); + return index; + } + + return clk_get_by_index_nodev(node, index, clk); +} + +int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk) +{ + int ret; + + ret = clk_get_by_name_nodev(node, name, clk); + if (ret == -ENODATA) + return 0; + + return ret; +} + int clk_release_all(struct clk *clk, int count) { int i, ret; @@ -391,7 +419,7 @@ int clk_free(struct clk *clk) const struct clk_ops *ops; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -406,7 +434,7 @@ ulong clk_get_rate(struct clk *clk) const struct clk_ops *ops; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -422,7 +450,7 @@ struct clk *clk_get_parent(struct clk *clk) struct clk *pclk; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return NULL; pdev = dev_get_parent(clk->dev); @@ -439,7 +467,7 @@ long long clk_get_parent_rate(struct clk *clk) struct clk *pclk; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; pclk = clk_get_parent(clk); @@ -462,7 +490,7 @@ ulong clk_set_rate(struct clk *clk, ulong rate) const struct clk_ops *ops; debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -477,7 +505,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) const struct clk_ops *ops; debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -494,7 +522,7 @@ int clk_enable(struct clk *clk) int ret; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -554,7 +582,7 @@ int clk_disable(struct clk *clk) int ret; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -678,7 +706,7 @@ struct clk *devm_clk_get_optional(struct udevice *dev, const char *id) { struct clk *clk = devm_clk_get(dev, id); - if (IS_ERR(clk)) + if (PTR_ERR(clk) == -ENODATA) return NULL; return clk; diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index f51126793e..2c20eddb0b 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -13,8 +13,15 @@ static ulong clk_fixed_rate_get_rate(struct clk *clk) return to_clk_fixed_rate(clk->dev)->fixed_rate; } +/* avoid clk_enable() return -ENOSYS */ +static int dummy_enable(struct clk *clk) +{ + return 0; +} + const struct clk_ops clk_fixed_rate_ops = { .get_rate = clk_fixed_rate_get_rate, + .enable = dummy_enable, }; static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev) diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e92bcd4efe..237fd17f16 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -3,7 +3,9 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o # SoC Drivers +obj-$(CONFIG_MT8512) += clk-mt8512.o obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o +obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c new file mode 100644 index 0000000000..a5b61a190b --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -0,0 +1,678 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT7622 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <asm/arch-mediatek/reset.h> +#include <asm/io.h> +#include <dt-bindings/clock/mt7622-clk.h> + +#include "clk-mtk.h" + +#define MT7622_CLKSQ_STB_CON0 0x20 +#define MT7622_PLL_ISO_CON0 0x2c +#define MT7622_PLL_FMAX (2500UL * MHZ) +#define MT7622_CON0_RST_BAR BIT(24) + +#define MCU_AXI_DIV 0x640 +#define AXI_DIV_MSK GENMASK(4, 0) +#define AXI_DIV_SEL(x) (x) + +#define MCU_BUS_MUX 0x7c0 +#define MCU_BUS_MSK GENMASK(10, 9) +#define MCU_BUS_SEL(x) ((x) << 9) + +/* apmixedsys */ +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ + _pd_shift, _pcw_reg, _pcw_shift) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .rst_bar_mask = MT7622_CON0_RST_BAR, \ + .fmax = MT7622_PLL_FMAX, \ + .flags = _flags, \ + .pcwbits = _pcwbits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, + 21, 0x204, 24, 0x204, 0), + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, + 21, 0x214, 24, 0x214, 0), + PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, + 7, 0x224, 24, 0x224, 14), + PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, + 21, 0x300, 1, 0x304, 0), + PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0, + 21, 0x314, 1, 0x318, 0), + PLL(CLK_APMIXED_AUD1PLL, 0x324, 0x330, 0x1, 0, + 31, 0x324, 1, 0x328, 0), + PLL(CLK_APMIXED_AUD2PLL, 0x334, 0x340, 0x1, 0, + 31, 0x334, 1, 0x338, 0), + PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0, + 21, 0x344, 1, 0x348, 0), + PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0, + 21, 0x358, 1, 0x35c, 0), +}; + +/* topckgen */ +#define FACTOR0(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define FACTOR1(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define FACTOR2(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, 0) + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000), + FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000), + FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000), + FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000), + FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000), + FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000), + FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333), + FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000), + FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000), + FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000), +}; + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4), + FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), + FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125), + FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), + FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), + FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), + FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), + FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), + FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2), + FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4), + FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8), + FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16), + FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12), + FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24), + FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10), + FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20), + FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14), + FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28), + FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112), + FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2), + FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16), + FACTOR1(CLK_TOP_UNIVPLL1_D16, CLK_TOP_UNIVPLL, 1, 32), + FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6), + FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12), + FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24), + FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48), + FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5), + FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10), + FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20), + FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80), + FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7), + FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320), + FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25), + FACTOR0(CLK_TOP_SGMIIPLL, CLK_APMIXED_SGMIPLL, 1, 1), + FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2), + FACTOR0(CLK_TOP_AUD1PLL, CLK_APMIXED_AUD1PLL, 1, 1), + FACTOR0(CLK_TOP_AUD2PLL, CLK_APMIXED_AUD2PLL, 1, 1), + FACTOR1(CLK_TOP_AUD_I2S2_MCK, CLK_TOP_I2S2_MCK_SEL, 1, 2), + FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_UNIVPLL2_D4, 1, 4), + FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), + FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), + FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), +}; + +static const int axi_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL_D7 +}; + +static const int mem_parents[] = { + CLK_XTAL, + CLK_TOP_DMPLL +}; + +static const int ddrphycfg_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D8 +}; + +static const int eth_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + -1, + CLK_TOP_UNIVPLL_D7 +}; + +static const int pwm_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int f10m_ref_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL4_D16 +}; + +static const int nfi_infra_parents[] = { + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_UNIVPLL1_D8, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_SYSPLL1_D4 +}; + +static const int flash_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL_D80_D4, + CLK_TOP_SYSPLL2_D8, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int uart_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int spi0_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D2, + CLK_XTAL, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_XTAL +}; + +static const int spi1_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D2, + CLK_XTAL, + CLK_TOP_SYSPLL4_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_XTAL +}; + +static const int msdc30_0_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D16, + CLK_TOP_UNIV48M +}; + +static const int a1sys_hp_parents[] = { + CLK_XTAL, + CLK_TOP_AUD1PLL, + CLK_TOP_AUD2PLL, + CLK_XTAL +}; + +static const int intdir_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL_D2, + CLK_TOP_SGMIIPLL +}; + +static const int aud_intbus_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_SYSPLL3_D2 +}; + +static const int pmicspi_parents[] = { + CLK_XTAL, + -1, + -1, + -1, + -1, + CLK_TOP_UNIVPLL2_D16 +}; + +static const int atb_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5 +}; + +static const int audio_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_SYSPLL4_D4, + CLK_TOP_UNIVPLL1_D16 +}; + +static const int usb20_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL1_D8, + CLK_XTAL +}; + +static const int aud1_parents[] = { + CLK_XTAL, + CLK_TOP_AUD1PLL +}; + +static const int asm_l_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL_D5, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int apll1_ck_parents[] = { + CLK_TOP_AUD1_SEL, + CLK_TOP_AUD2_SEL +}; + +static const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), + + /* CLK_CFG_1 */ + MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), + MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), + MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), + + /* CLK_CFG_2 */ + MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), + MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), + MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), + + /* CLK_CFG_3 */ + MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15), + MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23), + MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31), + + /* CLK_CFG_4 */ + MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7), + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), + MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), + MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31), + + /* CLK_CFG_5 */ + MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), + MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15, + CLK_DOMAIN_SCPSYS), + MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23), + MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), + + /* CLK_CFG_6 */ + MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), + MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), + MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23), + MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31), + + /* CLK_CFG_7 */ + MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7), + MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15), + MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23), + + /* CLK_AUDDIV_0 */ + MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1), + MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1), + MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1), + MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1), + MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1), + MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1), +}; + +/* infracfg */ +static const struct mtk_gate_regs infra_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +#define GATE_INFRA(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate infra_cgs[] = { + GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0), + GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2), + GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5), + GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16), + GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18), + GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22), +}; + +/* pericfg */ +static const struct mtk_gate_regs peri0_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0x10, + .sta_ofs = 0x18, +}; + +static const struct mtk_gate_regs peri1_cg_regs = { + .set_ofs = 0xC, + .clr_ofs = 0x14, + .sta_ofs = 0x1C, +}; + +#define GATE_PERI0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_PERI1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate peri_cgs[] = { + /* PERI0 */ + GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1), + GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2), + GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3), + GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4), + GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5), + GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6), + GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7), + GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8), + GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9), + GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12), + GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13), + GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14), + GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17), + GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18), + GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19), + GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20), + GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22), + GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23), + GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24), + GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25), + GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26), + GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27), + GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28), + GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29), + GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30), + GATE_PERI1(CLK_PERI_NFIECC_PD, CLK_TOP_AXI_SEL, 31), + + /* PERI1 */ + GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH_SEL, 1), + GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2), +}; + +/* ethsys */ +static const struct mtk_gate_regs eth_cg_regs = { + .sta_ofs = 0x30, +}; + +#define GATE_ETH(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = ð_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate eth_cgs[] = { + GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), + GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), + GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), + GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), + GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9), +}; + +static const struct mtk_gate_regs sgmii_cg_regs = { + .sta_ofs = 0xE4, +}; + +#define GATE_SGMII(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &sgmii_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ +} + +static const struct mtk_gate sgmii_cgs[] = { + GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2), + GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3), + GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4), + GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), +}; + +static const struct mtk_clk_tree mt7622_clk_tree = { + .xtal_rate = 25 * MHZ, + .xtal2_rate = 25 * MHZ, + .fdivs_offs = CLK_TOP_TO_USB3_SYS, + .muxes_offs = CLK_TOP_AXI_SEL, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, +}; + +static int mt7622_mcucfg_probe(struct udevice *dev) +{ + void __iomem *base; + + base = dev_read_addr_ptr(dev); + if (!base) + return -ENOENT; + + clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK, + AXI_DIV_SEL(0x12)); + clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK, + MCU_BUS_SEL(0x1)); + + return 0; +} + +static int mt7622_apmixedsys_probe(struct udevice *dev) +{ + struct mtk_clk_priv *priv = dev_get_priv(dev); + int ret; + + ret = mtk_common_clk_init(dev, &mt7622_clk_tree); + if (ret) + return ret; + + /* reduce clock square disable time */ + // writel(0x501, priv->base + MT7622_CLKSQ_STB_CON0); + writel(0x98940501, priv->base + MT7622_CLKSQ_STB_CON0); + + /* extend pwr/iso control timing to 1us */ + writel(0x80008, priv->base + MT7622_PLL_ISO_CON0); + + return 0; +} + +static int mt7622_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt7622_clk_tree); +} + +static int mt7622_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs); +} + +static int mt7622_pericfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs); +} + +static int mt7622_ethsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs); +} + +static int mt7622_ethsys_bind(struct udevice *dev) +{ + int ret = 0; + +#if CONFIG_IS_ENABLED(RESET_MEDIATEK) + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); + if (ret) + debug("Warning: failed to bind reset controller\n"); +#endif + + return ret; +} + +static int mt7622_sgmiisys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs); +} + +static const struct udevice_id mt7622_apmixed_compat[] = { + { .compatible = "mediatek,mt7622-apmixedsys" }, + { } +}; + +static const struct udevice_id mt7622_topckgen_compat[] = { + { .compatible = "mediatek,mt7622-topckgen" }, + { } +}; + +static const struct udevice_id mt7622_infracfg_compat[] = { + { .compatible = "mediatek,mt7622-infracfg", }, + { } +}; + +static const struct udevice_id mt7622_pericfg_compat[] = { + { .compatible = "mediatek,mt7622-pericfg", }, + { } +}; + +static const struct udevice_id mt7622_ethsys_compat[] = { + { .compatible = "mediatek,mt7622-ethsys", }, + { } +}; + +static const struct udevice_id mt7622_sgmiisys_compat[] = { + { .compatible = "mediatek,mt7622-sgmiisys", }, + { } +}; + +static const struct udevice_id mt7622_mcucfg_compat[] = { + { .compatible = "mediatek,mt7622-mcucfg" }, + { } +}; + +U_BOOT_DRIVER(mtk_mcucfg) = { + .name = "mt7622-mcucfg", + .id = UCLASS_SYSCON, + .of_match = mt7622_mcucfg_compat, + .probe = mt7622_mcucfg_probe, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt7622-clock-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt7622_apmixed_compat, + .probe = mt7622_apmixedsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt7622-clock-topckgen", + .id = UCLASS_CLK, + .of_match = mt7622_topckgen_compat, + .probe = mt7622_topckgen_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt7622-clock-infracfg", + .id = UCLASS_CLK, + .of_match = mt7622_infracfg_compat, + .probe = mt7622_infracfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_pericfg) = { + .name = "mt7622-clock-pericfg", + .id = UCLASS_CLK, + .of_match = mt7622_pericfg_compat, + .probe = mt7622_pericfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_ethsys) = { + .name = "mt7622-clock-ethsys", + .id = UCLASS_CLK, + .of_match = mt7622_ethsys_compat, + .probe = mt7622_ethsys_probe, + .bind = mt7622_ethsys_bind, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; + +U_BOOT_DRIVER(mtk_clk_sgmiisys) = { + .name = "mt7622-clock-sgmiisys", + .id = UCLASS_CLK, + .of_match = mt7622_sgmiisys_compat, + .probe = mt7622_sgmiisys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 30a919f224..858be85d15 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -539,6 +539,29 @@ static const struct mtk_gate sgmii_cgs[] = { GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), }; +static const struct mtk_gate_regs ssusb_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_SSUSB(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &ssusb_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ +} + +static const struct mtk_gate ssusb_cgs[] = { + GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0), + GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1), + GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5), + GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6), + GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_TO_USB3_MCU, 7), + GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_TO_USB3_DMA, 8), +}; + static const struct mtk_clk_tree mt7629_clk_tree = { .xtal_rate = 40 * MHZ, .xtal2_rate = 20 * MHZ, @@ -621,6 +644,11 @@ static int mt7629_sgmiisys_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs); } +static int mt7629_ssusbsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs); +} + static const struct udevice_id mt7629_apmixed_compat[] = { { .compatible = "mediatek,mt7629-apmixedsys" }, { } @@ -651,6 +679,11 @@ static const struct udevice_id mt7629_sgmiisys_compat[] = { { } }; +static const struct udevice_id mt7629_ssusbsys_compat[] = { + { .compatible = "mediatek,mt7629-ssusbsys" }, + { } +}; + static const struct udevice_id mt7629_mcucfg_compat[] = { { .compatible = "mediatek,mt7629-mcucfg" }, { } @@ -722,3 +755,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = { .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, }; + +U_BOOT_DRIVER(mtk_clk_ssusbsys) = { + .name = "mt7629-clock-ssusbsys", + .id = UCLASS_CLK, + .of_match = mt7629_ssusbsys_compat, + .probe = mt7629_ssusbsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c new file mode 100644 index 0000000000..cb168f146b --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -0,0 +1,873 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT8512 SoC + * + * Copyright (C) 2019 BayLibre, SAS + * Author: Chen Zhong <chen.zhong@mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <dt-bindings/clock/mt8512-clk.h> + +#include "clk-mtk.h" + +#define MT8512_PLL_FMAX (3800UL * MHZ) +#define MT8512_PLL_FMIN (1500UL * MHZ) +#define MT8512_CON0_RST_BAR BIT(23) + +/* apmixedsys */ +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ + _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .rst_bar_mask = MT8512_CON0_RST_BAR, \ + .fmax = MT8512_PLL_FMAX, \ + .fmin = MT8512_PLL_FMIN, \ + .flags = _flags, \ + .pcwbits = _pcwbits, \ + .pcwibits = 8, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcw_chg_reg = _pcw_chg_reg, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, + 0, 22, 0x0310, 24, 0x0310, 0, 0), + PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001, + HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0), + PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001, + HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0), + PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, + 0, 22, 0x0354, 24, 0x0354, 0, 0), + PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, + 0, 32, 0x0320, 24, 0x0324, 0, 0x0320), + PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001, + 0, 32, 0x0364, 24, 0x0368, 0, 0x0364), + PLL(CLK_APMIXED_IPPLL, 0x0374, 0x0380, 0x00000001, + 0, 22, 0x0378, 24, 0x0378, 0, 0), + PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001, + 0, 22, 0x0394, 24, 0x0394, 0, 0), + PLL(CLK_APMIXED_TCONPLL, 0x03A0, 0x03AC, 0x00000001, + 0, 22, 0x03A4, 24, 0x03A4, 0, 0), +}; + +/* topckgen */ +#define FACTOR0(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define FACTOR1(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define FACTOR2(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, 0) + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000), + FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000), +}; + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4), + FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8), + FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16), + FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32), + FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3), + FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6), + FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12), + FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24), + FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20), + FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), + FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14), + FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL2, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16), + FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3), + FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6), + FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12), + FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24), + FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5), + FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10), + FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20), + FACTOR0(CLK_TOP_TCONPLL_D2, CLK_APMIXED_TCONPLL, 1, 2), + FACTOR0(CLK_TOP_TCONPLL_D4, CLK_APMIXED_TCONPLL, 1, 4), + FACTOR0(CLK_TOP_TCONPLL_D8, CLK_APMIXED_TCONPLL, 1, 8), + FACTOR0(CLK_TOP_TCONPLL_D16, CLK_APMIXED_TCONPLL, 1, 16), + FACTOR0(CLK_TOP_TCONPLL_D32, CLK_APMIXED_TCONPLL, 1, 32), + FACTOR0(CLK_TOP_TCONPLL_D64, CLK_APMIXED_TCONPLL, 1, 64), + FACTOR1(CLK_TOP_USB20_192M, CLK_TOP_UNIVPLL, 2, 13), + FACTOR1(CLK_TOP_USB20_192M_D2, CLK_TOP_USB20_192M, 1, 2), + FACTOR1(CLK_TOP_USB20_192M_D4_T, CLK_TOP_USB20_192M, 1, 4), + FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1), + FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2), + FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3), + FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4), + FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8), + FACTOR0(CLK_TOP_APLL1_D16, CLK_APMIXED_APLL1, 1, 16), + FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1), + FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2), + FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3), + FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), + FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8), + FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16), + FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), + FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2), + FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1), + FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), + FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1), + FACTOR0(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2), + FACTOR0(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4), + FACTOR0(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8), + FACTOR0(CLK_TOP_IPPLL, CLK_APMIXED_IPPLL, 1, 1), + FACTOR0(CLK_TOP_IPPLL_D2, CLK_APMIXED_IPPLL, 1, 2), + FACTOR1(CLK_TOP_NFI2X_CK_D2, CLK_TOP_NFI2X_SEL, 1, 2), +}; + +static const int axi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYS_26M_D2, + CLK_TOP_CLK32K +}; + +static const int mem_parents[] = { + CLK_TOP_DSPPLL, + CLK_TOP_IPPLL, + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3 +}; + +static const int uart_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int spi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_SYSPLL4_D2 +}; + +static const int spis_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_SYSPLL4_D2 +}; + +static const int msdc50_0_hc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_SYSPLL2_D2 +}; + +static const int msdc50_0_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int msdc50_2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MSDCPLL, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4 +}; + +static const int audio_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_APLL1_D4, + CLK_TOP_APLL2_D4 +}; + +static const int aud_intbus_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_APLL2_D8, + CLK_TOP_SYS_26M_D2, + CLK_TOP_APLL1_D8, + CLK_TOP_UNIVPLL3_D4 +}; + +static const int hapll1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL1, + CLK_TOP_APLL1_D2, + CLK_TOP_APLL1_D3, + CLK_TOP_APLL1_D4, + CLK_TOP_APLL1_D8, + CLK_TOP_APLL1_D16, + CLK_TOP_SYS_26M_D2 +}; + +static const int hapll2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL2, + CLK_TOP_APLL2_D2, + CLK_TOP_APLL2_D3, + CLK_TOP_APLL2_D4, + CLK_TOP_APLL2_D8, + CLK_TOP_APLL2_D16, + CLK_TOP_SYS_26M_D2 +}; + +static const int asm_l_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL_D5 +}; + +static const int aud_spdif_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D2, + CLK_TOP_DSPPLL +}; + +static const int aud_1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL1 +}; + +static const int aud_2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL2 +}; + +static const int ssusb_sys_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL3_D2 +}; + +static const int spm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D8 +}; + +static const int i2c_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYS_26M_D2, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL2_D8, + CLK_TOP_CLK32K +}; + +static const int pwm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_SYS_26M_D2, + CLK_TOP_CLK32K +}; + +static const int dsp_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_DSPPLL, + CLK_TOP_DSPPLL_D2, + CLK_TOP_DSPPLL_D4, + CLK_TOP_DSPPLL_D8, + CLK_TOP_APLL2_D4, + CLK_TOP_SYS_26M_D2, + CLK_TOP_CLK32K +}; + +static const int nfi2x_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_SYSPLL_D7, + CLK_TOP_SYSPLL_D3, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL_D5 +}; + +static const int spinfi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL3_D2 +}; + +static const int ecc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D3 +}; + +static const int gcpu_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL2_D2 +}; + +static const int gcpu_cpm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4 +}; + +static const int mbist_diag_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYS_26M_D2 +}; + +static const int ip0_nna_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_DSPPLL, + CLK_TOP_DSPPLL_D2, + CLK_TOP_DSPPLL_D4, + CLK_TOP_IPPLL, + CLK_TOP_SYS_26M_D2, + CLK_TOP_IPPLL_D2, + CLK_TOP_MSDCPLL_D2 +}; + +static const int ip2_wfst_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_IPPLL, + CLK_TOP_IPPLL_D2, + CLK_TOP_SYS_26M_D2, + CLK_TOP_MSDCPLL +}; + +static const int sflash_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D16, + CLK_TOP_SYSPLL2_D8, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_TOP_USB20_192M_D2, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int sram_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_DSPPLL, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_APLL1, + CLK_TOP_APLL2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYS_26M_D2 +}; + +static const int mm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D3, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL_D3 +}; + +static const int dpi0_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_TCONPLL_D2, + CLK_TOP_TCONPLL_D4, + CLK_TOP_TCONPLL_D8, + CLK_TOP_TCONPLL_D16, + CLK_TOP_TCONPLL_D32, + CLK_TOP_TCONPLL_D64 +}; + +static const int dbg_atclk_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL_D5 +}; + +static const int occ_104m_parents[] = { + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int occ_68m_parents[] = { + CLK_TOP_SYSPLL1_D8, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int occ_182m_parents[] = { + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_UNIVPLL2_D8 +}; + +static const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents, + 0x040, 0x044, 0x048, 0, 3, 7, + 0x4, 0, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents, + 0x040, 0x044, 0x048, 8, 2, 15, + 0x4, 1, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents, + 0x040, 0x044, 0x048, 16, 1, 23, + 0x4, 2, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents, + 0x040, 0x044, 0x048, 24, 3, 31, + 0x4, 3, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_1 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents, + 0x050, 0x054, 0x058, 0, 3, 7, + 0x4, 4, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, + 0x050, 0x054, 0x058, 8, 2, 15, + 0x4, 5, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, + 0x050, 0x054, 0x058, 16, 2, 23, + 0x4, 6, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, + 0x050, 0x054, 0x058, 24, 3, 31, + 0x4, 7, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_2 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, + 0x060, 0x064, 0x068, 0, 3, 7, + 0x4, 8, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents, + 0x060, 0x064, 0x068, 8, 3, 15, + 0x4, 9, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents, + 0x060, 0x064, 0x068, 16, 2, 23, + 0x4, 10, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, + 0x060, 0x064, 0x068, 24, 3, 31, + 0x4, 11, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_3 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents, + 0x070, 0x074, 0x078, 0, 3, 7, + 0x4, 12, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents, + 0x070, 0x074, 0x078, 8, 3, 15, + 0x4, 13, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents, + 0x070, 0x074, 0x078, 16, 3, 23, + 0x4, 14, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents, + 0x070, 0x074, 0x078, 24, 3, 31, + 0x4, 15, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_4 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents, + 0x080, 0x084, 0x088, 0, 2, 7, + 0x4, 16, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents, + 0x080, 0x084, 0x088, 8, 2, 15, + 0x4, 17, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents, + 0x080, 0x084, 0x088, 16, 2, 23, + 0x4, 18, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, + 0x080, 0x084, 0x088, 24, 2, 31, + 0x4, 19, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_5 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents, + 0x090, 0x094, 0x098, 0, 1, 7, + 0x4, 20, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents, + 0x090, 0x094, 0x098, 8, 1, 15, + 0x4, 21, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, + 0x090, 0x094, 0x098, 16, 2, 23, + 0x4, 22, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, + 0x090, 0x094, 0x098, 24, 2, 31, + 0x4, 23, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_6 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents, + 0x0a0, 0x0a4, 0x0a8, 0, 1, 7, + 0x4, 24, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents, + 0x0a0, 0x0a4, 0x0a8, 8, 3, 15, + 0x4, 25, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents, + 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, + 0x4, 26, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents, + 0x0a0, 0x0a4, 0x0a8, 24, 3, 31, + 0x4, 27, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_7 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents, + 0x0b0, 0x0b4, 0x0b8, 0, 3, 7, + 0x4, 28, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents, + 0x0b0, 0x0b4, 0x0b8, 8, 3, 15, + 0x4, 29, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents, + 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, + 0x4, 30, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents, + 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, + 0x4, 31, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_8 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, + 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, + 0x8, 0, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents, + 0x0c0, 0x0c4, 0x0c8, 8, 1, 15, + 0x8, 1, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents, + 0x0c0, 0x0c4, 0x0c8, 16, 3, 23, + 0x8, 2, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents, + 0x0c0, 0x0c4, 0x0c8, 24, 3, 31, + 0x8, 3, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_9 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents, + 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, + 0x8, 4, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents, + 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, + 0x8, 5, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents, + 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, + 0x8, 6, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents, + 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, + 0x8, 7, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_10 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents, + 0x0e0, 0x0e4, 0x0e8, 0, 3, 7, + 0x8, 8, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, + 0x0e0, 0x0e4, 0x0e8, 8, 2, 15, + 0x8, 9, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents, + 0x0e0, 0x0e4, 0x0e8, 16, 1, 23, + 0x8, 10, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents, + 0x0e0, 0x0e4, 0x0e8, 24, 1, 31, + 0x8, 11, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_11 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents, + 0x0ec, 0x0f0, 0x0f4, 0, 2, 7, + 0x8, 12, CLK_MUX_SETCLR_UPD), +}; + +static const struct mtk_gate_regs top0_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +static const struct mtk_gate_regs top1_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x104, + .sta_ofs = 0x104, +}; + +#define GATE_TOP0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_TOP1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate top_clks[] = { + /* TOP0 */ + GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10), + GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11), + GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16), + GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17), + /* TOP1 */ + GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4_T, 8), + GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4_T, 9), + GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22), + GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23), +}; + +static const struct mtk_gate_regs infra0_cg_regs = { + .set_ofs = 0x294, + .clr_ofs = 0x294, + .sta_ofs = 0x294, +}; + +static const struct mtk_gate_regs infra1_cg_regs = { + .set_ofs = 0x80, + .clr_ofs = 0x84, + .sta_ofs = 0x90, +}; + +static const struct mtk_gate_regs infra2_cg_regs = { + .set_ofs = 0x88, + .clr_ofs = 0x8c, + .sta_ofs = 0x94, +}; + +static const struct mtk_gate_regs infra3_cg_regs = { + .set_ofs = 0xa4, + .clr_ofs = 0xa8, + .sta_ofs = 0xac, +}; + +static const struct mtk_gate_regs infra4_cg_regs = { + .set_ofs = 0xc0, + .clr_ofs = 0xc4, + .sta_ofs = 0xc8, +}; + +static const struct mtk_gate_regs infra5_cg_regs = { + .set_ofs = 0xd0, + .clr_ofs = 0xd4, + .sta_ofs = 0xd8, +}; + +#define GATE_INFRA0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA2(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra2_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA3(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra3_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA4(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra4_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA5(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra5_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate infra_clks[] = { + /* INFRA0 */ + GATE_INFRA0(CLK_INFRA_DSP_AXI, CLK_TOP_AXI_SEL, 8), + /* INFRA1 */ + GATE_INFRA1(CLK_INFRA_APXGPT, CLK_TOP_AXI_SEL, 6), + GATE_INFRA1(CLK_INFRA_ICUSB, CLK_TOP_AXI_SEL, 8), + GATE_INFRA1(CLK_INFRA_GCE, CLK_TOP_AXI_SEL, 9), + GATE_INFRA1(CLK_INFRA_THERM, CLK_TOP_AXI_SEL, 10), + GATE_INFRA1(CLK_INFRA_PWM_HCLK, CLK_TOP_AXI_SEL, 15), + GATE_INFRA1(CLK_INFRA_PWM1, CLK_TOP_PWM_SEL, 16), + GATE_INFRA1(CLK_INFRA_PWM2, CLK_TOP_PWM_SEL, 17), + GATE_INFRA1(CLK_INFRA_PWM3, CLK_TOP_PWM_SEL, 18), + GATE_INFRA1(CLK_INFRA_PWM4, CLK_TOP_PWM_SEL, 19), + GATE_INFRA1(CLK_INFRA_PWM5, CLK_TOP_PWM_SEL, 20), + GATE_INFRA1(CLK_INFRA_PWM, CLK_TOP_PWM_SEL, 21), + GATE_INFRA1(CLK_INFRA_UART0, CLK_TOP_UART_SEL, 22), + GATE_INFRA1(CLK_INFRA_UART1, CLK_TOP_UART_SEL, 23), + GATE_INFRA1(CLK_INFRA_UART2, CLK_TOP_UART_SEL, 24), + GATE_INFRA1(CLK_INFRA_DSP_UART, CLK_TOP_UART_SEL, 26), + GATE_INFRA1(CLK_INFRA_GCE_26M, CLK_TOP_CLK26M, 27), + GATE_INFRA1(CLK_INFRA_CQDMA_FPC, CLK_TOP_AXI_SEL, 28), + GATE_INFRA1(CLK_INFRA_BTIF, CLK_TOP_AXI_SEL, 31), + /* INFRA2 */ + GATE_INFRA2(CLK_INFRA_SPI, CLK_TOP_SPI_SEL, 1), + GATE_INFRA2(CLK_INFRA_MSDC0, CLK_TOP_MSDC50_0_HC_SEL, 2), + GATE_INFRA2(CLK_INFRA_MSDC1, CLK_TOP_AXI_SEL, 4), + GATE_INFRA2(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7), + GATE_INFRA2(CLK_INFRA_GCPU, CLK_TOP_AXI_SEL, 8), + GATE_INFRA2(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 9), + GATE_INFRA2(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10), + GATE_INFRA2(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14), + GATE_INFRA2(CLK_INFRA_AP_DMA, CLK_TOP_AXI_SEL, 18), + GATE_INFRA2(CLK_INFRA_DEBUGSYS, CLK_TOP_AXI_SEL, 24), + GATE_INFRA2(CLK_INFRA_AUDIO, CLK_TOP_AXI_SEL, 25), + GATE_INFRA2(CLK_INFRA_FLASHIF, CLK_TOP_SFLASH_SEL, 29), + /* INFRA3 */ + GATE_INFRA3(CLK_INFRA_PWM_FB6, CLK_TOP_PWM_SEL, 0), + GATE_INFRA3(CLK_INFRA_PWM_FB7, CLK_TOP_PWM_SEL, 1), + GATE_INFRA3(CLK_INFRA_AUD_ASRC, CLK_TOP_AXI_SEL, 3), + GATE_INFRA3(CLK_INFRA_AUD_26M, CLK_TOP_CLK26M, 4), + GATE_INFRA3(CLK_INFRA_SPIS, CLK_TOP_AXI_SEL, 6), + GATE_INFRA3(CLK_INFRA_CQ_DMA, CLK_TOP_AXI_SEL, 27), + /* INFRA4 */ + GATE_INFRA4(CLK_INFRA_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7), + GATE_INFRA4(CLK_INFRA_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8), + GATE_INFRA4(CLK_INFRA_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9), + GATE_INFRA4(CLK_INFRA_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10), + GATE_INFRA4(CLK_INFRA_IRRX_26M, CLK_TOP_AXI_SEL, 22), + GATE_INFRA4(CLK_INFRA_IRRX_32K, CLK_TOP_CLK32K, 23), + GATE_INFRA4(CLK_INFRA_I2C0_AXI, CLK_TOP_I2C_SEL, 24), + GATE_INFRA4(CLK_INFRA_I2C1_AXI, CLK_TOP_I2C_SEL, 25), + GATE_INFRA4(CLK_INFRA_I2C2_AXI, CLK_TOP_I2C_SEL, 26), + /* INFRA5 */ + GATE_INFRA5(CLK_INFRA_NFI, CLK_TOP_NFI2X_CK_D2, 1), + GATE_INFRA5(CLK_INFRA_NFIECC, CLK_TOP_NFI2X_CK_D2, 2), + GATE_INFRA5(CLK_INFRA_NFI_HCLK, CLK_TOP_AXI_SEL, 3), + GATE_INFRA5(CLK_INFRA_SUSB_133, CLK_TOP_AXI_SEL, 7), + GATE_INFRA5(CLK_INFRA_USB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9), + GATE_INFRA5(CLK_INFRA_USB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11), +}; + +static const struct mtk_clk_tree mt8512_clk_tree = { + .xtal_rate = 26 * MHZ, + .xtal2_rate = 26 * MHZ, + .fdivs_offs = CLK_TOP_SYSPLL1_D2, + .muxes_offs = CLK_TOP_AXI_SEL, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, +}; + +static int mt8512_apmixedsys_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8512_clk_tree); +} + +static int mt8512_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8512_clk_tree); +} + +static int mt8512_topckgen_cg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks); +} + +static int mt8512_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks); +} + +static const struct udevice_id mt8512_apmixed_compat[] = { + { .compatible = "mediatek,mt8512-apmixedsys", }, + { } +}; + +static const struct udevice_id mt8512_topckgen_compat[] = { + { .compatible = "mediatek,mt8512-topckgen", }, + { } +}; + +static const struct udevice_id mt8512_topckgen_cg_compat[] = { + { .compatible = "mediatek,mt8512-topckgen-cg", }, + { } +}; + +static const struct udevice_id mt8512_infracfg_compat[] = { + { .compatible = "mediatek,mt8512-infracfg", }, + { } +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt8512-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt8512_apmixed_compat, + .probe = mt8512_apmixedsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt8512-topckgen", + .id = UCLASS_CLK, + .of_match = mt8512_topckgen_compat, + .probe = mt8512_topckgen_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen_cg) = { + .name = "mt8512-topckgen-cg", + .id = UCLASS_CLK, + .of_match = mt8512_topckgen_cg_compat, + .probe = mt8512_topckgen_cg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt8512-infracfg", + .id = UCLASS_CLK, + .of_match = mt8512_infracfg_compat, + .probe = mt8512_infracfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 6c6b500d9b..09ae2d4860 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -39,7 +39,7 @@ * this function is recursively called to find the parent to calculate * the accurate frequency. */ -static int mtk_clk_find_parent_rate(struct clk *clk, int id, +static ulong mtk_clk_find_parent_rate(struct clk *clk, int id, const struct driver *drv) { struct clk parent = { .id = id, }; @@ -67,12 +67,23 @@ static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent, if (++index == mux->num_parents) return -EINVAL; - /* switch mux to a select parent */ - val = readl(base + mux->mux_reg); - val &= ~(mux->mux_mask << mux->mux_shift); + if (mux->flags & CLK_MUX_SETCLR_UPD) { + val = (mux->mux_mask << mux->mux_shift); + writel(val, base + mux->mux_clr_reg); - val |= index << mux->mux_shift; - writel(val, base + mux->mux_reg); + val = (index << mux->mux_shift); + writel(val, base + mux->mux_set_reg); + + if (mux->upd_shift >= 0) + writel(BIT(mux->upd_shift), base + mux->upd_reg); + } else { + /* switch mux to a select parent */ + val = readl(base + mux->mux_reg); + val &= ~(mux->mux_mask << mux->mux_shift); + + val |= index << mux->mux_shift; + writel(val, base + mux->mux_reg); + } return 0; } @@ -84,11 +95,13 @@ static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll, { int pcwbits = pll->pcwbits; int pcwfbits; + int ibits; u64 vco; u8 c = 0; /* The fractional part of the PLL divider. */ - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; + ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; + pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0; vco = (u64)fin * pcw; @@ -113,7 +126,7 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; - u32 val; + u32 val, chg; /* set postdiv */ val = readl(priv->base + pll->pd_reg); @@ -129,11 +142,16 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv) /* set pcw */ val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift); val |= pcw << pll->pcw_shift; - val &= ~CON1_PCW_CHG; - writel(val, priv->base + pll->pcw_reg); - val |= CON1_PCW_CHG; - writel(val, priv->base + pll->pcw_reg); + if (pll->pcw_chg_reg) { + chg = readl(priv->base + pll->pcw_chg_reg); + chg |= CON1_PCW_CHG; + writel(val, priv->base + pll->pcw_reg); + writel(chg, priv->base + pll->pcw_chg_reg); + } else { + val |= CON1_PCW_CHG; + writel(val, priv->base + pll->pcw_reg); + } udelay(20); } @@ -150,8 +168,9 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; - unsigned long fmin = 1000 * MHZ; + unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ; u64 _pcw; + int ibits; u32 val; if (freq > pll->fmax) @@ -164,7 +183,8 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, } /* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */ - _pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS); + ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; + _pcw = ((u64)freq << val) << (pll->pcwbits - ibits); do_div(_pcw, priv->tree->xtal2_rate); *pcw = (u32)_pcw; @@ -265,7 +285,7 @@ static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv, return rate; } -static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) +static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; @@ -287,7 +307,7 @@ static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) return mtk_factor_recalc_rate(fdiv, rate); } -static int mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) +static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux = &priv->tree->muxes[off]; @@ -332,9 +352,14 @@ static int mtk_topckgen_enable(struct clk *clk) return 0; /* enable clock gate */ - val = readl(priv->base + mux->gate_reg); - val &= ~BIT(mux->gate_shift); - writel(val, priv->base + mux->gate_reg); + if (mux->flags & CLK_MUX_SETCLR_UPD) { + val = BIT(mux->gate_shift); + writel(val, priv->base + mux->mux_clr_reg); + } else { + val = readl(priv->base + mux->gate_reg); + val &= ~BIT(mux->gate_shift); + writel(val, priv->base + mux->gate_reg); + } if (mux->flags & CLK_DOMAIN_SCPSYS) { /* enable scpsys clock off control */ @@ -360,9 +385,14 @@ static int mtk_topckgen_disable(struct clk *clk) return 0; /* disable clock gate */ - val = readl(priv->base + mux->gate_reg); - val |= BIT(mux->gate_shift); - writel(val, priv->base + mux->gate_reg); + if (mux->flags & CLK_MUX_SETCLR_UPD) { + val = BIT(mux->gate_shift); + writel(val, priv->base + mux->mux_set_reg); + } else { + val = readl(priv->base + mux->gate_reg); + val |= BIT(mux->gate_shift); + writel(val, priv->base + mux->gate_reg); + } return 0; } diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index dce93253ad..c7dc980861 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -12,6 +12,7 @@ #define HAVE_RST_BAR BIT(0) #define CLK_DOMAIN_SCPSYS BIT(0) +#define CLK_MUX_SETCLR_UPD BIT(1) #define CLK_GATE_SETCLR BIT(0) #define CLK_GATE_SETCLR_INV BIT(1) @@ -36,9 +37,12 @@ struct mtk_pll_data { u32 flags; u32 rst_bar_mask; u64 fmax; + u64 fmin; int pcwbits; + int pcwibits; u32 pcw_reg; int pcw_shift; + u32 pcw_chg_reg; }; /** @@ -102,9 +106,13 @@ struct mtk_composite { const int id; const int *parent; u32 mux_reg; + u32 mux_set_reg; + u32 mux_clr_reg; + u32 upd_reg; u32 gate_reg; u32 mux_mask; signed char mux_shift; + signed char upd_shift; signed char gate_shift; signed char num_parents; u16 flags; @@ -137,6 +145,24 @@ struct mtk_composite { .flags = 0, \ } +#define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\ + _mux_clr_ofs, _shift, _width, _gate, \ + _upd_ofs, _upd, _flags) { \ + .id = _id, \ + .mux_reg = _mux_ofs, \ + .mux_set_reg = _mux_set_ofs, \ + .mux_clr_reg = _mux_clr_ofs, \ + .upd_reg = _upd_ofs, \ + .upd_shift = _upd, \ + .mux_shift = _shift, \ + .mux_mask = BIT(_width) - 1, \ + .gate_reg = _mux_ofs, \ + .gate_shift = _gate, \ + .parent = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = _flags, \ + } + struct mtk_gate_regs { u32 sta_ofs; u32 clr_ofs; |