diff options
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/Kconfig | 8 | ||||
-rw-r--r-- | drivers/clk/Makefile | 3 | ||||
-rw-r--r-- | drivers/clk/clk_stm32f7.c | 329 | ||||
-rw-r--r-- | drivers/clk/clk_zynq.c | 488 |
4 files changed, 827 insertions, 1 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 335ef9e1d7..5ca958c007 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -28,6 +28,14 @@ config CLK_BOSTON help Enable this to support the clocks +config CLK_ZYNQ + bool "Enable clock driver support for Zynq" + depends on CLK && ARCH_ZYNQ + default y + help + This clock driver adds support for clock realted settings for + Zynq platform. + config CLK_ZYNQMP bool "Enable clock driver support for ZynqMP" depends on ARCH_ZYNQMP diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 884c21c68b..01a8cd641e 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o +obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o obj-y += tegra/ @@ -17,5 +18,5 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_AT91) += at91/ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o - obj-$(CONFIG_ARCH_ASPEED) += aspeed/ +obj-$(CONFIG_STM32F7) += clk_stm32f7.o diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c new file mode 100644 index 0000000000..0d86395d47 --- /dev/null +++ b/drivers/clk/clk_stm32f7.c @@ -0,0 +1,329 @@ +/* + * (C) Copyright 2017 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/rcc.h> +#include <asm/arch/stm32.h> +#include <asm/arch/stm32_periph.h> + +#define RCC_CR_HSION BIT(0) +#define RCC_CR_HSEON BIT(16) +#define RCC_CR_HSERDY BIT(17) +#define RCC_CR_HSEBYP BIT(18) +#define RCC_CR_CSSON BIT(19) +#define RCC_CR_PLLON BIT(24) +#define RCC_CR_PLLRDY BIT(25) + +#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0) +#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6) +#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16) +#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24) +#define RCC_PLLCFGR_PLLSRC BIT(22) +#define RCC_PLLCFGR_PLLM_SHIFT 0 +#define RCC_PLLCFGR_PLLN_SHIFT 6 +#define RCC_PLLCFGR_PLLP_SHIFT 16 +#define RCC_PLLCFGR_PLLQ_SHIFT 24 + +#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) +#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10) +#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13) +#define RCC_CFGR_SW0 BIT(0) +#define RCC_CFGR_SW1 BIT(1) +#define RCC_CFGR_SW_MASK GENMASK(1, 0) +#define RCC_CFGR_SW_HSI 0 +#define RCC_CFGR_SW_HSE RCC_CFGR_SW0 +#define RCC_CFGR_SW_PLL RCC_CFGR_SW1 +#define RCC_CFGR_SWS0 BIT(2) +#define RCC_CFGR_SWS1 BIT(3) +#define RCC_CFGR_SWS_MASK GENMASK(3, 2) +#define RCC_CFGR_SWS_HSI 0 +#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 +#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 +#define RCC_CFGR_HPRE_SHIFT 4 +#define RCC_CFGR_PPRE1_SHIFT 10 +#define RCC_CFGR_PPRE2_SHIFT 13 + +/* + * Offsets of some PWR registers + */ +#define PWR_CR1_ODEN BIT(16) +#define PWR_CR1_ODSWEN BIT(17) +#define PWR_CSR1_ODRDY BIT(16) +#define PWR_CSR1_ODSWRDY BIT(17) + +struct pll_psc { + u8 pll_m; + u16 pll_n; + u8 pll_p; + u8 pll_q; + u8 ahb_psc; + u8 apb1_psc; + u8 apb2_psc; +}; + +#define AHB_PSC_1 0 +#define AHB_PSC_2 0x8 +#define AHB_PSC_4 0x9 +#define AHB_PSC_8 0xA +#define AHB_PSC_16 0xB +#define AHB_PSC_64 0xC +#define AHB_PSC_128 0xD +#define AHB_PSC_256 0xE +#define AHB_PSC_512 0xF + +#define APB_PSC_1 0 +#define APB_PSC_2 0x4 +#define APB_PSC_4 0x5 +#define APB_PSC_8 0x6 +#define APB_PSC_16 0x7 + +#if !defined(CONFIG_STM32_HSE_HZ) +#error "CONFIG_STM32_HSE_HZ not defined!" +#else +#if (CONFIG_STM32_HSE_HZ == 25000000) +#if (CONFIG_SYS_CLK_FREQ == 200000000) +/* 200 MHz */ +struct pll_psc sys_pll_psc = { + .pll_m = 25, + .pll_n = 400, + .pll_p = 2, + .pll_q = 8, + .ahb_psc = AHB_PSC_1, + .apb1_psc = APB_PSC_4, + .apb2_psc = APB_PSC_2 +}; +#endif +#else +#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists" +#endif +#endif + +int configure_clocks(void) +{ + /* Reset RCC configuration */ + setbits_le32(&STM32_RCC->cr, RCC_CR_HSION); + writel(0, &STM32_RCC->cfgr); /* Reset CFGR */ + clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON + | RCC_CR_PLLON)); + writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */ + clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP); + writel(0, &STM32_RCC->cir); /* Disable all interrupts */ + + /* Configure for HSE+PLL operation */ + setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON); + while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY)) + ; + + setbits_le32(&STM32_RCC->cfgr, (( + sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) + | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) + | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); + + /* Configure the main PLL */ + uint32_t pllcfgr = 0; + pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */ + pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT; + pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT; + pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT; + pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT; + writel(pllcfgr, &STM32_RCC->pllcfgr); + + /* Enable the main PLL */ + setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON); + while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY)) + ; + + /* Enable high performance mode, System frequency up to 200 MHz */ + setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN); + setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN); + /* Infinite wait! */ + while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY)) + ; + /* Enable the Over-drive switch */ + setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN); + /* Infinite wait! */ + while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY)) + ; + + stm32_flash_latency_cfg(5); + clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); + setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); + + while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) != + RCC_CFGR_SWS_PLL) + ; + + return 0; +} + +unsigned long clock_get(enum clock clck) +{ + u32 sysclk = 0; + u32 shift = 0; + /* Prescaler table lookups for clock computation */ + u8 ahb_psc_table[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 + }; + u8 apb_psc_table[8] = { + 0, 0, 0, 0, 1, 2, 3, 4 + }; + + if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) == + RCC_CFGR_SWS_PLL) { + u16 pllm, plln, pllp; + pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); + plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) + >> RCC_PLLCFGR_PLLN_SHIFT); + pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) + >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); + sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; + } + + switch (clck) { + case CLOCK_CORE: + return sysclk; + break; + case CLOCK_AHB: + shift = ahb_psc_table[( + (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK) + >> RCC_CFGR_HPRE_SHIFT)]; + return sysclk >>= shift; + break; + case CLOCK_APB1: + shift = apb_psc_table[( + (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK) + >> RCC_CFGR_PPRE1_SHIFT)]; + return sysclk >>= shift; + break; + case CLOCK_APB2: + shift = apb_psc_table[( + (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK) + >> RCC_CFGR_PPRE2_SHIFT)]; + return sysclk >>= shift; + break; + default: + return 0; + break; + } +} + +static int stm32_clk_enable(struct clk *clk) +{ + u32 offset = clk->id / 32; + u32 bit_index = clk->id % 32; + + debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n", + __func__, clk->id, offset, bit_index); + setbits_le32(&STM32_RCC->ahb1enr + offset, BIT(bit_index)); + + return 0; +} + +void clock_setup(int peripheral) +{ + switch (peripheral) { + case GPIO_A_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN); + break; + case GPIO_B_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_B_EN); + break; + case GPIO_C_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_C_EN); + break; + case GPIO_D_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_D_EN); + break; + case GPIO_E_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_E_EN); + break; + case GPIO_F_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_F_EN); + break; + case GPIO_G_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_G_EN); + break; + case GPIO_H_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_H_EN); + break; + case GPIO_I_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_I_EN); + break; + case GPIO_J_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_J_EN); + break; + case GPIO_K_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_K_EN); + break; + case SYSCFG_CLOCK_CFG: + setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN); + break; + case TIMER2_CLOCK_CFG: + setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); + break; + case FMC_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN); + break; + case STMMAC_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN); + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN); + break; + case QSPI_CLOCK_CFG: + setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_QSPI_EN); + break; + default: + break; + } +} + +static int stm32_clk_probe(struct udevice *dev) +{ + debug("%s: stm32_clk_probe\n", __func__); + configure_clocks(); + + return 0; +} + +static int stm32_clk_of_xlate(struct clk *clk, + struct fdtdec_phandle_args *args) +{ + debug("%s(clk=%p)\n", __func__, clk); + + if (args->args_count != 2) { + debug("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (args->args_count) + clk->id = args->args[1]; + else + clk->id = 0; + + return 0; +} + +static struct clk_ops stm32_clk_ops = { + .of_xlate = stm32_clk_of_xlate, + .enable = stm32_clk_enable, +}; + +static const struct udevice_id stm32_clk_ids[] = { + { .compatible = "st,stm32f42xx-rcc"}, + {} +}; + +U_BOOT_DRIVER(stm32f7_clk) = { + .name = "stm32f7_clk", + .id = UCLASS_CLK, + .of_match = stm32_clk_ids, + .ops = &stm32_clk_ops, + .probe = stm32_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c new file mode 100644 index 0000000000..6edc4dc6ca --- /dev/null +++ b/drivers/clk/clk_zynq.c @@ -0,0 +1,488 @@ +/* + * Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG + * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> + * + * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com> + * Copyright (C) 2013 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/clk.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> + +/* Register bitfield defines */ +#define PLLCTRL_FBDIV_MASK 0x7f000 +#define PLLCTRL_FBDIV_SHIFT 12 +#define PLLCTRL_BPFORCE_MASK (1 << 4) +#define PLLCTRL_PWRDWN_MASK 2 +#define PLLCTRL_PWRDWN_SHIFT 1 +#define PLLCTRL_RESET_MASK 1 +#define PLLCTRL_RESET_SHIFT 0 + +#define ZYNQ_CLK_MAXDIV 0x3f +#define CLK_CTRL_DIV1_SHIFT 20 +#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT) +#define CLK_CTRL_DIV0_SHIFT 8 +#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) +#define CLK_CTRL_SRCSEL_SHIFT 4 +#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT) + +#define CLK_CTRL_DIV2X_SHIFT 26 +#define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT) +#define CLK_CTRL_DIV3X_SHIFT 20 +#define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT) + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SPL_BUILD +enum zynq_clk_rclk {mio_clk, emio_clk}; +#endif + +struct zynq_clk_priv { + ulong ps_clk_freq; +#ifndef CONFIG_SPL_BUILD + struct clk gem_emio_clk[2]; +#endif +}; + +static void *zynq_clk_get_register(enum zynq_clk id) +{ + switch (id) { + case armpll_clk: + return &slcr_base->arm_pll_ctrl; + case ddrpll_clk: + return &slcr_base->ddr_pll_ctrl; + case iopll_clk: + return &slcr_base->io_pll_ctrl; + case lqspi_clk: + return &slcr_base->lqspi_clk_ctrl; + case smc_clk: + return &slcr_base->smc_clk_ctrl; + case pcap_clk: + return &slcr_base->pcap_clk_ctrl; + case sdio0_clk ... sdio1_clk: + return &slcr_base->sdio_clk_ctrl; + case uart0_clk ... uart1_clk: + return &slcr_base->uart_clk_ctrl; + case spi0_clk ... spi1_clk: + return &slcr_base->spi_clk_ctrl; +#ifndef CONFIG_SPL_BUILD + case dci_clk: + return &slcr_base->dci_clk_ctrl; + case gem0_clk: + return &slcr_base->gem0_clk_ctrl; + case gem1_clk: + return &slcr_base->gem1_clk_ctrl; + case fclk0_clk: + return &slcr_base->fpga0_clk_ctrl; + case fclk1_clk: + return &slcr_base->fpga1_clk_ctrl; + case fclk2_clk: + return &slcr_base->fpga2_clk_ctrl; + case fclk3_clk: + return &slcr_base->fpga3_clk_ctrl; + case can0_clk ... can1_clk: + return &slcr_base->can_clk_ctrl; + case dbg_trc_clk ... dbg_apb_clk: + /* fall through */ +#endif + default: + return &slcr_base->dbg_clk_ctrl; + } +} + +static enum zynq_clk zynq_clk_get_cpu_pll(u32 clk_ctrl) +{ + u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + + switch (srcsel) { + case 2: + return ddrpll_clk; + case 3: + return iopll_clk; + case 0 ... 1: + default: + return armpll_clk; + } +} + +static enum zynq_clk zynq_clk_get_peripheral_pll(u32 clk_ctrl) +{ + u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + + switch (srcsel) { + case 2: + return armpll_clk; + case 3: + return ddrpll_clk; + case 0 ... 1: + default: + return iopll_clk; + } +} + +static ulong zynq_clk_get_pll_rate(struct zynq_clk_priv *priv, enum zynq_clk id) +{ + u32 clk_ctrl, reset, pwrdwn, mul, bypass; + + clk_ctrl = readl(zynq_clk_get_register(id)); + + reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT; + pwrdwn = (clk_ctrl & PLLCTRL_PWRDWN_MASK) >> PLLCTRL_PWRDWN_SHIFT; + if (reset || pwrdwn) + return 0; + + bypass = clk_ctrl & PLLCTRL_BPFORCE_MASK; + if (bypass) + mul = 1; + else + mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; + + return priv->ps_clk_freq * mul; +} + +#ifndef CONFIG_SPL_BUILD +static enum zynq_clk_rclk zynq_clk_get_gem_rclk(enum zynq_clk id) +{ + u32 clk_ctrl, srcsel; + + if (id == gem0_clk) + clk_ctrl = readl(&slcr_base->gem0_rclk_ctrl); + else + clk_ctrl = readl(&slcr_base->gem1_rclk_ctrl); + + srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; + if (srcsel) + return emio_clk; + else + return mio_clk; +} +#endif + +static ulong zynq_clk_get_cpu_rate(struct zynq_clk_priv *priv, enum zynq_clk id) +{ + u32 clk_621, clk_ctrl, div; + enum zynq_clk pll; + + clk_ctrl = readl(&slcr_base->arm_clk_ctrl); + + div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + + switch (id) { + case cpu_1x_clk: + div *= 2; + /* fall through */ + case cpu_2x_clk: + clk_621 = readl(&slcr_base->clk_621_true) & 1; + div *= 2 + clk_621; + break; + case cpu_3or2x_clk: + div *= 2; + /* fall through */ + case cpu_6or4x_clk: + break; + default: + return 0; + } + + pll = zynq_clk_get_cpu_pll(clk_ctrl); + + return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, pll), div); +} + +#ifndef CONFIG_SPL_BUILD +static ulong zynq_clk_get_ddr2x_rate(struct zynq_clk_priv *priv) +{ + u32 clk_ctrl, div; + + clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); + + div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT; + + return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, ddrpll_clk), div); +} +#endif + +static ulong zynq_clk_get_ddr3x_rate(struct zynq_clk_priv *priv) +{ + u32 clk_ctrl, div; + + clk_ctrl = readl(&slcr_base->ddr_clk_ctrl); + + div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT; + + return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, ddrpll_clk), div); +} + +#ifndef CONFIG_SPL_BUILD +static ulong zynq_clk_get_dci_rate(struct zynq_clk_priv *priv) +{ + u32 clk_ctrl, div0, div1; + + clk_ctrl = readl(&slcr_base->dci_clk_ctrl); + + div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; + + return DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST( + zynq_clk_get_pll_rate(priv, ddrpll_clk), div0), div1); +} +#endif + +static ulong zynq_clk_get_peripheral_rate(struct zynq_clk_priv *priv, + enum zynq_clk id, bool two_divs) +{ + enum zynq_clk pll; + u32 clk_ctrl, div0; + u32 div1 = 1; + + clk_ctrl = readl(zynq_clk_get_register(id)); + + div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; + if (!div0) + div0 = 1; + +#ifndef CONFIG_SPL_BUILD + if (two_divs) { + div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT; + if (!div1) + div1 = 1; + } +#endif + + pll = zynq_clk_get_peripheral_pll(clk_ctrl); + + return + DIV_ROUND_CLOSEST( + DIV_ROUND_CLOSEST( + zynq_clk_get_pll_rate(priv, pll), div0), + div1); +} + +#ifndef CONFIG_SPL_BUILD +static ulong zynq_clk_get_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id) +{ + struct clk *parent; + + if (zynq_clk_get_gem_rclk(id) == mio_clk) + return zynq_clk_get_peripheral_rate(priv, id, true); + + parent = &priv->gem_emio_clk[id - gem0_clk]; + if (parent->dev) + return clk_get_rate(parent); + + debug("%s: gem%d emio rx clock source unknown\n", __func__, + id - gem0_clk); + + return -ENOSYS; +} + +static unsigned long zynq_clk_calc_peripheral_two_divs(ulong rate, + ulong pll_rate, + u32 *div0, u32 *div1) +{ + long new_err, best_err = (long)(~0UL >> 1); + ulong new_rate, best_rate = 0; + u32 d0, d1; + + for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) { + for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) { + new_rate = DIV_ROUND_CLOSEST( + DIV_ROUND_CLOSEST(pll_rate, d0), d1); + new_err = abs(new_rate - rate); + + if (new_err < best_err) { + *div0 = d0; + *div1 = d1; + best_err = new_err; + best_rate = new_rate; + } + } + } + + return best_rate; +} + +static ulong zynq_clk_set_peripheral_rate(struct zynq_clk_priv *priv, + enum zynq_clk id, ulong rate, + bool two_divs) +{ + enum zynq_clk pll; + u32 clk_ctrl, div0 = 0, div1 = 0; + ulong pll_rate, new_rate; + u32 *reg; + + reg = zynq_clk_get_register(id); + clk_ctrl = readl(reg); + + pll = zynq_clk_get_peripheral_pll(clk_ctrl); + pll_rate = zynq_clk_get_pll_rate(priv, pll); + clk_ctrl &= ~CLK_CTRL_DIV0_MASK; + if (two_divs) { + clk_ctrl &= ~CLK_CTRL_DIV1_MASK; + new_rate = zynq_clk_calc_peripheral_two_divs(rate, pll_rate, + &div0, &div1); + clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT; + } else { + div0 = DIV_ROUND_CLOSEST(pll_rate, rate); + if (div0 > ZYNQ_CLK_MAXDIV) + div0 = ZYNQ_CLK_MAXDIV; + new_rate = DIV_ROUND_CLOSEST(rate, div0); + } + clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT; + + zynq_slcr_unlock(); + writel(clk_ctrl, reg); + zynq_slcr_lock(); + + return new_rate; +} + +static ulong zynq_clk_set_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id, + ulong rate) +{ + struct clk *parent; + + if (zynq_clk_get_gem_rclk(id) == mio_clk) + return zynq_clk_set_peripheral_rate(priv, id, rate, true); + + parent = &priv->gem_emio_clk[id - gem0_clk]; + if (parent->dev) + return clk_set_rate(parent, rate); + + debug("%s: gem%d emio rx clock source unknown\n", __func__, + id - gem0_clk); + + return -ENOSYS; +} +#endif + +#ifndef CONFIG_SPL_BUILD +static ulong zynq_clk_get_rate(struct clk *clk) +{ + struct zynq_clk_priv *priv = dev_get_priv(clk->dev); + enum zynq_clk id = clk->id; + bool two_divs = false; + + switch (id) { + case armpll_clk ... iopll_clk: + return zynq_clk_get_pll_rate(priv, id); + case cpu_6or4x_clk ... cpu_1x_clk: + return zynq_clk_get_cpu_rate(priv, id); + case ddr2x_clk: + return zynq_clk_get_ddr2x_rate(priv); + case ddr3x_clk: + return zynq_clk_get_ddr3x_rate(priv); + case dci_clk: + return zynq_clk_get_dci_rate(priv); + case gem0_clk ... gem1_clk: + return zynq_clk_get_gem_rate(priv, id); + case fclk0_clk ... can1_clk: + two_divs = true; + /* fall through */ + case dbg_trc_clk ... dbg_apb_clk: + case lqspi_clk ... pcap_clk: + case sdio0_clk ... spi1_clk: + return zynq_clk_get_peripheral_rate(priv, id, two_divs); + case dma_clk: + return zynq_clk_get_cpu_rate(priv, cpu_2x_clk); + case usb0_aper_clk ... smc_aper_clk: + return zynq_clk_get_cpu_rate(priv, cpu_1x_clk); + default: + return -ENXIO; + } +} + +static ulong zynq_clk_set_rate(struct clk *clk, ulong rate) +{ + struct zynq_clk_priv *priv = dev_get_priv(clk->dev); + enum zynq_clk id = clk->id; + bool two_divs = false; + + switch (id) { + case gem0_clk ... gem1_clk: + return zynq_clk_set_gem_rate(priv, id, rate); + case fclk0_clk ... can1_clk: + two_divs = true; + /* fall through */ + case lqspi_clk ... pcap_clk: + case sdio0_clk ... spi1_clk: + case dbg_trc_clk ... dbg_apb_clk: + return zynq_clk_set_peripheral_rate(priv, id, rate, two_divs); + default: + return -ENXIO; + } +} +#else +static ulong zynq_clk_get_rate(struct clk *clk) +{ + struct zynq_clk_priv *priv = dev_get_priv(clk->dev); + enum zynq_clk id = clk->id; + + switch (id) { + case cpu_6or4x_clk ... cpu_1x_clk: + return zynq_clk_get_cpu_rate(priv, id); + case ddr3x_clk: + return zynq_clk_get_ddr3x_rate(priv); + case lqspi_clk ... pcap_clk: + case sdio0_clk ... spi1_clk: + return zynq_clk_get_peripheral_rate(priv, id, 0); + default: + return -ENXIO; + } +} +#endif + +static struct clk_ops zynq_clk_ops = { + .get_rate = zynq_clk_get_rate, +#ifndef CONFIG_SPL_BUILD + .set_rate = zynq_clk_set_rate, +#endif +}; + +static int zynq_clk_probe(struct udevice *dev) +{ + struct zynq_clk_priv *priv = dev_get_priv(dev); +#ifndef CONFIG_SPL_BUILD + unsigned int i; + char name[16]; + int ret; + + for (i = 0; i < 2; i++) { + sprintf(name, "gem%d_emio_clk", i); + ret = clk_get_by_name(dev, name, &priv->gem_emio_clk[i]); + if (ret < 0 && ret != -FDT_ERR_NOTFOUND) { + dev_err(dev, "failed to get %s clock\n", name); + return ret; + } + } +#endif + + priv->ps_clk_freq = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "ps-clk-frequency", 33333333UL); + + return 0; +} + +static const struct udevice_id zynq_clk_ids[] = { + { .compatible = "xlnx,ps7-clkc"}, + {} +}; + +U_BOOT_DRIVER(zynq_clk) = { + .name = "zynq_clk", + .id = UCLASS_CLK, + .of_match = zynq_clk_ids, + .flags = DM_FLAG_PRE_RELOC, + .ops = &zynq_clk_ops, + .priv_auto_alloc_size = sizeof(struct zynq_clk_priv), + .probe = zynq_clk_probe, +}; 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