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path: root/drivers/ddr/fsl/ctrl_regs.c
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Diffstat (limited to 'drivers/ddr/fsl/ctrl_regs.c')
-rw-r--r--drivers/ddr/fsl/ctrl_regs.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 690e73dacf..391925751a 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1747,9 +1747,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts)
{
unsigned int clk_adjust; /* Clock adjust */
+ unsigned int ss_en = 0; /* Source synchronous enable */
+#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+ /* Per FSL Application Note: AN2805 */
+ ss_en = 1;
+#endif
clk_adjust = popts->clk_adjust;
- ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
+ ddr->ddr_sdram_clk_cntl = (0
+ | ((ss_en & 0x1) << 31)
+ | ((clk_adjust & 0xF) << 23)
+ );
debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
}