diff options
Diffstat (limited to 'drivers/misc')
| -rw-r--r-- | drivers/misc/Kconfig | 8 | ||||
| -rw-r--r-- | drivers/misc/ds4510.c | 53 | ||||
| -rw-r--r-- | drivers/misc/ds4510.h | 53 |
3 files changed, 72 insertions, 42 deletions
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 1aae4bcd07..ecca159d14 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -75,6 +75,14 @@ config CROS_EC_SPI provides a faster and more robust interface than I2C but the bugs are less interesting. +config DS4510 + bool "Enable support for DS4510 CPU supervisor" + help + Enable support for the Maxim DS4510 CPU supervisor. It has an + integrated 64-byte EEPROM, four programmable non-volatile I/O pins + and a configurable timer for the supervisor function. The device is + connected over I2C. + config FSL_SEC_MON bool "Enable FSL SEC_MON Driver" help diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c index d7c9bd73c8..55f8936513 100644 --- a/drivers/misc/ds4510.c +++ b/drivers/misc/ds4510.c @@ -12,12 +12,7 @@ #include <common.h> #include <i2c.h> #include <command.h> -#include <ds4510.h> - -/* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_DS4510_ADDR -#define CONFIG_SYS_I2C_DS4510_ADDR (~0) -#endif +#include "ds4510.h" enum { DS4510_CMD_INFO, @@ -35,7 +30,7 @@ enum { /* * Write to DS4510, taking page boundaries into account */ -int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count) +static int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count) { int wrlen; int i = 0; @@ -64,7 +59,7 @@ int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count) /* * General read from DS4510 */ -int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count) +static int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count) { return i2c_read(chip, offset, 1, buf, count); } @@ -74,7 +69,7 @@ int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count) * nv = 0 - Writes to SEEPROM registers behave like EEPROM * nv = 1 - Writes to SEEPROM registers behave like SRAM */ -int ds4510_see_write(uint8_t chip, uint8_t nv) +static int ds4510_see_write(uint8_t chip, uint8_t nv) { uint8_t data; @@ -92,7 +87,7 @@ int ds4510_see_write(uint8_t chip, uint8_t nv) /* * Write de-assertion of reset signal delay */ -int ds4510_rstdelay_write(uint8_t chip, uint8_t delay) +static int ds4510_rstdelay_write(uint8_t chip, uint8_t delay) { uint8_t data; @@ -108,7 +103,7 @@ int ds4510_rstdelay_write(uint8_t chip, uint8_t delay) /* * Write pullup characteristics of IO pins */ -int ds4510_pullup_write(uint8_t chip, uint8_t val) +static int ds4510_pullup_write(uint8_t chip, uint8_t val) { val &= DS4510_IO_MASK; @@ -118,7 +113,7 @@ int ds4510_pullup_write(uint8_t chip, uint8_t val) /* * Read pullup characteristics of IO pins */ -int ds4510_pullup_read(uint8_t chip) +static int ds4510_pullup_read(uint8_t chip) { uint8_t val; @@ -131,7 +126,7 @@ int ds4510_pullup_read(uint8_t chip) /* * Write drive level of IO pins */ -int ds4510_gpio_write(uint8_t chip, uint8_t val) +static int ds4510_gpio_write(uint8_t chip, uint8_t val) { uint8_t data; int i; @@ -155,7 +150,7 @@ int ds4510_gpio_write(uint8_t chip, uint8_t val) /* * Read drive level of IO pins */ -int ds4510_gpio_read(uint8_t chip) +static int ds4510_gpio_read(uint8_t chip) { uint8_t data; int val = 0; @@ -175,7 +170,7 @@ int ds4510_gpio_read(uint8_t chip) /* * Read physical level of IO pins */ -int ds4510_gpio_read_val(uint8_t chip) +static int ds4510_gpio_read_val(uint8_t chip) { uint8_t val; @@ -185,8 +180,6 @@ int ds4510_gpio_read_val(uint8_t chip) return val & DS4510_IO_MASK; } -#ifdef CONFIG_CMD_DS4510 -#ifdef CONFIG_CMD_DS4510_INFO /* * Display DS4510 information */ @@ -240,7 +233,6 @@ static int ds4510_info(uint8_t chip) return 0; } -#endif /* CONFIG_CMD_DS4510_INFO */ cmd_tbl_t cmd_ds4510[] = { U_BOOT_CMD_MKENT(device, 3, 0, (void *)DS4510_CMD_DEVICE, "", ""), @@ -248,33 +240,25 @@ cmd_tbl_t cmd_ds4510[] = { U_BOOT_CMD_MKENT(output, 4, 0, (void *)DS4510_CMD_OUTPUT, "", ""), U_BOOT_CMD_MKENT(input, 3, 0, (void *)DS4510_CMD_INPUT, "", ""), U_BOOT_CMD_MKENT(pullup, 4, 0, (void *)DS4510_CMD_PULLUP, "", ""), -#ifdef CONFIG_CMD_DS4510_INFO U_BOOT_CMD_MKENT(info, 2, 0, (void *)DS4510_CMD_INFO, "", ""), -#endif -#ifdef CONFIG_CMD_DS4510_RST U_BOOT_CMD_MKENT(rstdelay, 3, 0, (void *)DS4510_CMD_RSTDELAY, "", ""), -#endif -#ifdef CONFIG_CMD_DS4510_MEM U_BOOT_CMD_MKENT(eeprom, 6, 0, (void *)DS4510_CMD_EEPROM, "", ""), U_BOOT_CMD_MKENT(seeprom, 6, 0, (void *)DS4510_CMD_SEEPROM, "", ""), U_BOOT_CMD_MKENT(sram, 6, 0, (void *)DS4510_CMD_SRAM, "", ""), -#endif }; int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - static uint8_t chip = CONFIG_SYS_I2C_DS4510_ADDR; + static uint8_t chip = 0x51; cmd_tbl_t *c; ulong ul_arg2 = 0; ulong ul_arg3 = 0; int tmp; -#ifdef CONFIG_CMD_DS4510_MEM ulong addr; ulong off; ulong cnt; int end; int (*rw_func)(uint8_t, int, uint8_t *, int); -#endif c = find_cmd_tbl(argv[1], cmd_ds4510, ARRAY_SIZE(cmd_ds4510)); @@ -324,15 +308,10 @@ int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) else tmp &= ~(1 << ul_arg2); return ds4510_pullup_write(chip, tmp); -#ifdef CONFIG_CMD_DS4510_INFO case DS4510_CMD_INFO: return ds4510_info(chip); -#endif -#ifdef CONFIG_CMD_DS4510_RST case DS4510_CMD_RSTDELAY: return ds4510_rstdelay_write(chip, ul_arg2); -#endif -#ifdef CONFIG_CMD_DS4510_MEM case DS4510_CMD_EEPROM: end = DS4510_EEPROM + DS4510_EEPROM_SIZE; off = DS4510_EEPROM; @@ -345,13 +324,11 @@ int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) end = DS4510_SRAM + DS4510_SRAM_SIZE; off = DS4510_SRAM; break; -#endif default: /* We should never get here... */ return 1; } -#ifdef CONFIG_CMD_DS4510_MEM /* Only eeprom, seeprom, and sram commands should make it here */ if (strcmp(argv[2], "read") == 0) rw_func = ds4510_mem_read; @@ -370,7 +347,6 @@ int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } return rw_func(chip, off, (uint8_t *)addr, cnt); -#endif } U_BOOT_CMD( @@ -378,10 +354,8 @@ U_BOOT_CMD( "ds4510 eeprom/seeprom/sram/gpio access", "device [dev]\n" " - show or set current device address\n" -#ifdef CONFIG_CMD_DS4510_INFO "ds4510 info\n" " - display ds4510 info\n" -#endif "ds4510 output pin 0|1\n" " - set pin low or high-Z\n" "ds4510 input pin\n" @@ -390,12 +364,9 @@ U_BOOT_CMD( " - disable/enable pullup on specified pin\n" "ds4510 nv 0|1\n" " - make gpio and seeprom writes volatile/non-volatile" -#ifdef CONFIG_CMD_DS4510_RST "\n" "ds4510 rstdelay 0-3\n" " - set reset output delay" -#endif -#ifdef CONFIG_CMD_DS4510_MEM "\n" "ds4510 eeprom read addr off cnt\n" "ds4510 eeprom write addr off cnt\n" @@ -406,6 +377,4 @@ U_BOOT_CMD( "ds4510 sram read addr off cnt\n" "ds4510 sram write addr off cnt\n" " - read/write 'cnt' bytes at SRAM offset 'off'" -#endif ); -#endif /* CONFIG_CMD_DS4510 */ diff --git a/drivers/misc/ds4510.h b/drivers/misc/ds4510.h new file mode 100644 index 0000000000..a6c6c58cc4 --- /dev/null +++ b/drivers/misc/ds4510.h @@ -0,0 +1,53 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __DS4510_H_ +#define __DS4510_H_ + +/* General defines */ +#define DS4510_NUM_IO 0x04 +#define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1) +#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/* EEPROM from 0x00 - 0x39 */ +#define DS4510_EEPROM 0x00 +#define DS4510_EEPROM_SIZE 0x40 +#define DS4510_EEPROM_PAGE_SIZE 0x08 +#define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1)) + +/* SEEPROM from 0xf0 - 0xf7 */ +#define DS4510_SEEPROM 0xf0 +#define DS4510_SEEPROM_SIZE 0x08 + +/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */ +#define DS4510_PULLUP 0xF0 +#define DS4510_PULLUP_DIS 0x00 +#define DS4510_PULLUP_EN 0x01 +#define DS4510_RSTDELAY 0xF1 +#define DS4510_RSTDELAY_MASK 0x03 +#define DS4510_RSTDELAY_125 0x00 +#define DS4510_RSTDELAY_250 0x01 +#define DS4510_RSTDELAY_500 0x02 +#define DS4510_RSTDELAY_1000 0x03 +#define DS4510_IO3 0xF4 +#define DS4510_IO2 0xF5 +#define DS4510_IO1 0xF6 +#define DS4510_IO0 0xF7 + +/* Status configuration registers from 0xf8 - 0xf9*/ +#define DS4510_IO_STATUS 0xF8 +#define DS4510_CFG 0xF9 +#define DS4510_CFG_READY 0x80 +#define DS4510_CFG_TRIP_POINT 0x40 +#define DS4510_CFG_RESET 0x20 +#define DS4510_CFG_SEE 0x10 +#define DS4510_CFG_SWRST 0x08 + +/* SRAM from 0xfa - 0xff */ +#define DS4510_SRAM 0xfa +#define DS4510_SRAM_SIZE 0x06 + +#endif /* __DS4510_H_ */ |