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-rw-r--r--drivers/mtd/nand/Makefile1
-rw-r--r--drivers/mtd/nand/atmel_nand.c6
-rw-r--r--drivers/mtd/nand/davinci_nand.c12
-rw-r--r--drivers/mtd/nand/fsl_elbc_nand.c38
-rw-r--r--drivers/mtd/nand/fsl_ifc_nand.c38
-rw-r--r--drivers/mtd/nand/fsl_upm.c18
-rw-r--r--drivers/mtd/nand/lpc32xx_nand_mlc.c764
-rw-r--r--drivers/mtd/nand/mpc5121_nfc.c26
-rw-r--r--drivers/mtd/nand/mxc_nand.c33
-rw-r--r--drivers/mtd/nand/mxs_nand.c4
-rw-r--r--drivers/mtd/nand/nand_base.c65
-rw-r--r--drivers/mtd/nand/nand_util.c156
-rw-r--r--drivers/mtd/nand/ndfc.c18
-rw-r--r--drivers/mtd/nand/vf610_nfc.c28
14 files changed, 890 insertions, 317 deletions
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1f02bfc35f..347ea62e0b 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
+obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index b16e3aa157..a2016e7945 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1456,6 +1456,9 @@ int board_nand_init(struct nand_chip *nand)
nand->dev_ready = at91_nand_wait_ready;
#endif
nand->chip_delay = 20;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+ nand->bbt_options |= NAND_BBT_USE_FLASH;
+#endif
#ifdef CONFIG_ATMEL_NAND_HWECC
#ifdef CONFIG_ATMEL_NAND_HW_PMECC
@@ -1522,6 +1525,9 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)
nand->dev_ready = at91_nand_ready;
#endif
nand->chip_delay = 75;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+ nand->bbt_options |= NAND_BBT_USE_FLASH;
+#endif
ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
if (ret)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 41689b5165..a3970745c9 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -405,18 +405,6 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
goto err;
}
-#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
- /* Send command to read back the data */
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
-
- if (chip->verify_buf(mtd, buf, mtd->writesize)) {
- ret = -EIO;
- goto err;
- }
-
- /* Make sure the next page prog is preceded by a status read */
- chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
-#endif
err:
/* restore ECC layout */
if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 3372b64212..e85832d319 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -561,41 +561,6 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
len, avail);
}
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-/*
- * Verify buffer against the FCM Controller Data Buffer
- */
-static int fsl_elbc_verify_buf(struct mtd_info *mtd,
- const u_char *buf, int len)
-{
- struct nand_chip *chip = mtd->priv;
- struct fsl_elbc_mtd *priv = chip->priv;
- struct fsl_elbc_ctrl *ctrl = priv->ctrl;
- int i;
-
- if (len < 0) {
- printf("write_buf of %d bytes", len);
- return -EINVAL;
- }
-
- if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
- printf("verify_buf beyond end of buffer "
- "(%d requested, %u available)\n",
- len, ctrl->read_bytes - ctrl->index);
-
- ctrl->index = ctrl->read_bytes;
- return -EINVAL;
- }
-
- for (i = 0; i < len; i++)
- if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
- break;
-
- ctrl->index += len;
- return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
-}
-#endif
-
/* This function is called after Program and Erase Operations to
* check for success or failure.
*/
@@ -727,9 +692,6 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
nand->read_byte = fsl_elbc_read_byte;
nand->write_buf = fsl_elbc_write_buf;
nand->read_buf = fsl_elbc_read_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- nand->verify_buf = fsl_elbc_verify_buf;
-#endif
nand->select_chip = fsl_elbc_select_chip;
nand->cmdfunc = fsl_elbc_cmdfunc;
nand->waitfunc = fsl_elbc_wait;
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index b283eaea34..7903eebd53 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -683,41 +683,6 @@ static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
__func__, len, avail);
}
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-/*
- * Verify buffer against the IFC Controller Data Buffer
- */
-static int fsl_ifc_verify_buf(struct mtd_info *mtd,
- const u_char *buf, int len)
-{
- struct nand_chip *chip = mtd->priv;
- struct fsl_ifc_mtd *priv = chip->priv;
- struct fsl_ifc_ctrl *ctrl = priv->ctrl;
- int i;
-
- if (len < 0) {
- printf("%s of %d bytes", __func__, len);
- return -EINVAL;
- }
-
- if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
- printf("%s beyond end of buffer "
- "(%d requested, %u available)\n",
- __func__, len, ctrl->read_bytes - ctrl->index);
-
- ctrl->index = ctrl->read_bytes;
- return -EINVAL;
- }
-
- for (i = 0; i < len; i++)
- if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
- break;
-
- ctrl->index += len;
- return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
-}
-#endif
-
/* This function is called after Program and Erase Operations to
* check for success or failure.
*/
@@ -940,9 +905,6 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
nand->write_buf = fsl_ifc_write_buf;
nand->read_buf = fsl_ifc_read_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- nand->verify_buf = fsl_ifc_verify_buf;
-#endif
nand->select_chip = fsl_ifc_select_chip;
nand->cmdfunc = fsl_ifc_cmdfunc;
nand->waitfunc = fsl_ifc_wait;
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index 65ce98ad5e..5426c32114 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -153,21 +153,6 @@ static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
buf[i] = in_8(chip->IO_ADDR_R);
}
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-static int upm_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
-
- for (i = 0; i < len; i++) {
- if (buf[i] != in_8(chip->IO_ADDR_R))
- return -EFAULT;
- }
-
- return 0;
-}
-#endif
-
static int nand_dev_ready(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
@@ -193,9 +178,6 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
chip->read_byte = upm_nand_read_byte;
chip->read_buf = upm_nand_read_buf;
chip->write_buf = upm_nand_write_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- chip->verify_buf = upm_nand_verify_buf;
-#endif
if (fun->dev_ready)
chip->dev_ready = nand_dev_ready;
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c b/drivers/mtd/nand/lpc32xx_nand_mlc.c
new file mode 100644
index 0000000000..8156fe9613
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -0,0 +1,764 @@
+/*
+ * LPC32xx MLC NAND flash controller driver
+ *
+ * (C) Copyright 2014 3ADEV <http://3adev.com>
+ * Written by Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * NOTE:
+ *
+ * The MLC NAND flash controller provides hardware Reed-Solomon ECC
+ * covering in- and out-of-band data together. Therefore, in- and out-
+ * of-band data must be written together in order to have a valid ECC.
+ *
+ * Consequently, pages with meaningful in-band data are written with
+ * blank (all-ones) out-of-band data and a valid ECC, and any later
+ * out-of-band data write will void the ECC.
+ *
+ * Therefore, code which reads such late-written out-of-band data
+ * should not rely on the ECC validity.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * MLC NAND controller registers.
+ */
+struct lpc32xx_nand_mlc_registers {
+ u8 buff[32768]; /* controller's serial data buffer */
+ u8 data[32768]; /* NAND's raw data buffer */
+ u32 cmd;
+ u32 addr;
+ u32 ecc_enc_reg;
+ u32 ecc_dec_reg;
+ u32 ecc_auto_enc_reg;
+ u32 ecc_auto_dec_reg;
+ u32 rpr;
+ u32 wpr;
+ u32 rubp;
+ u32 robp;
+ u32 sw_wp_add_low;
+ u32 sw_wp_add_hig;
+ u32 icr;
+ u32 time_reg;
+ u32 irq_mr;
+ u32 irq_sr;
+ u32 lock_pr;
+ u32 isr;
+ u32 ceh;
+};
+
+/* LOCK_PR register defines */
+#define LOCK_PR_UNLOCK_KEY 0x0000A25E /* Magic unlock value */
+
+/* ICR defines */
+#define ICR_LARGE_BLOCKS 0x00000004 /* configure for 2KB blocks */
+#define ICR_ADDR4 0x00000002 /* configure for 4-word addrs */
+
+/* CEH defines */
+#define CEH_NORMAL_CE 0x00000001 /* do not force CE ON */
+
+/* ISR register defines */
+#define ISR_NAND_READY 0x00000001
+#define ISR_CONTROLLER_READY 0x00000002
+#define ISR_ECC_READY 0x00000004
+#define ISR_DECODER_ERRORS(s) ((((s) >> 4) & 3)+1)
+#define ISR_DECODER_FAILURE 0x00000040
+#define ISR_DECODER_ERROR 0x00000008
+
+/* time-out for NAND chip / controller loops, in us */
+#define LPC32X_NAND_TIMEOUT 5000
+
+/*
+ * There is a single instance of the NAND MLC controller
+ */
+
+static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers
+ = (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
+
+#define clkdiv(v, w, o) (((1+(clk/v)) & w) << o)
+
+/**
+ * OOB data in each small page are 6 'free' then 10 ECC bytes.
+ * To make things easier, when reading large pages, the four pages'
+ * 'free' OOB bytes are grouped in the first 24 bytes of the OOB buffer,
+ * while the the four ECC bytes are groupe in its last 40 bytes.
+ *
+ * The struct below represents how free vs ecc oob bytes are stored
+ * in the buffer.
+ *
+ * Note: the OOB bytes contain the bad block marker at offsets 0 and 1.
+ */
+
+struct lpc32xx_oob {
+ struct {
+ uint8_t free_oob_bytes[6];
+ } free[4];
+ struct {
+ uint8_t ecc_oob_bytes[10];
+ } ecc[4];
+};
+
+/*
+ * Initialize the controller
+ */
+
+static void lpc32xx_nand_init(void)
+{
+ unsigned int clk;
+
+ /* Configure controller for no software write protection, x8 bus
+ width, large block device, and 4 address words */
+
+ /* unlock controller registers with magic key */
+ writel(LOCK_PR_UNLOCK_KEY,
+ &lpc32xx_nand_mlc_registers->lock_pr);
+
+ /* enable large blocks and large NANDs */
+ writel(ICR_LARGE_BLOCKS | ICR_ADDR4,
+ &lpc32xx_nand_mlc_registers->icr);
+
+ /* Make sure MLC interrupts are disabled */
+ writel(0, &lpc32xx_nand_mlc_registers->irq_mr);
+
+ /* Normal chip enable operation */
+ writel(CEH_NORMAL_CE,
+ &lpc32xx_nand_mlc_registers->ceh);
+
+ /* Setup NAND timing */
+ clk = get_hclk_clk_rate();
+
+ writel(
+ clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) |
+ clkdiv(CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) |
+ clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) |
+ clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) |
+ clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) |
+ clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) |
+ clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0),
+ &lpc32xx_nand_mlc_registers->time_reg);
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+
+/**
+ * lpc32xx_cmd_ctrl - write command to either cmd or data register
+ */
+
+static void lpc32xx_cmd_ctrl(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
+{
+ if (cmd == NAND_CMD_NONE)
+ return;
+
+ if (ctrl & NAND_CLE)
+ writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->cmd);
+ else if (ctrl & NAND_ALE)
+ writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->addr);
+}
+
+/**
+ * lpc32xx_read_byte - read a byte from the NAND
+ * @mtd: MTD device structure
+ */
+
+static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
+{
+ return readb(&lpc32xx_nand_mlc_registers->data);
+}
+
+/**
+ * lpc32xx_dev_ready - test if NAND device (actually controller) is ready
+ * @mtd: MTD device structure
+ * @mode: mode to set the ECC HW to.
+ */
+
+static int lpc32xx_dev_ready(struct mtd_info *mtd)
+{
+ /* means *controller* ready for us */
+ int status = readl(&lpc32xx_nand_mlc_registers->isr);
+ return status & ISR_CONTROLLER_READY;
+}
+
+/**
+ * ECC layout -- this is needed whatever ECC mode we are using.
+ * In a 2KB (4*512B) page, R/S codes occupy 40 (4*10) bytes.
+ * To make U-Boot's life easier, we pack 'useable' OOB at the
+ * front and R/S ECC at the back.
+ */
+
+static struct nand_ecclayout lpc32xx_largepage_ecclayout = {
+ .eccbytes = 40,
+ .eccpos = {24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
+ 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
+ 44, 45, 46, 47, 48, 48, 50, 51, 52, 53,
+ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
+ },
+ .oobfree = {
+ /* bytes 0 and 1 are used for the bad block marker */
+ {
+ .offset = 2,
+ .length = 22
+ },
+ }
+};
+
+/**
+ * lpc32xx_read_page_hwecc - read in- and out-of-band data with ECC
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
+ * @page: page number to read
+ *
+ * Use large block Auto Decode Read Mode(1) as described in User Manual
+ * section 8.6.2.1.
+ *
+ * The initial Read Mode and Read Start commands are sent by the caller.
+ *
+ * ECC will be false if out-of-band data has been updated since in-band
+ * data was initially written.
+ */
+
+static int lpc32xx_read_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf, int oob_required,
+ int page)
+{
+ unsigned int i, status, timeout, err, max_bitflips = 0;
+ struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
+
+ /* go through all four small pages */
+ for (i = 0; i < 4; i++) {
+ /* start auto decode (reads 528 NAND bytes) */
+ writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
+ /* wait for controller to return to ready state */
+ for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
+ status = readl(&lpc32xx_nand_mlc_registers->isr);
+ if (status & ISR_CONTROLLER_READY)
+ break;
+ udelay(1);
+ }
+ /* if decoder failed, return failure */
+ if (status & ISR_DECODER_FAILURE)
+ return -1;
+ /* keep count of maximum bitflips performed */
+ if (status & ISR_DECODER_ERROR) {
+ err = ISR_DECODER_ERRORS(status);
+ if (err > max_bitflips)
+ max_bitflips = err;
+ }
+ /* copy first 512 bytes into buffer */
+ memcpy(buf+512*i, lpc32xx_nand_mlc_registers->buff, 512);
+ /* copy next 6 bytes at front of OOB buffer */
+ memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
+ /* copy last 10 bytes (R/S ECC) at back of OOB buffer */
+ memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10);
+ }
+ return max_bitflips;
+}
+
+/**
+ * lpc32xx_read_page_raw - read raw (in-band, out-of-band and ECC) data
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
+ * @page: page number to read
+ *
+ * Read NAND directly; can read pages with invalid ECC.
+ */
+
+static int lpc32xx_read_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf, int oob_required,
+ int page)
+{
+ unsigned int i, status, timeout;
+ struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
+
+ /* when we get here we've already had the Read Mode(1) */
+
+ /* go through all four small pages */
+ for (i = 0; i < 4; i++) {
+ /* wait for NAND to return to ready state */
+ for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
+ status = readl(&lpc32xx_nand_mlc_registers->isr);
+ if (status & ISR_NAND_READY)
+ break;
+ udelay(1);
+ }
+ /* if NAND stalled, return failure */
+ if (!(status & ISR_NAND_READY))
+ return -1;
+ /* copy first 512 bytes into buffer */
+ memcpy(buf+512*i, lpc32xx_nand_mlc_registers->data, 512);
+ /* copy next 6 bytes at front of OOB buffer */
+ memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->data, 6);
+ /* copy last 10 bytes (R/S ECC) at back of OOB buffer */
+ memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->data, 10);
+ }
+ return 0;
+}
+
+/**
+ * lpc32xx_read_oob - read out-of-band data
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to read
+ *
+ * Read out-of-band data. User Manual section 8.6.4 suggests using Read
+ * Mode(3) which the controller will turn into a Read Mode(1) internally
+ * but nand_base.c will turn Mode(3) into Mode(0), so let's use Mode(0)
+ * directly.
+ *
+ * ECC covers in- and out-of-band data and was written when out-of-band
+ * data was blank. Therefore, if the out-of-band being read here is not
+ * blank, then the ECC will be false and the read will return bitflips,
+ * even in case of ECC failure where we will return 5 bitflips. The
+ * caller should be prepared to handle this.
+ */
+
+static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ unsigned int i, status, timeout, err, max_bitflips = 0;
+ struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
+
+ /* No command was sent before calling read_oob() so send one */
+
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+
+ /* go through all four small pages */
+ for (i = 0; i < 4; i++) {
+ /* start auto decode (reads 528 NAND bytes) */
+ writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
+ /* wait for controller to return to ready state */
+ for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
+ status = readl(&lpc32xx_nand_mlc_registers->isr);
+ if (status & ISR_CONTROLLER_READY)
+ break;
+ udelay(1);
+ }
+ /* if decoder failure, count 'one too many' bitflips */
+ if (status & ISR_DECODER_FAILURE)
+ max_bitflips = 5;
+ /* keep count of maximum bitflips performed */
+ if (status & ISR_DECODER_ERROR) {
+ err = ISR_DECODER_ERRORS(status);
+ if (err > max_bitflips)
+ max_bitflips = err;
+ }
+ /* set read pointer to OOB area */
+ writel(0, &lpc32xx_nand_mlc_registers->robp);
+ /* copy next 6 bytes at front of OOB buffer */
+ memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
+ /* copy next 10 bytes (R/S ECC) at back of OOB buffer */
+ memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10);
+ }
+ return max_bitflips;
+}
+
+/**
+ * lpc32xx_write_page_hwecc - write in- and out-of-band data with ECC
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
+ *
+ * Use large block Auto Encode as per User Manual section 8.6.4.
+ *
+ * The initial Write Serial Input and final Auto Program commands are
+ * sent by the caller.
+ */
+
+static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf, int oob_required)
+{
+ unsigned int i, status, timeout;
+ struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
+
+ /* when we get here we've already had the SEQIN */
+ for (i = 0; i < 4; i++) {
+ /* start encode (expects 518 writes to buff) */
+ writel(0, &lpc32xx_nand_mlc_registers->ecc_enc_reg);
+ /* copy first 512 bytes from buffer */
+ memcpy(&lpc32xx_nand_mlc_registers->buff, buf+512*i, 512);
+ /* copy next 6 bytes from OOB buffer -- excluding ECC */
+ memcpy(&lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6);
+ /* wait for ECC to return to ready state */
+ for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
+ status = readl(&lpc32xx_nand_mlc_registers->isr);
+ if (status & ISR_ECC_READY)
+ break;
+ udelay(1);
+ }
+ /* if ECC stalled, return failure */
+ if (!(status & ISR_ECC_READY))
+ return -1;
+ /* Trigger auto encode (writes 528 bytes to NAND) */
+ writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_enc_reg);
+ /* wait for controller to return to ready state */
+ for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
+ status = readl(&lpc32xx_nand_mlc_registers->isr);
+ if (status & ISR_CONTROLLER_READY)
+ break;
+ udelay(1);
+ }
+ /* if controller stalled, return error */
+ if (!(status & ISR_CONTROLLER_READY))
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * lpc32xx_write_page_raw - write raw (in-band, out-of-band and ECC) data
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ * @oob_required: caller requires OOB data read to chip->oob_poi
+ * @page: page number to read
+ *
+ * Use large block write but without encode.
+ *
+ * The initial Write Serial Input and final Auto Program commands are
+ * sent by the caller.
+ *
+ * This function will write the full out-of-band data, including the
+ * ECC area. Therefore, it can write pages with valid *or* invalid ECC.
+ */
+
+static int lpc32xx_write_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf, int oob_required)
+{
+ unsigned int i;
+ struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
+
+ /* when we get here we've already had the Read Mode(1) */
+ for (i = 0; i < 4; i++) {
+ /* copy first 512 bytes from buffer */
+ memcpy(lpc32xx_nand_mlc_registers->buff, buf+512*i, 512);
+ /* copy next 6 bytes into OOB buffer -- excluding ECC */
+ memcpy(lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6);
+ /* copy next 10 bytes into OOB buffer -- that is 'ECC' */
+ memcpy(lpc32xx_nand_mlc_registers->buff, &oob->ecc[i], 10);
+ }
+ return 0;
+}
+
+/**
+ * lpc32xx_write_oob - write out-of-band data
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @page: page number to read
+ *
+ * Since ECC covers in- and out-of-band data, writing out-of-band data
+ * with ECC will render the page ECC wrong -- or, if the page was blank,
+ * then it will produce a good ECC but a later in-band data write will
+ * render it wrong.
+ *
+ * Therefore, do not compute or write any ECC, and always return success.
+ *
+ * This implies that we do four writes, since non-ECC out-of-band data
+ * are not contiguous in a large page.
+ */
+
+static int lpc32xx_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ /* update oob on all 4 subpages in sequence */
+ unsigned int i, status, timeout;
+ struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
+
+ for (i = 0; i < 4; i++) {
+ /* start data input */
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x200+0x210*i, page);
+ /* copy 6 non-ECC out-of-band bytes directly into NAND */
+ memcpy(lpc32xx_nand_mlc_registers->data, &oob->free[i], 6);
+ /* program page */
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+ /* wait for NAND to return to ready state */
+ for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
+ status = readl(&lpc32xx_nand_mlc_registers->isr);
+ if (status & ISR_NAND_READY)
+ break;
+ udelay(1);
+ }
+ /* if NAND stalled, return error */
+ if (!(status & ISR_NAND_READY))
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * lpc32xx_waitfunc - wait until a command is done
+ * @mtd: MTD device structure
+ * @chip: NAND chip structure
+ *
+ * Wait for controller and FLASH to both be ready.
+ */
+
+static int lpc32xx_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ int status;
+ unsigned int timeout;
+ /* wait until both controller and NAND are ready */
+ for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
+ status = readl(&lpc32xx_nand_mlc_registers->isr);
+ if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
+ == (ISR_CONTROLLER_READY || ISR_NAND_READY))
+ break;
+ udelay(1);
+ }
+ /* if controller or NAND stalled, return error */
+ if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
+ != (ISR_CONTROLLER_READY || ISR_NAND_READY))
+ return -1;
+ /* write NAND status command */
+ writel(NAND_CMD_STATUS, &lpc32xx_nand_mlc_registers->cmd);
+ /* read back status and return it */
+ return readb(&lpc32xx_nand_mlc_registers->data);
+}
+
+/*
+ * We are self-initializing, so we need our own chip struct
+ */
+
+static struct nand_chip lpc32xx_chip;
+
+/*
+ * Initialize the controller
+ */
+
+void board_nand_init(void)
+{
+ /* we have only one device anyway */
+ struct mtd_info *mtd = &nand_info[0];
+ /* chip is struct nand_chip, and is now provided by the driver. */
+ mtd->priv = &lpc32xx_chip;
+ /* to store return status in case we need to print it */
+ int ret;
+
+ /* Set all BOARDSPECIFIC (actually core-specific) fields */
+
+ lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff;
+ lpc32xx_chip.IO_ADDR_W = &lpc32xx_nand_mlc_registers->buff;
+ lpc32xx_chip.cmd_ctrl = lpc32xx_cmd_ctrl;
+ /* do not set init_size: nand_base.c will read sizes from chip */
+ lpc32xx_chip.dev_ready = lpc32xx_dev_ready;
+ /* do not set setup_read_retry: this is NAND-chip-specific */
+ /* do not set chip_delay: we have dev_ready defined. */
+ lpc32xx_chip.options |= NAND_NO_SUBPAGE_WRITE;
+
+ /* Set needed ECC fields */
+
+ lpc32xx_chip.ecc.mode = NAND_ECC_HW;
+ lpc32xx_chip.ecc.layout = &lpc32xx_largepage_ecclayout;
+ lpc32xx_chip.ecc.size = 512;
+ lpc32xx_chip.ecc.bytes = 10;
+ lpc32xx_chip.ecc.strength = 4;
+ lpc32xx_chip.ecc.read_page = lpc32xx_read_page_hwecc;
+ lpc32xx_chip.ecc.read_page_raw = lpc32xx_read_page_raw;
+ lpc32xx_chip.ecc.write_page = lpc32xx_write_page_hwecc;
+ lpc32xx_chip.ecc.write_page_raw = lpc32xx_write_page_raw;
+ lpc32xx_chip.ecc.read_oob = lpc32xx_read_oob;
+ lpc32xx_chip.ecc.write_oob = lpc32xx_write_oob;
+ lpc32xx_chip.waitfunc = lpc32xx_waitfunc;
+
+ lpc32xx_chip.read_byte = lpc32xx_read_byte; /* FIXME: NEEDED? */
+
+ /* BBT options: read from last two pages */
+ lpc32xx_chip.bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_LASTBLOCK
+ | NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE
+ | NAND_BBT_WRITE;
+
+ /* Initialize NAND interface */
+ lpc32xx_nand_init();
+
+ /* identify chip */
+ ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL);
+ if (ret) {
+ error("nand_scan_ident returned %i", ret);
+ return;
+ }
+
+ /* finish scanning the chip */
+ ret = nand_scan_tail(mtd);
+ if (ret) {
+ error("nand_scan_tail returned %i", ret);
+ return;
+ }
+
+ /* chip is good, register it */
+ ret = nand_register(0);
+ if (ret)
+ error("nand_register returned %i", ret);
+}
+
+#else /* defined(CONFIG_SPL_BUILD) */
+
+void nand_init(void)
+{
+ /* enable NAND controller */
+ lpc32xx_mlc_nand_init();
+ /* initialize NAND controller */
+ lpc32xx_nand_init();
+}
+
+void nand_deselect(void)
+{
+ /* nothing to do, but SPL requires this function */
+}
+
+static int read_single_page(uint8_t *dest, int page,
+ struct lpc32xx_oob *oob)
+{
+ int status, i, timeout, err, max_bitflips = 0;
+
+ /* enter read mode */
+ writel(NAND_CMD_READ0, &lpc32xx_nand_mlc_registers->cmd);
+ /* send column (lsb then MSB) and page (lsb to MSB) */
+ writel(0, &lpc32xx_nand_mlc_registers->addr);
+ writel(0, &lpc32xx_nand_mlc_registers->addr);
+ writel(page & 0xff, &lpc32xx_nand_mlc_registers->addr);
+ writel((page>>8) & 0xff, &lpc32xx_nand_mlc_registers->addr);
+ writel((page>>16) & 0xff, &lpc32xx_nand_mlc_registers->addr);
+ /* start reading */
+ writel(NAND_CMD_READSTART, &lpc32xx_nand_mlc_registers->cmd);
+
+ /* large page auto decode read */
+ for (i = 0; i < 4; i++) {
+ /* start auto decode (reads 528 NAND bytes) */
+ writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
+ /* wait for controller to return to ready state */
+ for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
+ status = readl(&lpc32xx_nand_mlc_registers->isr);
+ if (status & ISR_CONTROLLER_READY)
+ break;
+ udelay(1);
+ }
+ /* if controller stalled, return error */
+ if (!(status & ISR_CONTROLLER_READY))
+ return -1;
+ /* if decoder failure, return error */
+ if (status & ISR_DECODER_FAILURE)
+ return -1;
+ /* keep count of maximum bitflips performed */
+ if (status & ISR_DECODER_ERROR) {
+ err = ISR_DECODER_ERRORS(status);
+ if (err > max_bitflips)
+ max_bitflips = err;
+ }
+ /* copy first 512 bytes into buffer */
+ memcpy(dest+i*512, lpc32xx_nand_mlc_registers->buff, 512);
+ /* copy next 6 bytes bytes into OOB buffer */
+ memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
+ }
+ return max_bitflips;
+}
+
+/*
+ * Load U-Boot signed image.
+ * This loads an image from NAND, skipping bad blocks.
+ * A block is declared bad if at least one of its readable pages has
+ * a bad block marker in its OOB at position 0.
+ * If all pages ion a block are unreadable, the block is considered
+ * bad (i.e., assumed not to be part of the image) and skipped.
+ *
+ * IMPORTANT NOTE:
+ *
+ * If the first block of the image is fully unreadable, it will be
+ * ignored and skipped as if it had been marked bad. If it was not
+ * actually marked bad at the time of writing the image, the resulting
+ * image loaded will lack a header and magic number. It could thus be
+ * considered as a raw, headerless, image and SPL might erroneously
+ * jump into it.
+ *
+ * In order to avoid this risk, LPC32XX-based boards which use this
+ * driver MUST define CONFIG_SPL_PANIC_ON_RAW_IMAGE.
+ */
+
+#define BYTES_PER_PAGE 2048
+#define PAGES_PER_BLOCK 64
+#define BYTES_PER_BLOCK (BYTES_PER_PAGE * PAGES_PER_BLOCK)
+#define PAGES_PER_CHIP_MAX 524288
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+ int bytes_left = size;
+ int pages_left = DIV_ROUND_UP(size, BYTES_PER_PAGE);
+ int blocks_left = DIV_ROUND_UP(size, BYTES_PER_BLOCK);
+ int block = 0;
+ int page = offs / BYTES_PER_PAGE;
+ /* perform reads block by block */
+ while (blocks_left) {
+ /* compute first page number to read */
+ void *block_page_dst = dst;
+ /* read at most one block, possibly less */
+ int block_bytes_left = bytes_left;
+ if (block_bytes_left > BYTES_PER_BLOCK)
+ block_bytes_left = BYTES_PER_BLOCK;
+ /* keep track of good, failed, and "bad" pages */
+ int block_pages_good = 0;
+ int block_pages_bad = 0;
+ int block_pages_err = 0;
+ /* we shall read a full block of pages, maybe less */
+ int block_pages_left = pages_left;
+ if (block_pages_left > PAGES_PER_BLOCK)
+ block_pages_left = PAGES_PER_BLOCK;
+ int block_pages = block_pages_left;
+ int block_page = page;
+ /* while pages are left and the block is not known as bad */
+ while ((block_pages > 0) && (block_pages_bad == 0)) {
+ /* we will read OOB, too, for bad block markers */
+ struct lpc32xx_oob oob;
+ /* read page */
+ int res = read_single_page(block_page_dst, block_page,
+ &oob);
+ /* count readable pages */
+ if (res >= 0) {
+ /* this page is good */
+ block_pages_good++;
+ /* this page is bad */
+ if ((oob.free[0].free_oob_bytes[0] != 0xff)
+ | (oob.free[0].free_oob_bytes[1] != 0xff))
+ block_pages_bad++;
+ } else
+ /* count errors */
+ block_pages_err++;
+ /* we're done with this page */
+ block_page++;
+ block_page_dst += BYTES_PER_PAGE;
+ if (block_pages)
+ block_pages--;
+ }
+ /* a fully unreadable block is considered bad */
+ if (block_pages_good == 0)
+ block_pages_bad = block_pages_err;
+ /* errors are fatal only in good blocks */
+ if ((block_pages_err > 0) && (block_pages_bad == 0))
+ return -1;
+ /* we keep reads only of good blocks */
+ if (block_pages_bad == 0) {
+ dst += block_bytes_left;
+ bytes_left -= block_bytes_left;
+ pages_left -= block_pages_left;
+ blocks_left--;
+ }
+ /* good or bad, we're done with this block */
+ block++;
+ page += PAGES_PER_BLOCK;
+ }
+
+ /* report success */
+ return 0;
+}
+
+#endif /* CONFIG_SPL_BUILD */
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index 7233bfc127..e621c3665e 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -459,29 +459,6 @@ static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
mpc5121_nfc_buf_copy(mtd, (u_char *) buf, len, 1);
}
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-/* Compare buffer with NAND flash */
-static int mpc5121_nfc_verify_buf(struct mtd_info *mtd,
- const u_char * buf, int len)
-{
- u_char tmp[256];
- uint bsize;
-
- while (len) {
- bsize = min(len, 256);
- mpc5121_nfc_read_buf(mtd, tmp, bsize);
-
- if (memcmp(buf, tmp, bsize))
- return 1;
-
- buf += bsize;
- len -= bsize;
- }
-
- return 0;
-}
-#endif
-
/* Read byte from NFC buffers */
static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
{
@@ -609,9 +586,6 @@ int board_nand_init(struct nand_chip *chip)
chip->read_word = mpc5121_nfc_read_word;
chip->read_buf = mpc5121_nfc_read_buf;
chip->write_buf = mpc5121_nfc_write_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- chip->verify_buf = mpc5121_nfc_verify_buf;
-#endif
chip->select_chip = mpc5121_nfc_select_chip;
chip->bbt_options = NAND_BBT_USE_FLASH;
chip->ecc.mode = NAND_ECC_SOFT;
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 2e5b5b9bf9..f12b07e7ad 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -949,34 +949,6 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
host->col_addr = col;
}
-#ifdef __UBOOT__
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-/*
- * Used by the upper layer to verify the data in NAND Flash
- * with the data in the buf.
- */
-static int mxc_nand_verify_buf(struct mtd_info *mtd,
- const u_char *buf, int len)
-{
- u_char tmp[256];
- uint bsize;
-
- while (len) {
- bsize = min(len, 256);
- mxc_nand_read_buf(mtd, tmp, bsize);
-
- if (memcmp(buf, tmp, bsize))
- return 1;
-
- buf += bsize;
- len -= bsize;
- }
-
- return 0;
-}
-#endif
-#endif
-
/*
* This function is used by upper layer for select and
* deselect of the NAND chip
@@ -1207,11 +1179,6 @@ int board_nand_init(struct nand_chip *this)
this->read_word = mxc_nand_read_word;
this->write_buf = mxc_nand_write_buf;
this->read_buf = mxc_nand_read_buf;
-#ifdef __UBOOT__
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- this->verify_buf = mxc_nand_verify_buf;
-#endif
-#endif
host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
#ifdef MXC_NFC_V3_2
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 7a064ab1bf..2d2b938633 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -453,7 +453,7 @@ static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
d->cmd.data =
MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
- MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
+ MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
d->cmd.address = 0;
@@ -510,7 +510,7 @@ static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
d->cmd.data =
MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
- (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
+ (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
(length << MXS_DMA_DESC_BYTES_OFFSET);
d->cmd.address = (dma_addr_t)nand_info->data_buf;
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 6db6566e73..c0e381ad2d 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -361,51 +361,6 @@ void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
ioread8_rep(chip->IO_ADDR_R, buf, len);
}
-#ifdef __UBOOT__
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-/**
- * nand_verify_buf - [DEFAULT] Verify chip data against buffer
- * @mtd: MTD device structure
- * @buf: buffer containing the data to compare
- * @len: number of bytes to compare
- *
- * Default verify function for 8bit buswidth.
- */
-static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
-
- for (i = 0; i < len; i++)
- if (buf[i] != readb(chip->IO_ADDR_R))
- return -EFAULT;
- return 0;
-}
-
-/**
- * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
- * @mtd: MTD device structure
- * @buf: buffer containing the data to compare
- * @len: number of bytes to compare
- *
- * Default verify function for 16bit buswidth.
- */
-static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
- u16 *p = (u16 *) buf;
- len >>= 1;
-
- for (i = 0; i < len; i++)
- if (p[i] != readw(chip->IO_ADDR_R))
- return -EFAULT;
-
- return 0;
-}
-#endif
-#endif
-
/**
* nand_write_buf16 - [DEFAULT] write buffer to chip
* @mtd: MTD device structure
@@ -2435,20 +2390,6 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
status = chip->waitfunc(mtd, chip);
}
-
-#ifdef __UBOOT__
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- /* Send command to read back the data */
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
-
- if (chip->verify_buf(mtd, buf, mtd->writesize))
- return -EIO;
-
- /* Make sure the next page prog is preceded by a status read */
- chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
-#endif
-#endif
-
return 0;
}
@@ -3139,12 +3080,6 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
if (!chip->scan_bbt)
chip->scan_bbt = nand_default_bbt;
-#ifdef __UBOOT__
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- if (!chip->verify_buf)
- chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
-#endif
-#endif
if (!chip->controller) {
chip->controller = &chip->hwcontrol;
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index afdd160d81..12dd26a33f 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -464,6 +464,87 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
#endif
/**
+ * nand_verify_page_oob:
+ *
+ * Verify a page of NAND flash, including the OOB.
+ * Reads page of NAND and verifies the contents and OOB against the
+ * values in ops.
+ *
+ * @param nand NAND device
+ * @param ops MTD operations, including data to verify
+ * @param ofs offset in flash
+ * @return 0 in case of success
+ */
+int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs)
+{
+ int rval;
+ struct mtd_oob_ops vops;
+ size_t verlen = nand->writesize + nand->oobsize;
+
+ memcpy(&vops, ops, sizeof(vops));
+
+ vops.datbuf = malloc(verlen);
+
+ if (!vops.datbuf)
+ return -ENOMEM;
+
+ vops.oobbuf = vops.datbuf + nand->writesize;
+
+ rval = mtd_read_oob(nand, ofs, &vops);
+ if (!rval)
+ rval = memcmp(ops->datbuf, vops.datbuf, vops.len);
+ if (!rval)
+ rval = memcmp(ops->oobbuf, vops.oobbuf, vops.ooblen);
+
+ free(vops.datbuf);
+
+ return rval ? -EIO : 0;
+}
+
+/**
+ * nand_verify:
+ *
+ * Verify a region of NAND flash.
+ * Reads NAND in page-sized chunks and verifies the contents against
+ * the contents of a buffer. The offset into the NAND must be
+ * page-aligned, and the function doesn't handle skipping bad blocks.
+ *
+ * @param nand NAND device
+ * @param ofs offset in flash
+ * @param len buffer length
+ * @param buf buffer to read from
+ * @return 0 in case of success
+ */
+int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf)
+{
+ int rval = 0;
+ size_t verofs;
+ size_t verlen = nand->writesize;
+ uint8_t *verbuf = malloc(verlen);
+
+ if (!verbuf)
+ return -ENOMEM;
+
+ /* Read the NAND back in page-size groups to limit malloc size */
+ for (verofs = ofs; verofs < ofs + len;
+ verofs += verlen, buf += verlen) {
+ verlen = min(nand->writesize, (uint32_t)(ofs + len - verofs));
+ rval = nand_read(nand, verofs, &verlen, verbuf);
+ if (!rval || (rval == -EUCLEAN))
+ rval = memcmp(buf, verbuf, verlen);
+
+ if (rval)
+ break;
+ }
+
+ free(verbuf);
+
+ return rval ? -EIO : 0;
+}
+
+
+
+/**
* nand_write_skip_bad:
*
* Write image to NAND flash.
@@ -499,24 +580,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
if (actual)
*actual = 0;
-#ifdef CONFIG_CMD_NAND_YAFFS
- if (flags & WITH_YAFFS_OOB) {
- if (flags & ~WITH_YAFFS_OOB)
- return -EINVAL;
-
- int pages;
- pages = nand->erasesize / nand->writesize;
- blocksize = (pages * nand->oobsize) + nand->erasesize;
- if (*length % (nand->writesize + nand->oobsize)) {
- printf("Attempt to write incomplete page"
- " in yaffs mode\n");
- return -EINVAL;
- }
- } else
-#endif
- {
- blocksize = nand->erasesize;
- }
+ blocksize = nand->erasesize;
/*
* nand_write() handles unaligned, partial page writes.
@@ -554,6 +618,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
if (!need_skip && !(flags & WITH_DROP_FFS)) {
rval = nand_write(nand, offset, length, buffer);
+
+ if ((flags & WITH_WR_VERIFY) && !rval)
+ rval = nand_verify(nand, offset, *length, buffer);
+
if (rval == 0)
return 0;
@@ -581,48 +649,22 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
else
write_size = blocksize - block_offset;
-#ifdef CONFIG_CMD_NAND_YAFFS
- if (flags & WITH_YAFFS_OOB) {
- int page, pages;
- size_t pagesize = nand->writesize;
- size_t pagesize_oob = pagesize + nand->oobsize;
- struct mtd_oob_ops ops;
-
- ops.len = pagesize;
- ops.ooblen = nand->oobsize;
- ops.mode = MTD_OPS_AUTO_OOB;
- ops.ooboffs = 0;
-
- pages = write_size / pagesize_oob;
- for (page = 0; page < pages; page++) {
- WATCHDOG_RESET();
-
- ops.datbuf = p_buffer;
- ops.oobbuf = ops.datbuf + pagesize;
-
- rval = mtd_write_oob(nand, offset, &ops);
- if (rval != 0)
- break;
-
- offset += pagesize;
- p_buffer += pagesize_oob;
- }
- }
- else
-#endif
- {
- truncated_write_size = write_size;
+ truncated_write_size = write_size;
#ifdef CONFIG_CMD_NAND_TRIMFFS
- if (flags & WITH_DROP_FFS)
- truncated_write_size = drop_ffs(nand, p_buffer,
- &write_size);
+ if (flags & WITH_DROP_FFS)
+ truncated_write_size = drop_ffs(nand, p_buffer,
+ &write_size);
#endif
- rval = nand_write(nand, offset, &truncated_write_size,
- p_buffer);
- offset += write_size;
- p_buffer += write_size;
- }
+ rval = nand_write(nand, offset, &truncated_write_size,
+ p_buffer);
+
+ if ((flags & WITH_WR_VERIFY) && !rval)
+ rval = nand_verify(nand, offset,
+ truncated_write_size, p_buffer);
+
+ offset += write_size;
+ p_buffer += write_size;
if (rval != 0) {
printf("NAND write to offset %llx failed %d\n",
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 265959502d..8a68cb0a67 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -118,21 +118,6 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
out_be32((u32 *)(base + NDFC_DATA), *p++);
}
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
-static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
- struct nand_chip *this = mtdinfo->priv;
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- uint32_t *p = (uint32_t *) buf;
-
- for (; len > 0; len -= 4)
- if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
- return -1;
-
- return 0;
-}
-#endif
-
/*
* Read a byte from the NDFC.
*/
@@ -207,9 +192,6 @@ int board_nand_init(struct nand_chip *nand)
#endif
nand->write_buf = ndfc_write_buf;
-#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
- nand->verify_buf = ndfc_verify_buf;
-#endif
nand->read_byte = ndfc_read_byte;
chip++;
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index 928d58b3a7..d98dd28800 100644
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -146,6 +146,7 @@ struct vf610_nfc {
void __iomem *regs;
uint column;
int spareonly;
+ int page_sz;
int page;
/* Status and ID are in alternate locations. */
int alt_buf;
@@ -329,6 +330,11 @@ static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
ROW_ADDR_SHIFT, page);
}
+static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
+{
+ __raw_writel(size, regbase + NFC_SECTOR_SIZE);
+}
+
/* Send command to NAND chip */
static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
int column, int page)
@@ -342,12 +348,14 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
switch (command) {
case NAND_CMD_PAGEPROG:
nfc->page = -1;
+ vf610_nfc_transfer_size(nfc->regs, nfc->page_sz);
vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
command, PROGRAM_PAGE_CMD_CODE);
vf610_nfc_addr_cycle(mtd, column, page);
break;
case NAND_CMD_RESET:
+ vf610_nfc_transfer_size(nfc->regs, 0);
vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
break;
/*
@@ -363,14 +371,15 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
if (nfc->page == page)
return;
nfc->page = page;
+ vf610_nfc_transfer_size(nfc->regs, nfc->page_sz);
vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
vf610_nfc_addr_cycle(mtd, column, page);
break;
case NAND_CMD_ERASE1:
- if (nfc->page == page)
- nfc->page = -1;
+ nfc->page = -1;
+ vf610_nfc_transfer_size(nfc->regs, 0);
vf610_nfc_send_commands(nfc->regs, command,
NAND_CMD_ERASE2, ERASE_CMD_CODE);
vf610_nfc_addr_cycle(mtd, column, page);
@@ -378,11 +387,13 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
case NAND_CMD_READID:
nfc->alt_buf = ALT_BUF_ID;
+ vf610_nfc_transfer_size(nfc->regs, 0);
vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
break;
case NAND_CMD_STATUS:
nfc->alt_buf = ALT_BUF_STAT;
+ vf610_nfc_transfer_size(nfc->regs, 0);
vf610_nfc_send_command(nfc->regs, command,
STATUS_READ_CMD_CODE);
break;
@@ -580,7 +591,6 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
struct nand_chip *chip;
struct vf610_nfc *nfc;
int err = 0;
- int page_sz;
struct vf610_nfc_config cfg = {
.hardware_ecc = 1,
#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
@@ -634,9 +644,8 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
chip->bbt_td = &bbt_main_descr;
chip->bbt_md = &bbt_mirror_descr;
- page_sz = PAGE_2K + OOB_64;
- page_sz += cfg.width == 16 ? 1 : 0;
- vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz);
+ nfc->page_sz = PAGE_2K + OOB_64;
+ nfc->page_sz += cfg.width == 16 ? 1 : 0;
/* Set configuration register. */
vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
@@ -665,16 +674,15 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
chip->ecc.mode = NAND_ECC_SOFT; /* default */
- page_sz = mtd->writesize + mtd->oobsize;
+ nfc->page_sz = mtd->writesize + mtd->oobsize;
/* Single buffer only, max 256 OOB minus ECC status */
- if (page_sz > PAGE_2K + 256 - 8) {
+ if (nfc->page_sz > PAGE_2K + 256 - 8) {
dev_err(nfc->dev, "Unsupported flash size\n");
err = -ENXIO;
goto error;
}
- page_sz += cfg.width == 16 ? 1 : 0;
- vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz);
+ nfc->page_sz += cfg.width == 16 ? 1 : 0;
if (cfg.hardware_ecc) {
if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
generated by cgit (git 2.34.1) at 2025-01-16 15:50:01 +0000