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-rw-r--r--drivers/mtd/spi/sf_internal.h5
-rw-r--r--drivers/mtd/spi/sf_ops.c138
-rw-r--r--drivers/mtd/spi/sf_params.c5
-rw-r--r--drivers/mtd/spi/sf_probe.c67
4 files changed, 115 insertions, 100 deletions
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 9c95d5616e..8a3e5ec3d7 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -51,6 +51,11 @@ enum {
#define SST_WR (SST_BP | SST_WP)
+enum spi_nor_option_flags {
+ SNOR_F_SST_WR = (1 << 0),
+ SNOR_F_USE_FSR = (1 << 1),
+};
+
#define SPI_FLASH_3B_ADDR_LEN 3
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN 0x1000000
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 900ec1f2a9..f2a9244a14 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -41,6 +41,20 @@ int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
return 0;
}
+static int read_fsr(struct spi_flash *flash, u8 *fsr)
+{
+ int ret;
+ const u8 cmd = CMD_FLAG_STATUS;
+
+ ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1);
+ if (ret < 0) {
+ debug("SF: fail to read flag status register\n");
+ return ret;
+ }
+
+ return 0;
+}
+
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws)
{
u8 cmd;
@@ -95,15 +109,14 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
#endif
#ifdef CONFIG_SPI_FLASH_BAR
-static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
+static int spi_flash_write_bank(struct spi_flash *flash, u32 offset)
{
- u8 cmd;
+ u8 cmd, bank_sel;
int ret;
- if (flash->bank_curr == bank_sel) {
- debug("SF: not require to enable bank%d\n", bank_sel);
- return 0;
- }
+ bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
+ if (bank_sel == flash->bank_curr)
+ goto bar_end;
cmd = flash->bank_write_cmd;
ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
@@ -111,25 +124,10 @@ static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
debug("SF: fail to write bank register\n");
return ret;
}
- flash->bank_curr = bank_sel;
-
- return 0;
-}
-
-static int spi_flash_bank(struct spi_flash *flash, u32 offset)
-{
- u8 bank_sel;
- int ret;
- bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
-
- ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
- if (ret) {
- debug("SF: fail to set bank%d\n", bank_sel);
- return ret;
- }
-
- return bank_sel;
+bar_end:
+ flash->bank_curr = bank_sel;
+ return flash->bank_curr;
}
#endif
@@ -155,72 +153,65 @@ static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
}
#endif
-static int spi_flash_poll_status(struct spi_slave *spi, unsigned long timeout,
- u8 cmd, u8 poll_bit)
+static int spi_flash_sr_ready(struct spi_flash *flash)
{
- unsigned long timebase;
- unsigned long flags = SPI_XFER_BEGIN;
+ u8 sr;
int ret;
- u8 status;
- u8 check_status = 0x0;
- if (cmd == CMD_FLAG_STATUS)
- check_status = poll_bit;
-
-#ifdef CONFIG_SF_DUAL_FLASH
- if (spi->flags & SPI_XFER_U_PAGE)
- flags |= SPI_XFER_U_PAGE;
-#endif
- ret = spi_xfer(spi, 8, &cmd, NULL, flags);
- if (ret) {
- debug("SF: fail to read %s status register\n",
- cmd == CMD_READ_STATUS ? "read" : "flag");
+ ret = spi_flash_cmd_read_status(flash, &sr);
+ if (ret < 0)
return ret;
- }
- timebase = get_timer(0);
- do {
- WATCHDOG_RESET();
+ return !(sr & STATUS_WIP);
+}
- ret = spi_xfer(spi, 8, NULL, &status, 0);
- if (ret)
- return -1;
+static int spi_flash_fsr_ready(struct spi_flash *flash)
+{
+ u8 fsr;
+ int ret;
- if ((status & poll_bit) == check_status)
- break;
+ ret = read_fsr(flash, &fsr);
+ if (ret < 0)
+ return ret;
- } while (get_timer(timebase) < timeout);
+ return fsr & STATUS_PEC;
+}
- spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
+static int spi_flash_ready(struct spi_flash *flash)
+{
+ int sr, fsr;
- if ((status & poll_bit) == check_status)
- return 0;
+ sr = spi_flash_sr_ready(flash);
+ if (sr < 0)
+ return sr;
- /* Timed out */
- debug("SF: time out!\n");
- return -1;
+ fsr = 1;
+ if (flash->flags & SNOR_F_USE_FSR) {
+ fsr = spi_flash_fsr_ready(flash);
+ if (fsr < 0)
+ return fsr;
+ }
+
+ return sr && fsr;
}
int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
{
- struct spi_slave *spi = flash->spi;
- int ret;
- u8 poll_bit = STATUS_WIP;
- u8 cmd = CMD_READ_STATUS;
+ int timebase, ret;
- ret = spi_flash_poll_status(spi, timeout, cmd, poll_bit);
- if (ret < 0)
- return ret;
+ timebase = get_timer(0);
- if (flash->poll_cmd == CMD_FLAG_STATUS) {
- poll_bit = STATUS_PEC;
- cmd = CMD_FLAG_STATUS;
- ret = spi_flash_poll_status(spi, timeout, cmd, poll_bit);
+ while (get_timer(timebase) < timeout) {
+ ret = spi_flash_ready(flash);
if (ret < 0)
return ret;
+ if (ret)
+ return 0;
}
- return 0;
+ printf("SF: Timeout!\n");
+
+ return -ETIMEDOUT;
}
int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
@@ -285,7 +276,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
spi_flash_dual_flash(flash, &erase_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_bank(flash, erase_addr);
+ ret = spi_flash_write_bank(flash, erase_addr);
if (ret < 0)
return ret;
#endif
@@ -327,7 +318,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
spi_flash_dual_flash(flash, &write_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- ret = spi_flash_bank(flash, write_addr);
+ ret = spi_flash_write_bank(flash, write_addr);
if (ret < 0)
return ret;
#endif
@@ -422,9 +413,10 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
spi_flash_dual_flash(flash, &read_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
- bank_sel = spi_flash_bank(flash, read_addr);
- if (bank_sel < 0)
+ ret = spi_flash_write_bank(flash, read_addr);
+ if (ret < 0)
return ret;
+ bank_sel = flash->bank_curr;
#endif
remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
(bank_sel + 1)) - offset;
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 8f5bdda3d7..4f37e33eb0 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -35,6 +35,11 @@ const struct spi_flash_params spi_flash_params_table[] = {
{"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
{"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
#endif
+#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
+ {"IS25LP032", 0x9d6016, 0x0, 64 * 1024, 64, RD_NORM, 0},
+ {"IS25LP064", 0x9d6017, 0x0, 64 * 1024, 128, RD_NORM, 0},
+ {"IS25LP128", 0x9d6018, 0x0, 64 * 1024, 256, RD_NORM, 0},
+#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
{"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0},
{"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0},
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 3bf03f7a0a..c000c53274 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -99,6 +99,37 @@ static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
}
}
+#ifdef CONFIG_SPI_FLASH_BAR
+static int spi_flash_read_bank(struct spi_flash *flash, u8 idcode0)
+{
+ u8 curr_bank = 0;
+ int ret;
+
+ if (flash->size <= SPI_FLASH_16MB_BOUN)
+ goto bank_end;
+
+ switch (idcode0) {
+ case SPI_FLASH_CFI_MFR_SPANSION:
+ flash->bank_read_cmd = CMD_BANKADDR_BRRD;
+ flash->bank_write_cmd = CMD_BANKADDR_BRWR;
+ default:
+ flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
+ flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
+ }
+
+ ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
+ &curr_bank, 1);
+ if (ret) {
+ debug("SF: fail to read bank addr register\n");
+ return ret;
+ }
+
+bank_end:
+ flash->bank_curr = curr_bank;
+ return 0;
+}
+#endif
+
static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
struct spi_flash *flash)
{
@@ -132,15 +163,15 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
flash->name = params->name;
flash->memory_map = spi->memory_map;
flash->dual_flash = flash->spi->option;
-#ifdef CONFIG_DM_SPI_FLASH
- flash->flags = params->flags;
-#endif
/* Assign spi_flash ops */
#ifndef CONFIG_DM_SPI_FLASH
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
- if (params->flags & SST_WR) {
+ if (params->flags & SST_WR)
+ flash->flags |= SNOR_F_SST_WR;
+
+ if (params->flags & SNOR_F_SST_WR) {
if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
flash->write = sst_write_bp;
else
@@ -226,34 +257,16 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
flash->dummy_byte = 1;
}
- /* Poll cmd selection */
- flash->poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
if (params->flags & E_FSR)
- flash->poll_cmd = CMD_FLAG_STATUS;
+ flash->flags |= SNOR_F_USE_FSR;
#endif
/* Configure the BAR - discover bank cmds and read current bank */
#ifdef CONFIG_SPI_FLASH_BAR
- u8 curr_bank = 0;
- if (flash->size > SPI_FLASH_16MB_BOUN) {
- int ret;
-
- flash->bank_read_cmd = (idcode[0] == 0x01) ?
- CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
- flash->bank_write_cmd = (idcode[0] == 0x01) ?
- CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
-
- ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
- &curr_bank, 1);
- if (ret) {
- debug("SF: fail to read bank addr register\n");
- return ret;
- }
- flash->bank_curr = curr_bank;
- } else {
- flash->bank_curr = curr_bank;
- }
+ int ret = spi_flash_read_bank(flash, idcode[0]);
+ if (ret < 0)
+ return ret;
#endif
/* Flash powers up read-only, so clear BP# bits */
@@ -451,7 +464,7 @@ int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
struct spi_flash *flash = dev_get_uclass_priv(dev);
#if defined(CONFIG_SPI_FLASH_SST)
- if (flash->flags & SST_WR) {
+ if (flash->flags & SNOR_F_SST_WR) {
if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
return sst_write_bp(flash, offset, len, buf);
else
generated by cgit (git 2.34.1) at 2024-12-27 10:21:35 +0000