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-rw-r--r--drivers/mtd/cfi_flash.c22
-rw-r--r--drivers/mtd/nand/nand_base.c13
-rw-r--r--drivers/mtd/nand/nand_ecc.c1
-rw-r--r--drivers/mtd/nand/tegra_nand.c36
-rw-r--r--drivers/mtd/ubi/crc32.c12
5 files changed, 59 insertions, 25 deletions
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 43140f3647..b2dfc5369d 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -752,8 +752,8 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
*/
static flash_sect_t find_sector (flash_info_t * info, ulong addr)
{
- static flash_sect_t saved_sector = 0; /* previously found sector */
- static flash_info_t *saved_info = 0; /* previously used flash bank */
+ static flash_sect_t saved_sector; /* previously found sector */
+ static flash_info_t *saved_info; /* previously used flash bank */
flash_sect_t sector = saved_sector;
if ((info != saved_info) || (sector >= info->sector_count))
@@ -1147,8 +1147,9 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
}
if (use_flash_status_poll(info)) {
- cfiword_t cword = (cfiword_t)0xffffffffffffffffULL;
+ cfiword_t cword;
void *dest;
+ cword.ll = 0xffffffffffffffffULL;
dest = flash_map(info, sect, 0);
st = flash_status_poll(info, &cword, dest,
info->erase_blk_tout, "erase");
@@ -1430,8 +1431,8 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot)
{
- if ((info->manufacturer_id == (uchar)INTEL_MANUFACT) &&
- (info->device_id == NUMONYX_256MBIT)) {
+ if (info->manufacturer_id == ((INTEL_MANUFACT & FLASH_VENDMASK) >> 16)
+ && info->device_id == NUMONYX_256MBIT) {
/*
* see errata called
* "Numonyx Axcell P33/P30 Specification Update" :)
@@ -1487,7 +1488,8 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
case CFI_CMDSET_AMD_EXTENDED:
case CFI_CMDSET_AMD_STANDARD:
/* U-Boot only checks the first byte */
- if (info->manufacturer_id == (uchar)ATM_MANUFACT) {
+ if (info->manufacturer_id ==
+ ((ATM_MANUFACT & FLASH_VENDMASK) >> 16)) {
if (prot) {
flash_unlock_seq (info, 0);
flash_write_cmd (info, 0,
@@ -1505,7 +1507,8 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
0, ATM_CMD_UNLOCK_SECT);
}
}
- if (info->manufacturer_id == (uchar)AMD_MANUFACT) {
+ if (info->manufacturer_id ==
+ ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) {
int flag = disable_interrupts();
int lock_flag;
@@ -1735,7 +1738,8 @@ static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
#ifdef CONFIG_SYS_FLASH_PROTECTION
- if (info->ext_addr && info->manufacturer_id == (uchar)AMD_MANUFACT) {
+ if (info->ext_addr && info->manufacturer_id ==
+ ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) {
ushort spus;
/* read sector protect/unprotect scheme */
@@ -1854,7 +1858,7 @@ static void flash_read_cfi (flash_info_t *info, void *buf,
p[i] = flash_read_uchar(info, start + i);
}
-void __flash_cmd_reset(flash_info_t *info)
+static void __flash_cmd_reset(flash_info_t *info)
{
/*
* We do not yet know what kind of commandset to use, so we issue
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 71f5027889..d3b71a50ad 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2601,6 +2601,7 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
int *maf_id, int *dev_id,
const struct nand_flash_dev *type)
{
+ const char *name;
int i, maf_idx;
u8 id_data[8];
int ret;
@@ -2848,14 +2849,14 @@ ident_done:
chip->cmdfunc = nand_command_lp;
/* TODO onfi flash name */
- MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
- " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
- nand_manuf_ids[maf_idx].name,
+ name = type->name;
#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
- chip->onfi_version ? chip->onfi_params.model : type->name);
-#else
- type->name);
+ if (chip->onfi_version)
+ name = chip->onfi_params.model;
#endif
+ MTDDEBUG(MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
+ " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
+ nand_manuf_ids[maf_idx].name, name);
return type;
}
diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c
index 81f0e0812b..097cf625b8 100644
--- a/drivers/mtd/nand/nand_ecc.c
+++ b/drivers/mtd/nand/nand_ecc.c
@@ -39,6 +39,7 @@
#include <asm/errno.h>
#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand_ecc.h>
/* The PPC4xx NDFC uses Smart Media (SMC) bytes order */
#ifdef CONFIG_NAND_NDFC
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index 5408c51ffb..4d94cc6f56 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -219,6 +219,34 @@ static uint8_t read_byte(struct mtd_info *mtd)
}
/**
+ * Read len bytes from the chip into a buffer
+ *
+ * @param mtd MTD device structure
+ * @param buf buffer to store data to
+ * @param len number of bytes to read
+ *
+ * Read function for 8bit bus-width
+ */
+static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ int i, s;
+ unsigned int reg;
+ struct nand_chip *chip = mtd->priv;
+ struct nand_drv *info = (struct nand_drv *)chip->priv;
+
+ for (i = 0; i < len; i += 4) {
+ s = (len - i) > 4 ? 4 : len - i;
+ writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
+ ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
+ &info->reg->command);
+ if (!nand_waitfor_cmd_completion(info->reg))
+ puts("Command timeout during read_buf\n");
+ reg = readl(&info->reg->resp);
+ memcpy(buf + i, &reg, s);
+ }
+}
+
+/**
* Check NAND status to see if it is ready or not
*
* @param mtd MTD device structure
@@ -317,6 +345,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
switch (command) {
case NAND_CMD_READID:
writel(NAND_CMD_READID, &info->reg->cmd_reg1);
+ writel(column & 0xFF, &info->reg->addr_reg1);
writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
| CMD_RX |
((4 - 1) << CMD_TRANS_SIZE_SHIFT)
@@ -324,6 +353,12 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
&info->reg->command);
info->pio_byte_index = 0;
break;
+ case NAND_CMD_PARAM:
+ writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
+ writel(column & 0xFF, &info->reg->addr_reg1);
+ writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
+ &info->reg->command);
+ break;
case NAND_CMD_READ0:
writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
@@ -976,6 +1011,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum)
nand->options = LP_OPTIONS;
nand->cmdfunc = nand_command;
nand->read_byte = read_byte;
+ nand->read_buf = read_buf;
nand->ecc.read_page = nand_read_page_hwecc;
nand->ecc.write_page = nand_write_page_hwecc;
nand->ecc.read_page_raw = nand_read_page_raw;
diff --git a/drivers/mtd/ubi/crc32.c b/drivers/mtd/ubi/crc32.c
index a7e26b0456..ab439b3e20 100644
--- a/drivers/mtd/ubi/crc32.c
+++ b/drivers/mtd/ubi/crc32.c
@@ -38,17 +38,9 @@
#include "crc32defs.h"
#define CRC_LE_BITS 8
-# define __force
-#ifndef __constant_cpu_to_le32
-#define __constant_cpu_to_le32(x) ((__force __le32)(__u32)(x))
-#endif
-#ifndef __constant_le32_to_cpu
-#define __constant_le32_to_cpu(x) ((__force __u32)(__le32)(x))
-#endif
-
#if CRC_LE_BITS == 8
-#define tole(x) __constant_cpu_to_le32(x)
-#define tobe(x) __constant_cpu_to_be32(x)
+#define tole(x) cpu_to_le32(x)
+#define tobe(x) cpu_to_be32(x)
#else
#define tole(x) (x)
#define tobe(x) (x)
generated by cgit (git 2.34.1) at 2025-01-19 15:10:45 +0000