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-rw-r--r--drivers/mtd/nand/mxs_nand.c4
-rw-r--r--drivers/mtd/nand/nand.c17
-rw-r--r--drivers/mtd/nand/vf610_nfc.c5
-rw-r--r--drivers/mtd/spi/sf-uclass.c15
-rw-r--r--drivers/mtd/spi/sf_internal.h55
-rw-r--r--drivers/mtd/spi/sf_probe.c2
-rw-r--r--drivers/mtd/spi/spi_flash.c194
-rw-r--r--drivers/mtd/ubi/build.c1
8 files changed, 175 insertions, 118 deletions
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index f15cf36c88..ba019a0763 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -30,7 +30,7 @@
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
-#if defined(CONFIG_MX6)
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
#else
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
@@ -152,7 +152,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
int max_ecc_strength_supported;
/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
- if (is_cpu_type(MXC_CPU_MX6SX))
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
max_ecc_strength_supported = 62;
else
max_ecc_strength_supported = 40;
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 4cf4c1c707..8f0a9210ec 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -3,22 +3,7 @@
* 2N Telekomunikace, a.s. <www.2n.cz>
* Ladislav Michl <michl@2n.cz>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index 06266f3cbd..1faec5e1f2 100644
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -12,10 +12,7 @@
*
* Based on original driver mpc5121_nfc.c.
*
- * This is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*
* Limitations:
* - Untested on MPC5125 and M54418.
diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c
index 72e0f6b3fb..19de964e61 100644
--- a/drivers/mtd/spi/sf-uclass.c
+++ b/drivers/mtd/spi/sf-uclass.c
@@ -46,7 +46,7 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
void spi_flash_free(struct spi_flash *flash)
{
- spi_flash_remove(flash->spi->dev);
+ device_remove(flash->spi->dev);
}
int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
@@ -55,11 +55,17 @@ int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
{
struct spi_slave *slave;
struct udevice *bus;
- char name[30], *str;
+ char *str;
int ret;
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_TINY_PRINTF)
+ str = "spi_flash";
+#else
+ char name[30];
+
snprintf(name, sizeof(name), "spi_flash@%d:%d", busnum, cs);
str = strdup(name);
+#endif
ret = spi_get_bus_and_cs(busnum, cs, max_hz, spi_mode,
"spi_flash_std", str, &bus, &slave);
if (ret)
@@ -69,11 +75,6 @@ int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
return 0;
}
-int spi_flash_remove(struct udevice *dev)
-{
- return device_remove(dev);
-}
-
static int spi_flash_post_bind(struct udevice *dev)
{
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index ed5c391dc2..007a5a085c 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -16,18 +16,18 @@
/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
enum spi_dual_flash {
SF_SINGLE_FLASH = 0,
- SF_DUAL_STACKED_FLASH = 1 << 0,
- SF_DUAL_PARALLEL_FLASH = 1 << 1,
+ SF_DUAL_STACKED_FLASH = BIT(0),
+ SF_DUAL_PARALLEL_FLASH = BIT(1),
};
/* Enum list - Full read commands */
enum spi_read_cmds {
- ARRAY_SLOW = 1 << 0,
- ARRAY_FAST = 1 << 1,
- DUAL_OUTPUT_FAST = 1 << 2,
- DUAL_IO_FAST = 1 << 3,
- QUAD_OUTPUT_FAST = 1 << 4,
- QUAD_IO_FAST = 1 << 5,
+ ARRAY_SLOW = BIT(0),
+ ARRAY_FAST = BIT(1),
+ DUAL_OUTPUT_FAST = BIT(2),
+ QUAD_OUTPUT_FAST = BIT(3),
+ DUAL_IO_FAST = BIT(4),
+ QUAD_IO_FAST = BIT(5),
};
/* Normal - Extended - Full command set */
@@ -37,20 +37,20 @@ enum spi_read_cmds {
/* sf param flags */
enum {
-#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
- SECT_4K = 1 << 0,
+#ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS
+ SECT_4K = 0,
#else
- SECT_4K = 0 << 0,
+ SECT_4K = BIT(0),
#endif
- SECT_32K = 1 << 1,
- E_FSR = 1 << 2,
- SST_WR = 1 << 3,
- WR_QPP = 1 << 4,
+ SECT_32K = BIT(1),
+ E_FSR = BIT(2),
+ SST_WR = BIT(3),
+ WR_QPP = BIT(4),
};
enum spi_nor_option_flags {
- SNOR_F_SST_WR = (1 << 0),
- SNOR_F_USE_FSR = (1 << 1),
+ SNOR_F_SST_WR = BIT(0),
+ SNOR_F_USE_FSR = BIT(1),
};
#define SPI_FLASH_3B_ADDR_LEN 3
@@ -75,12 +75,9 @@ enum spi_nor_option_flags {
#define CMD_WRITE_STATUS 0x01
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
-#define CMD_READ_STATUS 0x05
-#define CMD_QUAD_PAGE_PROGRAM 0x32
-#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
-#define CMD_READ_CONFIG 0x35
-#define CMD_FLAG_STATUS 0x70
+#define CMD_QUAD_PAGE_PROGRAM 0x32
+#define CMD_WRITE_EVCR 0x61
/* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03
@@ -90,6 +87,11 @@ enum spi_nor_option_flags {
#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
#define CMD_READ_QUAD_IO_FAST 0xeb
#define CMD_READ_ID 0x9f
+#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS1 0x35
+#define CMD_READ_CONFIG 0x35
+#define CMD_FLAG_STATUS 0x70
+#define CMD_READ_EVCR 0x65
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
@@ -100,10 +102,11 @@ enum spi_nor_option_flags {
#endif
/* Common status */
-#define STATUS_WIP (1 << 0)
-#define STATUS_QEB_WINSPAN (1 << 1)
-#define STATUS_QEB_MXIC (1 << 6)
-#define STATUS_PEC (1 << 7)
+#define STATUS_WIP BIT(0)
+#define STATUS_QEB_WINSPAN BIT(1)
+#define STATUS_QEB_MXIC BIT(6)
+#define STATUS_PEC BIT(7)
+#define STATUS_QEB_MICRON BIT(7)
#define SR_BP0 BIT(2) /* Block protect 0 */
#define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 0cafc29123..daa1d5b249 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -128,7 +128,7 @@ static int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
#if defined(CONFIG_SPI_FLASH_SST)
if (flash->flags & SNOR_F_SST_WR) {
- if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
+ if (flash->spi->mode & SPI_TX_BYTE)
return sst_write_bp(flash, offset, len, buf);
else
return sst_write_wp(flash, offset, len, buf);
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index b7b7f0044e..8a60c72926 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -29,16 +29,6 @@ static void spi_flash_addr(u32 addr, u8 *cmd)
cmd[3] = addr >> 0;
}
-/* Read commands array */
-static u8 spi_read_cmds_array[] = {
- CMD_READ_ARRAY_SLOW,
- CMD_READ_ARRAY_FAST,
- CMD_READ_DUAL_OUTPUT_FAST,
- CMD_READ_DUAL_IO_FAST,
- CMD_READ_QUAD_OUTPUT_FAST,
- CMD_READ_QUAD_IO_FAST,
-};
-
static int read_sr(struct spi_flash *flash, u8 *rs)
{
int ret;
@@ -121,6 +111,37 @@ static int write_cr(struct spi_flash *flash, u8 wc)
}
#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO
+static int read_evcr(struct spi_flash *flash, u8 *evcr)
+{
+ int ret;
+ const u8 cmd = CMD_READ_EVCR;
+
+ ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1);
+ if (ret < 0) {
+ debug("SF: error reading EVCR\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int write_evcr(struct spi_flash *flash, u8 evcr)
+{
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_WRITE_EVCR;
+ ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1);
+ if (ret < 0) {
+ debug("SF: error while writing EVCR register\n");
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
{
@@ -149,7 +170,7 @@ static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0)
int ret;
if (flash->size <= SPI_FLASH_16MB_BOUN)
- goto bank_end;
+ goto bar_end;
switch (idcode0) {
case SPI_FLASH_CFI_MFR_SPANSION:
@@ -168,7 +189,7 @@ static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0)
return ret;
}
-bank_end:
+bar_end:
flash->bank_curr = curr_bank;
return 0;
}
@@ -177,13 +198,15 @@ bank_end:
#ifdef CONFIG_SF_DUAL_FLASH
static void spi_flash_dual(struct spi_flash *flash, u32 *addr)
{
+ struct spi_slave *spi = flash->spi;
+
switch (flash->dual_flash) {
case SF_DUAL_STACKED_FLASH:
if (*addr >= (flash->size >> 1)) {
*addr -= flash->size >> 1;
- flash->spi->flags |= SPI_XFER_U_PAGE;
+ spi->flags |= SPI_XFER_U_PAGE;
} else {
- flash->spi->flags &= ~SPI_XFER_U_PAGE;
+ spi->flags &= ~SPI_XFER_U_PAGE;
}
break;
case SF_DUAL_PARALLEL_FLASH:
@@ -268,7 +291,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
if (buf == NULL)
timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
@@ -353,6 +376,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
size_t len, const void *buf)
{
+ struct spi_slave *spi = flash->spi;
unsigned long byte_addr, page_size;
u32 write_addr;
size_t chunk_len, actual;
@@ -385,9 +409,9 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
byte_addr = offset % page_size;
chunk_len = min(len - actual, (size_t)(page_size - byte_addr));
- if (flash->spi->max_write_size)
+ if (spi->max_write_size)
chunk_len = min(chunk_len,
- (size_t)flash->spi->max_write_size);
+ (size_t)spi->max_write_size);
spi_flash_addr(write_addr, cmd);
@@ -413,7 +437,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
struct spi_slave *spi = flash->spi;
int ret;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
@@ -438,6 +462,7 @@ void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len)
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
+ struct spi_slave *spi = flash->spi;
u8 *cmd, cmdsz;
u32 remain_len, read_len, read_addr;
int bank_sel = 0;
@@ -445,15 +470,15 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
/* Handle memory-mapped SPI */
if (flash->memory_map) {
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
}
- spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
spi_flash_copy_mmap(data, flash->memory_map + offset, len);
- spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
- spi_release_bus(flash->spi);
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
+ spi_release_bus(spi);
return 0;
}
@@ -505,6 +530,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
#ifdef CONFIG_SPI_FLASH_SST
static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
{
+ struct spi_slave *spi = flash->spi;
int ret;
u8 cmd[4] = {
CMD_SST_BP,
@@ -514,13 +540,13 @@ static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
};
debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
+ spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset);
ret = spi_flash_cmd_write_enable(flash);
if (ret)
return ret;
- ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
+ ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1);
if (ret)
return ret;
@@ -530,11 +556,12 @@ static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf)
{
+ struct spi_slave *spi = flash->spi;
size_t actual, cmd_len;
int ret;
u8 cmd[4];
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Unable to claim SPI bus\n");
return ret;
@@ -561,10 +588,10 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
for (; actual < len - 1; actual += 2) {
debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
- spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
+ spi_w8r8(spi, CMD_READ_STATUS), buf + actual,
cmd[0], offset);
- ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
+ ret = spi_flash_cmd_write(spi, cmd, cmd_len,
buf + actual, 2);
if (ret) {
debug("SF: sst word program failed\n");
@@ -590,17 +617,18 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
ret ? "failure" : "success", len, offset - actual);
- spi_release_bus(flash->spi);
+ spi_release_bus(spi);
return ret;
}
int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf)
{
+ struct spi_slave *spi = flash->spi;
size_t actual;
int ret;
- ret = spi_claim_bus(flash->spi);
+ ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Unable to claim SPI bus\n");
return ret;
@@ -621,7 +649,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
ret ? "failure" : "success", len, offset - actual);
- spi_release_bus(flash->spi);
+ spi_release_bus(spi);
return ret;
}
#endif
@@ -803,7 +831,7 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
#ifdef CONFIG_SPI_FLASH_MACRONIX
-static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+static int macronix_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
int ret;
@@ -812,12 +840,18 @@ static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
if (ret < 0)
return ret;
- if (qeb_status & STATUS_QEB_MXIC) {
- debug("SF: mxic: QEB is already set\n");
- } else {
- ret = write_sr(flash, STATUS_QEB_MXIC);
- if (ret < 0)
- return ret;
+ if (qeb_status & STATUS_QEB_MXIC)
+ return 0;
+
+ ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC);
+ if (ret < 0)
+ return ret;
+
+ /* read SR and check it */
+ ret = read_sr(flash, &qeb_status);
+ if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) {
+ printf("SF: Macronix SR Quad bit not clear\n");
+ return -EINVAL;
}
return ret;
@@ -825,7 +859,7 @@ static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
-static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+static int spansion_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
int ret;
@@ -834,34 +868,67 @@ static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
if (ret < 0)
return ret;
- if (qeb_status & STATUS_QEB_WINSPAN) {
- debug("SF: winspan: QEB is already set\n");
- } else {
- ret = write_cr(flash, STATUS_QEB_WINSPAN);
- if (ret < 0)
- return ret;
+ if (qeb_status & STATUS_QEB_WINSPAN)
+ return 0;
+
+ ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN);
+ if (ret < 0)
+ return ret;
+
+ /* read CR and check it */
+ ret = read_cr(flash, &qeb_status);
+ if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) {
+ printf("SF: Spansion CR Quad bit not clear\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_SPI_FLASH_STMICRO
+static int micron_quad_enable(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ int ret;
+
+ ret = read_evcr(flash, &qeb_status);
+ if (ret < 0)
+ return ret;
+
+ if (!(qeb_status & STATUS_QEB_MICRON))
+ return 0;
+
+ ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON);
+ if (ret < 0)
+ return ret;
+
+ /* read EVCR and check it */
+ ret = read_evcr(flash, &qeb_status);
+ if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) {
+ printf("SF: Micron EVCR Quad bit not clear\n");
+ return -EINVAL;
}
return ret;
}
#endif
-static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
+static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
{
switch (idcode0) {
#ifdef CONFIG_SPI_FLASH_MACRONIX
case SPI_FLASH_CFI_MFR_MACRONIX:
- return spi_flash_set_qeb_mxic(flash);
+ return macronix_quad_enable(flash);
#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
case SPI_FLASH_CFI_MFR_SPANSION:
case SPI_FLASH_CFI_MFR_WINBOND:
- return spi_flash_set_qeb_winspan(flash);
+ return spansion_quad_enable(flash);
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
case SPI_FLASH_CFI_MFR_STMICRO:
- debug("SF: QEB is volatile for %02x flash\n", idcode0);
- return 0;
+ return micron_quad_enable(flash);
#endif
default:
printf("SF: Need set QEB func for %02x flash\n", idcode0);
@@ -872,14 +939,10 @@ static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
#if CONFIG_IS_ENABLED(OF_CONTROL)
int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
{
+#ifdef CONFIG_DM_SPI_FLASH
fdt_addr_t addr;
fdt_size_t size;
- int node;
-
- /* If there is no node, do nothing */
- node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
- if (node < 0)
- return 0;
+ int node = flash->dev->of_offset;
addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
if (addr == FDT_ADDR_T_NONE) {
@@ -892,6 +955,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
return -1;
}
flash->memory_map = map_sysmem(addr, size);
+#endif
return 0;
}
@@ -902,9 +966,15 @@ int spi_flash_scan(struct spi_flash *flash)
struct spi_slave *spi = flash->spi;
const struct spi_flash_params *params;
u16 jedec, ext_jedec;
- u8 idcode[5];
- u8 cmd;
+ u8 cmd, idcode[5];
int ret;
+ static u8 spi_read_cmds_array[] = {
+ CMD_READ_ARRAY_SLOW,
+ CMD_READ_ARRAY_FAST,
+ CMD_READ_DUAL_OUTPUT_FAST,
+ CMD_READ_QUAD_OUTPUT_FAST,
+ CMD_READ_DUAL_IO_FAST,
+ CMD_READ_QUAD_IO_FAST };
/* Read the ID codes */
ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
@@ -950,7 +1020,7 @@ int spi_flash_scan(struct spi_flash *flash)
/* Assign spi data */
flash->name = params->name;
flash->memory_map = spi->memory_map;
- flash->dual_flash = flash->spi->option;
+ flash->dual_flash = spi->option;
/* Assign spi flash flags */
if (params->flags & SST_WR)
@@ -961,7 +1031,7 @@ int spi_flash_scan(struct spi_flash *flash)
flash->write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
if (flash->flags & SNOR_F_SST_WR) {
- if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
+ if (spi->mode & SPI_TX_BYTE)
flash->write = sst_write_bp;
else
flash->write = sst_write_wp;
@@ -1025,7 +1095,7 @@ int spi_flash_scan(struct spi_flash *flash)
flash->sector_size = flash->erase_size;
/* Look for the fastest read cmd */
- cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
+ cmd = fls(params->e_rd_cmd & spi->mode_rx);
if (cmd) {
cmd = spi_read_cmds_array[cmd - 1];
flash->read_cmd = cmd;
@@ -1035,7 +1105,7 @@ int spi_flash_scan(struct spi_flash *flash)
}
/* Not require to look for fastest only two write cmds yet */
- if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
+ if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD)
flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
else
/* Go for default supported write cmd */
@@ -1045,7 +1115,7 @@ int spi_flash_scan(struct spi_flash *flash)
if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
(flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
(flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
- ret = spi_flash_set_qeb(flash, idcode[0]);
+ ret = set_quad_mode(flash, idcode[0]);
if (ret) {
debug("SF: Fail to set QEB for %02x\n", idcode[0]);
return -EINVAL;
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index f484e62b32..baf4e2d25b 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -30,6 +30,7 @@
#include <linux/slab.h>
#include <linux/major.h>
#else
+#include <linux/bug.h>
#include <linux/log2.h>
#endif
#include <linux/err.h>
generated by cgit (git 2.34.1) at 2025-01-15 21:35:22 +0000