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-rw-r--r--drivers/mtd/nand/Makefile1
-rw-r--r--drivers/mtd/nand/arasan_nfc.c7
-rw-r--r--drivers/mtd/nand/nand_ecc.c16
-rw-r--r--drivers/mtd/nand/ndfc.c200
-rw-r--r--drivers/mtd/spi/spi_flash.c2
-rw-r--r--drivers/mtd/ubi/Kconfig7
6 files changed, 12 insertions, 221 deletions
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 9f7d9d6ff7..332d905a3a 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -57,7 +57,6 @@ obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
obj-$(CONFIG_NAND_MXS) += mxs_nand.o
-obj-$(CONFIG_NAND_NDFC) += ndfc.o
obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 3c9a0215c5..9c82c7db33 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -86,7 +86,7 @@ struct arasan_nand_command_format {
#define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000
#define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28
-#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000
+#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF
#define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF
#define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16
#define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF
@@ -795,10 +795,11 @@ static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
writel(reg_val, &arasan_nand_base->cmd_reg);
- page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
+ page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
- writel(page | column, &arasan_nand_base->memadr_reg1);
+ writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
+ &arasan_nand_base->memadr_reg1);
reg_val = readl(&arasan_nand_base->memadr_reg2);
reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c
index 8b548b204d..13a6535bd5 100644
--- a/drivers/mtd/nand/nand_ecc.c
+++ b/drivers/mtd/nand/nand_ecc.c
@@ -29,11 +29,6 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand_ecc.h>
-/* The PPC4xx NDFC uses Smart Media (SMC) bytes order */
-#ifdef CONFIG_NAND_NDFC
-#define CONFIG_MTD_NAND_ECC_SMC
-#endif
-
/*
* NAND-SPL has no sofware ECC for now, so don't include nand_calculate_ecc(),
* only nand_correct_data() is needed
@@ -110,13 +105,8 @@ int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */
/* Calculate final ECC code */
-#ifdef CONFIG_MTD_NAND_ECC_SMC
- ecc_code[0] = ~tmp2;
- ecc_code[1] = ~tmp1;
-#else
ecc_code[0] = ~tmp1;
ecc_code[1] = ~tmp2;
-#endif
ecc_code[2] = ((~reg1) << 2) | 0x03;
return 0;
@@ -146,15 +136,9 @@ int nand_correct_data(struct mtd_info *mtd, u_char *dat,
{
uint8_t s0, s1, s2;
-#ifdef CONFIG_MTD_NAND_ECC_SMC
- s0 = calc_ecc[0] ^ read_ecc[0];
- s1 = calc_ecc[1] ^ read_ecc[1];
- s2 = calc_ecc[2] ^ read_ecc[2];
-#else
s1 = calc_ecc[0] ^ read_ecc[0];
s0 = calc_ecc[1] ^ read_ecc[1];
s2 = calc_ecc[2] ^ read_ecc[2];
-#endif
if ((s0 | s1 | s2) == 0)
return 0;
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
deleted file mode 100644
index 0a9849e9bc..0000000000
--- a/drivers/mtd/nand/ndfc.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * Overview:
- * Platform independent driver for NDFC (NanD Flash Controller)
- * integrated into IBM/AMCC PPC4xx cores
- *
- * (C) Copyright 2006-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Based on original work by
- * Thomas Gleixner
- * Copyright 2006 IBM
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <linux/mtd/ndfc.h>
-#include <linux/mtd/nand_ecc.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx.h>
-
-#ifndef CONFIG_SYS_NAND_BCR
-#define CONFIG_SYS_NAND_BCR 0x80002222
-#endif
-#ifndef CONFIG_SYS_NDFC_EBC0_CFG
-#define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000
-#endif
-
-/*
- * We need to store the info, which chip-select (CS) is used for the
- * chip number. For example on Sequoia NAND chip #0 uses
- * CS #3.
- */
-static int ndfc_cs[NDFC_MAX_BANKS];
-
-static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtd);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF);
- else
- out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF);
-}
-
-static int ndfc_dev_ready(struct mtd_info *mtdinfo)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
-
- return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
-}
-
-static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- u32 ccr;
-
- ccr = in_be32((u32 *)(base + NDFC_CCR));
- ccr |= NDFC_CCR_RESET_ECC;
- out_be32((u32 *)(base + NDFC_CCR), ccr);
-}
-
-static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
- const u_char *dat, u_char *ecc_code)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- u32 ecc;
- u8 *p = (u8 *)&ecc;
-
- ecc = in_be32((u32 *)(base + NDFC_ECC));
-
- /* The NDFC uses Smart Media (SMC) bytes order
- */
- ecc_code[0] = p[1];
- ecc_code[1] = p[2];
- ecc_code[2] = p[3];
-
- return 0;
-}
-
-/*
- * Speedups for buffer read/write/verify
- *
- * NDFC allows 32bit read/write of data. So we can speed up the buffer
- * functions. No further checking, as nand_base will always read/write
- * page aligned.
- */
-static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- uint32_t *p = (uint32_t *) buf;
-
- for (;len > 0; len -= 4)
- *p++ = in_be32((u32 *)(base + NDFC_DATA));
-}
-
-/*
- * Don't use these speedup functions in NAND boot image, since the image
- * has to fit into 4kByte.
- */
-static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
-{
- struct nand_chip *this = mtd_to_nand(mtdinfo);
- ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
- uint32_t *p = (uint32_t *) buf;
-
- for (; len > 0; len -= 4)
- out_be32((u32 *)(base + NDFC_DATA), *p++);
-}
-
-/*
- * Read a byte from the NDFC.
- */
-static uint8_t ndfc_read_byte(struct mtd_info *mtd)
-{
-
- struct nand_chip *chip = mtd_to_nand(mtd);
-
-#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
- return (uint8_t) readw(chip->IO_ADDR_R);
-#else
- return readb(chip->IO_ADDR_R);
-#endif
-
-}
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
- /*
- * Don't use "chip" to address the NAND device,
- * generate the cs from the address where it is encoded.
- */
- ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
- int cs = ndfc_cs[chip];
-
- /* Set NandFlash Core Configuration Register */
- /* 1 col x 2 rows */
- out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
- out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
-}
-
-static void ndfc_select_chip(struct mtd_info *mtd, int chip)
-{
- /*
- * Nothing to do here!
- */
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
- ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
- static int chip = 0;
-
- /*
- * Save chip-select for this chip #
- */
- ndfc_cs[chip] = cs;
-
- /*
- * Select required NAND chip in NDFC
- */
- board_nand_select_device(nand, chip);
-
- nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA);
- nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA);
- nand->cmd_ctrl = ndfc_hwcontrol;
- nand->chip_delay = 50;
- nand->read_buf = ndfc_read_buf;
- nand->dev_ready = ndfc_dev_ready;
- nand->ecc.correct = nand_correct_data;
- nand->ecc.hwctl = ndfc_enable_hwecc;
- nand->ecc.calculate = ndfc_calculate_ecc;
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.size = 256;
- nand->ecc.bytes = 3;
- nand->ecc.strength = 1;
- nand->select_chip = ndfc_select_chip;
-
-#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
- nand->options |= NAND_BUSWIDTH_16;
-#endif
-
- nand->write_buf = ndfc_write_buf;
- nand->read_byte = ndfc_read_byte;
-
- chip++;
-
- return 0;
-}
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 294d9f9d79..2e61685d3e 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -320,7 +320,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
erase_size = flash->erase_size;
if (offset % erase_size || len % erase_size) {
- debug("SF: Erase offset/length not multiple of erase size\n");
+ printf("SF: Erase offset/length not multiple of erase size\n");
return -1;
}
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index caa5197df5..cf84783356 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -1,5 +1,12 @@
menu "UBI support"
+config CONFIG_UBI_SILENCE_MSG
+ bool "UBI silence verbose messages"
+ default ENV_IS_IN_UBI
+ help
+ Make the verbose messages from UBI stop printing. This leaves
+ warnings and errors enabled.
+
config MTD_UBI
bool "Enable UBI - Unsorted block images"
select CRC32