diff options
Diffstat (limited to 'drivers/net/phy/cortina.c')
| -rw-r--r-- | drivers/net/phy/cortina.c | 59 |
1 files changed, 30 insertions, 29 deletions
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index 637d89a1e1..9cb3a52c20 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ * * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * */ @@ -27,6 +28,7 @@ #error The Cortina PHY needs 10G support #endif +#ifndef CORTINA_NO_FW_UPLOAD struct cortina_reg_config cortina_reg_cfg[] = { /* CS4315_enable_sr_mode */ {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, @@ -215,12 +217,22 @@ void cs4340_upload_firmware(struct phy_device *phydev) phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); } } +#endif int cs4340_phy_init(struct phy_device *phydev) { +#ifndef CORTINA_NO_FW_UPLOAD int timeout = 100; /* 100ms */ +#endif int reg_value; + /* + * Cortina phy has provision to store + * phy firmware in attached dedicated EEPROM. + * Boards designed with EEPROM attached to Cortina + * does not require FW upload. + */ +#ifndef CORTINA_NO_FW_UPLOAD /* step1: BIST test */ phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); @@ -241,6 +253,7 @@ int cs4340_phy_init(struct phy_device *phydev) /* setp2: upload ucode */ cs4340_upload_firmware(phydev); +#endif reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); if (reg_value) { debug("%s checksum status failed.\n", __func__); @@ -295,45 +308,33 @@ int phy_cortina_init(void) int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) { int phy_reg; - bool is_cortina_phy = false; - - switch (addr) { -#ifdef CORTINA_PHY_ADDR1 - case CORTINA_PHY_ADDR1: -#endif -#ifdef CORTINA_PHY_ADDR2 - case CORTINA_PHY_ADDR2: -#endif -#ifdef CORTINA_PHY_ADDR3 - case CORTINA_PHY_ADDR3: -#endif -#ifdef CORTINA_PHY_ADDR4 - case CORTINA_PHY_ADDR4: -#endif - is_cortina_phy = true; - break; - default: - break; - } /* Cortina PHY has non-standard offset of PHY ID registers */ - if (is_cortina_phy) - phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB); - else - phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); + phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB); + if (phy_reg < 0) + return -EIO; + *phy_id = (phy_reg & 0xffff) << 16; + phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB); if (phy_reg < 0) return -EIO; + *phy_id |= (phy_reg & 0xffff); - *phy_id = (phy_reg & 0xffff) << 16; - if (is_cortina_phy) - phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB); - else - phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); + if (*phy_id == PHY_UID_CS4340) + return 0; + /* + * If Cortina PHY not detected, + * try generic way to find PHY ID registers + */ + phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); if (phy_reg < 0) return -EIO; + *phy_id = (phy_reg & 0xffff) << 16; + phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); + if (phy_reg < 0) + return -EIO; *phy_id |= (phy_reg & 0xffff); return 0; |