diff options
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/at91_emac.c | 10 | ||||
| -rw-r--r-- | drivers/net/davinci_emac.c | 8 | ||||
| -rw-r--r-- | drivers/net/designware.c | 4 | ||||
| -rw-r--r-- | drivers/net/e1000.c | 77 | ||||
| -rw-r--r-- | drivers/net/e1000.h | 4 | ||||
| -rw-r--r-- | drivers/net/fsl-mc/mc.c | 2 | ||||
| -rw-r--r-- | drivers/net/keystone_net.c | 473 | ||||
| -rw-r--r-- | drivers/net/lan91c96.c | 2 | ||||
| -rw-r--r-- | drivers/net/ne2000_base.c | 2 | ||||
| -rw-r--r-- | drivers/net/pch_gbe.c | 27 | ||||
| -rw-r--r-- | drivers/net/pch_gbe.h | 2 | ||||
| -rw-r--r-- | drivers/net/phy/marvell.c | 26 | ||||
| -rw-r--r-- | drivers/net/phy/micrel.c | 6 |
13 files changed, 546 insertions, 97 deletions
diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c index 26595929c5..9151600190 100644 --- a/drivers/net/at91_emac.c +++ b/drivers/net/at91_emac.c @@ -12,7 +12,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_emac.h> -#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> #include <asm/arch/at91_pio.h> #include <net.h> #include <netdev.h> @@ -321,7 +321,6 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd) emac_device *dev; at91_emac_t *emac; at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; emac = (at91_emac_t *) netdev->iobase; dev = (emac_device *) netdev->priv; @@ -347,7 +346,8 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd) writel(value, &pio->piob.pdr); writel(value, &pio->piob.bsr); - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC); + writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); /* Init Ethernet buffers */ @@ -452,10 +452,10 @@ static int at91emac_recv(struct eth_device *netdev) static int at91emac_write_hwaddr(struct eth_device *netdev) { at91_emac_t *emac; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; emac = (at91_emac_t *) netdev->iobase; - writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + at91_periph_clk_enable(ATMEL_ID_EMAC); + debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n", netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3], diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 92c3dcae3c..b030498402 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -459,11 +459,11 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) /* Set DMA 8 TX / 8 RX Head pointers to 0 */ addr = &adap_emac->TX0HDP; - for(cnt = 0; cnt < 16; cnt++) + for (cnt = 0; cnt < 8; cnt++) writel(0, addr++); addr = &adap_emac->RX0HDP; - for(cnt = 0; cnt < 16; cnt++) + for (cnt = 0; cnt < 8; cnt++) writel(0, addr++); /* Clear Statistics (do this before setting MacControl register) */ @@ -692,8 +692,10 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) davinci_invalidate_rx_descs(); rx_curr_desc = emac_rx_active_head; + if (!rx_curr_desc) + return 0; status = rx_curr_desc->pkt_flag_len; - if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { + if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) { if (status & EMAC_CPPI_RX_ERROR_FRAME) { /* Error in packet - discard it and requeue desc */ printf ("WARN: emac_rcv_pkt: Error in packet\n"); diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 77b98c94c0..ca58f34f13 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -591,11 +591,9 @@ static int designware_eth_probe(struct udevice *dev) * or via a PCI bridge, fill in platdata before we probe the hardware. */ if (device_is_on_pci_bus(dev)) { - pci_dev_t bdf = dm_pci_get_bdf(dev); - dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); iobase &= PCI_BASE_ADDRESS_MEM_MASK; - iobase = pci_mem_to_phys(bdf, iobase); + iobase = dm_pci_mem_to_phys(dev, iobase); pdata->iobase = iobase; pdata->phy_interface = PHY_INTERFACE_MODE_RMII; diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 70fc02ee5c..196989b386 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -38,8 +38,13 @@ tested on both gig copper and gig fiber boards #define TOUT_LOOP 100000 +#ifdef CONFIG_DM_ETH +#define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v)) +#define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a) +#else #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) +#endif #define E1000_DEFAULT_PCI_PBA 0x00000030 #define E1000_DEFAULT_PCIE_PBA 0x000a0026 @@ -1395,8 +1400,13 @@ e1000_reset_hw(struct e1000_hw *hw) /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ if (hw->mac_type == e1000_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCI_COMMAND, + hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); +#else pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); +#endif } /* Clear interrupt mask to stop board from generating interrupts */ @@ -1469,7 +1479,11 @@ e1000_reset_hw(struct e1000_hw *hw) /* If MWI was previously enabled, reenable it. */ if (hw->mac_type == e1000_82542_rev2_0) { +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); +#else pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); +#endif } if (hw->mac_type != e1000_igb) E1000_WRITE_REG(hw, PBA, pba); @@ -1655,9 +1669,15 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ if (hw->mac_type == e1000_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCI_COMMAND, + hw-> + pci_cmd_word & ~PCI_COMMAND_INVALIDATE); +#else pci_write_config_word(hw->pdev, PCI_COMMAND, hw-> pci_cmd_word & ~PCI_COMMAND_INVALIDATE); +#endif E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); E1000_WRITE_FLUSH(hw); mdelay(5); @@ -1673,7 +1693,11 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) E1000_WRITE_REG(hw, RCTL, 0); E1000_WRITE_FLUSH(hw); mdelay(1); +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); +#else pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); +#endif } /* Zero out the Multicast HASH table */ @@ -1696,10 +1720,17 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) default: /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ if (hw->bus_type == e1000_bus_type_pcix) { +#ifdef CONFIG_DM_ETH + dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER, + &pcix_cmd_word); + dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI, + &pcix_stat_hi_word); +#else pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word); pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); +#endif cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> PCIX_COMMAND_MMRBC_SHIFT; @@ -1711,8 +1742,13 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) if (cmd_mmrbc > stat_mmrbc) { pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER, + pcix_cmd_word); +#else pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word); +#endif } } break; @@ -4809,6 +4845,16 @@ e1000_sw_init(struct e1000_hw *hw) int result; /* PCI config space info */ +#ifdef CONFIG_DM_ETH + dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); + dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id); + dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, + &hw->subsystem_vendor_id); + dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); + + dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id); + dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); +#else pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, @@ -4817,6 +4863,7 @@ e1000_sw_init(struct e1000_hw *hw) pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); +#endif /* identify the MAC */ result = e1000_set_mac_type(hw); @@ -5232,25 +5279,46 @@ void e1000_get_bus_type(struct e1000_hw *hw) static LIST_HEAD(e1000_hw_list); #endif +#ifdef CONFIG_DM_ETH +static int e1000_init_one(struct e1000_hw *hw, int cardnum, + struct udevice *devno, unsigned char enetaddr[6]) +#else static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, unsigned char enetaddr[6]) +#endif { u32 val; /* Assign the passed-in values */ +#ifdef CONFIG_DM_ETH hw->pdev = devno; +#else + hw->pdev = devno; +#endif hw->cardnum = cardnum; /* Print a debug message with the IO base address */ +#ifdef CONFIG_DM_ETH + dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val); +#else pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); +#endif E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); /* Try to enable I/O accesses and bus-mastering */ val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; +#ifdef CONFIG_DM_ETH + dm_pci_write_config32(devno, PCI_COMMAND, val); +#else pci_write_config_dword(devno, PCI_COMMAND, val); +#endif /* Make sure it worked */ +#ifdef CONFIG_DM_ETH + dm_pci_read_config32(devno, PCI_COMMAND, &val); +#else pci_read_config_dword(devno, PCI_COMMAND, &val); +#endif if (!(val & PCI_COMMAND_MEMORY)) { E1000_ERR(hw, "Can't enable I/O memory\n"); return -ENOSPC; @@ -5269,8 +5337,13 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, #ifndef CONFIG_E1000_NO_NVM hw->eeprom_semaphore_present = true; #endif +#ifdef CONFIG_DM_ETH + hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); +#else hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); +#endif hw->mac_type = e1000_undefined; /* MAC and Phy settings */ @@ -5380,7 +5453,7 @@ e1000_initialize(bd_t * bis) for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { /* * These will never get freed due to errors, this allows us to - * perform SPI EEPROM programming from U-boot, for example. + * perform SPI EEPROM programming from U-Boot, for example. */ struct eth_device *nic = malloc(sizeof(*nic)); struct e1000_hw *hw = malloc(sizeof(*hw)); @@ -5554,7 +5627,7 @@ static int e1000_eth_probe(struct udevice *dev) hw->name = dev->name; ret = e1000_init_one(hw, trailing_strtol(dev->name), - dm_pci_get_bdf(dev), plat->enetaddr); + dev, plat->enetaddr); if (ret < 0) { printf(pr_fmt("failed to initialize card: %d\n"), ret); return ret; diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index e46edcd4e1..fcb7df0d83 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -1084,7 +1084,11 @@ struct e1000_hw { #endif unsigned int cardnum; +#ifdef CONFIG_DM_ETH + struct udevice *pdev; +#else pci_dev_t pdev; +#endif uint8_t *hw_addr; e1000_mac_type mac_type; e1000_phy_type phy_type; diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index fdbd584186..53c4966c33 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -455,7 +455,7 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) /* * Management Complex cores should be held at reset out of POR. - * U-boot should be the first software to touch MC. To be safe, + * U-Boot should be the first software to touch MC. To be safe, * we reset all cores again by setting GCR1 to 0. It doesn't do * anything if they are held at reset. After we setup the firmware * we kick off MC by deasserting the reset bit for core 0, and diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 209fae94a7..6b28df0f96 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -10,6 +10,8 @@ #include <command.h> #include <console.h> +#include <dm.h> + #include <net.h> #include <phy.h> #include <errno.h> @@ -18,10 +20,15 @@ #include <asm/ti-common/keystone_nav.h> #include <asm/ti-common/keystone_net.h> #include <asm/ti-common/keystone_serdes.h> +#include <asm/arch/psc_defs.h> + +DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_DM_ETH unsigned int emac_open; static struct mii_dev *mdio_bus; static unsigned int sys_has_mdio = 1; +#endif #ifdef KEYSTONE2_EMAC_GIG_ENABLE #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) @@ -36,40 +43,74 @@ static unsigned int sys_has_mdio = 1; static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); +#ifndef CONFIG_DM_ETH struct rx_buff_desc net_rx_buffs = { .buff_ptr = rx_buffs, .num_buffs = RX_BUFF_NUMS, .buff_len = RX_BUFF_LEN, .rx_flow = 22, }; - -#ifndef CONFIG_SOC_K2G -static void keystone2_net_serdes_setup(void); #endif -int keystone2_eth_read_mac_addr(struct eth_device *dev) -{ - struct eth_priv_t *eth_priv; - u32 maca = 0; - u32 macb = 0; +#ifdef CONFIG_DM_ETH - eth_priv = (struct eth_priv_t *)dev->priv; +enum link_type { + LINK_TYPE_MAC_TO_MAC_AUTO = 0, + LINK_TYPE_MAC_TO_PHY_MODE = 1, + LINK_TYPE_MAC_TO_MAC_FORCED_MODE = 2, + LINK_TYPE_MAC_TO_FIBRE_MODE = 3, + LINK_TYPE_MAC_TO_PHY_NO_MDIO_MODE = 4, + LINK_TYPE_10G_MAC_TO_PHY_MODE = 10, + LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11, +}; - /* Read the e-fuse mac address */ - if (eth_priv->slave_port == 1) { - maca = __raw_readl(MAC_ID_BASE_ADDR); - macb = __raw_readl(MAC_ID_BASE_ADDR + 4); - } +#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ + ((mac)[2] << 16) | ((mac)[3] << 24)) +#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) - dev->enetaddr[0] = (macb >> 8) & 0xff; - dev->enetaddr[1] = (macb >> 0) & 0xff; - dev->enetaddr[2] = (maca >> 24) & 0xff; - dev->enetaddr[3] = (maca >> 16) & 0xff; - dev->enetaddr[4] = (maca >> 8) & 0xff; - dev->enetaddr[5] = (maca >> 0) & 0xff; +#ifdef CONFIG_KSNET_NETCP_V1_0 - return 0; -} +#define EMAC_EMACSW_BASE_OFS 0x90800 +#define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60) + +/* CPSW Switch slave registers */ +#define CPGMACSL_REG_SA_LO 0x10 +#define CPGMACSL_REG_SA_HI 0x14 + +#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \ + (x) * 0x30) + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define EMAC_EMACSW_PORT_BASE_OFS 0x222000 + +/* CPSW Switch slave registers */ +#define CPGMACSL_REG_SA_LO 0x308 +#define CPGMACSL_REG_SA_HI 0x30c + +#define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \ + (x) * 0x1000) + +#endif + + +struct ks2_eth_priv { + struct udevice *dev; + struct phy_device *phydev; + struct mii_dev *mdio_bus; + int phy_addr; + phy_interface_t phy_if; + int sgmii_link_type; + void *mdio_base; + struct rx_buff_desc net_rx_buffs; + struct pktdma_cfg *netcp_pktdma; + void *hd; + int slave_port; + enum link_type link_type; + bool emac_open; + bool has_mdio; +}; +#endif /* MDIO */ @@ -140,6 +181,7 @@ static int keystone2_mdio_write(struct mii_dev *bus, return 0; } +#ifndef CONFIG_DM_ETH static void __attribute__((unused)) keystone2_eth_gigabit_enable(struct eth_device *dev) { @@ -163,6 +205,31 @@ static void __attribute__((unused)) EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL); } +#else +static void __attribute__((unused)) + keystone2_eth_gigabit_enable(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + u_int16_t data; + + if (priv->has_mdio) { + data = keystone2_mdio_read(priv->mdio_bus, priv->phy_addr, + MDIO_DEVAD_NONE, 0); + /* speed selection MSB */ + if (!(data & (1 << 6))) + return; + } + + /* + * Check if link detected is giga-bit + * If Gigabit mode detected, enable gigbit in MAC + */ + writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) + + CPGMACSL_REG_CTL) | + EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, + DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL); +} +#endif #ifdef CONFIG_SOC_K2G int keystone_rgmii_config(struct phy_device *phy_dev) @@ -401,6 +468,58 @@ int ethss_stop(void) return 0; } +struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { + .clk = SERDES_CLOCK_156P25M, + .rate = SERDES_RATE_5G, + .rate_mode = SERDES_QUARTER_RATE, + .intf = SERDES_PHY_SGMII, + .loopback = 0, +}; + +#ifndef CONFIG_SOC_K2G +static void keystone2_net_serdes_setup(void) +{ + ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, + &ks2_serdes_sgmii_156p25mhz, + CONFIG_KSNET_SERDES_LANES_PER_SGMII); + +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) + ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, + &ks2_serdes_sgmii_156p25mhz, + CONFIG_KSNET_SERDES_LANES_PER_SGMII); +#endif + + /* wait till setup */ + udelay(5000); +} +#endif + +#ifndef CONFIG_DM_ETH + +int keystone2_eth_read_mac_addr(struct eth_device *dev) +{ + struct eth_priv_t *eth_priv; + u32 maca = 0; + u32 macb = 0; + + eth_priv = (struct eth_priv_t *)dev->priv; + + /* Read the e-fuse mac address */ + if (eth_priv->slave_port == 1) { + maca = __raw_readl(MAC_ID_BASE_ADDR); + macb = __raw_readl(MAC_ID_BASE_ADDR + 4); + } + + dev->enetaddr[0] = (macb >> 8) & 0xff; + dev->enetaddr[1] = (macb >> 0) & 0xff; + dev->enetaddr[2] = (maca >> 24) & 0xff; + dev->enetaddr[3] = (maca >> 16) & 0xff; + dev->enetaddr[4] = (maca >> 8) & 0xff; + dev->enetaddr[5] = (maca >> 0) & 0xff; + + return 0; +} + int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) { if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) @@ -556,6 +675,7 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv) int res; struct eth_device *dev; struct phy_device *phy_dev; + struct mdio_regs *adap_mdio = (struct mdio_regs *)EMAC_MDIO_BASE_ADDR; dev = malloc(sizeof(struct eth_device)); if (dev == NULL) @@ -612,28 +732,301 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv) return 0; } -struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { - .clk = SERDES_CLOCK_156P25M, - .rate = SERDES_RATE_5G, - .rate_mode = SERDES_QUARTER_RATE, - .intf = SERDES_PHY_SGMII, - .loopback = 0, -}; +#else -#ifndef CONFIG_SOC_K2G -static void keystone2_net_serdes_setup(void) +static int ks2_eth_start(struct udevice *dev) { - ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, - &ks2_serdes_sgmii_156p25mhz, - CONFIG_KSNET_SERDES_LANES_PER_SGMII); + struct ks2_eth_priv *priv = dev_get_priv(dev); -#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) - ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, - &ks2_serdes_sgmii_156p25mhz, - CONFIG_KSNET_SERDES_LANES_PER_SGMII); +#ifdef CONFIG_SOC_K2G + keystone_rgmii_config(priv->phydev); +#else + keystone_sgmii_config(priv->phydev, priv->slave_port - 1, + priv->sgmii_link_type); #endif - /* wait till setup */ - udelay(5000); + udelay(10000); + + /* On chip switch configuration */ + ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); + + qm_init(); + + if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) { + error("ksnav_init failed\n"); + goto err_knav_init; + } + + /* + * Streaming switch configuration. If not present this + * statement is defined to void in target.h. + * If present this is usually defined to a series of register writes + */ + hw_config_streaming_switch(); + + if (priv->has_mdio) { + phy_startup(priv->phydev); + if (priv->phydev->link == 0) { + error("phy startup failed\n"); + goto err_phy_start; + } + } + + emac_gigabit_enable(dev); + + ethss_start(); + + priv->emac_open = true; + + return 0; + +err_phy_start: + ksnav_close(priv->netcp_pktdma); +err_knav_init: + qm_close(); + + return -EFAULT; +} + +static int ks2_eth_send(struct udevice *dev, void *packet, int length) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + + genphy_update_link(priv->phydev); + if (priv->phydev->link == 0) + return -1; + + if (length < EMAC_MIN_ETHERNET_PKT_SIZE) + length = EMAC_MIN_ETHERNET_PKT_SIZE; + + return ksnav_send(priv->netcp_pktdma, (u32 *)packet, + length, (priv->slave_port) << 16); +} + +static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + int pkt_size; + u32 *pkt = NULL; + + priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size); + if (priv->hd == NULL) + return -EAGAIN; + + *packetp = (uchar *)pkt; + + return pkt_size; +} + +static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + + ksnav_release_rxhd(priv->netcp_pktdma, priv->hd); + + return 0; +} + +static void ks2_eth_stop(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + + if (!priv->emac_open) + return; + ethss_stop(); + + ksnav_close(priv->netcp_pktdma); + qm_close(); + phy_shutdown(priv->phydev); + priv->emac_open = false; +} + +int ks2_eth_read_rom_hwaddr(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + u32 maca = 0; + u32 macb = 0; + + /* Read the e-fuse mac address */ + if (priv->slave_port == 1) { + maca = __raw_readl(MAC_ID_BASE_ADDR); + macb = __raw_readl(MAC_ID_BASE_ADDR + 4); + } + + pdata->enetaddr[0] = (macb >> 8) & 0xff; + pdata->enetaddr[1] = (macb >> 0) & 0xff; + pdata->enetaddr[2] = (maca >> 24) & 0xff; + pdata->enetaddr[3] = (maca >> 16) & 0xff; + pdata->enetaddr[4] = (maca >> 8) & 0xff; + pdata->enetaddr[5] = (maca >> 0) & 0xff; + + return 0; +} + +int ks2_eth_write_hwaddr(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + + writel(mac_hi(pdata->enetaddr), + DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) + + CPGMACSL_REG_SA_HI); + writel(mac_lo(pdata->enetaddr), + DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) + + CPGMACSL_REG_SA_LO); + + return 0; +} + +static int ks2_eth_probe(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + struct mii_dev *mdio_bus; + int ret; + + priv->dev = dev; + + /* These clock enables has to be moved to common location */ + if (cpu_is_k2g()) + writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG); + + /* By default, select PA PLL clock as PA clock source */ +#ifndef CONFIG_SOC_K2G + if (psc_enable_module(KS2_LPSC_PA)) + return -EACCES; +#endif + if (psc_enable_module(KS2_LPSC_CPGMAC)) + return -EACCES; + if (psc_enable_module(KS2_LPSC_CRYPTO)) + return -EACCES; + + if (cpu_is_k2e() || cpu_is_k2l()) + pll_pa_clk_sel(); + + + priv->net_rx_buffs.buff_ptr = rx_buffs, + priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS, + priv->net_rx_buffs.buff_len = RX_BUFF_LEN, + + /* Register MDIO bus */ + mdio_bus = mdio_alloc(); + if (!mdio_bus) { + error("MDIO alloc failed\n"); + return -ENOMEM; + } + priv->mdio_bus = mdio_bus; + mdio_bus->read = keystone2_mdio_read; + mdio_bus->write = keystone2_mdio_write; + mdio_bus->reset = keystone2_mdio_reset; + mdio_bus->priv = priv->mdio_base; + sprintf(mdio_bus->name, "ethernet-mdio"); + + ret = mdio_register(mdio_bus); + if (ret) { + error("MDIO bus register failed\n"); + return ret; + } + +#ifndef CONFIG_SOC_K2G + keystone2_net_serdes_setup(); +#endif + + priv->netcp_pktdma = &netcp_pktdma; + + priv->phydev = phy_connect(mdio_bus, priv->phy_addr, dev, priv->phy_if); + phy_config(priv->phydev); + + return 0; } + +int ks2_eth_remove(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + + free(priv->phydev); + mdio_unregister(priv->mdio_bus); + mdio_free(priv->mdio_bus); + + return 0; +} + +static const struct eth_ops ks2_eth_ops = { + .start = ks2_eth_start, + .send = ks2_eth_send, + .recv = ks2_eth_recv, + .free_pkt = ks2_eth_free_pkt, + .stop = ks2_eth_stop, + .read_rom_hwaddr = ks2_eth_read_rom_hwaddr, + .write_hwaddr = ks2_eth_write_hwaddr, +}; + + +static int ks2_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + const void *fdt = gd->fdt_blob; + int interfaces; + int interface_0; + int netcp_gbe_0; + int phy; + int mdio; + u32 dma_channel[6]; + + interfaces = fdt_subnode_offset(fdt, dev->of_offset, + "netcp-interfaces"); + interface_0 = fdt_subnode_offset(fdt, interfaces, "interface-0"); + + netcp_gbe_0 = fdtdec_lookup_phandle(fdt, interface_0, "netcp-gbe"); + priv->link_type = fdtdec_get_int(fdt, netcp_gbe_0, + "link-interface", -1); + priv->slave_port = fdtdec_get_int(fdt, netcp_gbe_0, "slave-port", -1); + /* U-Boot slave port number starts with 1 instead of 0 */ + priv->slave_port += 1; + + phy = fdtdec_lookup_phandle(fdt, netcp_gbe_0, "phy-handle"); + priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1); + + mdio = fdt_parent_offset(fdt, phy); + if (mdio < 0) { + error("mdio dt not found\n"); + return -ENODEV; + } + priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg"); + + if (priv->link_type == LINK_TYPE_MAC_TO_PHY_MODE) { + priv->phy_if = PHY_INTERFACE_MODE_SGMII; + pdata->phy_interface = priv->phy_if; + priv->sgmii_link_type = SGMII_LINK_MAC_PHY; + priv->has_mdio = true; + } + pdata->iobase = dev_get_addr(dev); + + fdtdec_get_int_array(fdt, dev->of_offset, "ti,navigator-dmas", + dma_channel, 6); + priv->net_rx_buffs.rx_flow = dma_channel[1]; + + return 0; +} + +static const struct udevice_id ks2_eth_ids[] = { + { .compatible = "ti,netcp-1.0" }, + { } +}; + + +U_BOOT_DRIVER(eth_ks2) = { + .name = "eth_ks2", + .id = UCLASS_ETH, + .of_match = ks2_eth_ids, + .ofdata_to_platdata = ks2_eth_ofdata_to_platdata, + .probe = ks2_eth_probe, + .remove = ks2_eth_remove, + .ops = &ks2_eth_ops, + .priv_auto_alloc_size = sizeof(struct ks2_eth_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; #endif diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c index c4dd01ec2a..3526876d14 100644 --- a/drivers/net/lan91c96.c +++ b/drivers/net/lan91c96.c @@ -1,7 +1,7 @@ /*------------------------------------------------------------------------ * lan91c96.c * This is a driver for SMSC's LAN91C96 single-chip Ethernet device, based - * on the SMC91111 driver from U-boot. + * on the SMC91111 driver from U-Boot. * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c index 887cfd957b..71d133cc8f 100644 --- a/drivers/net/ne2000_base.c +++ b/drivers/net/ne2000_base.c @@ -650,7 +650,7 @@ dp83902a_poll(void) } -/* U-boot specific routines */ +/* U-Boot specific routines */ static u8 *pbuf = NULL; static int pkey = -1; diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index 56d29d47af..137818b390 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -117,15 +117,15 @@ static void pch_gbe_rx_descs_init(struct udevice *dev) memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM); for (i = 0; i < PCH_GBE_DESC_NUM; i++) - rx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, + rx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (u32)(priv->rx_buff[i])); - writel(pci_phys_to_mem(priv->bdf, (u32)rx_desc), + writel(dm_pci_phys_to_mem(priv->dev, (u32)rx_desc), &mac_regs->rx_dsc_base); writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1), &mac_regs->rx_dsc_size); - writel(pci_phys_to_mem(priv->bdf, (u32)(rx_desc + 1)), + writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_desc + 1)), &mac_regs->rx_dsc_sw_p); } @@ -137,11 +137,11 @@ static void pch_gbe_tx_descs_init(struct udevice *dev) memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM); - writel(pci_phys_to_mem(priv->bdf, (u32)tx_desc), + writel(dm_pci_phys_to_mem(priv->dev, (u32)tx_desc), &mac_regs->tx_dsc_base); writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1), &mac_regs->tx_dsc_size); - writel(pci_phys_to_mem(priv->bdf, (u32)(tx_desc + 1)), + writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_desc + 1)), &mac_regs->tx_dsc_sw_p); } @@ -251,7 +251,7 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length) if (length < 64) frame_ctrl |= PCH_GBE_TXD_CTRL_APAD; - tx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, (u32)packet); + tx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (u32)packet); tx_desc->length = length; tx_desc->tx_words_eob = length + 3; tx_desc->tx_frame_ctrl = frame_ctrl; @@ -262,7 +262,7 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length) if (++priv->tx_idx >= PCH_GBE_DESC_NUM) priv->tx_idx = 0; - writel(pci_phys_to_mem(priv->bdf, (u32)(tx_head + priv->tx_idx)), + writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_head + priv->tx_idx)), &mac_regs->tx_dsc_sw_p); start = get_timer(0); @@ -294,7 +294,7 @@ static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp) if ((u32)rx_desc == hw_desc) return -EAGAIN; - buffer_addr = pci_mem_to_phys(priv->bdf, rx_desc->buffer_addr); + buffer_addr = dm_pci_mem_to_phys(priv->dev, rx_desc->buffer_addr); *packetp = (uchar *)buffer_addr; length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN; @@ -315,7 +315,7 @@ static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length) if (++rx_swp >= PCH_GBE_DESC_NUM) rx_swp = 0; - writel(pci_phys_to_mem(priv->bdf, (u32)(rx_head + rx_swp)), + writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_head + rx_swp)), &mac_regs->rx_dsc_sw_p); return 0; @@ -421,11 +421,8 @@ int pch_gbe_probe(struct udevice *dev) { struct pch_gbe_priv *priv; struct eth_pdata *plat = dev_get_platdata(dev); - pci_dev_t devno; u32 iobase; - devno = dm_pci_get_bdf(dev); - /* * The priv structure contains the descriptors and frame buffers which * need a strict buswidth alignment (64 bytes). This is guaranteed by @@ -433,11 +430,11 @@ int pch_gbe_probe(struct udevice *dev) */ priv = dev_get_priv(dev); - priv->bdf = devno; + priv->dev = dev; - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase); iobase &= PCI_BASE_ADDRESS_MEM_MASK; - iobase = pci_mem_to_phys(devno, iobase); + iobase = dm_pci_mem_to_phys(dev, iobase); plat->iobase = iobase; priv->mac_regs = (struct pch_gbe_regs *)iobase; diff --git a/drivers/net/pch_gbe.h b/drivers/net/pch_gbe.h index afcb03dd36..0ea0c73a4f 100644 --- a/drivers/net/pch_gbe.h +++ b/drivers/net/pch_gbe.h @@ -290,7 +290,7 @@ struct pch_gbe_priv { struct phy_device *phydev; struct mii_dev *bus; struct pch_gbe_regs *mac_regs; - pci_dev_t bdf; + struct udevice *dev; int rx_idx; int tx_idx; }; diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index eab15585c3..b8b1157a0a 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -172,7 +172,6 @@ static int m88e1011s_startup(struct phy_device *phydev) static int m88e1111s_config(struct phy_device *phydev) { int reg; - int timeout; if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || @@ -236,16 +235,7 @@ static int m88e1111s_config(struct phy_device *phydev) MIIM_88E1111_PHY_EXT_SR, reg); /* soft reset */ - timeout = 1000; - phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); - udelay(1000); - reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); - while ((reg & BMCR_RESET) && --timeout) { - udelay(1000); - reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); - } - if (!timeout) - printf("%s: phy soft reset timeout\n", __func__); + phy_reset(phydev); reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); @@ -258,20 +248,10 @@ static int m88e1111s_config(struct phy_device *phydev) } /* soft reset */ - timeout = 1000; - phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); - udelay(1000); - reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); - while ((reg & BMCR_RESET) && --timeout) { - udelay(1000); - reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); - } - if (!timeout) - printf("%s: phy soft reset timeout\n", __func__); + phy_reset(phydev); genphy_config_aneg(phydev); - - phy_reset(phydev); + genphy_restart_aneg(phydev); return 0; } diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index c3da1606dc..8fcf737cb8 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -279,7 +279,8 @@ static int ksz90x1_of_config_group(struct phy_device *phydev, #define CTRL1000_CONFIG_MASTER (1 << 11) #define CTRL1000_MANUAL_CONFIG (1 << 12) -#ifdef CONFIG_DM_ETH +#if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \ + defined(CONFIG_PHY_MICREL_KSZ9031)) static const struct ksz90x1_reg_field ksz9021_clk_grp[] = { { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 }, { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 }, @@ -385,7 +386,8 @@ static struct phy_driver ksz9021_driver = { #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d #define MII_KSZ9031_MMD_REG_DATA 0x0e -#ifdef CONFIG_DM_ETH +#if defined(CONFIG_DM_ETH) && (defined(CONFIG_PHY_MICREL_KSZ9021) || \ + defined(CONFIG_PHY_MICREL_KSZ9031)) static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = { { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } }; static const struct ksz90x1_reg_field ksz9031_clk_grp[] = |