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-rw-r--r--drivers/net/Kconfig2
-rw-r--r--drivers/net/zynq_gem.c4
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 5441da47d1..f1f0e2d94e 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -344,7 +344,7 @@ config XILINX_EMACLITE
This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
config ZYNQ_GEM
- depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP)
+ depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL)
select PHYLIB
bool "Xilinx Ethernet GEM"
help
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index e22d048e8f..bc33126536 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -461,6 +461,7 @@ static int zynq_gem_init(struct udevice *dev)
break;
}
+#if !defined(CONFIG_ARCH_VERSAL)
ret = clk_set_rate(&priv->clk, clk_rate);
if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
dev_err(dev, "failed to set tx clock rate\n");
@@ -472,6 +473,9 @@ static int zynq_gem_init(struct udevice *dev)
dev_err(dev, "failed to enable tx clock\n");
return ret;
}
+#else
+ debug("requested clk_rate %ld\n", clk_rate);
+#endif
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);