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path: root/drivers/pci/fsl_pci_init.c
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Diffstat (limited to 'drivers/pci/fsl_pci_init.c')
-rw-r--r--drivers/pci/fsl_pci_init.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 152045ed93..52792dcd59 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -697,8 +697,14 @@ void fsl_pci_config_unlock(struct pci_controller *hose)
pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
if (pcie_cap != 0x0) {
+ ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
+ u32 block_rev = in_be32(&pci->block_rev1);
/* PCIe - set CFG_READY bit of Configuration Ready Register */
- pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
+ if (block_rev >= PEX_IP_BLK_REV_3_0)
+ setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
+ else
+ pci_hose_write_config_byte(hose, dev,
+ FSL_PCIE_CFG_RDY, 0x1);
} else {
/* PCI - clear ACL bit of PBFR */
pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);