diff options
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/Kconfig | 8 | ||||
| -rw-r--r-- | drivers/pci/Makefile | 1 | ||||
| -rw-r--r-- | drivers/pci/pci-uclass.c | 58 | ||||
| -rw-r--r-- | drivers/pci/pci_tegra.c | 50 | ||||
| -rw-r--r-- | drivers/pci/pcie_ecam_generic.c | 143 | ||||
| -rw-r--r-- | drivers/pci/pcie_imx.c | 8 | ||||
| -rw-r--r-- | drivers/pci/pcie_layerscape.c | 68 | ||||
| -rw-r--r-- | drivers/pci/pcie_xilinx.c | 55 |
8 files changed, 264 insertions, 127 deletions
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 8af2470268..58f128d8a6 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -33,6 +33,14 @@ config PCI_PNP help Enable PCI memory and I/O space resource allocation and assignment. +config PCIE_ECAM_GENERIC + bool "Generic ECAM-based PCI host controller support" + default n + depends on DM_PCI + help + Say Y here if you want to enable support for generic ECAM-based + PCIe host controllers, such as the one emulated by QEMU. + config PCIE_DW_MVEBU bool "Enable Armada-8K PCIe driver (DesignWare core)" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index ad44e83996..5eb12efbf5 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PCI) += pci.o pci_auto_old.o endif obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o +obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 86df141d60..5a24eb6428 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -518,6 +518,64 @@ int pci_auto_config_devices(struct udevice *bus) return sub_bus; } +int pci_generic_mmap_write_config( + struct udevice *bus, + int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp), + pci_dev_t bdf, + uint offset, + ulong value, + enum pci_size_t size) +{ + void *address; + + if (addr_f(bus, bdf, offset, &address) < 0) + return 0; + + switch (size) { + case PCI_SIZE_8: + writeb(value, address); + return 0; + case PCI_SIZE_16: + writew(value, address); + return 0; + case PCI_SIZE_32: + writel(value, address); + return 0; + default: + return -EINVAL; + } +} + +int pci_generic_mmap_read_config( + struct udevice *bus, + int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp), + pci_dev_t bdf, + uint offset, + ulong *valuep, + enum pci_size_t size) +{ + void *address; + + if (addr_f(bus, bdf, offset, &address) < 0) { + *valuep = pci_get_ff(size); + return 0; + } + + switch (size) { + case PCI_SIZE_8: + *valuep = readb(address); + return 0; + case PCI_SIZE_16: + *valuep = readw(address); + return 0; + case PCI_SIZE_32: + *valuep = readl(address); + return 0; + default: + return -EINVAL; + } +} + int dm_pci_hose_probe_bus(struct udevice *bus) { int sub_bus; diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 7d920d423d..b5bd25ec56 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -369,7 +369,7 @@ static int tegra_pcie_port_parse_dt(ofnode node, struct tegra_pcie_port *port) addr = ofnode_get_property(node, "assigned-addresses", &len); if (!addr) { - error("property \"assigned-addresses\" not found"); + pr_err("property \"assigned-addresses\" not found"); return -FDT_ERR_NOTFOUND; } @@ -460,7 +460,7 @@ static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes) err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1); if (err < 0) { - error("failed to parse \"nvidia,num-lanes\" property"); + pr_err("failed to parse \"nvidia,num-lanes\" property"); return err; } @@ -468,7 +468,7 @@ static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes) err = ofnode_read_pci_addr(node, 0, "reg", &addr); if (err < 0) { - error("failed to parse \"reg\" property"); + pr_err("failed to parse \"reg\" property"); return err; } @@ -491,25 +491,25 @@ static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id, err = dev_read_resource(dev, 0, &pcie->pads); if (err < 0) { - error("resource \"pads\" not found"); + pr_err("resource \"pads\" not found"); return err; } err = dev_read_resource(dev, 1, &pcie->afi); if (err < 0) { - error("resource \"afi\" not found"); + pr_err("resource \"afi\" not found"); return err; } err = dev_read_resource(dev, 2, &pcie->cs); if (err < 0) { - error("resource \"cs\" not found"); + pr_err("resource \"cs\" not found"); return err; } err = tegra_pcie_board_init(); if (err < 0) { - error("tegra_pcie_board_init() failed: err=%d", err); + pr_err("tegra_pcie_board_init() failed: err=%d", err); return err; } @@ -518,7 +518,7 @@ static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id, if (pcie->phy) { err = tegra_xusb_phy_prepare(pcie->phy); if (err < 0) { - error("failed to prepare PHY: %d", err); + pr_err("failed to prepare PHY: %d", err); return err; } } @@ -530,7 +530,7 @@ static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id, err = tegra_pcie_parse_port_info(subnode, &index, &num_lanes); if (err < 0) { - error("failed to obtain root port info"); + pr_err("failed to obtain root port info"); continue; } @@ -560,7 +560,7 @@ static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id, err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id, &pcie->xbar); if (err < 0) { - error("invalid lane configuration"); + pr_err("invalid lane configuration"); return err; } @@ -574,31 +574,31 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie) ret = power_domain_on(&pcie->pwrdom); if (ret) { - error("power_domain_on() failed: %d\n", ret); + pr_err("power_domain_on() failed: %d\n", ret); return ret; } ret = clk_enable(&pcie->clk_afi); if (ret) { - error("clk_enable(afi) failed: %d\n", ret); + pr_err("clk_enable(afi) failed: %d\n", ret); return ret; } ret = clk_enable(&pcie->clk_pex); if (ret) { - error("clk_enable(pex) failed: %d\n", ret); + pr_err("clk_enable(pex) failed: %d\n", ret); return ret; } ret = reset_deassert(&pcie->reset_afi); if (ret) { - error("reset_deassert(afi) failed: %d\n", ret); + pr_err("reset_deassert(afi) failed: %d\n", ret); return ret; } ret = reset_deassert(&pcie->reset_pex); if (ret) { - error("reset_deassert(pex) failed: %d\n", ret); + pr_err("reset_deassert(pex) failed: %d\n", ret); return ret; } @@ -618,14 +618,14 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie) err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); if (err < 0) { - error("failed to power off PCIe partition: %d", err); + pr_err("failed to power off PCIe partition: %d", err); return err; } err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, PERIPH_ID_PCIE); if (err < 0) { - error("failed to power up PCIe partition: %d", err); + pr_err("failed to power up PCIe partition: %d", err); return err; } @@ -645,7 +645,7 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie) err = tegra_plle_enable(); if (err < 0) { - error("failed to enable PLLE: %d\n", err); + pr_err("failed to enable PLLE: %d\n", err); return err; } @@ -705,7 +705,7 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) /* wait for the PLL to lock */ err = tegra_pcie_pll_wait(pcie, 500); if (err < 0) { - error("PLL failed to lock: %d", err); + pr_err("PLL failed to lock: %d", err); return err; } @@ -769,7 +769,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) err = tegra_pcie_phy_enable(pcie); if (err < 0) { - error("failed to power on PHY: %d\n", err); + pr_err("failed to power on PHY: %d\n", err); return err; } #endif @@ -778,7 +778,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) #ifdef CONFIG_TEGRA186 err = reset_deassert(&pcie->reset_pcie_x); if (err) { - error("reset_deassert(pcie_x) failed: %d\n", err); + pr_err("reset_deassert(pcie_x) failed: %d\n", err); return err; } #else @@ -1143,25 +1143,25 @@ static int pci_tegra_probe(struct udevice *dev) err = tegra_pcie_power_on(pcie); if (err < 0) { - error("failed to power on"); + pr_err("failed to power on"); return err; } err = tegra_pcie_enable_controller(pcie); if (err < 0) { - error("failed to enable controller"); + pr_err("failed to enable controller"); return err; } err = tegra_pcie_setup_translations(dev); if (err < 0) { - error("failed to decode ranges"); + pr_err("failed to decode ranges"); return err; } err = tegra_pcie_enable(pcie); if (err < 0) { - error("failed to enable PCIe"); + pr_err("failed to enable PCIe"); return err; } diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c new file mode 100644 index 0000000000..c7540ff80e --- /dev/null +++ b/drivers/pci/pcie_ecam_generic.c @@ -0,0 +1,143 @@ +/* + * Generic PCIE host provided by e.g. QEMU + * + * Heavily based on drivers/pci/pcie_xilinx.c + * + * Copyright (C) 2016 Imagination Technologies + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <pci.h> + +#include <asm/io.h> + +/** + * struct generic_ecam_pcie - generic_ecam PCIe controller state + * @cfg_base: The base address of memory mapped configuration space + */ +struct generic_ecam_pcie { + void *cfg_base; +}; + +/** + * pci_generic_ecam_conf_address() - Calculate the address of a config access + * @bus: Pointer to the PCI bus + * @bdf: Identifies the PCIe device to access + * @offset: The offset into the device's configuration space + * @paddress: Pointer to the pointer to write the calculates address to + * + * Calculates the address that should be accessed to perform a PCIe + * configuration space access for a given device identified by the PCIe + * controller device @pcie and the bus, device & function numbers in @bdf. If + * access to the device is not valid then the function will return an error + * code. Otherwise the address to access will be written to the pointer pointed + * to by @paddress. + */ +static int pci_generic_ecam_conf_address(struct udevice *bus, pci_dev_t bdf, + uint offset, void **paddress) +{ + struct generic_ecam_pcie *pcie = dev_get_priv(bus); + void *addr; + + addr = pcie->cfg_base; + addr += PCI_BUS(bdf) << 20; + addr += PCI_DEV(bdf) << 15; + addr += PCI_FUNC(bdf) << 12; + addr += offset; + *paddress = addr; + + return 0; +} + +/** + * pci_generic_ecam_read_config() - Read from configuration space + * @bus: Pointer to the PCI bus + * @bdf: Identifies the PCIe device to access + * @offset: The offset into the device's configuration space + * @valuep: A pointer at which to store the read value + * @size: Indicates the size of access to perform + * + * Read a value of size @size from offset @offset within the configuration + * space of the device identified by the bus, device & function numbers in @bdf + * on the PCI bus @bus. + */ +static int pci_generic_ecam_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address, + bdf, offset, valuep, size); +} + +/** + * pci_generic_ecam_write_config() - Write to configuration space + * @bus: Pointer to the PCI bus + * @bdf: Identifies the PCIe device to access + * @offset: The offset into the device's configuration space + * @value: The value to write + * @size: Indicates the size of access to perform + * + * Write the value @value of size @size from offset @offset within the + * configuration space of the device identified by the bus, device & function + * numbers in @bdf on the PCI bus @bus. + */ +static int pci_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address, + bdf, offset, value, size); +} + +/** + * pci_generic_ecam_ofdata_to_platdata() - Translate from DT to device state + * @dev: A pointer to the device being operated on + * + * Translate relevant data from the device tree pertaining to device @dev into + * state that the driver will later make use of. This state is stored in the + * device's private data structure. + * + * Return: 0 on success, else -EINVAL + */ +static int pci_generic_ecam_ofdata_to_platdata(struct udevice *dev) +{ + struct generic_ecam_pcie *pcie = dev_get_priv(dev); + struct fdt_resource reg_res; + DECLARE_GLOBAL_DATA_PTR; + int err; + + err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", + 0, ®_res); + if (err < 0) { + pr_err("\"reg\" resource not found\n"); + return err; + } + + pcie->cfg_base = map_physmem(reg_res.start, + fdt_resource_size(®_res), + MAP_NOCACHE); + + return 0; +} + +static const struct dm_pci_ops pci_generic_ecam_ops = { + .read_config = pci_generic_ecam_read_config, + .write_config = pci_generic_ecam_write_config, +}; + +static const struct udevice_id pci_generic_ecam_ids[] = { + { .compatible = "pci-host-ecam-generic" }, + { } +}; + +U_BOOT_DRIVER(pci_generic_ecam) = { + .name = "pci_generic_ecam", + .id = UCLASS_PCI, + .of_match = pci_generic_ecam_ids, + .ops = &pci_generic_ecam_ops, + .ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct generic_ecam_pcie), +}; diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index eab0a2b602..2900c8d9d1 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -431,7 +431,7 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d, /* * Initial bus setup */ -static int imx6_pcie_assert_core_reset(void) +static int imx6_pcie_assert_core_reset(bool prepare_for_boot) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -459,7 +459,7 @@ static int imx6_pcie_assert_core_reset(void) * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong * indication that the bootloader activated the link. */ - if (is_mx6dq()) { + if (is_mx6dq() && prepare_for_boot) { u32 val, gpr1, gpr12; gpr1 = readl(&iomuxc_regs->gpr[1]); @@ -605,7 +605,7 @@ static int imx_pcie_link_up(void) uint32_t tmp; int count = 0; - imx6_pcie_assert_core_reset(); + imx6_pcie_assert_core_reset(false); imx6_pcie_init_phy(); imx6_pcie_deassert_core_reset(); @@ -687,7 +687,7 @@ void imx_pcie_init(void) void imx_pcie_remove(void) { - imx6_pcie_assert_core_reset(); + imx6_pcie_assert_core_reset(true); } /* Probe function. */ diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 610f85c4e8..0cb7f6d564 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -241,14 +241,19 @@ static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf) return 0; } -void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf, - int offset) +int ls_pcie_conf_address(struct udevice *bus, pci_dev_t bdf, + uint offset, void **paddress) { - struct udevice *bus = pcie->bus; + struct ls_pcie *pcie = dev_get_priv(bus); u32 busdev; - if (PCI_BUS(bdf) == bus->seq) - return pcie->dbi + offset; + if (ls_pcie_addr_valid(pcie, bdf)) + return -EINVAL; + + if (PCI_BUS(bdf) == bus->seq) { + *paddress = pcie->dbi + offset; + return 0; + } busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) | PCIE_ATU_DEV(PCI_DEV(bdf)) | @@ -256,67 +261,28 @@ void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf, if (PCI_BUS(bdf) == bus->seq + 1) { ls_pcie_cfg0_set_busdev(pcie, busdev); - return pcie->cfg0 + offset; + *paddress = pcie->cfg0 + offset; } else { ls_pcie_cfg1_set_busdev(pcie, busdev); - return pcie->cfg1 + offset; + *paddress = pcie->cfg1 + offset; } + return 0; } static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { - struct ls_pcie *pcie = dev_get_priv(bus); - void *address; - - if (ls_pcie_addr_valid(pcie, bdf)) { - *valuep = pci_get_ff(size); - return 0; - } - - address = ls_pcie_conf_address(pcie, bdf, offset); - - switch (size) { - case PCI_SIZE_8: - *valuep = readb(address); - return 0; - case PCI_SIZE_16: - *valuep = readw(address); - return 0; - case PCI_SIZE_32: - *valuep = readl(address); - return 0; - default: - return -EINVAL; - } + return pci_generic_mmap_read_config(bus, ls_pcie_conf_address, + bdf, offset, valuep, size); } static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size) { - struct ls_pcie *pcie = dev_get_priv(bus); - void *address; - - if (ls_pcie_addr_valid(pcie, bdf)) - return 0; - - address = ls_pcie_conf_address(pcie, bdf, offset); - - switch (size) { - case PCI_SIZE_8: - writeb(value, address); - return 0; - case PCI_SIZE_16: - writew(value, address); - return 0; - case PCI_SIZE_32: - writel(value, address); - return 0; - default: - return -EINVAL; - } + return pci_generic_mmap_write_config(bus, ls_pcie_conf_address, + bdf, offset, value, size); } /* Clear multi-function bit */ diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c index 4ba32df516..57112f5333 100644 --- a/drivers/pci/pcie_xilinx.c +++ b/drivers/pci/pcie_xilinx.c @@ -41,7 +41,7 @@ static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie) /** * pcie_xilinx_config_address() - Calculate the address of a config access - * @pcie: Pointer to the PCI controller state + * @udev: Pointer to the PCI bus * @bdf: Identifies the PCIe device to access * @offset: The offset into the device's configuration space * @paddress: Pointer to the pointer to write the calculates address to @@ -55,9 +55,10 @@ static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie) * * Return: 0 on success, else -ENODEV */ -static int pcie_xilinx_config_address(struct xilinx_pcie *pcie, pci_dev_t bdf, +static int pcie_xilinx_config_address(struct udevice *udev, pci_dev_t bdf, uint offset, void **paddress) { + struct xilinx_pcie *pcie = dev_get_priv(udev); unsigned int bus = PCI_BUS(bdf); unsigned int dev = PCI_DEV(bdf); unsigned int func = PCI_FUNC(bdf); @@ -101,29 +102,8 @@ static int pcie_xilinx_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { - struct xilinx_pcie *pcie = dev_get_priv(bus); - void *address; - int err; - - err = pcie_xilinx_config_address(pcie, bdf, offset, &address); - if (err < 0) { - *valuep = pci_get_ff(size); - return 0; - } - - switch (size) { - case PCI_SIZE_8: - *valuep = __raw_readb(address); - return 0; - case PCI_SIZE_16: - *valuep = __raw_readw(address); - return 0; - case PCI_SIZE_32: - *valuep = __raw_readl(address); - return 0; - default: - return -EINVAL; - } + return pci_generic_mmap_read_config(bus, pcie_xilinx_config_address, + bdf, offset, valuep, size); } /** @@ -144,27 +124,8 @@ static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size) { - struct xilinx_pcie *pcie = dev_get_priv(bus); - void *address; - int err; - - err = pcie_xilinx_config_address(pcie, bdf, offset, &address); - if (err < 0) - return 0; - - switch (size) { - case PCI_SIZE_8: - __raw_writeb(value, address); - return 0; - case PCI_SIZE_16: - __raw_writew(value, address); - return 0; - case PCI_SIZE_32: - __raw_writel(value, address); - return 0; - default: - return -EINVAL; - } + return pci_generic_mmap_write_config(bus, pcie_xilinx_config_address, + bdf, offset, value, size); } /** @@ -187,7 +148,7 @@ static int pcie_xilinx_ofdata_to_platdata(struct udevice *dev) err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", 0, ®_res); if (err < 0) { - error("\"reg\" resource not found\n"); + pr_err("\"reg\" resource not found\n"); return err; } |