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-rw-r--r--drivers/phy/Kconfig33
-rw-r--r--drivers/phy/Makefile5
-rw-r--r--drivers/phy/bcm6318-usbh-phy.c144
-rw-r--r--drivers/phy/bcm6348-usbh-phy.c94
-rw-r--r--drivers/phy/bcm6358-usbh-phy.c94
-rw-r--r--drivers/phy/bcm6368-usbh-phy.c196
-rw-r--r--drivers/phy/meson-gxl-usb2.c238
-rw-r--r--drivers/phy/meson-gxl-usb3.c201
8 files changed, 1005 insertions, 0 deletions
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 3b9a09ce18..119edec204 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -59,6 +59,31 @@ config SPL_NOP_PHY
This is useful when a driver uses the PHY framework but no real PHY
hardware exists.
+config BCM6318_USBH_PHY
+ bool "BCM6318 USBH PHY support"
+ depends on PHY && ARCH_BMIPS
+ select POWER_DOMAIN
+ help
+ Support for the Broadcom MIPS BCM6318 USBH PHY.
+
+config BCM6348_USBH_PHY
+ bool "BCM6348 USBH PHY support"
+ depends on PHY && ARCH_BMIPS
+ help
+ Support for the Broadcom MIPS BCM6348 USBH PHY.
+
+config BCM6358_USBH_PHY
+ bool "BCM6358 USBH PHY support"
+ depends on PHY && ARCH_BMIPS
+ help
+ Support for the Broadcom MIPS BCM6358 USBH PHY.
+
+config BCM6368_USBH_PHY
+ bool "BCM6368 USBH PHY support"
+ depends on PHY && ARCH_BMIPS
+ help
+ Support for the Broadcom MIPS BCM6368 USBH PHY.
+
config PIPE3_PHY
bool "Support omap's PIPE3 PHY"
depends on PHY && ARCH_OMAP2PLUS
@@ -85,4 +110,12 @@ config STI_USB_PHY
used by USB2 and USB3 Host controllers available on
STiH407 SoC families.
+config MESON_GXL_USB_PHY
+ bool "Amlogic Meson GXL USB PHYs"
+ depends on PHY && ARCH_MESON && MESON_GXL
+ imply REGMAP
+ help
+ This is the generic phy driver for the Amlogic Meson GXL
+ USB2 and USB3 PHYS.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 668040b0bb..72c14921b0 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,11 @@
obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o
obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o
+obj-$(CONFIG_BCM6318_USBH_PHY) += bcm6318-usbh-phy.o
+obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o
+obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o
+obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o
obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
+obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
diff --git a/drivers/phy/bcm6318-usbh-phy.c b/drivers/phy/bcm6318-usbh-phy.c
new file mode 100644
index 0000000000..6d54214581
--- /dev/null
+++ b/drivers/phy/bcm6318-usbh-phy.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/usb-common.c:
+ * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <power-domain.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+/* USBH Setup register */
+#define USBH_SETUP_REG 0x00
+#define USBH_SETUP_IOC BIT(4)
+
+/* USBH PLL Control register */
+#define USBH_PLL_REG 0x04
+#define USBH_PLL_SUSP_EN BIT(27)
+#define USBH_PLL_IDDQ_PWRDN BIT(31)
+
+/* USBH Swap Control register */
+#define USBH_SWAP_REG 0x0c
+#define USBH_SWAP_OHCI_DATA BIT(0)
+#define USBH_SWAP_OHCI_ENDIAN BIT(1)
+#define USBH_SWAP_EHCI_DATA BIT(3)
+#define USBH_SWAP_EHCI_ENDIAN BIT(4)
+
+/* USBH Sim Control register */
+#define USBH_SIM_REG 0x20
+#define USBH_SIM_LADDR BIT(5)
+
+struct bcm6318_usbh_priv {
+ void __iomem *regs;
+};
+
+static int bcm6318_usbh_init(struct phy *phy)
+{
+ struct bcm6318_usbh_priv *priv = dev_get_priv(phy->dev);
+
+ /* enable pll control susp */
+ setbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_SUSP_EN);
+
+ /* configure to work in native cpu endian */
+ clrsetbits_be32(priv->regs + USBH_SWAP_REG,
+ USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
+ USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
+
+ /* setup config */
+ setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
+
+ /* disable pll control pwrdn */
+ clrbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_IDDQ_PWRDN);
+
+ /* sim control config */
+ setbits_be32(priv->regs + USBH_SIM_REG, USBH_SIM_LADDR);
+
+ return 0;
+}
+
+static struct phy_ops bcm6318_usbh_ops = {
+ .init = bcm6318_usbh_init,
+};
+
+static const struct udevice_id bcm6318_usbh_ids[] = {
+ { .compatible = "brcm,bcm6318-usbh" },
+ { /* sentinel */ }
+};
+
+static int bcm6318_usbh_probe(struct udevice *dev)
+{
+ struct bcm6318_usbh_priv *priv = dev_get_priv(dev);
+ struct power_domain pwr_dom;
+ struct reset_ctl rst_ctl;
+ struct clk clk;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+
+ /* enable usbh clock */
+ ret = clk_get_by_name(dev, "usbh", &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_free(&clk);
+ if (ret < 0)
+ return ret;
+
+ /* enable power domain */
+ ret = power_domain_get(dev, &pwr_dom);
+ if (ret < 0)
+ return ret;
+
+ ret = power_domain_on(&pwr_dom);
+ if (ret < 0)
+ return ret;
+
+ ret = power_domain_free(&pwr_dom);
+ if (ret < 0)
+ return ret;
+
+ /* perform reset */
+ ret = reset_get_by_index(dev, 0, &rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_deassert(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_free(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ mdelay(100);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bcm6318_usbh) = {
+ .name = "bcm6318-usbh",
+ .id = UCLASS_PHY,
+ .of_match = bcm6318_usbh_ids,
+ .ops = &bcm6318_usbh_ops,
+ .priv_auto_alloc_size = sizeof(struct bcm6318_usbh_priv),
+ .probe = bcm6318_usbh_probe,
+};
diff --git a/drivers/phy/bcm6348-usbh-phy.c b/drivers/phy/bcm6348-usbh-phy.c
new file mode 100644
index 0000000000..169ee0ecec
--- /dev/null
+++ b/drivers/phy/bcm6348-usbh-phy.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/usb-common.c:
+ * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+#define USBH_SETUP_PORT1_EN BIT(0)
+
+struct bcm6348_usbh_priv {
+ void __iomem *regs;
+};
+
+static int bcm6348_usbh_init(struct phy *phy)
+{
+ struct bcm6348_usbh_priv *priv = dev_get_priv(phy->dev);
+
+ writel_be(USBH_SETUP_PORT1_EN, priv->regs);
+
+ return 0;
+}
+
+static struct phy_ops bcm6348_usbh_ops = {
+ .init = bcm6348_usbh_init,
+};
+
+static const struct udevice_id bcm6348_usbh_ids[] = {
+ { .compatible = "brcm,bcm6348-usbh" },
+ { /* sentinel */ }
+};
+
+static int bcm6348_usbh_probe(struct udevice *dev)
+{
+ struct bcm6348_usbh_priv *priv = dev_get_priv(dev);
+ struct reset_ctl rst_ctl;
+ struct clk clk;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+
+ /* enable usbh clock */
+ ret = clk_get_by_name(dev, "usbh", &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_free(&clk);
+ if (ret < 0)
+ return ret;
+
+ /* perform reset */
+ ret = reset_get_by_index(dev, 0, &rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_deassert(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_free(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bcm6348_usbh) = {
+ .name = "bcm6348-usbh",
+ .id = UCLASS_PHY,
+ .of_match = bcm6348_usbh_ids,
+ .ops = &bcm6348_usbh_ops,
+ .priv_auto_alloc_size = sizeof(struct bcm6348_usbh_priv),
+ .probe = bcm6348_usbh_probe,
+};
diff --git a/drivers/phy/bcm6358-usbh-phy.c b/drivers/phy/bcm6358-usbh-phy.c
new file mode 100644
index 0000000000..e000316a93
--- /dev/null
+++ b/drivers/phy/bcm6358-usbh-phy.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/usb-common.c:
+ * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+/* USBH Swap Control register */
+#define USBH_SWAP_REG 0x00
+#define USBH_SWAP_OHCI_DATA BIT(0)
+#define USBH_SWAP_OHCI_ENDIAN BIT(1)
+#define USBH_SWAP_EHCI_DATA BIT(3)
+#define USBH_SWAP_EHCI_ENDIAN BIT(4)
+
+/* USBH Test register */
+#define USBH_TEST_REG 0x24
+#define USBH_TEST_PORT_CTL 0x1c0020
+
+struct bcm6358_usbh_priv {
+ void __iomem *regs;
+};
+
+static int bcm6358_usbh_init(struct phy *phy)
+{
+ struct bcm6358_usbh_priv *priv = dev_get_priv(phy->dev);
+
+ /* configure to work in native cpu endian */
+ clrsetbits_be32(priv->regs + USBH_SWAP_REG,
+ USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
+ USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
+
+ /* test port control */
+ writel_be(USBH_TEST_PORT_CTL, priv->regs + USBH_TEST_REG);
+
+ return 0;
+}
+
+static struct phy_ops bcm6358_usbh_ops = {
+ .init = bcm6358_usbh_init,
+};
+
+static const struct udevice_id bcm6358_usbh_ids[] = {
+ { .compatible = "brcm,bcm6358-usbh" },
+ { /* sentinel */ }
+};
+
+static int bcm6358_usbh_probe(struct udevice *dev)
+{
+ struct bcm6358_usbh_priv *priv = dev_get_priv(dev);
+ struct reset_ctl rst_ctl;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+
+ /* perform reset */
+ ret = reset_get_by_index(dev, 0, &rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_deassert(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_free(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bcm6358_usbh) = {
+ .name = "bcm6358-usbh",
+ .id = UCLASS_PHY,
+ .of_match = bcm6358_usbh_ids,
+ .ops = &bcm6358_usbh_ops,
+ .priv_auto_alloc_size = sizeof(struct bcm6358_usbh_priv),
+ .probe = bcm6358_usbh_probe,
+};
diff --git a/drivers/phy/bcm6368-usbh-phy.c b/drivers/phy/bcm6368-usbh-phy.c
new file mode 100644
index 0000000000..71abc0fcc4
--- /dev/null
+++ b/drivers/phy/bcm6368-usbh-phy.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/bcm63xx/usb-common.c:
+ * Copyright 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright 2013 Florian Fainelli <florian@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <power-domain.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <dm/device.h>
+
+/* USBH PLL Control register */
+#define USBH_PLL_REG 0x18
+#define USBH_PLL_IDDQ_PWRDN BIT(9)
+#define USBH_PLL_PWRDN_DELAY BIT(10)
+
+/* USBH Swap Control register */
+#define USBH_SWAP_REG 0x1c
+#define USBH_SWAP_OHCI_DATA BIT(0)
+#define USBH_SWAP_OHCI_ENDIAN BIT(1)
+#define USBH_SWAP_EHCI_DATA BIT(3)
+#define USBH_SWAP_EHCI_ENDIAN BIT(4)
+
+/* USBH Setup register */
+#define USBH_SETUP_REG 0x28
+#define USBH_SETUP_IOC BIT(4)
+#define USBH_SETUP_IPP BIT(5)
+
+struct bcm6368_usbh_hw {
+ uint32_t setup_clr;
+ uint32_t pll_clr;
+};
+
+struct bcm6368_usbh_priv {
+ const struct bcm6368_usbh_hw *hw;
+ void __iomem *regs;
+};
+
+static int bcm6368_usbh_init(struct phy *phy)
+{
+ struct bcm6368_usbh_priv *priv = dev_get_priv(phy->dev);
+ const struct bcm6368_usbh_hw *hw = priv->hw;
+
+ /* configure to work in native cpu endian */
+ clrsetbits_be32(priv->regs + USBH_SWAP_REG,
+ USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN,
+ USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA);
+
+ /* setup config */
+ if (hw->setup_clr)
+ clrbits_be32(priv->regs + USBH_SETUP_REG, hw->setup_clr);
+
+ setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC);
+
+ /* enable pll control */
+ if (hw->pll_clr)
+ clrbits_be32(priv->regs + USBH_PLL_REG, hw->pll_clr);
+
+ return 0;
+}
+
+static struct phy_ops bcm6368_usbh_ops = {
+ .init = bcm6368_usbh_init,
+};
+
+static const struct bcm6368_usbh_hw bcm6328_hw = {
+ .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
+ .setup_clr = 0,
+};
+
+static const struct bcm6368_usbh_hw bcm6362_hw = {
+ .pll_clr = 0,
+ .setup_clr = 0,
+};
+
+static const struct bcm6368_usbh_hw bcm6368_hw = {
+ .pll_clr = 0,
+ .setup_clr = 0,
+};
+
+static const struct bcm6368_usbh_hw bcm63268_hw = {
+ .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY,
+ .setup_clr = USBH_SETUP_IPP,
+};
+
+static const struct udevice_id bcm6368_usbh_ids[] = {
+ {
+ .compatible = "brcm,bcm6328-usbh",
+ .data = (ulong)&bcm6328_hw,
+ }, {
+ .compatible = "brcm,bcm6362-usbh",
+ .data = (ulong)&bcm6362_hw,
+ }, {
+ .compatible = "brcm,bcm6368-usbh",
+ .data = (ulong)&bcm6368_hw,
+ }, {
+ .compatible = "brcm,bcm63268-usbh",
+ .data = (ulong)&bcm63268_hw,
+ }, { /* sentinel */ }
+};
+
+static int bcm6368_usbh_probe(struct udevice *dev)
+{
+ struct bcm6368_usbh_priv *priv = dev_get_priv(dev);
+ const struct bcm6368_usbh_hw *hw =
+ (const struct bcm6368_usbh_hw *)dev_get_driver_data(dev);
+#if defined(CONFIG_POWER_DOMAIN)
+ struct power_domain pwr_dom;
+#endif
+ struct reset_ctl rst_ctl;
+ struct clk clk;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+ priv->hw = hw;
+
+ /* enable usbh clock */
+ ret = clk_get_by_name(dev, "usbh", &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_free(&clk);
+ if (ret < 0)
+ return ret;
+
+#if defined(CONFIG_POWER_DOMAIN)
+ /* enable power domain */
+ ret = power_domain_get(dev, &pwr_dom);
+ if (ret < 0)
+ return ret;
+
+ ret = power_domain_on(&pwr_dom);
+ if (ret < 0)
+ return ret;
+
+ ret = power_domain_free(&pwr_dom);
+ if (ret < 0)
+ return ret;
+#endif
+
+ /* perform reset */
+ ret = reset_get_by_index(dev, 0, &rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_deassert(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ ret = reset_free(&rst_ctl);
+ if (ret < 0)
+ return ret;
+
+ /* enable usb_ref clock */
+ ret = clk_get_by_name(dev, "usb_ref", &clk);
+ if (!ret) {
+ ret = clk_enable(&clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_free(&clk);
+ if (ret < 0)
+ return ret;
+ }
+
+ mdelay(100);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(bcm6368_usbh) = {
+ .name = "bcm6368-usbh",
+ .id = UCLASS_PHY,
+ .of_match = bcm6368_usbh_ids,
+ .ops = &bcm6368_usbh_ops,
+ .priv_auto_alloc_size = sizeof(struct bcm6368_usbh_priv),
+ .probe = bcm6368_usbh_probe,
+};
diff --git a/drivers/phy/meson-gxl-usb2.c b/drivers/phy/meson-gxl-usb2.c
new file mode 100644
index 0000000000..15c9c89fd9
--- /dev/null
+++ b/drivers/phy/meson-gxl-usb2.c
@@ -0,0 +1,238 @@
+/*
+ * Meson GXL and GXM USB2 PHY driver
+ *
+ * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <clk.h>
+
+#include <linux/bitops.h>
+#include <linux/compat.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* bits [31:27] are read-only */
+#define U2P_R0 0x0
+ #define U2P_R0_BYPASS_SEL BIT(0)
+ #define U2P_R0_BYPASS_DM_EN BIT(1)
+ #define U2P_R0_BYPASS_DP_EN BIT(2)
+ #define U2P_R0_TXBITSTUFF_ENH BIT(3)
+ #define U2P_R0_TXBITSTUFF_EN BIT(4)
+ #define U2P_R0_DM_PULLDOWN BIT(5)
+ #define U2P_R0_DP_PULLDOWN BIT(6)
+ #define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7)
+ #define U2P_R0_DP_VBUS_VLD_EXT BIT(8)
+ #define U2P_R0_ADP_PRB_EN BIT(9)
+ #define U2P_R0_ADP_DISCHARGE BIT(10)
+ #define U2P_R0_ADP_CHARGE BIT(11)
+ #define U2P_R0_DRV_VBUS BIT(12)
+ #define U2P_R0_ID_PULLUP BIT(13)
+ #define U2P_R0_LOOPBACK_EN_B BIT(14)
+ #define U2P_R0_OTG_DISABLE BIT(15)
+ #define U2P_R0_COMMON_ONN BIT(16)
+ #define U2P_R0_FSEL_MASK GENMASK(19, 17)
+ #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
+ #define U2P_R0_POWER_ON_RESET BIT(22)
+ #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
+ #define U2P_R0_ID_SET_ID_DQ BIT(25)
+ #define U2P_R0_ATE_RESET BIT(26)
+ #define U2P_R0_FSV_MINUS BIT(27)
+ #define U2P_R0_FSV_PLUS BIT(28)
+ #define U2P_R0_BYPASS_DM_DATA BIT(29)
+ #define U2P_R0_BYPASS_DP_DATA BIT(30)
+
+#define U2P_R1 0x4
+ #define U2P_R1_BURN_IN_TEST BIT(0)
+ #define U2P_R1_ACA_ENABLE BIT(1)
+ #define U2P_R1_DCD_ENABLE BIT(2)
+ #define U2P_R1_VDAT_SRC_EN_B BIT(3)
+ #define U2P_R1_VDAT_DET_EN_B BIT(4)
+ #define U2P_R1_CHARGES_SEL BIT(5)
+ #define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6)
+ #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
+ #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
+ #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
+ #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
+ #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
+ #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
+ #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
+ #define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26)
+ #define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29)
+
+/* bits [31:14] are read-only */
+#define U2P_R2 0x8
+ #define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0)
+ #define U2P_R2_TESTADDR_MASK GENMASK(11, 8)
+ #define U2P_R2_TESTDATA_OUT_SEL BIT(12)
+ #define U2P_R2_TESTCLK BIT(13)
+ #define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14)
+ #define U2P_R2_ACA_PIN_RANGE_C BIT(18)
+ #define U2P_R2_ACA_PIN_RANGE_B BIT(19)
+ #define U2P_R2_ACA_PIN_RANGE_A BIT(20)
+ #define U2P_R2_ACA_PIN_GND BIT(21)
+ #define U2P_R2_ACA_PIN_FLOAT BIT(22)
+ #define U2P_R2_CHARGE_DETECT BIT(23)
+ #define U2P_R2_DEVICE_SESSION_VALID BIT(24)
+ #define U2P_R2_ADP_PROBE BIT(25)
+ #define U2P_R2_ADP_SENSE BIT(26)
+ #define U2P_R2_SESSION_END BIT(27)
+ #define U2P_R2_VBUS_VALID BIT(28)
+ #define U2P_R2_B_VALID BIT(29)
+ #define U2P_R2_A_VALID BIT(30)
+ #define U2P_R2_ID_DIG BIT(31)
+
+#define U2P_R3 0xc
+
+#define RESET_COMPLETE_TIME 500
+
+struct phy_meson_gxl_usb2_priv {
+ struct regmap *regmap;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ struct udevice *phy_supply;
+#endif
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+#endif
+};
+
+static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv)
+{
+ uint val;
+
+ regmap_read(priv->regmap, U2P_R0, &val);
+
+ /* reset the PHY and wait until settings are stabilized */
+ val |= U2P_R0_POWER_ON_RESET;
+ regmap_write(priv->regmap, U2P_R0, val);
+ udelay(RESET_COMPLETE_TIME);
+
+ val &= ~U2P_R0_POWER_ON_RESET;
+ regmap_write(priv->regmap, U2P_R0, val);
+ udelay(RESET_COMPLETE_TIME);
+}
+
+static void
+phy_meson_gxl_usb2_set_host_mode(struct phy_meson_gxl_usb2_priv *priv)
+{
+ uint val;
+
+ regmap_read(priv->regmap, U2P_R0, &val);
+ val |= U2P_R0_DM_PULLDOWN;
+ val |= U2P_R0_DP_PULLDOWN;
+ val &= ~U2P_R0_ID_PULLUP;
+ regmap_write(priv->regmap, U2P_R0, val);
+
+ phy_meson_gxl_usb2_reset(priv);
+}
+
+static int phy_meson_gxl_usb2_power_on(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
+ uint val;
+
+ regmap_read(priv->regmap, U2P_R0, &val);
+ /* power on the PHY by taking it out of reset mode */
+ val &= ~U2P_R0_POWER_ON_RESET;
+ regmap_write(priv->regmap, U2P_R0, val);
+
+ phy_meson_gxl_usb2_set_host_mode(priv);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (priv->phy_supply) {
+ int ret = regulator_set_enable(priv->phy_supply, true);
+ if (ret)
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static int phy_meson_gxl_usb2_power_off(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
+ uint val;
+
+ regmap_read(priv->regmap, U2P_R0, &val);
+ /* power off the PHY by putting it into reset mode */
+ val |= U2P_R0_POWER_ON_RESET;
+ regmap_write(priv->regmap, U2P_R0, val);
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (priv->phy_supply) {
+ int ret = regulator_set_enable(priv->phy_supply, false);
+ if (ret) {
+ pr_err("Error disabling PHY supply\n");
+ return ret;
+ }
+ }
+#endif
+
+ return 0;
+}
+
+struct phy_ops meson_gxl_usb2_phy_ops = {
+ .power_on = phy_meson_gxl_usb2_power_on,
+ .power_off = phy_meson_gxl_usb2_power_off,
+};
+
+int meson_gxl_usb2_phy_probe(struct udevice *dev)
+{
+ struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = regmap_init_mem(dev, &priv->regmap);
+ if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+ pr_err("failed to enable PHY clock\n");
+ clk_free(&priv->clk);
+ return ret;
+ }
+#endif
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get PHY regulator\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id meson_gxl_usb2_phy_ids[] = {
+ { .compatible = "amlogic,meson-gxl-usb2-phy" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
+ .name = "meson_gxl_usb2_phy",
+ .id = UCLASS_PHY,
+ .of_match = meson_gxl_usb2_phy_ids,
+ .probe = meson_gxl_usb2_phy_probe,
+ .ops = &meson_gxl_usb2_phy_ops,
+ .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv),
+};
diff --git a/drivers/phy/meson-gxl-usb3.c b/drivers/phy/meson-gxl-usb3.c
new file mode 100644
index 0000000000..a385fbdf12
--- /dev/null
+++ b/drivers/phy/meson-gxl-usb3.c
@@ -0,0 +1,201 @@
+/*
+ * Meson GXL USB3 PHY driver
+ *
+ * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstron@baylibre.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <clk.h>
+
+#include <linux/bitops.h>
+#include <linux/compat.h>
+#include <linux/bitfield.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define USB_R0 0x00
+ #define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
+ #define USB_R0_P30_PHY_RESET BIT(6)
+ #define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7)
+ #define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8)
+ #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
+ #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
+ #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
+ #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
+ #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
+ #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
+ #define USB_R0_U2D_ACT BIT(31)
+
+#define USB_R1 0x04
+ #define USB_R1_U3H_BIGENDIAN_GS BIT(0)
+ #define USB_R1_U3H_PME_ENABLE BIT(1)
+ #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
+ #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
+ #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
+ #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
+ #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
+ #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
+ #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
+ #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
+
+#define USB_R2 0x08
+ #define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0)
+ #define USB_R2_P30_CR_READ BIT(16)
+ #define USB_R2_P30_CR_WRITE BIT(17)
+ #define USB_R2_P30_CR_CAP_ADDR BIT(18)
+ #define USB_R2_P30_CR_CAP_DATA BIT(19)
+ #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
+ #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
+
+#define USB_R3 0x0c
+ #define USB_R3_P30_SSC_ENABLE BIT(0)
+ #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
+ #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
+ #define USB_R3_P30_REF_SSP_EN BIT(13)
+ #define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16)
+ #define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19)
+ #define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24)
+
+#define USB_R4 0x10
+ #define USB_R4_P21_PORT_RESET_0 BIT(0)
+ #define USB_R4_P21_SLEEP_M0 BIT(1)
+ #define USB_R4_MEM_PD_MASK GENMASK(3, 2)
+ #define USB_R4_P21_ONLY BIT(4)
+
+#define USB_R5 0x14
+ #define USB_R5_ID_DIG_SYNC BIT(0)
+ #define USB_R5_ID_DIG_REG BIT(1)
+ #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
+ #define USB_R5_ID_DIG_EN_0 BIT(4)
+ #define USB_R5_ID_DIG_EN_1 BIT(5)
+ #define USB_R5_ID_DIG_CURR BIT(6)
+ #define USB_R5_ID_DIG_IRQ BIT(7)
+ #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
+ #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
+
+/* read-only register */
+#define USB_R6 0x18
+ #define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0)
+ #define USB_R6_P30_CR_ACK BIT(16)
+
+struct phy_meson_gxl_usb3_priv {
+ struct regmap *regmap;
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+#endif
+};
+
+static int
+phy_meson_gxl_usb3_set_host_mode(struct phy_meson_gxl_usb3_priv *priv)
+{
+ uint val;
+
+ regmap_read(priv->regmap, USB_R0, &val);
+ val &= ~USB_R0_U2D_ACT;
+ regmap_write(priv->regmap, USB_R0, val);
+
+ regmap_read(priv->regmap, USB_R4, &val);
+ val &= ~USB_R4_P21_SLEEP_M0;
+ regmap_write(priv->regmap, USB_R4, val);
+
+ return 0;
+}
+
+static int phy_meson_gxl_usb3_power_on(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+ uint val;
+
+ regmap_read(priv->regmap, USB_R5, &val);
+ val |= USB_R5_ID_DIG_EN_0;
+ val |= USB_R5_ID_DIG_EN_1;
+ val &= ~USB_R5_ID_DIG_TH_MASK;
+ val |= FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff);
+ regmap_write(priv->regmap, USB_R5, val);
+
+ return phy_meson_gxl_usb3_set_host_mode(priv);
+}
+
+static int phy_meson_gxl_usb3_power_off(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+ uint val;
+
+ regmap_read(priv->regmap, USB_R5, &val);
+ val &= ~USB_R5_ID_DIG_EN_0;
+ val &= ~USB_R5_ID_DIG_EN_1;
+ regmap_write(priv->regmap, USB_R5, val);
+
+ return 0;
+}
+
+static int phy_meson_gxl_usb3_init(struct phy *phy)
+{
+ struct udevice *dev = phy->dev;
+ struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+ uint val;
+
+ regmap_read(priv->regmap, USB_R1, &val);
+ val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK;
+ val |= FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20);
+ regmap_write(priv->regmap, USB_R1, val);
+
+ return 0;
+}
+
+struct phy_ops meson_gxl_usb3_phy_ops = {
+ .init = phy_meson_gxl_usb3_init,
+ .power_on = phy_meson_gxl_usb3_power_on,
+ .power_off = phy_meson_gxl_usb3_power_off,
+};
+
+int meson_gxl_usb3_phy_probe(struct udevice *dev)
+{
+ struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = regmap_init_mem(dev, &priv->regmap);
+ if (ret)
+ return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
+ pr_err("failed to enable PHY clock\n");
+ clk_free(&priv->clk);
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id meson_gxl_usb3_phy_ids[] = {
+ { .compatible = "amlogic,meson-gxl-usb3-phy" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_gxl_usb3_phy) = {
+ .name = "meson_gxl_usb3_phy",
+ .id = UCLASS_PHY,
+ .of_match = meson_gxl_usb3_phy_ids,
+ .probe = meson_gxl_usb3_phy_probe,
+ .ops = &meson_gxl_usb3_phy_ops,
+ .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb3_priv),
+};
generated by cgit (git 2.34.1) at 2024-12-23 19:58:11 +0000