diff options
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 52 | ||||
| -rw-r--r-- | drivers/pinctrl/rockchip/pinctrl_rk3036.c | 410 | ||||
| -rw-r--r-- | drivers/pinctrl/rockchip/pinctrl_rk3188.c | 380 | ||||
| -rw-r--r-- | drivers/pinctrl/rockchip/pinctrl_rk3399.c | 61 |
4 files changed, 877 insertions, 26 deletions
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 2bf853eba1..010eb203b7 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -44,7 +44,7 @@ DECLARE_GLOBAL_DATA_PTR; #define IRQ_STATUS 0x10 #define IRQ_WKUP 0x18 -#define NB_FUNCS 2 +#define NB_FUNCS 3 #define GPIO_PER_REG 32 /** @@ -128,6 +128,16 @@ struct armada_37xx_pinctrl { .funcs = {_func1, "gpio"} \ } +#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \ + { \ + .name = _name, \ + .start_pin = _start, \ + .npins = _nr, \ + .reg_mask = _mask, \ + .val = {_v1, _v2, _v3}, \ + .funcs = {_f1, _f2, "gpio"} \ + } + #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \ _f1, _f2) \ { \ @@ -149,8 +159,8 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"), PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"), PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"), - PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"), - PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"), + PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"), + PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"), PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"), PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"), PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"), @@ -172,13 +182,15 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"), - PIN_GRP_GPIO("sdio_sb", 24, 5, BIT(2), "sdio"), - PIN_GRP_EXTRA("rgmii", 6, 14, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"), - PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"), - PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"), + PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), + PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"), + PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), + PIN_GRP_GPIO("pcie1", 3, 3, BIT(5) | BIT(9) | BIT(10), "pcie"), + PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), - PIN_GRP("mii_col", 23, 1, BIT(8), "mii", "mii_err"), + PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), + "mii", "mii_err"), }; const struct armada_37xx_pin_data armada_37xx_pin_nb = { @@ -189,18 +201,18 @@ const struct armada_37xx_pin_data armada_37xx_pin_nb = { }; const struct armada_37xx_pin_data armada_37xx_pin_sb = { - .nr_pins = 29, + .nr_pins = 30, .name = "GPIO2", .groups = armada_37xx_sb_groups, .ngroups = ARRAY_SIZE(armada_37xx_sb_groups), }; static inline void armada_37xx_update_reg(unsigned int *reg, - unsigned int offset) + unsigned int *offset) { /* We never have more than 2 registers */ - if (offset >= GPIO_PER_REG) { - offset -= GPIO_PER_REG; + if (*offset >= GPIO_PER_REG) { + *offset -= GPIO_PER_REG; *reg += sizeof(u32); } } @@ -210,7 +222,7 @@ static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp, { int f; - for (f = 0; f < NB_FUNCS; f++) + for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) if (!strcmp(grp->funcs[f], func)) return f; @@ -352,7 +364,7 @@ static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) for (j = 0; j < grp->extra_npins; j++) grp->pins[i+j] = grp->extra_pin + j; - for (f = 0; f < NB_FUNCS; f++) { + for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) { int ret; /* check for unique functions and count groups */ ret = armada_37xx_add_function(info->funcs, &funcsize, @@ -404,7 +416,7 @@ static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) struct armada_37xx_pin_group *gp = &info->groups[g]; int f; - for (f = 0; f < NB_FUNCS; f++) { + for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) { if (strcmp(gp->funcs[f], name) == 0) { *groups = gp->name; groups++; @@ -421,7 +433,7 @@ static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset) unsigned int reg = INPUT_VAL; unsigned int val, mask; - armada_37xx_update_reg(®, offset); + armada_37xx_update_reg(®, &offset); mask = BIT(offset); val = readl(info->base + reg); @@ -436,7 +448,7 @@ static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset, unsigned int reg = OUTPUT_VAL; unsigned int mask, val; - armada_37xx_update_reg(®, offset); + armada_37xx_update_reg(®, &offset); mask = BIT(offset); val = value ? mask : 0; @@ -452,7 +464,7 @@ static int armada_37xx_gpio_get_direction(struct udevice *dev, unsigned int reg = OUTPUT_EN; unsigned int val, mask; - armada_37xx_update_reg(®, offset); + armada_37xx_update_reg(®, &offset); mask = BIT(offset); val = readl(info->base + reg); @@ -469,7 +481,7 @@ static int armada_37xx_gpio_direction_input(struct udevice *dev, unsigned int reg = OUTPUT_EN; unsigned int mask; - armada_37xx_update_reg(®, offset); + armada_37xx_update_reg(®, &offset); mask = BIT(offset); clrbits_le32(info->base + reg, mask); @@ -484,7 +496,7 @@ static int armada_37xx_gpio_direction_output(struct udevice *dev, unsigned int reg = OUTPUT_EN; unsigned int mask; - armada_37xx_update_reg(®, offset); + armada_37xx_update_reg(®, &offset); mask = BIT(offset); setbits_le32(info->base + reg, mask); diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c index 94f6d7ad40..7e93d85dbb 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c @@ -18,6 +18,416 @@ DECLARE_GLOBAL_DATA_PTR; +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 1 << GPIO0A3_SHIFT, + GPIO0A3_GPIO = 0, + GPIO0A3_I2C1_SDA, + + GPIO0A2_SHIFT = 4, + GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, + GPIO0A2_GPIO = 0, + GPIO0A2_I2C1_SCL, + + GPIO0A1_SHIFT = 2, + GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, + GPIO0A1_GPIO = 0, + GPIO0A1_I2C0_SDA, + GPIO0A1_PWM2, + + GPIO0A0_SHIFT = 0, + GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, + GPIO0A0_GPIO = 0, + GPIO0A0_I2C0_SCL, + GPIO0A0_PWM1, +}; + +/* GRF_GPIO0B_IOMUX */ +enum { + GPIO0B6_SHIFT = 12, + GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, + GPIO0B6_GPIO = 0, + GPIO0B6_MMC1_D3, + GPIO0B6_I2S1_SCLK, + + GPIO0B5_SHIFT = 10, + GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, + GPIO0B5_GPIO = 0, + GPIO0B5_MMC1_D2, + GPIO0B5_I2S1_SDI, + + GPIO0B4_SHIFT = 8, + GPIO0B4_MASK = 3 << GPIO0B4_SHIFT, + GPIO0B4_GPIO = 0, + GPIO0B4_MMC1_D1, + GPIO0B4_I2S1_LRCKTX, + + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, + GPIO0B3_GPIO = 0, + GPIO0B3_MMC1_D0, + GPIO0B3_I2S1_LRCKRX, + + GPIO0B1_SHIFT = 2, + GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, + GPIO0B1_GPIO = 0, + GPIO0B1_MMC1_CLKOUT, + GPIO0B1_I2S1_MCLK, + + GPIO0B0_SHIFT = 0, + GPIO0B0_MASK = 3, + GPIO0B0_GPIO = 0, + GPIO0B0_MMC1_CMD, + GPIO0B0_I2S1_SDO, +}; + +/* GRF_GPIO0C_IOMUX */ +enum { + GPIO0C4_SHIFT = 8, + GPIO0C4_MASK = 1 << GPIO0C4_SHIFT, + GPIO0C4_GPIO = 0, + GPIO0C4_DRIVE_VBUS, + + GPIO0C3_SHIFT = 6, + GPIO0C3_MASK = 1 << GPIO0C3_SHIFT, + GPIO0C3_GPIO = 0, + GPIO0C3_UART0_CTSN, + + GPIO0C2_SHIFT = 4, + GPIO0C2_MASK = 1 << GPIO0C2_SHIFT, + GPIO0C2_GPIO = 0, + GPIO0C2_UART0_RTSN, + + GPIO0C1_SHIFT = 2, + GPIO0C1_MASK = 1 << GPIO0C1_SHIFT, + GPIO0C1_GPIO = 0, + GPIO0C1_UART0_SIN, + + + GPIO0C0_SHIFT = 0, + GPIO0C0_MASK = 1 << GPIO0C0_SHIFT, + GPIO0C0_GPIO = 0, + GPIO0C0_UART0_SOUT, +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, + GPIO0D4_GPIO = 0, + GPIO0D4_SPDIF, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, + GPIO0D3_GPIO = 0, + GPIO0D3_PWM3, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, + GPIO0D2_GPIO = 0, + GPIO0D2_PWM0, +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A5_SHIFT = 10, + GPIO1A5_MASK = 1 << GPIO1A5_SHIFT, + GPIO1A5_GPIO = 0, + GPIO1A5_I2S_SDI, + + GPIO1A4_SHIFT = 8, + GPIO1A4_MASK = 1 << GPIO1A4_SHIFT, + GPIO1A4_GPIO = 0, + GPIO1A4_I2S_SD0, + + GPIO1A3_SHIFT = 6, + GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, + GPIO1A3_GPIO = 0, + GPIO1A3_I2S_LRCKTX, + + GPIO1A2_SHIFT = 4, + GPIO1A2_MASK = 3 << GPIO1A2_SHIFT, + GPIO1A2_GPIO = 0, + GPIO1A2_I2S_LRCKRX, + GPIO1A2_PWM1_0, + + GPIO1A1_SHIFT = 2, + GPIO1A1_MASK = 1 << GPIO1A1_SHIFT, + GPIO1A1_GPIO = 0, + GPIO1A1_I2S_SCLK, + + GPIO1A0_SHIFT = 0, + GPIO1A0_MASK = 1 << GPIO1A0_SHIFT, + GPIO1A0_GPIO = 0, + GPIO1A0_I2S_MCLK, + +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, + GPIO1B7_GPIO = 0, + GPIO1B7_MMC0_CMD, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 1 << GPIO1B3_SHIFT, + GPIO1B3_GPIO = 0, + GPIO1B3_HDMI_HPD, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 1 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_HDMI_SCL, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 1 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_HDMI_SDA, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 1 << GPIO1B0_SHIFT, + GPIO1B0_GPIO = 0, + GPIO1B0_HDMI_CEC, +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, + GPIO1C5_GPIO = 0, + GPIO1C5_MMC0_D3, + GPIO1C5_JTAG_TMS, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, + GPIO1C4_GPIO = 0, + GPIO1C4_MMC0_D2, + GPIO1C4_JTAG_TCK, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_MMC0_D1, + GPIO1C3_UART2_SOUT, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , + GPIO1C2_GPIO = 0, + GPIO1C2_MMC0_D0, + GPIO1C2_UART2_SIN, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, + GPIO1C1_GPIO = 0, + GPIO1C1_MMC0_DETN, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, + GPIO1C0_GPIO = 0, + GPIO1C0_MMC0_CLKOUT, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, + GPIO1D7_GPIO = 0, + GPIO1D7_NAND_D7, + GPIO1D7_EMMC_D7, + GPIO1D7_SPI_CSN1, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, + GPIO1D6_GPIO = 0, + GPIO1D6_NAND_D6, + GPIO1D6_EMMC_D6, + GPIO1D6_SPI_CSN0, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, + GPIO1D5_GPIO = 0, + GPIO1D5_NAND_D5, + GPIO1D5_EMMC_D5, + GPIO1D5_SPI_TXD, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, + GPIO1D4_GPIO = 0, + GPIO1D4_NAND_D4, + GPIO1D4_EMMC_D4, + GPIO1D4_SPI_RXD, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, + GPIO1D3_GPIO = 0, + GPIO1D3_NAND_D3, + GPIO1D3_EMMC_D3, + GPIO1D3_SFC_SIO3, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, + GPIO1D2_GPIO = 0, + GPIO1D2_NAND_D2, + GPIO1D2_EMMC_D2, + GPIO1D2_SFC_SIO2, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, + GPIO1D1_GPIO = 0, + GPIO1D1_NAND_D1, + GPIO1D1_EMMC_D1, + GPIO1D1_SFC_SIO1, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, + GPIO1D0_GPIO = 0, + GPIO1D0_NAND_D0, + GPIO1D0_EMMC_D0, + GPIO1D0_SFC_SIO0, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 1 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_TESTCLK_OUT, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, + GPIO2A6_GPIO = 0, + GPIO2A6_NAND_CS0, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_NAND_RDY, + GPIO2A4_EMMC_CMD, + GPIO2A3_SFC_CLK, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_NAND_RDN, + GPIO2A4_SFC_CSN1, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_NAND_WRN, + GPIO2A4_SFC_CSN0, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_NAND_CLE, + GPIO2A1_EMMC_CLKOUT, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_NAND_ALE, + GPIO2A0_SPI_CLK, +}; + +/* GRF_GPIO2B_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 1 << GPIO2B7_SHIFT, + GPIO2B7_GPIO = 0, + GPIO2B7_MAC_RXER, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, + GPIO2B6_GPIO = 0, + GPIO2B6_MAC_CLKOUT, + GPIO2B6_MAC_CLKIN, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, + GPIO2B5_GPIO = 0, + GPIO2B5_MAC_TXEN, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 1 << GPIO2B4_SHIFT, + GPIO2B4_GPIO = 0, + GPIO2B4_MAC_MDIO, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, + GPIO2B2_GPIO = 0, + GPIO2B2_MAC_CRS, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C7_SHIFT = 14, + GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, + GPIO2C7_GPIO = 0, + GPIO2C7_UART1_SOUT, + GPIO2C7_TESTCLK_OUT1, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 1 << GPIO2C6_SHIFT, + GPIO2C6_GPIO = 0, + GPIO2C6_UART1_SIN, + + GPIO2C5_SHIFT = 10, + GPIO2C5_MASK = 1 << GPIO2C5_SHIFT, + GPIO2C5_GPIO = 0, + GPIO2C5_I2C2_SCL, + + GPIO2C4_SHIFT = 8, + GPIO2C4_MASK = 1 << GPIO2C4_SHIFT, + GPIO2C4_GPIO = 0, + GPIO2C4_I2C2_SDA, + + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 1 << GPIO2C3_SHIFT, + GPIO2C3_GPIO = 0, + GPIO2C3_MAC_TXD0, + + GPIO2C2_SHIFT = 4, + GPIO2C2_MASK = 1 << GPIO2C2_SHIFT, + GPIO2C2_GPIO = 0, + GPIO2C2_MAC_TXD1, + + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 1 << GPIO2C1_SHIFT, + GPIO2C1_GPIO = 0, + GPIO2C1_MAC_RXD0, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 1 << GPIO2C0_SHIFT, + GPIO2C0_GPIO = 0, + GPIO2C0_MAC_RXD1, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, + GPIO2D6_GPIO = 0, + GPIO2D6_I2S_SDO1, + + GPIO2D5_SHIFT = 10, + GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, + GPIO2D5_GPIO = 0, + GPIO2D5_I2S_SDO2, + + GPIO2D4_SHIFT = 8, + GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, + GPIO2D4_GPIO = 0, + GPIO2D4_I2S_SDO3, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 1 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_MAC_MDC, +}; + struct rk3036_pinctrl_priv { struct rk3036_grf *grf; }; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3188.c b/drivers/pinctrl/rockchip/pinctrl_rk3188.c index 692d8e298d..fdab836e5a 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3188.c @@ -20,6 +20,386 @@ DECLARE_GLOBAL_DATA_PTR; +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D7_SHIFT = 14, + GPIO0D7_MASK = 1, + GPIO0D7_GPIO = 0, + GPIO0D7_SPI1_CSN0, + + GPIO0D6_SHIFT = 12, + GPIO0D6_MASK = 1, + GPIO0D6_GPIO = 0, + GPIO0D6_SPI1_CLK, + + GPIO0D5_SHIFT = 10, + GPIO0D5_MASK = 1, + GPIO0D5_GPIO = 0, + GPIO0D5_SPI1_TXD, + + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 1, + GPIO0D4_GPIO = 0, + GPIO0D4_SPI0_RXD, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 3, + GPIO0D3_GPIO = 0, + GPIO0D3_FLASH_CSN3, + GPIO0D3_EMMC_RSTN_OUT, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 3, + GPIO0D2_GPIO = 0, + GPIO0D2_FLASH_CSN2, + GPIO0D2_EMMC_CMD, + + GPIO0D1_SHIFT = 2, + GPIO0D1_MASK = 1, + GPIO0D1_GPIO = 0, + GPIO0D1_FLASH_CSN1, + + GPIO0D0_SHIFT = 0, + GPIO0D0_MASK = 3, + GPIO0D0_GPIO = 0, + GPIO0D0_FLASH_DQS, + GPIO0D0_EMMC_CLKOUT +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A7_SHIFT = 14, + GPIO1A7_MASK = 3, + GPIO1A7_GPIO = 0, + GPIO1A7_UART1_RTS_N, + GPIO1A7_SPI0_CSN0, + + GPIO1A6_SHIFT = 12, + GPIO1A6_MASK = 3, + GPIO1A6_GPIO = 0, + GPIO1A6_UART1_CTS_N, + GPIO1A6_SPI0_CLK, + + GPIO1A5_SHIFT = 10, + GPIO1A5_MASK = 3, + GPIO1A5_GPIO = 0, + GPIO1A5_UART1_SOUT, + GPIO1A5_SPI0_TXD, + + GPIO1A4_SHIFT = 8, + GPIO1A4_MASK = 3, + GPIO1A4_GPIO = 0, + GPIO1A4_UART1_SIN, + GPIO1A4_SPI0_RXD, + + GPIO1A3_SHIFT = 6, + GPIO1A3_MASK = 1, + GPIO1A3_GPIO = 0, + GPIO1A3_UART0_RTS_N, + + GPIO1A2_SHIFT = 4, + GPIO1A2_MASK = 1, + GPIO1A2_GPIO = 0, + GPIO1A2_UART0_CTS_N, + + GPIO1A1_SHIFT = 2, + GPIO1A1_MASK = 1, + GPIO1A1_GPIO = 0, + GPIO1A1_UART0_SOUT, + + GPIO1A0_SHIFT = 0, + GPIO1A0_MASK = 1, + GPIO1A0_GPIO = 0, + GPIO1A0_UART0_SIN, +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 1, + GPIO1B7_GPIO = 0, + GPIO1B7_SPI0_CSN1, + + GPIO1B6_SHIFT = 12, + GPIO1B6_MASK = 3, + GPIO1B6_GPIO = 0, + GPIO1B6_SPDIF_TX, + GPIO1B6_SPI1_CSN1, + + GPIO1B5_SHIFT = 10, + GPIO1B5_MASK = 3, + GPIO1B5_GPIO = 0, + GPIO1B5_UART3_RTS_N, + GPIO1B5_RESERVED, + + GPIO1B4_SHIFT = 8, + GPIO1B4_MASK = 3, + GPIO1B4_GPIO = 0, + GPIO1B4_UART3_CTS_N, + GPIO1B4_GPS_RFCLK, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 3, + GPIO1B3_GPIO = 0, + GPIO1B3_UART3_SOUT, + GPIO1B3_GPS_SIG, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3, + GPIO1B2_GPIO = 0, + GPIO1B2_UART3_SIN, + GPIO1B2_GPS_MAG, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3, + GPIO1B1_GPIO = 0, + GPIO1B1_UART2_SOUT, + GPIO1B1_JTAG_TDO, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3, + GPIO1B0_GPIO = 0, + GPIO1B0_UART2_SIN, + GPIO1B0_JTAG_TDI, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 1, + GPIO1D7_GPIO = 0, + GPIO1D7_I2C4_SCL, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 1, + GPIO1D6_GPIO = 0, + GPIO1D6_I2C4_SDA, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 1, + GPIO1D5_GPIO = 0, + GPIO1D5_I2C2_SCL, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 1, + GPIO1D4_GPIO = 0, + GPIO1D4_I2C2_SDA, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 1, + GPIO1D3_GPIO = 0, + GPIO1D3_I2C1_SCL, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 1, + GPIO1D2_GPIO = 0, + GPIO1D2_I2C1_SDA, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 1, + GPIO1D1_GPIO = 0, + GPIO1D1_I2C0_SCL, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 1, + GPIO1D0_GPIO = 0, + GPIO1D0_I2C0_SDA, +}; + +/* GRF_GPIO3A_IOMUX */ +enum { + GPIO3A7_SHIFT = 14, + GPIO3A7_MASK = 1, + GPIO3A7_GPIO = 0, + GPIO3A7_SDMMC0_DATA3, + + GPIO3A6_SHIFT = 12, + GPIO3A6_MASK = 1, + GPIO3A6_GPIO = 0, + GPIO3A6_SDMMC0_DATA2, + + GPIO3A5_SHIFT = 10, + GPIO3A5_MASK = 1, + GPIO3A5_GPIO = 0, + GPIO3A5_SDMMC0_DATA1, + + GPIO3A4_SHIFT = 8, + GPIO3A4_MASK = 1, + GPIO3A4_GPIO = 0, + GPIO3A4_SDMMC0_DATA0, + + GPIO3A3_SHIFT = 6, + GPIO3A3_MASK = 1, + GPIO3A3_GPIO = 0, + GPIO3A3_SDMMC0_CMD, + + GPIO3A2_SHIFT = 4, + GPIO3A2_MASK = 1, + GPIO3A2_GPIO = 0, + GPIO3A2_SDMMC0_CLKOUT, + + GPIO3A1_SHIFT = 2, + GPIO3A1_MASK = 1, + GPIO3A1_GPIO = 0, + GPIO3A1_SDMMC0_PWREN, + + GPIO3A0_SHIFT = 0, + GPIO3A0_MASK = 1, + GPIO3A0_GPIO = 0, + GPIO3A0_SDMMC0_RSTN, +}; + +/* GRF_GPIO3B_IOMUX */ +enum { + GPIO3B7_SHIFT = 14, + GPIO3B7_MASK = 3, + GPIO3B7_GPIO = 0, + GPIO3B7_CIF_DATA11, + GPIO3B7_I2C3_SCL, + + GPIO3B6_SHIFT = 12, + GPIO3B6_MASK = 3, + GPIO3B6_GPIO = 0, + GPIO3B6_CIF_DATA10, + GPIO3B6_I2C3_SDA, + + GPIO3B5_SHIFT = 10, + GPIO3B5_MASK = 3, + GPIO3B5_GPIO = 0, + GPIO3B5_CIF_DATA1, + GPIO3B5_HSADC_DATA9, + + GPIO3B4_SHIFT = 8, + GPIO3B4_MASK = 3, + GPIO3B4_GPIO = 0, + GPIO3B4_CIF_DATA0, + GPIO3B4_HSADC_DATA8, + + GPIO3B3_SHIFT = 6, + GPIO3B3_MASK = 1, + GPIO3B3_GPIO = 0, + GPIO3B3_CIF_CLKOUT, + + GPIO3B2_SHIFT = 4, + GPIO3B2_MASK = 1, + GPIO3B2_GPIO = 0, + /* no muxes */ + + GPIO3B1_SHIFT = 2, + GPIO3B1_MASK = 1, + GPIO3B1_GPIO = 0, + GPIO3B1_SDMMC0_WRITE_PRT, + + GPIO3B0_SHIFT = 0, + GPIO3B0_MASK = 1, + GPIO3B0_GPIO = 0, + GPIO3B0_SDMMC_DETECT_N, +}; + +/* GRF_GPIO3C_IOMUX */ +enum { + GPIO3C7_SHIFT = 14, + GPIO3C7_MASK = 3, + GPIO3C7_GPIO = 0, + GPIO3C7_SDMMC1_WRITE_PRT, + GPIO3C7_RMII_CRS_DVALID, + GPIO3C7_RESERVED, + + GPIO3C6_SHIFT = 12, + GPIO3C6_MASK = 3, + GPIO3C6_GPIO = 0, + GPIO3C6_SDMMC1_DECTN, + GPIO3C6_RMII_RX_ERR, + GPIO3C6_RESERVED, + + GPIO3C5_SHIFT = 10, + GPIO3C5_MASK = 3, + GPIO3C5_GPIO = 0, + GPIO3C5_SDMMC1_CLKOUT, + GPIO3C5_RMII_CLKOUT, + GPIO3C5_RMII_CLKIN, + + GPIO3C4_SHIFT = 8, + GPIO3C4_MASK = 3, + GPIO3C4_GPIO = 0, + GPIO3C4_SDMMC1_DATA3, + GPIO3C4_RMII_RXD1, + GPIO3C4_RESERVED, + + GPIO3C3_SHIFT = 6, + GPIO3C3_MASK = 3, + GPIO3C3_GPIO = 0, + GPIO3C3_SDMMC1_DATA2, + GPIO3C3_RMII_RXD0, + GPIO3C3_RESERVED, + + GPIO3C2_SHIFT = 4, + GPIO3C2_MASK = 3, + GPIO3C2_GPIO = 0, + GPIO3C2_SDMMC1_DATA1, + GPIO3C2_RMII_TXD0, + GPIO3C2_RESERVED, + + GPIO3C1_SHIFT = 2, + GPIO3C1_MASK = 3, + GPIO3C1_GPIO = 0, + GPIO3C1_SDMMC1_DATA0, + GPIO3C1_RMII_TXD1, + GPIO3C1_RESERVED, + + GPIO3C0_SHIFT = 0, + GPIO3C0_MASK = 3, + GPIO3C0_GPIO = 0, + GPIO3C0_SDMMC1_CMD, + GPIO3C0_RMII_TX_EN, + GPIO3C0_RESERVED, +}; + +/* GRF_GPIO3D_IOMUX */ +enum { + GPIO3D6_SHIFT = 12, + GPIO3D6_MASK = 3, + GPIO3D6_GPIO = 0, + GPIO3D6_PWM_3, + GPIO3D6_JTAG_TMS, + GPIO3D6_HOST_DRV_VBUS, + + GPIO3D5_SHIFT = 10, + GPIO3D5_MASK = 3, + GPIO3D5_GPIO = 0, + GPIO3D5_PWM_2, + GPIO3D5_JTAG_TCK, + GPIO3D5_OTG_DRV_VBUS, + + GPIO3D4_SHIFT = 8, + GPIO3D4_MASK = 3, + GPIO3D4_GPIO = 0, + GPIO3D4_PWM_1, + GPIO3D4_JTAG_TRSTN, + + GPIO3D3_SHIFT = 6, + GPIO3D3_MASK = 3, + GPIO3D3_GPIO = 0, + GPIO3D3_PWM_0, + + GPIO3D2_SHIFT = 4, + GPIO3D2_MASK = 3, + GPIO3D2_GPIO = 0, + GPIO3D2_SDMMC1_INT_N, + + GPIO3D1_SHIFT = 2, + GPIO3D1_MASK = 3, + GPIO3D1_GPIO = 0, + GPIO3D1_SDMMC1_BACKEND_PWR, + GPIO3D1_MII_MDCLK, + + GPIO3D0_SHIFT = 0, + GPIO3D0_MASK = 3, + GPIO3D0_GPIO = 0, + GPIO3D0_SDMMC1_PWR_EN, + GPIO3D0_MII_MD, +}; + struct rk3188_pinctrl_priv { struct rk3188_grf *grf; struct rk3188_pmu *pmu; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index 19a7415522..c7052257aa 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -70,6 +70,60 @@ static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf, PMUGRF_GPIO1C0_SEL_MASK, PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT); break; + + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio4a_iomux, + GRF_GPIO4A1_SEL_MASK, + GRF_I2C1_SDA << GRF_GPIO4A1_SEL_SHIFT); + rk_clrsetreg(&grf->gpio4a_iomux, + GRF_GPIO4A2_SEL_MASK, + GRF_I2C1_SCL << GRF_GPIO4A2_SEL_SHIFT); + break; + + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A0_SEL_MASK, + GRF_I2C2_SDA << GRF_GPIO2A0_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A1_SEL_MASK, + GRF_I2C2_SCL << GRF_GPIO2A1_SEL_SHIFT); + break; + case PERIPH_ID_I2C3: + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C0_SEL_MASK, + GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT); + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C1_SEL_MASK, + GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT); + break; + + case PERIPH_ID_I2C4: + rk_clrsetreg(&pmugrf->gpio1b_iomux, + PMUGRF_GPIO1B3_SEL_MASK, + PMUGRF_I2C4_SDA << PMUGRF_GPIO1B3_SEL_SHIFT); + rk_clrsetreg(&pmugrf->gpio1b_iomux, + PMUGRF_GPIO1B4_SEL_MASK, + PMUGRF_I2C4_SCL << PMUGRF_GPIO1B4_SEL_SHIFT); + break; + + case PERIPH_ID_I2C7: + rk_clrsetreg(&grf->gpio2a_iomux, + GRF_GPIO2A7_SEL_MASK, + GRF_I2C7_SDA << GRF_GPIO2A7_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2b_iomux, + GRF_GPIO2B0_SEL_MASK, + GRF_I2C7_SCL << GRF_GPIO2B0_SEL_SHIFT); + break; + + case PERIPH_ID_I2C6: + rk_clrsetreg(&grf->gpio2b_iomux, + GRF_GPIO2B1_SEL_MASK, + GRF_I2C6_SDA << GRF_GPIO2B1_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2b_iomux, + GRF_GPIO2B2_SEL_MASK, + GRF_I2C6_SDA << GRF_GPIO2B2_SEL_SHIFT); + break; + case PERIPH_ID_I2C8: rk_clrsetreg(&pmugrf->gpio1c_iomux, PMUGRF_GPIO1C4_SEL_MASK, @@ -78,13 +132,8 @@ static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf, PMUGRF_GPIO1C5_SEL_MASK, PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT); break; - case PERIPH_ID_I2C1: - case PERIPH_ID_I2C2: - case PERIPH_ID_I2C3: - case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: - case PERIPH_ID_I2C6: - case PERIPH_ID_I2C7: default: debug("i2c id = %d iomux error!\n", i2c_id); break; |